diff options
| author | Guillaume Knispel <gknispel@avencall.com> | 2012-07-13 16:14:43 +0200 |
|---|---|---|
| committer | Guillaume Knispel <gknispel@avencall.com> | 2012-07-13 16:14:43 +0200 |
| commit | 657fcc9ad078091599c4e4e86127b2d1692c975b (patch) | |
| tree | 011d72980937598470e1e08bfd6a09daea6c0e65 | |
| parent | 509b6ca836a0ee64ed0bb04b5de68b3fc17a382e (diff) | |
import Telephony
181 files changed, 71858 insertions, 1 deletions
diff --git a/Acceleration/Makefile b/Acceleration/Makefile new file mode 100644 index 0000000..6cdcfea --- /dev/null +++ b/Acceleration/Makefile @@ -0,0 +1,134 @@ +############################################################################### +# +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# +# +############################################################################### + + +# Ensure The ICP_ROOT environmental var is defined. +ifndef ICP_ROOT +$(error ICP_ROOT is undefined. Please set the path \ + "-> setenv ICP_ROOT <path>") +endif + +export ICP_BUILDSYSTEM_PATH=$(ICP_ROOT)/build_system +export ICP_ACCEL_INC=YES + + +DATE=$(shell date '+%m_%d_%y') + +#Paths to Top-Level Makefiles for each team# +OSAL_PATH=$(ICP_ROOT)/Acceleration/library/icp_utils/OSAL/ +ICP_BUILD_OUTPUT?=$(ICP_ROOT)/Acceleration/build_$(DATE) +VOICE_SERVICE=voice_service +VOICE_INSTALL_SCRIPT=install_voice.sh + +#Voice variables +VOICE_PATH=$(ICP_ROOT)/Acceleration/library/icp_telephony +VOICE_DRIVER_PATH=$(ICP_ROOT)/Acceleration/drivers/icp_tdm + +VOICE_COMPS=icp_telephony +VOICE_DRIVER_COMPS=hss_voice_driver tdm_setup_driver + + +all: startup_script osal $(VOICE_COMPS) $(VOICE_DRIVER_COMPS) cp_voice_modules + + @chmod 777 $(ICP_BUILD_OUTPUT)/* + @echo 'Acceleration Build Done'; + +output_dir: + test -d $(ICP_BUILD_OUTPUT) || mkdir $(ICP_BUILD_OUTPUT); + +startup_script: output_dir + @chmod 777 $(ICP_ROOT)/Install/*; + cp $(ICP_ROOT)/Install/$(VOICE_SERVICE) $(ICP_BUILD_OUTPUT)/ + cp $(ICP_ROOT)/Install/$(VOICE_INSTALL_SCRIPT) $(ICP_BUILD_OUTPUT)/ +osal: + @echo ; echo 'Building OSAL'; + @cd $(OSAL_PATH) && make libosal IX_TARGET=linuxle IX_DEVICE=EP805XX IX_OSAL_OS_LEVEL=kernel_space IX_LINUXVER=2.6.18; \ + +$(VOICE_COMPS): + @echo ; echo 'Building $@'; + @cd $(VOICE_PATH) && export ICP_ENV_DIR=$(VOICE_PATH) && make kernel_module; \ + +$(VOICE_DRIVER_COMPS): + @echo ; echo 'Building $@'; + @cd $(VOICE_DRIVER_PATH)/$@ && export ICP_ENV_DIR=$(VOICE_PATH) && make install; \ + +cp_voice_modules: + cp $(VOICE_PATH)/build/linux_2.6/kernel_space/tdm_infra.ko $(ICP_BUILD_OUTPUT)/ + cp $(VOICE_DRIVER_PATH)/hss_voice_driver/build/linux_2.6/kernel_space/hssvoice_driver.ko $(ICP_BUILD_OUTPUT)/ + cp $(VOICE_DRIVER_PATH)/tdm_setup_driver/build/linux_2.6/kernel_space/tdm_setup_driver.ko $(ICP_BUILD_OUTPUT)/ + cp $(ICP_ROOT)/Acceleration/firmware/IxPiuMicrocode.dat $(ICP_BUILD_OUTPUT)/ + +clean: + @echo ; echo 'Cleaning OSAL'; + @cd $(OSAL_PATH) && make clean IX_TARGET=linuxle IX_DEVICE=EP805XX IX_OSAL_OS_LEVEL=kernel_space IX_LINUXVER=2.6.18; + @echo ; echo 'Cleaning Voice Components'; + rm -rf $(VOICE_PATH)/build/linux_2.6/kernel_space/; + rm -rf $(VOICE_PATH)/tdm_io_access/build/linux_2.6/kernel_space/; + rm -rf $(VOICE_PATH)/tdm_infrastructure_message_handler/build/linux_2.6/kernel_space/; + rm -rf $(VOICE_PATH)/tdm_infrastructure_queue_manager/build/linux_2.6/kernel_space/; + rm -rf $(VOICE_PATH)/tdm_infrastructure_downloader/build/linux_2.6/kernel_space/; + rm -rf $(VOICE_PATH)/ssp_access/build/linux_2.6/kernel_space/; + rm -rf $(VOICE_DRIVER_PATH)/hss_voice_driver/build/linux_2.6/kernel_space/; + rm -rf $(VOICE_DRIVER_PATH)/tdm_setup_driver/build/linux_2.6/kernel_space/; + @echo ; echo 'Cleaning Binaries in Output Dir'; + @rm -rf $(ICP_BUILD_OUTPUT); + @echo ; echo 'Cleaning done'; diff --git a/Acceleration/drivers/icp_tdm/hss_voice_driver/Makefile b/Acceleration/drivers/icp_tdm/hss_voice_driver/Makefile new file mode 100644 index 0000000..860d40c --- /dev/null +++ b/Acceleration/drivers/icp_tdm/hss_voice_driver/Makefile @@ -0,0 +1,127 @@ +######################################################################### +# +# Targets supported +# all - builds everything and installs +# install - identical to all +# depend - build dependencies +# clean - clears derived objects except the .depend files +# distclean- clears all derived objects and the .depend file +# +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# +############################################################################ + + +####################Common variables and definitions######################## +# Ensure The ICP_ENV_DIR environmental var is defined. +ifndef ICP_ENV_DIR +$(error ICP_ENV_DIR is undefined. Please set the path to your environment makefile \ + "-> setenv ICP_ENV_DIR <path>") +endif + +#Add your project environment Makefile +include $(ICP_ENV_DIR)/environment.mk + + +#include the makefile with all the default and common Make variable definitions +include $(ICP_BUILDSYSTEM_PATH)/build_files/common.mk + + +#Add the name for the executable, Library or Module output definitions +OUTPUT_NAME=hssvoice_driver + +# List of Source Files to be compiled (to be in a single line or on different lines separated by a "\" and tab. +MODULE_SOURCES=$(ICP_COMMON_PLATFORM)$(ICP_SLASH)$(ICP_OS_TYPE)$(ICP_SLASH)icp_hssvoicedrv.c + +#common includes between all supported OSes +INCLUDES+= -I $(ICP_API_DIR)\ + -I $(ICP_API_DIR)/hss \ + -I $(ICP_OSAL_DIR)/common/include \ + -I $(ICP_DRIVERS_DIR)/include + + + + +ifeq ($(ICP_INTEL_DEV),YES) +INCLUDES += -I $(ICP_OSAL_DIR)/common/include/modules \ + -I $(ICP_OSAL_DIR)/common/include/modules/ddk \ + -I $(ICP_OSAL_DIR)/common/include/modules/bufferMgt \ + -I $(ICP_OSAL_DIR)/common/include/modules/ioMem +endif + + +ifdef ICP_DEBUG + CFLAGS+= -DDEBUG +endif +EXTRA_CFLAGS += -DENABLE_IOMEM -DENABLE_BUFFERMGT + + +#include your $(ICP_OS)_$(ICP_OS_LEVEL).mk file +include $(ICP_VOICE_DRV_DIR)/$(ICP_OS)_$(ICP_OS_LEVEL).mk + +# On the line directly below list the outputs you wish to build for, +# e.g "lib_static lib_shared exe module" as show below +install: module + + + + +###################Include rules makefiles######################## +include $(ICP_BUILDSYSTEM_PATH)/build_files/rules.mk +###################End of Rules inclusion######################### diff --git a/Acceleration/drivers/icp_tdm/hss_voice_driver/icp_hssvoicedrv.c b/Acceleration/drivers/icp_tdm/hss_voice_driver/icp_hssvoicedrv.c new file mode 100644 index 0000000..f17ef67 --- /dev/null +++ b/Acceleration/drivers/icp_tdm/hss_voice_driver/icp_hssvoicedrv.c @@ -0,0 +1,2774 @@ +/****************************************************************************** + * @file icp_hssvoicedrv.c + * + * @description C file for HSS Voice Driver + * + * + * @Revision 1.0 + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + *****************************************************************************/ +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/fs.h> +#include <linux/cdev.h> +#include <linux/file.h> +#include <asm/uaccess.h> +#include <linux/semaphore.h> +#include <linux/poll.h> + +#include "IxOsal.h" +#include "icp.h" +#include "icp_hssacc.h" +#include "icp_hssvoicedrv.h" +#include "icp_hssdrv_common.h" + + +MODULE_DESCRIPTION("HSS TDM I/O Unit Voice Driver"); +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_VERSION("1.0"); +MODULE_AUTHOR("Intel Corp"); + +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + +/*Load time parameters*/ +int hssvoicedrv_major = 0; /* Dynamic allocation */ +int hssvoicedrv_minor = 0; /* Dynamic allocation */ + +int hssvoicedrv_enable_int = TRUE; /*Default is : interrupt turned on */ + +/*Module parameter - major number*/ +module_param(hssvoicedrv_major, int, S_IRUGO); +/*Module parameter - interrupt enable */ +module_param(hssvoicedrv_enable_int, int, S_IRUGO); + +#define HSSVOICEDRV_DEVS 1 + +/*Function Declarations*/ + +/*Implementations of Linux char device driver operations*/ +/*write implementation*/ +ssize_t hssvoicedrv_write(struct file *filep, const char __user * buf, + size_t size, loff_t * offset); +/*read implementation*/ +ssize_t hssvoicedrv_read(struct file *filep, char __user * buffer, size_t size, + loff_t * offset); +/*open implementation*/ +int hssvoicedrv_open(struct inode *inode, struct file *filep); +/*release implementation*/ +int hssvoicedrv_release(struct inode *inode, struct file *filep); +/*ioctl implementation*/ +int hssvoicedrv_ioctl(struct inode *inode, struct file *filep, + unsigned int cmd, unsigned long arg); +/*poll implementation*/ +unsigned int hssvoicedrv_poll(struct file *filp, poll_table * wait); + +/*Stats functions*/ +/*channel stats*/ +void hssvoicedrv_display_channel_stat(unsigned int hss_chan_num); +/*client stats*/ +void hssvoicedrv_display_client_stat(unsigned int client); + +/*Callbacks*/ +/*receive*/ +void rx_callback(icp_user_context_t userContext); +/*tx done*/ +void txdone_callback(icp_user_context_t userContext); + +/*Error Callbacks*/ +/*Port errors callback*/ +void hssvoicedrv_port_error_callback(icp_user_context_t user_context, + icp_hssacc_port_error_t error_type); +/*General errors callback*/ +void hssvoicedrv_error_callback(icp_user_context_t user_context, + icp_hssacc_error_t error_type); +/*Osal buffer management functions*/ +/*get an osal buffer with an attached data buffer of the specified size*/ +int get_osal_buf_with_data_buf(IX_OSAL_MBUF ** osal_buf, + unsigned int data_buf_length); +/*put an osal buffer with an attached data buffer of the specified size*/ +void put_osal_buf_with_data_buf(IX_OSAL_MBUF * osal_buf); +/*This function extracts the data buffer atached to an osal buffer*/ +void read_data_buff_from_osalbuf(IX_OSAL_MBUF * osal_buf, unsigned int *len, + char **data_buf); + +/*Cleanup functions*/ +/*removes the cdev*/ +void hssvoicedrv_cdev_delete(void); +/*unregisters the device*/ +void hssvoicedrv_dev_unregister(void); +/* module exit implementation */ +static void hssvoicedrv_cleanup_module(void); +/*deallocates a hss channel*/ +void hssvoicedrv_deallocate_channel(unsigned int hss_chan_id); + +/*Defines*/ +/* header and payload sizes */ +#define ICP_HSSVOICEDRV_HEADER_SIZE 4 + +/*WideBand is the max allowable payload size*/ +#define ICP_HSSVOICEDRV_WB_SAMPLE_SIZE 320 + +/*Min Tx Size*/ +#define ICP_HSSVOICEDRV_MIN_CLIENT_TX_PACKET_SIZE 5 +/*Min Rx Size*/ +#define ICP_HSSVOICEDRV_MIN_CLIENT_RX_PACKET_SIZE 84 + +/*Max amount of replenishment*/ +#define ICP_HSSVOICEDRV_MAX_RX_REPLENISH 2048 + +/*Size of a Gain Control Table*/ +#define GCT_SIZE 256 +#define GCT_ALIGN_PADDING 8 +#define GCT_ALIGN_MASK 0xFFFFFFF8 + +#define SIZE_OF_BYTE 8 +#define U16_BIT_MASK 0xFFFF + +/* The time in jiffies for a blocking read() to wait for data on a channel + * before waking up and checking that it is still valid to wait for data + * on this channel*/ +#define BLOCKING_READ_WAIT_TIME 10 + +#define CLIENT_CHAN_MSB 2 +#define CLIENT_CHAN_LSB 3 + +#define PACKET_LEN_MSB 0 +#define PACKET_LEN_LSB 1 + + +#define ICP_HSSVOICEDRV_PRIVATE static + +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + +/*Data Structures*/ +struct file_operations hssvoicedrv_fops = { + .owner = THIS_MODULE, + .read = hssvoicedrv_read, /* read method */ + .write = hssvoicedrv_write, /* write method */ + .poll = hssvoicedrv_poll, /* poll method */ + .ioctl = hssvoicedrv_ioctl, /* ioctl method */ + .open = hssvoicedrv_open, /* open moethod */ + .release = hssvoicedrv_release /* release method */ +}; + + +/*Mode tracking*/ +typedef enum { + ICP_HSSVOICEDRV_NOTSET = 0, + /**< HSS Voice Driver mode is not set. */ + ICP_HSSVOICEDRV_BLOCKING, + /**< HSS Voice Driver mode is operating in blocking mode. */ + ICP_HSSVOICEDRV_NONBLOCKING + /**< HSS Voice Driver mode is operating in non-blocking mode. */ +} icp_hssvoicedrv_mode; + +/*Channel State tracking*/ +typedef enum { + ICP_HSSVOICEDRV_UNUSED = 0, + /**< Channel is unused. */ + ICP_HSSVOICEDRV_ENABLED, + /**< Channel is enabled. */ + ICP_HSSVOICEDRV_DISABLED + /**< Channel is disabled. */ +} icp_hssvoicedrv_channel_state; + +/*structure to represent a client*/ +typedef struct icp_client_s { + /*client is use or not */ + unsigned int enabled; + /*mutex used to synchronise client reads */ + struct semaphore client_read_mutex; +} icp_client_t; + +/* Channel structure */ +typedef struct icp_client_chan_map_s { + unsigned int client_id; /*client number */ + unsigned int client_chan_id; /*client channel number */ + icp_hssvoicedrv_channel_state state; /*state of the channel */ + unsigned int port_id; /*Hss port for this channel */ + /*If enabled this indicates that this channel is the + * source of bypass for another channel */ + unsigned int src_bypass_enabled; + /*The destination channel for which this + * channel is the source of bypass */ + unsigned int dest_of_bypass; + /*The Voice bypass Id */ + unsigned int voice_bypass_id; + /*If enabled this indicates that this channel is the + * destination of bypass from another channel */ + unsigned int dest_bypass_enabled; + /*The source channel for which this channel + * is the destination of bypass */ + unsigned int src_of_bypass; + /*outstanding hssacc receive callbacks */ + volatile signed int rx_data_ready; + /*wait queue used for rx blocking mode */ + wait_queue_head_t rx_wait_queue; +} icp_client_chan_map_t; + +/*Globals*/ + +/* total of how many osal buffers are allocated by this + * driver at a given time*/ +ICP_HSSVOICEDRV_PRIVATE unsigned int hssvoicedrv_current_bufs = 0; + +struct cdev *hssvoicedrv_cdev = NULL; + +ICP_HSSVOICEDRV_PRIVATE unsigned int icp_hssacc_max_clients = 0; +ICP_HSSVOICEDRV_PRIVATE unsigned int icp_hssacc_max_ports = 0; +ICP_HSSVOICEDRV_PRIVATE unsigned int icp_hssacc_max_chans = 0; +ICP_HSSVOICEDRV_PRIVATE unsigned int icp_voicedriver_max_chans_per_client = 0; + +/*pre-allocated osal buffer for replenishment*/ +IX_OSAL_MBUF *spare_wheel_osal_buf = NULL; + +/*Mutex for access to control functionality*/ +DECLARE_MUTEX(control_mutex); + +/*Head of arrays that will be allocated on init*/ +icp_client_t *clients = NULL; +ICP_HSSVOICEDRV_PRIVATE icp_client_chan_map_t *chan_mapper = NULL; + +/* Global to keep track of whether the voice driver is being used + * in blocking or non-blocking mode*/ +static int hssvoicedrv_mode = ICP_HSSVOICEDRV_NOTSET; + + +/*Check if the requested client channel id is available for use*/ +icp_status_t check_client_chan_num_is_available(unsigned int client_id, + unsigned int chan) +{ + unsigned int i = 0; + icp_status_t status = ICP_STATUS_FAIL; + + /*for all possible channels */ + for (i = 0; i < icp_hssacc_max_chans; i++) { + /*check is this channel is used by the voice driver */ + if (chan_mapper[i].state != ICP_HSSVOICEDRV_UNUSED) { + /*check if this channel is owned by this client */ + if (chan_mapper[i].client_id == client_id) { + /*check if the existing channel number + is the same as the requested one */ + if (chan_mapper[i].client_chan_id == chan) { + /* The client already has a channel + * with this client channel number*/ + return ICP_STATUS_FAIL; + } + } + } else { + status = ICP_STATUS_SUCCESS; + } + } + return status; +} + +/*Check if the requested client channel id is available for use*/ +icp_status_t check_client_for_max_chans_per_client_limit(unsigned int client_id) +{ + unsigned int num_client_chans_used = 0; + unsigned int i = 0; + icp_status_t status = ICP_STATUS_SUCCESS; + + for (i = 0; i < icp_hssacc_max_chans; i++) { + if (chan_mapper[i].client_id == client_id && + chan_mapper[i].state != ICP_HSSVOICEDRV_UNUSED) { + num_client_chans_used++; + } + } + + if (icp_voicedriver_max_chans_per_client <= num_client_chans_used) { + status = ICP_STATUS_FAIL; + } + + return status; +} + +/*Check if the voice driver uses any hss channels */ +icp_status_t check_no_channels_exist(void) +{ + unsigned int i = 0; + /*for all possible channels */ + for (i = 0; i < icp_hssacc_max_chans; i++) { + if (chan_mapper[i].state != ICP_HSSVOICEDRV_UNUSED) { + /*There is at least one channel that is + * enabled or disabled */ + return ICP_STATUS_FAIL; + } + } + return ICP_STATUS_SUCCESS; +} + +/*Check if the voice driver has any open clients */ +icp_status_t check_no_clients_exist(void) +{ + unsigned int i = 0; + /*for all possible clients */ + for (i = 0; i < icp_hssacc_max_clients; i++) { + if (clients[i].enabled != FALSE) { + /*There is at least one client enabled */ + return ICP_STATUS_FAIL; + } + } + return ICP_STATUS_SUCCESS; +} + +/*Check the client has no enabled or disabled channels*/ +icp_status_t check_no_client_channels_exist(unsigned int client_id) +{ + unsigned int i = 0; + + for (i = 0; i < icp_hssacc_max_chans; i++) { + if (chan_mapper[i].state != ICP_HSSVOICEDRV_UNUSED) { + if (chan_mapper[i].client_id == client_id) { + /* This client has at least one channel + * in either enabled or disabled state*/ + return ICP_STATUS_FAIL; + } + } + } + return ICP_STATUS_SUCCESS; +} + +/*Given the client id and the client channel id, + * find the associated hss channel id number, if any*/ +inline icp_status_t find_hss_chanid_to_this_client_and_chanid(unsigned int + client_id, + unsigned int chan, + unsigned int + *hss_chan_id) +{ + unsigned int i = 0; + + for (i = 0; i < icp_hssacc_max_chans; i++) { + if (chan_mapper[i].state != ICP_HSSVOICEDRV_UNUSED) { + if (chan_mapper[i].client_id == client_id) { + if (chan_mapper[i].client_chan_id == chan) { + /* found correxponding hss channel + * to this client and client chan num*/ + *hss_chan_id = i; + return ICP_STATUS_SUCCESS; + } + } + } + } + return ICP_STATUS_FAIL; + +} + +/*Find a free client id*/ +icp_status_t find_free_client_id(unsigned int *client_num) +{ + unsigned int i = 0; + + for (i = 0; i < icp_hssacc_max_clients; i++) { + if (clients[i].enabled == FALSE) { + /*This client id is free */ + clients[i].enabled = TRUE; + *client_num = i; + return ICP_STATUS_SUCCESS; + } + } + return ICP_STATUS_FAIL; +} + +/*Mark the given client id as being free*/ +void delete_client_id(unsigned int client_id) +{ + /*Indicate that this client is no longer used */ + clients[client_id].enabled = FALSE; + return; +} + +/* Construct a datapath header - pkt len and client chan id*/ +inline icp_status_t hssvoicedrv_header_create(char *data_header, + unsigned int rx_len, + unsigned int client_chan_id, + unsigned int free_buf_space) +{ + + /*Insert the client channel id */ + /*client_chan_id LSB */ + data_header[CLIENT_CHAN_LSB] = cpu_to_le16(client_chan_id) & 0xFF; + /*client_chan_id MSB */ + data_header[CLIENT_CHAN_MSB] = (cpu_to_le16(client_chan_id) & 0xFF00) >> 8; + + /*check if there is enough room left in the buffer for this data */ + if (free_buf_space < rx_len) { + printk(KERN_ERR + "%s - ERROR: There is not enough buffer space to " + "receive data on channel %d \n", + __FUNCTION__, client_chan_id); + return ICP_STATUS_FAIL; + } + + /*check len is less than 16 bits - otherwise it won't fit in the + * header */ + if (rx_len & 0xFFFF0000) { + printk(KERN_ERR + "%s - ERROR: Above the max receive size received " + "on channel %d \n", __FUNCTION__, client_chan_id); + return ICP_STATUS_FAIL; + } + + /*Insert the length */ + /*rx_len LSB */ + data_header[1] = cpu_to_le16(rx_len) & 0xFF; + /*rx_len MSB */ + data_header[0] = (cpu_to_le16(rx_len) & 0xFF00) >> SIZE_OF_BYTE; + + return ICP_STATUS_SUCCESS; +} + +/* This function resets and replenishs an osal buffer*/ +inline void hssvoicedrv_cleanup_rx_osalbuf(IX_OSAL_MBUF * osal_buf) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + + /*reset the buffer length */ + IX_OSAL_MBUF_MLEN(osal_buf) = IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(osal_buf); + + /*Try and replenish */ + status = + icp_HssAccRxFreeReplenish(ICP_HSSACC_CHAN_TYPE_VOICE, osal_buf); + if (status != ICP_STATUS_SUCCESS) { + /*We couldn't replenish it - no option but to put it */ + put_osal_buf_with_data_buf(osal_buf); + } +} + +/************************************************************************* +* +* Module init function +* +*************************************************************************/ +ICP_HSSVOICEDRV_PRIVATE int __init hssvoicedrv_init_module(void) +{ + int result; + dev_t hssvoicedrv_dev = 0; + unsigned int i = 0; + icp_status_t status = 0; + unsigned int ret_val = 0; + icp_boolean_t interrupt_generation = ICP_TRUE; + + /**********CHAR DEVICE DRIVER REGISTRATION**********/ + /* Setup the major and minor device numbers and register the device */ + if (hssvoicedrv_major) { + hssvoicedrv_dev = MKDEV(hssvoicedrv_major, hssvoicedrv_minor); + result = + register_chrdev_region(hssvoicedrv_dev, HSSVOICEDRV_DEVS, + "hssvoicedrv"); + printk(KERN_DEBUG "%s - DEBUG: Major Num set by user as %d\n", + __FUNCTION__, hssvoicedrv_major); + } else { + result = + alloc_chrdev_region(&hssvoicedrv_dev, hssvoicedrv_minor, + HSSVOICEDRV_DEVS, "hssvoicedrv"); + hssvoicedrv_major = MAJOR(hssvoicedrv_dev); + hssvoicedrv_dev = MKDEV(hssvoicedrv_major, hssvoicedrv_minor); + } + if (result < 0) { + printk(KERN_ERR "%s - ERROR: Can't get major number %d\n", + __FUNCTION__, hssvoicedrv_major); + return result; + } + + /* Setup the cdev structure */ + hssvoicedrv_cdev = cdev_alloc(); + cdev_init(hssvoicedrv_cdev, &hssvoicedrv_fops); + hssvoicedrv_cdev->owner = THIS_MODULE; + hssvoicedrv_cdev->ops = &hssvoicedrv_fops; + result = cdev_add(hssvoicedrv_cdev, hssvoicedrv_dev, 1); + + /* Fail gracefully if needs be */ + if (result) { + printk(KERN_ERR + "%s - ERROR: Error %d adding hssvoicedrv cdev \n", + __FUNCTION__, result); + hssvoicedrv_dev_unregister(); + return result; + } + /**********END CHAR DEVICE DRIVER REGISTRATION**********/ + + /**********GET THE MAX SIZES**********/ + /*Get the max number of hss ports */ + icp_hssacc_max_ports = icp_HssAccNumSupportedPortsGet(); + if (!icp_hssacc_max_ports) { + /*HssAcc doesn't support any ports */ + printk(KERN_ERR + "%s - ERROR: HSS Acc does not support any ports \n", + __FUNCTION__); + hssvoicedrv_cleanup_module(); + return -EPERM; + } + + /*Get max number of hssacc channels */ + icp_hssacc_max_chans = icp_HssAccNumSupportedChannelsGet(); + if (!icp_hssacc_max_chans) { + /*HssAcc doesn't support any channels - + * no point in continuing */ + printk(KERN_ERR + "%s - ERROR: HSS Acc does not support any channels \n", + __FUNCTION__); + hssvoicedrv_cleanup_module(); + return -EPERM; + } + /*Max channels is also the max clients, as there can be + * one channel per client */ + icp_hssacc_max_clients = icp_hssacc_max_chans; + + /*Max channels per client is half the max number of hssacc channels */ + icp_voicedriver_max_chans_per_client = (icp_hssacc_max_chans >> 1); + + + /**********END GET THE MAX SIZES**********/ + + /**********ALLOCATE THE ARRAYS**********/ + /*chan mapper array */ + chan_mapper = + (icp_client_chan_map_t *) kzalloc(sizeof(icp_client_chan_map_t) * + icp_hssacc_max_chans, GFP_KERNEL); + if (!chan_mapper) { + /*Could not allocate the memory */ + printk(KERN_ERR "%s - ERROR: Could not allocate memory \n", + __FUNCTION__); + hssvoicedrv_cleanup_module(); + return -ENOMEM; + } + + /*clients */ + clients = (icp_client_t *) kzalloc(sizeof(icp_client_t) + * icp_hssacc_max_chans, GFP_KERNEL); + if (!clients) { + /*Could not allocate the memory */ + printk(KERN_ERR "%s - ERROR: Could not allocate memory \n", + __FUNCTION__); + hssvoicedrv_cleanup_module(); + return -ENOMEM; + } + /**********END ALLOCATE THE ARRAYS**********/ + + /**********INITIALISATIONS**********/ + /*Initialise chan_mapper array and the clients array */ + for (i = 0; i < icp_hssacc_max_chans; i++) { + /*initialise chan_mapper array */ + init_waitqueue_head(&(chan_mapper[i].rx_wait_queue)); + chan_mapper[i].state = ICP_HSSVOICEDRV_UNUSED; + + /*initialise clients array */ + init_MUTEX(&(clients[i].client_read_mutex)); + clients[i].enabled = FALSE; + } + + /*Check the interrupt generation module parameter */ + if (hssvoicedrv_enable_int == FALSE) { + /*Need to use ICP_ types for call to Hss Acc */ + interrupt_generation = ICP_FALSE; + } + + /*initialise the hssacc voice service - set the rx max to the + * 4 timeslot sample size */ + status = + icp_HssAccVoiceInit(ICP_HSSVOICEDRV_WB_SAMPLE_SIZE, + interrupt_generation); + if (status != ICP_STATUS_SUCCESS) { + printk(KERN_ERR + "%s - ERROR: icp_HssAccVoiceInit returned error %d \n", + __FUNCTION__, status); + hssvoicedrv_cleanup_module(); + return -EPERM; + } + + /*Initialise the pre-allocated osal buffer */ + ret_val = + get_osal_buf_with_data_buf(&spare_wheel_osal_buf, + ICP_HSSVOICEDRV_WB_SAMPLE_SIZE); + if (ret_val) { + /*I can't allocate memory. this is not a critical error now. + * but easier to find if I return an error now */ + printk(KERN_ERR "%s - ERROR: Could not allocate memory \n", + __FUNCTION__); + hssvoicedrv_cleanup_module(); + return -ENOMEM; + } + + /**********END INITIALISATIONS**********/ + /*Register for Error Callbacks*/ + status = + icp_HssAccErrorCallbackRegister(ICP_HSSACC_CHAN_TYPE_VOICE, + (icp_user_context_t) NULL, + hssvoicedrv_error_callback); + if (status != ICP_STATUS_SUCCESS) { + printk(KERN_ERR + "%s - ERROR: " + "icp_HssAccErrorCallbackRegister " + "returned error %d \n", __FUNCTION__, status); + hssvoicedrv_cleanup_module(); + return -EPERM; + } + + printk("hssvoicedrv_init_module :: " + "LOADED SUCCESSFULLY HSS TDM I/O Voice Driver ... \n"); + + return 0; +} + +/*deletes the cdev*/ +void hssvoicedrv_cdev_delete(void) +{ + /* Remove the cdev */ + cdev_del(hssvoicedrv_cdev); +} + +/*unregisters char driver region*/ +void hssvoicedrv_dev_unregister(void) +{ + dev_t hssvoicedrv_dev = MKDEV(hssvoicedrv_major, hssvoicedrv_minor); + + /* Unregister the dev */ + unregister_chrdev_region(hssvoicedrv_dev, HSSVOICEDRV_DEVS); +} + +/************************************************************************* +* +* Module exit function +* +*************************************************************************/ +static void hssvoicedrv_cleanup_module(void) +{ + /*cleanup char device driver related registrations */ + hssvoicedrv_cdev_delete(); + hssvoicedrv_dev_unregister(); + + /*deallocate global memory */ + if (NULL != chan_mapper) { + kfree(chan_mapper); + chan_mapper = NULL; + } + if (NULL != clients) { + kfree(clients); + clients = NULL; + } + + /*deallocate the pre-allocated osal buffer */ + put_osal_buf_with_data_buf(spare_wheel_osal_buf); + +} + +/************************************************************************* +* +* Open the voice driver +* +*************************************************************************/ +int hssvoicedrv_open(struct inode *inode, struct file *filep) +{ + unsigned int new_client_id = icp_hssacc_max_clients; + icp_status_t status = ICP_STATUS_SUCCESS; + unsigned int blocking = FALSE; + + if (filep->f_flags & O_NONBLOCK) { + blocking = FALSE; + } + else { + blocking = TRUE; + } + + if ((hssvoicedrv_enable_int == FALSE) + && (blocking == TRUE)) { + /* Client is trying to open the device file in + * blocking mode after loading this module + * (hence initialising icp_HssAccVoiceInit())with + * interrupt generation turned off. This combination is not + * possible */ + printk(KERN_ERR + "%s - ERROR: Cannot open the device file in blocking" + " mode as interrupt generation was turned off as a " + "module parameter\n", __FUNCTION__); + return -EINVAL; + } + + /*Get the control mutex */ + if (down_interruptible(&control_mutex)) { + printk(KERN_ERR "%s - ERROR: Unable to get control mutex \n", + __FUNCTION__); + return -ERESTARTSYS; + } + + + /* Set the mode of the Voice driver to ensure that HSS Acc will only + * be used in either callback or polling mode*/ + switch (hssvoicedrv_mode) { + case ICP_HSSVOICEDRV_NOTSET: + /* There is currently no open device files, hence the + * voice driver mode is not set and therefore HSS Acc + * voice service is not being used in callback or + * polling mode*/ + if(blocking == TRUE) { + hssvoicedrv_mode = ICP_HSSVOICEDRV_BLOCKING; + } + else { + hssvoicedrv_mode = ICP_HSSVOICEDRV_NONBLOCKING; + } + break; + case ICP_HSSVOICEDRV_BLOCKING: + /* Another device file is open in blocking mode, + * meaning that HSS Acc is currently being used + * in callback mode*/ + if(blocking == FALSE) { + /* The voice driver can only be in blocking or + * non-blocking mode at a given time as the + * HSS Acc voice service can only be used in + * either callback or polling mode at a given + * time. It is not possible to allow this + * device file to be opened in non-blocking + * mode at this time*/ + up(&control_mutex); + printk(KERN_ERR + "%s - ERROR: Cannot open the device file " + "in non-blocking mode as a device file in " + "blocking mode already exists. " + "\n", __FUNCTION__); + return -EINVAL; + } + break; + case ICP_HSSVOICEDRV_NONBLOCKING: + /* Another device file is open in non-blocking mode, + * meaning that HSS Acc is currently being used in + * polling mode*/ + if(blocking == TRUE) { + /* The voice driver can only be in blocking or + * non-blocking mode at a given time as the + * HSS Acc voice service can only be used in + * either callback or polling mode at a + * given time. It is not possible to allow + * this device file to be opened in blocking + * mode at this time*/ + up(&control_mutex); + printk(KERN_ERR + "%s - ERROR: Cannot open the device file " + "in blocking mode as a device file in " + "non-blocking mode exists. " + "\n", __FUNCTION__); + return -EINVAL; + } + break; + }; + + /**********ALLOCATE CLIENT ID**********/ + /*Get a new client id for this file descriptor */ + status = find_free_client_id(&new_client_id); + /*Release the mutex */ + up(&control_mutex); + if (status != ICP_STATUS_SUCCESS) { + /*could not find a free client - all clients are used */ + printk(KERN_ERR "%s - ERROR: Max Number of clients reached \n", + __FUNCTION__); + return -ENOSR; + } + + /*Set the file structs private_data with the client id */ + filep->private_data = (unsigned int *)new_client_id; + /**********END ALLOCATE CLIENT ID**********/ + return 0; +} + +/************************************************************************* +* +* Close the voice driver +* +*************************************************************************/ +int hssvoicedrv_release(struct inode *inode, struct file *filep) +{ + unsigned int client_id = 0; + icp_status_t status = ICP_STATUS_SUCCESS; + + if (filep == NULL) { + printk(KERN_ERR "%s - ERROR: NULL pointer parameter \n", + __FUNCTION__); + return -EINVAL; + } + + /*get the client id from the file descriptor */ + client_id = (unsigned int)filep->private_data; + + if (client_id >= icp_hssacc_max_clients) { + printk(KERN_ERR "%s - ERROR: Client Id out of range\n", + __FUNCTION__); + return -EINVAL; + } + /*Get the control mutex */ + if (down_interruptible(&control_mutex)) { + printk(KERN_ERR "%s - ERROR: Unable to get control mutex \n", + __FUNCTION__); + return -ERESTARTSYS; + } + + status = check_no_client_channels_exist(client_id); + if (status != ICP_STATUS_SUCCESS) { + printk(KERN_ERR + "%s - ERROR: Cannot close as client has " + "active channels \n", __FUNCTION__); + up(&control_mutex); + return -EINVAL; + } + + /*delete this client */ + delete_client_id(client_id); + + status = check_no_clients_exist(); + if (status == ICP_STATUS_SUCCESS) { + /* This was the last existing client. + * We can reset the HSS Acc mode */ + hssvoicedrv_mode = ICP_HSSVOICEDRV_NOTSET; + } + + up(&control_mutex); + return 0; +} + +/* + * Control Functions + * + * */ + /*Bring a HSS port up */ +int hssvoicedrv_port_up(icp_hssdrv_portup_t * port_up) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + icp_hssacc_port_config_params_t hss_port_config; + + /*Check parameters */ + if (port_up->portId >= icp_hssacc_max_ports) { + printk(KERN_ERR "%s - ERROR: Invalid Port Number \n", + __FUNCTION__); + return -EINVAL; + } + if (port_up->port_config >= + ICP_HSSDRV_PORT_CONFIG_DELIMITER) { + printk(KERN_ERR "%s - ERROR: Invalid Port Configuration \n", + __FUNCTION__); + return -EINVAL; + } + if (port_up->loopbackMode >= ICP_HSSDRV_EXTERNAL_LOOPBACK_DELIMITER) { + printk(KERN_ERR "%s - ERROR: Invalid Port loopback mode \n", + __FUNCTION__); + return -EINVAL; + } + + /*Create the hssacc data structure for port configuration */ + port_config_create(port_up->port_config, port_up->loopbackMode, + &hss_port_config); + + /*Configure the port */ + status = icp_HssAccPortConfig(port_up->portId, &hss_port_config); + if (status != ICP_STATUS_SUCCESS) { + printk(KERN_ERR + "%s - ERROR: icp_HssAccPortConfig returned error %d \n", + __FUNCTION__, status); + return -EPERM; + } + /*Register for port error callbacks*/ + status = icp_HssAccPortErrorCallbackRegister(port_up->portId, + ICP_HSSACC_CHAN_TYPE_VOICE, + (icp_user_context_t) port_up->portId, + hssvoicedrv_port_error_callback); + if (status != ICP_STATUS_SUCCESS) { + printk(KERN_ERR + "%s - ERROR: icp_HssAccPortErrorCallbackRegister" + " returned error %d \n", + __FUNCTION__, status); + return -EPERM; + } + + /*Bring the port up*/ + status = icp_HssAccPortUp(port_up->portId); + if (status != ICP_STATUS_SUCCESS) { + printk(KERN_ERR + "%s - ERROR: icp_HssAccPortUp returned error %d \n", + __FUNCTION__, status); + return -EPERM; + } + + return 0; +} + +/*Bring a HSS port down*/ +int hssvoicedrv_port_down(unsigned int port_id) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + + /*Check parameter */ + if (port_id >= icp_hssacc_max_ports) { + printk(KERN_ERR "%s - ERROR: Invalid " + "Port Id \n", __FUNCTION__); + return -EINVAL; + } + /*Try to bring the port down */ + status = icp_HssAccPortDown(port_id); + if (status != ICP_STATUS_SUCCESS) { + printk(KERN_ERR + "%s - ERROR: icp_HssAccPortDown returned error %d \n", + __FUNCTION__, status); + return -EPERM; + } + return 0; +} + +/*Add a hss voice channel */ +int hssvoicedrv_chan_add(unsigned int client_id, + icp_hssvoicedrv_channeladd_t * chan_add, + unsigned int *hss_channel_id) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + icp_hssacc_timeslot_map_t ts_map; + unsigned int hss_chan_id = 0; + unsigned int ret_val = 0; + unsigned int num_replenish = 0; + icp_hssacc_channel_voice_tx_idle_action_t idle_action = + ICP_HSSACC_VOICE_TX_IDLE_PATTERN; + + /*parameter check - check this as I need to use it */ + if (chan_add->channelId >= icp_hssacc_max_chans) { + printk(KERN_ERR "%s - ERROR: Channel Id out of range\n", + __FUNCTION__); + return -EINVAL; + } + + /*Check if that client chan number is free to use */ + status = + check_client_chan_num_is_available(client_id, chan_add->channelId); + if (status != ICP_STATUS_SUCCESS) { + /*This client channel number is already used by this client */ + printk(KERN_ERR "%s - ERROR: Channel not available \n", + __FUNCTION__); + return -EINVAL; + } + + /*Check that client has not reached limit for number of channels */ + status = + check_client_for_max_chans_per_client_limit(client_id); + if (status != ICP_STATUS_SUCCESS) { + /*This client has already opened the max number of channels */ + printk(KERN_ERR "%s - ERROR: Client has reached max channels " + "per file descriptor limit (%u) \n", + __FUNCTION__, + icp_voicedriver_max_chans_per_client); + return -EINVAL; + } + + /*Translate the Timeslot Map */ + timeslot_map_translate(&(chan_add->tsMap), &ts_map); + + /*Allocate the channel */ + status = + icp_HssAccChannelAllocate(&hss_chan_id, chan_add->portId, ts_map, + ICP_HSSACC_CHAN_TYPE_VOICE); + if (status != ICP_STATUS_SUCCESS) { + printk(KERN_ERR + "%s - ERROR: icp_HssAccChannelAllocate returned " + "error %d \n", __FUNCTION__, status); + return -EPERM; + } + + /*Configure the channel */ + status = + icp_HssAccChannelConfigure(hss_chan_id, + chan_add->channelDataInvert, + chan_add->channelBitEndianness, + chan_add->channelByteSwap, + ICP_FALSE, ICP_FALSE, ICP_FALSE); + if (status != ICP_STATUS_SUCCESS) { + printk(KERN_ERR + "%s - ERROR: icp_HssAccChannelConfigure returned " + "error %d \n", __FUNCTION__, status); + /*deallocate the hss acc channel */ + hssvoicedrv_deallocate_channel(hss_chan_id); + return -EPERM; + } + + /*Convert the idle action to hss acc api if required */ + if (chan_add->voiceIdleAction == 1) { + idle_action = ICP_HSSACC_VOICE_TX_IDLE_REPEAT_LAST_FRAME; + } + + /*Configure the voice service for this channel */ + status = + icp_HssAccChannelVoiceServiceConfigure(hss_chan_id, idle_action, + chan_add->voiceIdlePattern, + chan_add->voicePacketSize); + if (status != ICP_STATUS_SUCCESS) { + printk(KERN_ERR + "%s - ERROR: icp_HssAccChannelVoiceServiceConfigure " + "returned error %d \n", __FUNCTION__, status); + /*deallocate the hss acc channel */ + hssvoicedrv_deallocate_channel(hss_chan_id); + return -EPERM; + } + + if (spare_wheel_osal_buf == NULL) { + printk(KERN_ERR "%s - ERROR: Spare wheel buffer = NULL \n", + __FUNCTION__); + /*deallocate the hss acc channel */ + hssvoicedrv_deallocate_channel(hss_chan_id); + return -EPERM; + } + + /*Ensure there are enough rx buffers replenished */ + + /*while (no errors)AND + * (We haven't reached the max amount to replenish + * at one time) AND (We haven't reached the max + * amount of buffers that we want to replenish into + * the system)*/ + while ((status == ICP_STATUS_SUCCESS) && + (num_replenish < ICP_HSSVOICEDRV_MAX_RX_REPLENISH) && + (hssvoicedrv_current_bufs < ICP_HSSVOICEDRV_MAX_RX_REPLENISH)) { + + /*Try to replenish */ + status = + icp_HssAccRxFreeReplenish(ICP_HSSACC_CHAN_TYPE_VOICE, + spare_wheel_osal_buf); + + if (status == ICP_STATUS_SUCCESS) { + /*increment a counter as we don't want to + * replenish forever */ + num_replenish++; + /*we succesfully replenished, so allocate + * another osal buffer */ + ret_val = + get_osal_buf_with_data_buf(&spare_wheel_osal_buf, + ICP_HSSVOICEDRV_WB_SAMPLE_SIZE); + if (ret_val) { + /*I can't allocate memory ? this is not a + * critical error now. but easier to find + * if I return an error now */ + printk(KERN_ERR + "%s - ERROR: Could not allocate " + "memory \n", __FUNCTION__); + /*deallocate the hss acc channel */ + hssvoicedrv_deallocate_channel(hss_chan_id); + return -ENOMEM; + } + } + } + + /*We've now added a channel, that is in disabled state, + * update the data struct */ + chan_mapper[hss_chan_id].client_chan_id = chan_add->channelId; + chan_mapper[hss_chan_id].client_id = client_id; + chan_mapper[hss_chan_id].port_id = chan_add->portId; + chan_mapper[hss_chan_id].state = ICP_HSSVOICEDRV_DISABLED; + chan_mapper[hss_chan_id].src_bypass_enabled = FALSE; + chan_mapper[hss_chan_id].dest_bypass_enabled = FALSE; + chan_mapper[hss_chan_id].rx_data_ready = 0; + + /*Pass back the allocated hssacc channel id */ + *hss_channel_id = hss_chan_id; + return 0; + +} + +/*Deallocate a hss voice channel */ +void hssvoicedrv_deallocate_channel(unsigned int hss_chan_id) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + + status = icp_HssAccChannelDelete(hss_chan_id); + if (status != ICP_STATUS_SUCCESS) { + printk(KERN_ERR + "%s - ERROR: icp_HssAccChannelDelete returned " + "error %d \n", __FUNCTION__, status); + } +} + +/*Remove a hss voice channel */ +int hssvoicedrv_chan_remove(unsigned int client_id, unsigned int chan_id, + unsigned int *hss_channel_id) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + unsigned int hss_chan_id = 0; + IX_OSAL_MBUF *osal_buf = NULL; + IX_OSAL_MBUF *temp_buf = NULL; + IX_OSAL_MBUF *temp_next_pkt_in_chain_ptr = NULL; + IX_OSAL_MBUF *temp_next_buffer_in_pkt_ptr = NULL; + icp_status_t chan_exists = ICP_STATUS_SUCCESS; + + /*parameter check */ + if (chan_id >= icp_hssacc_max_chans) { + printk(KERN_ERR "%s - ERROR: Channel Id out of range \n", + __FUNCTION__); + return -EINVAL; + } + + /*get the hssacc channel id */ + status = + find_hss_chanid_to_this_client_and_chanid(client_id, chan_id, + &hss_chan_id); + if (status != ICP_STATUS_SUCCESS) { + /*we don't have a record of this channel, so we can't + * remove it */ + printk(KERN_ERR "%s - ERROR: Channel does not exist \n", + __FUNCTION__); + return -EINVAL; + } + + if (chan_mapper[hss_chan_id].state != ICP_HSSVOICEDRV_DISABLED) { + printk(KERN_ERR "%s - ERROR: Channel is not disabled \n", + __FUNCTION__); + return -EINVAL; + } + + /*Retrieve the buffer associated with the channel from HSS Acc */ + status = icp_HssAccAllBuffersRetrieve(hss_chan_id, &osal_buf); + if (status != ICP_STATUS_SUCCESS) { + printk(KERN_ERR + "%s - ERROR: icp_HssAccAllBuffersRetrieve returned " + "error %d \n", __FUNCTION__, status); + return -EPERM; + } + + /*Delete the channel */ + status = icp_HssAccChannelDelete(hss_chan_id); + if (status != ICP_STATUS_SUCCESS) { + printk(KERN_ERR + "%s - ERROR: icp_HssAccChannelDelete returned " + "error %d \n", __FUNCTION__, status); + return -EPERM; + } + + /*Set the status of this channel */ + chan_mapper[hss_chan_id].state = ICP_HSSVOICEDRV_UNUSED; + + /*now deal with the buffers that may have been returned by + * icp_HssAccAllBuffersRetrieve() */ + if (osal_buf != NULL) { + /*check to see if there are other channels */ + chan_exists = check_no_channels_exist(); + if (chan_exists) { + /*Other channels exist, we should try and replenish + * these buffers */ + do { + + temp_buf = osal_buf; + osal_buf = + IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR + (osal_buf); + + /*store the "next" fields in case + * replenish fails */ + temp_next_pkt_in_chain_ptr = + IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR + (temp_buf); + temp_next_buffer_in_pkt_ptr = + IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR + (temp_buf); + + /*reset the fields of the buffer we are going + * to try to replenish */ + IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(temp_buf) = + NULL; + IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(temp_buf) = + NULL; + IX_OSAL_MBUF_MLEN(temp_buf) = + IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(temp_buf); + + /*Try to replenish */ + status = + icp_HssAccRxFreeReplenish + (ICP_HSSACC_CHAN_TYPE_VOICE, temp_buf); + if (status != ICP_STATUS_SUCCESS) { + /*We couldn't replenish - set "next" + * fields to previous values and + * roll back the osal_buf to avoid + * losing this osal buffer*/ + IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR + (temp_buf) = + temp_next_pkt_in_chain_ptr; + IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR + (temp_buf) = + temp_next_buffer_in_pkt_ptr; + osal_buf = temp_buf; + } + /*we continue replenishing until all buffers + * are gone, or we can't replenish anymore */ + } while ((status == ICP_STATUS_SUCCESS) + && (osal_buf != NULL)); + } + + while (osal_buf != NULL) { + /*We have osal buffers either because we are the + * last channel and we shouldn't replenish, or we + * had more than we could/wanted to replenish. + * We must put these buffers. + */ + temp_buf = osal_buf; + osal_buf = IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(osal_buf); + put_osal_buf_with_data_buf(temp_buf); + } + } + + /*At this point we have no more osal buffers */ + *hss_channel_id = hss_chan_id; + + return 0; +} + +/*Enable a hss voice channel */ +int hssvoicedrv_chan_up(unsigned int client_id, unsigned int chan_id, + unsigned int blocking) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + unsigned int hss_chan_id = 0; + + /*parameter check */ + if (chan_id >= icp_hssacc_max_chans) { + printk(KERN_ERR "%s - ERROR: Channel Id out of range\n", + __FUNCTION__); + return -EINVAL; + } + + status = + find_hss_chanid_to_this_client_and_chanid(client_id, chan_id, + &hss_chan_id); + if (status != ICP_STATUS_SUCCESS) { + /*we don't have a record of this channel, so we can't + * change it's state */ + printk(KERN_ERR "%s - ERROR: Channel does not exist \n", + __FUNCTION__); + return -EINVAL; + } + + /*If this channel is blocking, we need to register callbacks */ + if (blocking) { + /*Register the callbacks for this channel now */ + status = + icp_HssAccChannelCallbacksRegister(hss_chan_id, + (icp_user_context_t) + hss_chan_id, + rx_callback, + txdone_callback); + if (status != ICP_STATUS_SUCCESS) { + /*We were not able to register the callbacks on + * a channel that has a blocking read. don't + * bring channel up as it will not operate correctly + */ + printk(KERN_ERR + "%s - ERROR: " + "icp_HssAccChannelCallbacksRegister " + "returned error %d \n", __FUNCTION__, status); + return -EPERM; + } + } + + /*Bring the channel up */ + status = icp_HssAccChannelUp(hss_chan_id); + if (status != ICP_STATUS_SUCCESS) { + printk(KERN_ERR + "%s - ERROR: icp_HssAccChannelUp returned error %d \n", + __FUNCTION__, status); + return -EPERM; + } + + /*change the state */ + chan_mapper[hss_chan_id].state = ICP_HSSVOICEDRV_ENABLED; + + return 0; +} + +/*Disable a hss voice channel */ +int hssvoicedrv_chan_down(unsigned int client_id, unsigned int chan_id) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + unsigned int hss_chan_id = 0; + + /*parameter check */ + if (chan_id >= icp_hssacc_max_chans) { + printk(KERN_ERR "%s - ERROR: Channel Id out of range\n", + __FUNCTION__); + return -EINVAL; + } + + status = + find_hss_chanid_to_this_client_and_chanid(client_id, chan_id, + &hss_chan_id); + if (status != ICP_STATUS_SUCCESS) { + /*we don't have a record of this channel, so we + * can't remove it */ + printk(KERN_ERR "%s - ERROR: Channel does not exist \n", + __FUNCTION__); + return -EINVAL; + } + + /*take the channel down */ + status = icp_HssAccChannelDown(hss_chan_id); + if (status != ICP_STATUS_SUCCESS) { + printk(KERN_ERR + "%s - ERROR: icp_HssAccChannelDown returned " + "error %d \n", __FUNCTION__, status); + return -EPERM; + } + chan_mapper[hss_chan_id].state = ICP_HSSVOICEDRV_DISABLED; + + return 0; +} + +/*Enable a hss voice channel bypass*/ +int hssvoicedrv_chan_bypass_enable(unsigned int client_id, + icp_hssvoicedrv_channelbypass_t * + chan_bypass_info, char *gct_table) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + unsigned int hss_src_chan_id = 0; + unsigned int hss_dest_chan_id = 0; + unsigned int max_num_gcts = 0; + unsigned int gct_number = 0; + unsigned int voice_bypass_id = 0; + unsigned int max_num_bypasses = 0; + unsigned int port_id = 0; + + /*parameter check - check these as I am going to use them */ + if ((chan_bypass_info->srcChannelId >= icp_hssacc_max_chans) + || (chan_bypass_info->destChannelId >= icp_hssacc_max_chans)) { + printk(KERN_ERR "%s - ERROR: Channel Id out of range \n", + __FUNCTION__); + return -EINVAL; + } + + /*convert the source and dest chan nums into hss chan id's */ + status = + find_hss_chanid_to_this_client_and_chanid(client_id, + chan_bypass_info-> + srcChannelId, + &hss_src_chan_id); + if (status != ICP_STATUS_SUCCESS) { + /*we don't have a record of this channel, so we can't + * set bypass on it */ + printk(KERN_ERR "%s - ERROR: Channel does not exist \n", + __FUNCTION__); + return -EINVAL; + } + status = + find_hss_chanid_to_this_client_and_chanid(client_id, + chan_bypass_info-> + destChannelId, + &hss_dest_chan_id); + if (status != ICP_STATUS_SUCCESS) { + /*we don't have a record of this channel, so we can't + * set bypass on it */ + printk(KERN_ERR "%s - ERROR: Channel does not exist \n", + __FUNCTION__); + return -EINVAL; + } + + if ((chan_mapper[hss_src_chan_id].src_bypass_enabled == TRUE) + || (chan_mapper[hss_dest_chan_id].dest_bypass_enabled == TRUE)) { + /*there is already voice bypass on these channels */ + printk(KERN_ERR + "%s - ERROR: Bypass already enabled on this channel \n", + __FUNCTION__); + return -EINVAL; + } + + /*check channels are on the same port */ + if (chan_mapper[hss_src_chan_id].port_id != + chan_mapper[hss_dest_chan_id].port_id) { + /*Cannot create bypass between channels on different ports */ + printk(KERN_ERR + "%s - ERROR: Cannot create bypass between channels " + "on different ports \n", __FUNCTION__); + return -EINVAL; + } + + max_num_gcts = icp_HssAccNumSupportedGCTsGet(); + for (gct_number = 0; gct_number < max_num_gcts; gct_number++) { + status = + icp_HssAccVoiceBypassGctDownload(gct_number, gct_table); + if (status == ICP_STATUS_SUCCESS) { + /*successfully downloaded this GCT - no need to + * try the next number */ + break; + } + } + /*Check to see if we successfully downloaded the GCT */ + if (gct_number == max_num_gcts) { + /*We couldn't download this GCT */ + printk(KERN_ERR "%s - ERROR: GCT could not be downloaded \n", + __FUNCTION__); + return -EPERM; + } + + /*Find what port these channels are associated with */ + port_id = chan_mapper[hss_src_chan_id].port_id; + + /*Enable bypass */ + /*Get the Max number of bypasses */ + max_num_bypasses = icp_HssAccNumSupportedVoiceBypassesGet(); + + for (voice_bypass_id = 0; voice_bypass_id < max_num_bypasses; + voice_bypass_id++) { + status = + icp_HssAccVoiceBypassEnable(port_id, voice_bypass_id, + gct_number, hss_src_chan_id, + hss_dest_chan_id); + if (status == ICP_STATUS_SUCCESS) { + /*successfully enabled bypass on these channels - + * no need to try the next bypass number */ + break; + } + } + if (voice_bypass_id == max_num_bypasses) { + printk(KERN_ERR + "%s - ERROR: Could not enable bypass on " + "these channels %d \n", __FUNCTION__, status); + return -EPERM; + } + + /*Update the data structures */ + chan_mapper[hss_src_chan_id].src_bypass_enabled = TRUE; + chan_mapper[hss_src_chan_id].dest_of_bypass = hss_dest_chan_id; + + chan_mapper[hss_src_chan_id].voice_bypass_id = voice_bypass_id; + + chan_mapper[hss_dest_chan_id].dest_bypass_enabled = TRUE; + chan_mapper[hss_dest_chan_id].src_of_bypass = hss_src_chan_id; + + return 0; +} + +/*Disable a hss voice channel bypass*/ +int hssvoicedrv_chan_bypass_disable(unsigned int client_id, + icp_hssvoicedrv_channelbypass_t * + chan_bypass_info) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + unsigned int hss_src_chan_id = 0; + unsigned int hss_dest_chan_id = 0; + + /*parameter check - check these as I am going to use them */ + if ((chan_bypass_info->srcChannelId >= icp_hssacc_max_chans) + || (chan_bypass_info->destChannelId >= icp_hssacc_max_chans)) { + printk(KERN_ERR "%s - ERROR: Channel Id out of range \n", + __FUNCTION__); + return -EINVAL; + } + + /*convert the source and dest chan nums into hss chan id's */ + status = + find_hss_chanid_to_this_client_and_chanid(client_id, + chan_bypass_info-> + srcChannelId, + &hss_src_chan_id); + if (status != ICP_STATUS_SUCCESS) { + /*we don't have a record of this channel, so we can't + * set bypass on it */ + printk(KERN_ERR "%s - ERROR: Channel does not exist \n", + __FUNCTION__); + return -EINVAL; + } + status = + find_hss_chanid_to_this_client_and_chanid(client_id, + chan_bypass_info-> + destChannelId, + &hss_dest_chan_id); + if (status != ICP_STATUS_SUCCESS) { + /*we don't have a record of this channel, so we can't + * set bypass on it */ + printk(KERN_ERR "%s - ERROR: Channel does not exist \n", + __FUNCTION__); + return -EINVAL; + } + if ((chan_mapper[hss_src_chan_id].src_bypass_enabled == FALSE) + || (chan_mapper[hss_dest_chan_id].dest_bypass_enabled == FALSE)) { + /*there is no voice bypass between these channels */ + printk(KERN_ERR + "%s - ERROR: Bypass not enabled on these channels \n", + __FUNCTION__); + return -EINVAL; + } + + if (((chan_mapper[hss_src_chan_id].dest_of_bypass) != hss_dest_chan_id) + || ((chan_mapper[hss_dest_chan_id].src_of_bypass) != + hss_src_chan_id)) { + /*there is no voice bypass between these channels */ + printk(KERN_ERR + "%s - ERROR: Bypass not enabled between these " + "two channels \n", __FUNCTION__); + return -EINVAL; + } + + status = + icp_HssAccVoiceBypassDisable(chan_mapper[hss_src_chan_id]. + voice_bypass_id); + if (status != ICP_STATUS_SUCCESS) { + /*There was a failure - report the error */ + printk(KERN_ERR + "%s - ERROR: icp_HssAccVoiceBypassDisable returned " + "error %d \n", __FUNCTION__, status); + return -EPERM; + } + /*reset the voiceBypassId's */ + chan_mapper[hss_src_chan_id].src_bypass_enabled = FALSE; + chan_mapper[hss_dest_chan_id].dest_bypass_enabled = FALSE; + + return 0; +} + +/*Display stats for a channel */ +void hssvoicedrv_display_channel_stat(unsigned int hss_chan_num) +{ + if (hss_chan_num < icp_hssacc_max_chans) { + printk(KERN_DEBUG + "%s - STATS: *** Displaying Stats for " + "HSS Channel: %d *** \n", __FUNCTION__, hss_chan_num); + switch (chan_mapper[hss_chan_num].state) { + case ICP_HSSVOICEDRV_UNUSED: + { + printk(KERN_DEBUG + "%s - STATS: HSS Channel %d not used " + "by the HSS Voice Driver \n", + __FUNCTION__, hss_chan_num); + break; + } + case ICP_HSSVOICEDRV_ENABLED: + case ICP_HSSVOICEDRV_DISABLED: + { + printk(KERN_DEBUG + "%s - STATS: HSS Channel: %d \n", + __FUNCTION__, hss_chan_num); + printk(KERN_DEBUG "%s - STATS: HSS Port: " + "%d \n", + __FUNCTION__, + chan_mapper[hss_chan_num].port_id); + printk(KERN_DEBUG "%s - STATS: Client: %d \n", + __FUNCTION__, + chan_mapper[hss_chan_num].client_id); + printk(KERN_DEBUG + "%s - STATS: Client Chan Id: %d \n", + __FUNCTION__, + chan_mapper[hss_chan_num]. + client_chan_id); + if (chan_mapper[hss_chan_num].state == + ICP_HSSVOICEDRV_ENABLED) { + printk(KERN_DEBUG + "%s - STATS: " + "State: ENABLED \n", + __FUNCTION__); + } else { + printk(KERN_DEBUG + "%s - STATS: " + "State: DISABLED \n", + __FUNCTION__); + } + + if (chan_mapper[hss_chan_num]. + src_bypass_enabled == FALSE) { + printk(KERN_DEBUG + "%s - STATS: Source Bypass " + "State: DISABLED \n", + __FUNCTION__); + } else { + printk(KERN_DEBUG + "%s - STATS: Source Bypass " + "State: ENABLED. Source of " + "bypass to HSS Chan %d \n", + __FUNCTION__, + chan_mapper[hss_chan_num]. + dest_of_bypass); + } + + if (chan_mapper[hss_chan_num]. + dest_bypass_enabled == FALSE) { + printk(KERN_DEBUG + "%s - STATS: Destination " + "Bypass State: DISABLED \n", + __FUNCTION__); + } else { + printk(KERN_DEBUG + "%s - STATS: Destination " + "Bypass State: ENABLED. " + "Destination of bypass from " + "HSS Chan %d \n", + __FUNCTION__, + chan_mapper[hss_chan_num]. + src_of_bypass); + } + printk(KERN_DEBUG + "%s - STATS: (only valid when for " + "blocking rx)Rx Data ready count " + "of: %d \n", + __FUNCTION__, + chan_mapper[hss_chan_num].rx_data_ready); + + break; + } + } + } else { + printk(KERN_DEBUG "%s - STATS: Invalid Channel number %d \n", + __FUNCTION__, hss_chan_num); + } +} + +/*Display stats for a client */ +void hssvoicedrv_display_client_stat(unsigned int client) +{ + if (client < icp_hssacc_max_clients) { + printk(KERN_DEBUG + "%s - STATS: *** Displaying Stats for " + "Client: %d *** \n", __FUNCTION__, client); + if (clients[client].enabled == FALSE) { + printk(KERN_DEBUG "%s - STATS: Client %d DISABLED \n", + __FUNCTION__, client); + } else { + printk(KERN_DEBUG "%s - STATS: Client %d ENABLED \n", + __FUNCTION__, client); + } + } else { + printk(KERN_DEBUG "%s - STATS: Invalid Client number %d \n", + __FUNCTION__, client); + } +} + +/*Display all stats */ +void hssvoicedrv_display_stats(void) +{ + unsigned int i = 0; + + printk(KERN_DEBUG "%s - STATS: Max Number HSS channels: %d \n", + __FUNCTION__, icp_hssacc_max_chans); + printk(KERN_DEBUG "%s - STATS: Max Number HSS Ports : %d \n", + __FUNCTION__, icp_hssacc_max_ports); + printk(KERN_DEBUG "%s - STATS: Max Number Clients: %d \n", + __FUNCTION__, icp_hssacc_max_clients); + printk(KERN_DEBUG + "%s - STATS: Printing stats for in use clients and " + "channels. \n", __FUNCTION__); + + for (i = 0; i < icp_hssacc_max_clients; i++) { + if (clients[i].enabled == TRUE) { + hssvoicedrv_display_client_stat(i); + } + } + + for (i = 0; i < icp_hssacc_max_chans; i++) { + if (chan_mapper[i].state != ICP_HSSVOICEDRV_UNUSED) { + hssvoicedrv_display_channel_stat(i); + } + } + +} + +/************************************************************************* +* +* IOCTLS to configure the HSS TDM I/O Unit ports and channels +* +*************************************************************************/ +int hssvoicedrv_ioctl(struct inode *inode, struct file *filep, + unsigned int cmd, unsigned long arg) +{ + icp_hssdrv_portup_t port_up; + int ret_val = 0; + unsigned int port_id = 0; + unsigned client_id = 0; + icp_hssvoicedrv_channeladd_t chan_add; + unsigned int hss_chan_id = 0; + unsigned chan_id = 0; + icp_hssvoicedrv_channelbypass_t chan_bypass_info; + char * gct_table = NULL; + char * aligned_gct_table = NULL; + unsigned int blocking = 0; + unsigned alignment_mask = 0; + + + /*Check for NULL pointers */ + if (filep == NULL) { + printk(KERN_ERR "%s - ERROR: NULL pointer parameter \n", + __FUNCTION__); + return -EINVAL; + } + + /*get the client id from the file descriptor */ + client_id = (unsigned int)filep->private_data; + + if (client_id >= icp_hssacc_max_clients) { + printk(KERN_ERR + "%s - ERROR: File structure parameter indicates " + "an invalid client \n", __FUNCTION__); + return -EINVAL; + } + + /*Get the control mutex */ + if (down_interruptible(&control_mutex)) { + printk(KERN_ERR "%s - ERROR: Unable to get control mutex \n", + __FUNCTION__); + return -ERESTARTSYS; + } + + switch (cmd) { + case ICP_HSSVOICEDRV_PORT_UP: + { + if ((void *)arg == NULL) { + printk(KERN_ERR + "%s - ERROR: ICP_HSSVOICEDRV_PORT_UP:" + "Argument is a NULL pointer \n", + __FUNCTION__); + + /*release the mutex */ + up(&control_mutex); + return -EINVAL; + } + /*copy the structure from user memory */ + + ret_val = + copy_from_user(&port_up, + (icp_hssdrv_portup_t *) arg, + sizeof(icp_hssdrv_portup_t)); + if (ret_val) { + printk(KERN_ERR + "%s - ERROR: ICP_HSSVOICEDRV_PORT_UP:" + "Unable to copy arguments from " + "User Space\n", __FUNCTION__); + ret_val = -EFAULT; + } else { + ret_val = hssvoicedrv_port_up(&port_up); + } + break; + } + + case ICP_HSSVOICEDRV_PORT_DOWN: + { + port_id = (unsigned int)arg; + + ret_val = hssvoicedrv_port_down(port_id); + break; + } + + case ICP_HSSVOICEDRV_CHAN_ADD: + { + if ((void *)arg == NULL) { + printk(KERN_ERR + "%s - ERROR: ICP_HSSVOICEDRV_CHAN_ADD:" + "Argument is a NULL pointer \n", + __FUNCTION__); + + /*release the mutex */ + up(&control_mutex); + return -EINVAL; + } + /*Get the argument */ + ret_val = copy_from_user(&chan_add, + (icp_hssvoicedrv_channeladd_t + *) arg, + sizeof + (icp_hssvoicedrv_channeladd_t)); + if (ret_val) { + printk(KERN_ERR + "%s - ERROR: ICP_HSSVOICEDRV_CHAN_ADD:" + "Unable to copy arguments from " + "User Space\n", __FUNCTION__); + ret_val = -EFAULT; + } else { + ret_val = + hssvoicedrv_chan_add(client_id, &chan_add, + &hss_chan_id); + } + break; + } + + case ICP_HSSVOICEDRV_CHAN_REMOVE: + { + /*Get the argument */ + chan_id = (unsigned int)arg; + + ret_val = + hssvoicedrv_chan_remove(client_id, chan_id, + &hss_chan_id); + if (ret_val == 0) { + /*wake up the rx wait queue + * for this channel - as it is not going + * to get any data now */ + wake_up_interruptible(&chan_mapper[hss_chan_id]. + rx_wait_queue); + } + break; + } + + case ICP_HSSVOICEDRV_CHAN_BYPASS_ENABLE: + { + if ((void *)arg == NULL) { + printk(KERN_ERR + "%s - ERROR: " + "ICP_HSSVOICEDRV_CHAN_BYPASS_ENABLE:" + "Argument is a NULL pointer \n", + __FUNCTION__); + /*release the mutex */ + up(&control_mutex); + return -EINVAL; + } + /*Get the argument */ + ret_val = copy_from_user(&chan_bypass_info, + (icp_hssvoicedrv_channelbypass_t + *) arg, + sizeof + (icp_hssvoicedrv_channelbypass_t)); + if (ret_val) { + printk(KERN_ERR + "%s - ERROR: " + "ICP_HSSVOICEDRV_CHAN_BYPASS_ENABLE:" + "Unable to copy arguments from " + "User Space\n", __FUNCTION__); + ret_val = -EFAULT; + } else { + if ((void *) + chan_bypass_info.gainControlTable == NULL) { + printk(KERN_ERR + "%s - ERROR: " + "ICP_HSSVOICEDRV_CHAN" + "_BYPASS_ENABLE:Gain Control " + "Table pointer is NULL \n", + __FUNCTION__); + /*release the mutex */ + up(&control_mutex); + return -EINVAL; + } + + + gct_table = kmalloc(GCT_SIZE+GCT_ALIGN_PADDING, + GFP_KERNEL); + if (!gct_table) + { + printk(KERN_ERR + "%s - ERROR: " + "ICP_HSSVOICEDRV_CHAN" + "_BYPASS_ENABLE:Gain Control " + "Table failed allocation\n", + __FUNCTION__); + /*release the mutex */ + up(&control_mutex); + return -EINVAL; + } + aligned_gct_table = (char*)((unsigned)gct_table + GCT_ALIGN_PADDING); + alignment_mask = GCT_ALIGN_MASK; + aligned_gct_table = + (char*)(((unsigned)aligned_gct_table) & + alignment_mask); + + /*Copy the gain control table */ + ret_val = + copy_from_user(aligned_gct_table, (unsigned char *) + chan_bypass_info. + gainControlTable, GCT_SIZE); + if (ret_val) { + printk(KERN_ERR + "%s - ERROR: " + "ICP_HSSVOICEDRV_CHAN_BYPASS_ENABLE:" + "Unable to copy arguments from " + "User Space\n", __FUNCTION__); + ret_val = -EFAULT; + } else { + ret_val = + hssvoicedrv_chan_bypass_enable + (client_id, &chan_bypass_info, + aligned_gct_table); + } + kfree(gct_table); + } + break; + } + + case ICP_HSSVOICEDRV_CHAN_BYPASS_DISABLE: + { + + if ((void *)arg == NULL) { + printk(KERN_ERR + "%s - ERROR: " + "ICP_HSSVOICEDRV_CHAN_BYPASS_DISABLE:" + "Argument is a NULL pointer \n", + __FUNCTION__); + /*release the mutex */ + up(&control_mutex); + return -EINVAL; + } + + /*Get the argument (the GCT is unused + * for bypass disable) */ + ret_val = copy_from_user(&chan_bypass_info, + (icp_hssvoicedrv_channelbypass_t + *) + arg, + sizeof + (icp_hssvoicedrv_channelbypass_t)); + if (ret_val) { + printk(KERN_ERR + "%s - ERROR: " + "ICP_HSSVOICEDRV_CHAN_BYPASS_DISABLE:" + "Unable to copy arguments from " + "User Space\n", __FUNCTION__); + ret_val = -EFAULT; + } else { + ret_val = + hssvoicedrv_chan_bypass_disable(client_id, + &chan_bypass_info); + } + break; + } + case ICP_HSSVOICEDRV_CHAN_UP: + { + + /*Get the argument */ + chan_id = (unsigned int)arg; + + if (filep->f_flags & O_NONBLOCK) { + blocking = 0; + } else { + blocking = 1; + } + + ret_val = + hssvoicedrv_chan_up(client_id, chan_id, blocking); + + break; + } + + case ICP_HSSVOICEDRV_CHAN_DOWN: + { + /*Get the argument */ + chan_id = (unsigned int)arg; + + ret_val = hssvoicedrv_chan_down(client_id, chan_id); + if (ret_val == 0) { + /*wake up the rx wait queue for this + * channel - as it is not going to get any + * data now */ + wake_up_interruptible(&chan_mapper[hss_chan_id]. + rx_wait_queue); + } + break; + } + case ICP_HSSVOICEDRV_STATS: + { + hssvoicedrv_display_stats(); + break; + } + default: + { + ret_val = -ENOSYS; + break; + } + } + /*release the mutex */ + up(&control_mutex); + + return ret_val; +} + +/*This function extracts the data buffer atached to an osal buffer*/ +void read_data_buff_from_osalbuf(IX_OSAL_MBUF * osal_buf, unsigned int *len, + char **data_buf) +{ + + /*get the data_buf complete with headers */ + *data_buf = IX_OSAL_MBUF_MDATA(osal_buf); + /*extract the length */ + *len = IX_OSAL_MBUF_MLEN(osal_buf); + + return; +} + +/* This function allocates an OSAL buffer, and a data buffer of specified + * length. It also points the OSAL buffer's data buf ptr to the data buffer + * and updates relevant fields in the OSAL buffer. + */ +int get_osal_buf_with_data_buf(IX_OSAL_MBUF ** osal_buf, + unsigned int data_buf_length) +{ + IX_OSAL_MBUF *temp_osal_buf; + char *data_buf; + + /*allocate the osal buf */ + temp_osal_buf = kmalloc(sizeof(IX_OSAL_MBUF), GFP_KERNEL); + if (!temp_osal_buf) { + return 1; + } + + /*allocate the data buf */ + data_buf = kmalloc(data_buf_length, GFP_KERNEL); + if (!data_buf) { + /*deallocate the osal buffer */ + kfree(temp_osal_buf); + return 1; + } + + /*Fill in the allocated size of the data buf */ + IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(temp_osal_buf) = data_buf_length; + IX_OSAL_MBUF_MLEN(temp_osal_buf) = data_buf_length; + + IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(temp_osal_buf) = NULL; + IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(temp_osal_buf) = NULL; + + /*Attach the data buf to the OSAL buf */ + IX_OSAL_MBUF_MDATA(temp_osal_buf) = data_buf; + + *osal_buf = temp_osal_buf; + /*Increment the current total of buffers allocated by + * this driver in the system */ + hssvoicedrv_current_bufs++; + return 0; +} + +/* This function deallocates and frees an OSAL buffer, and any data + * buffer that is pointed to by the OSAL buffer's data buf ptr. + */ +void put_osal_buf_with_data_buf(IX_OSAL_MBUF * osal_buf) +{ + char *data_buf = NULL; + + /*get and free the data buf */ + if (osal_buf != NULL) { + data_buf = IX_OSAL_MBUF_MDATA(osal_buf); + if (data_buf != NULL) { + kfree(data_buf); + } + /*free the osal buf */ + kfree(osal_buf); + } + /*Reset the pointer */ + osal_buf = NULL; + /*Decrement the current total of buffers allocated by + * this driver in the system */ + hssvoicedrv_current_bufs--; + return; +} + +/************************************************************************* +* +* Write voice payload for channels configured for this file out to the HSS +* TDM I/O Unit for tranmission +* +*************************************************************************/ +ssize_t hssvoicedrv_write(struct file * filp, const char __user * buffer, + size_t size, loff_t * offset) +{ + + ssize_t buffer_pos = 0; + unsigned int pkt_length = 0; + IX_OSAL_MBUF *osal_buf_ptr = NULL; + signed int status = 0; + unsigned int client_id = 0; + unsigned int client_chan_id = 0; + unsigned int hss_chan_num = 0; + unsigned int ret_val = 0; + u8 header[ICP_HSSVOICEDRV_HEADER_SIZE]; + + + /**********PARAMETER CHECKS**********/ + /*check for NULL pointers */ + if ((filp == NULL) || (buffer == NULL)) { + printk(KERN_ERR "%s - ERROR: NULL pointer parameter \n", + __FUNCTION__); + return -EINVAL; + } + + /*check user space buffer is ok to access */ + /* check that user buffer is readable here, to avoid possibly checking + * multiple times in copy_from_user() calls*/ + status = access_ok(VERIFY_READ, (void __user *)buffer, size); + if (status < 1) { + /*There is a problem with accessing the user space memory */ + printk(KERN_ERR + "%s - ERROR: Unable to access user space memory \n", + __FUNCTION__); + return -EFAULT; + } + + /**********END PARAMETER CHECKS**********/ + + /*get the client id from the file descriptor */ + client_id = (unsigned int)filp->private_data; + + /**********LOOP THROUGH THE BUFFER UNTIL IT IS EMPTY**********/ + /*Process each active channel while there is enough user + * data for a minimum transmit */ + while ((buffer_pos + ICP_HSSVOICEDRV_MIN_CLIENT_TX_PACKET_SIZE) <= + size) { + /**********GET AND CHECK THE HEADERS**********/ + /*extract the channel number for the current packet */ + ret_val = + __copy_from_user(&header, &(buffer[buffer_pos]), + ICP_HSSVOICEDRV_HEADER_SIZE); + if (ret_val) { + /*non-recoverable return fail */ + printk(KERN_ERR + "%s - ERROR: Unable to copy data from " + "user space buffer \n", __FUNCTION__); + return buffer_pos; + } + + pkt_length = + cpu_to_le16(((header[PACKET_LEN_LSB] | + (header[PACKET_LEN_MSB] << SIZE_OF_BYTE)) & + U16_BIT_MASK)); + client_chan_id = + cpu_to_le16(((header[CLIENT_CHAN_LSB] | + (header[CLIENT_CHAN_MSB] << SIZE_OF_BYTE)) & + U16_BIT_MASK)); + + /*Check the length is ok */ + if ((pkt_length > ICP_HSSVOICEDRV_WB_SAMPLE_SIZE) + || (pkt_length == 0)) { + /*there is an error in the length */ + printk(KERN_ERR "%s - ERROR: Invalid Data Length \n", + __FUNCTION__); + return buffer_pos; + } + /**********END GET AND CHECK THE HEADERS**********/ + + /**********CHECK IT'S VALID TO SEND ON THIS CHANNEL**********/ + /*Get the associated hss channel for this client and + * client channel id */ + status = + find_hss_chanid_to_this_client_and_chanid(client_id, + client_chan_id, + &hss_chan_num); + if (status != ICP_STATUS_SUCCESS) { + /*there is no record of this client having + * this channel */ + printk(KERN_ERR + "%s - ERROR: Invalid client or " + "channel number \n", __FUNCTION__); + return buffer_pos; + } + /**********END CHECK IT'S VALID TO SEND ON THIS CHANNEL**********/ + + /**********GET AN OSAL BUF TO USE FOR TRANSMIT**********/ + /*Try to retrieve a used osal buf with attached + * data buf from the hss acc for this channel */ + status = icp_HssAccTxDoneRetrieve(hss_chan_num, &osal_buf_ptr); + if (status != ICP_STATUS_SUCCESS) { + /*only normal return fail value is an underflow */ + if (status == ICP_STATUS_UNDERFLOW) { + /*As there are no used osal buf available, + * get an osal buffer */ + if (get_osal_buf_with_data_buf + (&osal_buf_ptr, + ICP_HSSVOICEDRV_WB_SAMPLE_SIZE)) { + /*Cannot get an osal buf to complete + * this transmission */ + printk(KERN_ERR + "%s - ERROR: Could not " + "allocate memory \n", + __FUNCTION__); + return buffer_pos; + } + + } else { + /*non-recoverable return fail */ + printk(KERN_ERR + "%s - ERROR: icp_HssAccTxDoneRetrieve " + "returned error %d for channel %d \n", + __FUNCTION__, status, hss_chan_num); + return buffer_pos; + } + } + /*We have an OSAL buffer with an attached data buf + * to use for transmit */ + /**********END GET AN OSAL BUF TO USE FOR TRANSMIT**********/ + + /**********TRANSMIT THE BUFFER**********/ + /*copy the user space buffer into the osal buf's data buf */ + ret_val = + __copy_from_user(IX_OSAL_MBUF_MDATA(osal_buf_ptr), + &(buffer + [buffer_pos + + ICP_HSSVOICEDRV_HEADER_SIZE]), + pkt_length); + + if (ret_val) { + /*non-recoverable return fail */ + printk(KERN_ERR + "%s - ERROR: Unable to copy data from " + "user space buffer \n", __FUNCTION__); + put_osal_buf_with_data_buf(osal_buf_ptr); + return buffer_pos; + } + /*set the length in the osal buf */ + IX_OSAL_MBUF_MLEN(osal_buf_ptr) = pkt_length; + IX_OSAL_MBUF_PKT_LEN(osal_buf_ptr) = pkt_length; + + status = icp_HssAccTransmit(hss_chan_num, osal_buf_ptr); + if (status != ICP_STATUS_SUCCESS) { + /*If we cannot transmit on this channel, we must + * return to the client as for multiple channel + * writes, the write() interface does not allow + * us to indicate to the user which channel + * failed + */ + if (status != ICP_STATUS_OVERFLOW) { + printk(KERN_ERR + "%s - ERROR: icp_HssAccTransmit returned " + "error %d for channel %d \n", + __FUNCTION__, status, hss_chan_num); + } + put_osal_buf_with_data_buf(osal_buf_ptr); + return buffer_pos; + } + + /*update the buffer_pos */ + buffer_pos += pkt_length + ICP_HSSVOICEDRV_HEADER_SIZE; + /**********END TRANSMIT THE BUFFER**********/ + } + /**********END LOOP THROUGH THE BUFFER UNTIL IT IS EMPTY**********/ + + return buffer_pos; +} + +/*Receive callback */ +void rx_callback(icp_user_context_t userContext) +{ + unsigned int hss_chan_id = 0; + + /*cast the userContext to the hss channel id */ + hss_chan_id = (unsigned int)userContext; + + /*Check that the hss chan id is valid */ + if (hss_chan_id < icp_hssacc_max_chans) { + /*increment because there is more data available */ + chan_mapper[hss_chan_id].rx_data_ready++; + + /*wake up the wait queue */ + wake_up_interruptible(&chan_mapper[hss_chan_id].rx_wait_queue); + } + return; +} + +/* dummy callback for txdone. We take no action upon recieving a txdone + * callback because we will service the hss acc txdone queues in the + * context of a write()*/ +void txdone_callback(icp_user_context_t userContext) +{ + return; +} + +/*Receive and report port error callbacks*/ +void hssvoicedrv_port_error_callback(icp_user_context_t user_context, + icp_hssacc_port_error_t error_type) +{ + switch (error_type) { + case ICP_HSSACC_PORT_ERROR_TX_LOS: + printk(KERN_ERR "%s - Port error for port %u :" + " Transmit loss of sync\n", + __FUNCTION__, + (unsigned) user_context); + break; + case ICP_HSSACC_PORT_ERROR_RX_LOS: + printk(KERN_ERR "%s - Port error for port %u :" + " Receive loss of sync\n", + __FUNCTION__, + (unsigned) user_context); + break; + case ICP_HSSACC_PORT_ERROR_TX_UNDERFLOW: + printk(KERN_ERR "%s - Port error for port %u :" + " Transmit underflow\n", + __FUNCTION__, + (unsigned) user_context); + break; + case ICP_HSSACC_PORT_ERROR_RX_OVERFLOW: + printk(KERN_ERR "%s - Port error for port %u :" + " Receive overflow\n", + __FUNCTION__, + (unsigned) user_context); + break; + case ICP_HSSACC_PORT_ERROR_TX_PARITY: + printk(KERN_ERR "%s - Port error for port %u :" + " Tx Parity Error\n", + __FUNCTION__, + (unsigned) user_context); + break; + case ICP_HSSACC_PORT_ERROR_RX_PARITY: + printk(KERN_ERR "%s - Port error for port %u :" + " Rx Parity Error\n", + __FUNCTION__, + (unsigned) user_context); + break; + default: + printk(KERN_ERR "%s - Port error for port %u :" + " Unidentified error %u\n", + __FUNCTION__, + (unsigned) user_context, + error_type); + break; + } +} +/*Receive and report general error callbacks*/ +void hssvoicedrv_error_callback(icp_user_context_t user_context, + icp_hssacc_error_t error_type) +{ + switch (error_type) { + case ICP_HSSACC_ERROR_RX_OVERFLOW: + printk(KERN_ERR "%s - Error: Receive Queue Overflow " + "reported\n", + __FUNCTION__); + break; + case ICP_HSSACC_ERROR_RX_FREE_UNDERFLOW: + printk(KERN_ERR "%s - Error: Receive Free Queue Underflow " + " reported\n", + __FUNCTION__); + break; + case ICP_HSSACC_ERROR_MESSAGE_FIFO_OVERFLOW: + printk(KERN_ERR "%s - Error: Messaging FIFO Overflow " + "reported\n", + __FUNCTION__); + break; + default: + printk(KERN_ERR "%s - Unidentified Error %u\n", + __FUNCTION__, + error_type); + } +} + +/************************************************************************* +* +* Poll the voice driver to see if calling the read() and/or write() methods +* are valid to call and will not block. +* +*************************************************************************/ +unsigned int hssvoicedrv_poll(struct file *filp, poll_table * wait) +{ + unsigned int mask = 0; + unsigned int status = 0, hss_chan_num = 0; + unsigned int client_id = 0; + + /**********PARAMETER CHECKS**********/ + /*check that there is a client id embedded in the private data */ + if (filp == NULL) { + printk(KERN_ERR "%s - ERROR: NULL pointer parameter \n", + __FUNCTION__); + return mask; + } + + /*get the client id from the file descriptor */ + client_id = (unsigned int)filp->private_data; + + if (client_id >= icp_hssacc_max_clients) { + printk(KERN_ERR "%s - ERROR: invalid client parameter \n", + __FUNCTION__); + return mask; + } + /**********END PARAMETER CHECKS**********/ + + /**********VALID TO POLL CHECKS**********/ + /*Get the read mutex for this client */ + if (down_interruptible(&(clients[client_id].client_read_mutex))) { + printk(KERN_ERR "%s - ERROR: Unable to get read mutex \n", + __FUNCTION__); + return -ERESTARTSYS; + } + + /*should only be polling if we are doing blocking reads - + * for non-blocking, read() should be used directly + */ + if (filp->f_flags & O_NONBLOCK) { + /*client is non-blocking - shouldn't be using poll */ + printk(KERN_ERR + "%s - ERROR: Invalid to use Poll in " + "Non-Blocking mode \n", __FUNCTION__); + /*release the mutex */ + up(&(clients[client_id].client_read_mutex)); + return mask; + } + /**********END VALID TO POLL CHECK**********/ + + /**********CHECK THE STATUS OF EACH CHANNEL**********/ + for (hss_chan_num = 0; hss_chan_num < icp_hssacc_max_chans; + hss_chan_num++) { + if (chan_mapper[hss_chan_num].client_id == client_id) { + if (chan_mapper[hss_chan_num].state == + ICP_HSSVOICEDRV_ENABLED) { + /* Set status to indicate that there was at + * least one enabled channel for this client*/ + status = 1; + if (chan_mapper[hss_chan_num].rx_data_ready <= + 0) { + /* There is no data ready for this + * channel - we must wait for it, so + * add the wait_queue for this + * channel to the kernel table of + * wait queues. NB *This function* + * does not block here, it returns + * to the kernel and the kernel checks + * if the wait_queues on the table + * and sleeps until one of them is + * woken up, it then calls this + * function again.*/ + + /* NB As documented in the API, the + * client must use a timeout on the + * poll to allow for race conditions */ + + /*add the wait queue to the wait + * queue table */ + poll_wait(filp, + &(chan_mapper[hss_chan_num]. + rx_wait_queue), wait); + break; + } + } + } + } + /**********END CHECK THE STATUS OF EACH CHANNEL**********/ + + /**********SET THE MASK**********/ + if (status == 1) { + /*There is at least one enabled channel for this client */ + /*The device will never block on a write() */ + mask |= POLLOUT | POLLWRNORM; + + if (hss_chan_num == icp_hssacc_max_chans) { + /* Nothing has been added to the wait queue, + * therefore read() for this client will not block */ + mask |= POLLIN | POLLRDNORM; + } + } + /**********END SET THE MASK**********/ + + up(&(clients[client_id].client_read_mutex)); + + return mask; +} + +inline signed int wait_for_rx_data(unsigned int client_id, + unsigned int hss_chan_id) +{ + unsigned int waits = 0; + + /**********BLOCKING MODE - WAIT FOR DATA**********/ + do { + + /* blocking mode so wait until there is data to be read, + * but we also must guard in case a channel that is being + * waited on gets disabled/removed. + * + * If there is no data ready for a channel after 10ms we + * will force a wakeup and check that the channel is still + * enabled. If enabled, keep waiting for data on it. + * If disabled, skip it and continue trying to process any + * remaining enabled channels. + */ + if (wait_event_interruptible_timeout + ((chan_mapper[hss_chan_id].rx_wait_queue), + ((chan_mapper[hss_chan_id].rx_data_ready) > 0), + (BLOCKING_READ_WAIT_TIME)) < 0) { + /*sleep was interrupted by a signal but the + * condition is not true - the file system will + * handle this */ + printk(KERN_ERR + "%s - ERROR: A signal interrupted the " + "rx wait queue \n", __FUNCTION__); + return -ERESTARTSYS; + } + + waits++; + if(waits == 2000) + { + printk(KERN_ERR + "%s - ERROR: Waited 2 Secs for data on " + "enabled channel %d. \n", __FUNCTION__, + hss_chan_id); + return -EPERM; + } + + /*We will sleep again if there is no data, the client has + * not deleted the channel and the channel is enabled */ + } while ((chan_mapper[hss_chan_id].state == ICP_HSSVOICEDRV_ENABLED && + chan_mapper[hss_chan_id].client_id == client_id) && + (chan_mapper[hss_chan_id].rx_data_ready <= 0)); + + /*if there is no data indication, there is no reason to attempt to + * receive data from hss acc for this channel */ + if (chan_mapper[hss_chan_id].rx_data_ready <= 0) { + /*go to the next channel */ + return 1; + } + /**********END OF BLOCKING MODE - WAIT FOR DATA**********/ + return 0; +} + +/************************************************************************* +* +* Read voice payload for channels configured for this file from the HSS +* TDM I/O Unit and pass to the HSS Voice Driver client +* +*************************************************************************/ +ssize_t hssvoicedrv_read(struct file * filp, char __user * buffer, size_t size, + loff_t * offset) +{ + ssize_t buffer_pos = 0; + IX_OSAL_MBUF *osal_buf_ptr = NULL; + char data_header[ICP_HSSVOICEDRV_HEADER_SIZE]; + unsigned int rx_len = 0; + unsigned int client_id = 0; + int ret_val = 0; + unsigned int status = 0; + unsigned int i = 0; + unsigned int hss_chan_id = 0; + unsigned int client_chan_id = 0; + char *data_buf_ptr = NULL; + + + /**********PARAMETER CHECKS**********/ + /*Check for NULL pointers */ + if ((filp == NULL) || (buffer == NULL)) { + printk(KERN_ERR "%s - ERROR: NULL pointer parameter \n", + __FUNCTION__); + return -EINVAL; + } + + /*check size is ok */ + if (size < ICP_HSSVOICEDRV_MIN_CLIENT_RX_PACKET_SIZE) { + /*Buffer is too short for data */ + printk(KERN_ERR "%s - ERROR: User Space buffer too small \n", + __FUNCTION__); + return -EINVAL; + } + + client_id = (unsigned int)filp->private_data; + + /*Check that this client Id is within range */ + if (client_id >= icp_hssacc_max_clients) { + printk(KERN_ERR "%s - ERROR: Invalid File Structure\n", + __FUNCTION__); + return -EINVAL; + } + /*check user space buffer is ok to access */ + ret_val = access_ok(VERIFY_WRITE, (void __user *)buffer, size); + if (ret_val < 1) { + /*There is a problem with accessing the user space memory */ + printk(KERN_ERR + "%s - ERROR: Unable to access user space memory \n", + __FUNCTION__); + return -EFAULT; + } + /**********END PARAMETER CHECKS**********/ + + /**********SETUP FOR THE READ**********/ + /*Get the read mutex for this client */ + if (down_interruptible(&(clients[client_id].client_read_mutex))) { + printk(KERN_ERR "%s - ERROR: Unable to get read mutex \n", + __FUNCTION__); + return -ERESTARTSYS; + } + /**********END SETUP FOR THE READ**********/ + + /**********PROCESS THE READ FOR EACH CHANNEL**********/ + /*Process each active channel */ + for (i = 0; i < icp_hssacc_max_chans; i++) { + /**********FIND A VALID CHANNEL TO READ ON**********/ + if ((chan_mapper[i].client_id != client_id) + || (chan_mapper[i].state != ICP_HSSVOICEDRV_ENABLED)) { + /*We should not get data from this channel because it + * is not associated with the current client or is + * not enabled*/ + continue; + } + + /*store the hss_chan_id number */ + hss_chan_id = i; + /*store the client chan id number */ + client_chan_id = (chan_mapper[hss_chan_id].client_chan_id); + /**********END FIND A VALID CHANNEL TO READ ON**********/ + + /*Check if this is a blocking or non-blocking read */ + if (!(filp->f_flags & O_NONBLOCK)) { + /**********BLOCKING MODE - WAIT FOR DATA**********/ + ret_val = wait_for_rx_data(client_id, hss_chan_id); + if (ret_val != 0) { + if (ret_val > 0) { + /*no data available on this channel, + * likely due to a state change - + * move to next channel */ + continue; + } else { + /* an error condition has occurred */ + up(& + (clients[client_id]. + client_read_mutex)); + return ret_val; + } + } + /**********END OF BLOCKING MODE - WAIT FOR DATA**********/ + } + + /*end if (blocking) */ + /**********TRY TO RETRIEVE DATA FROM HSSACC**********/ + /*try and retreive from HSS Acc Lib */ + status = icp_HssAccReceive(hss_chan_id, &osal_buf_ptr); + + if ((status != ICP_STATUS_SUCCESS) || (osal_buf_ptr == NULL)) { + /* We couldn't get data for this channel + * (blocking: an error has occured. + * non-blocking: there is no data available, or an + * error has occured) at this point we don't wait + * for data - move to the next channel*/ + continue; + } + + /*decrement the rx_ready flag */ + chan_mapper[hss_chan_id].rx_data_ready--; + + /**********END TRY TO RETRIEVE DATA FROM HSSACC**********/ + + /**********PROCESS THE OSAL BUF**********/ + /*At this point we have osal buf containing data - hooray! */ + /*Extract the voice samples */ + read_data_buff_from_osalbuf(osal_buf_ptr, &rx_len, + &data_buf_ptr); + + /**********PROCESS THE HEADERS**********/ + ret_val = + hssvoicedrv_header_create((char *)&data_header, rx_len, + client_chan_id, + (size - buffer_pos)); + if (ret_val != ICP_STATUS_SUCCESS) { + /*Couldn't process the headers for this channel - + * skip to the next channel */ + printk(KERN_ERR + "%s - ERROR: Unable to create headers for " + "client_chan_id %u \n", + __FUNCTION__, client_chan_id); + hssvoicedrv_cleanup_rx_osalbuf(osal_buf_ptr); + continue; + } + /**********END PROCESS THE HEADERS**********/ + + /**********COPY TO USER SPACE**********/ + + /*copy into the user buffer */ + ret_val = + __copy_to_user(buffer + buffer_pos, &data_header, + ICP_HSSVOICEDRV_HEADER_SIZE); + if (ret_val) { + /*could not copy the header into the + * user space buffer - skip to the next channel */ + printk(KERN_ERR + "%s - ERROR: Unable to copy data to " + "user space buffer \n", __FUNCTION__); + hssvoicedrv_cleanup_rx_osalbuf(osal_buf_ptr); + continue; + } + /*move on the buffer position */ + buffer_pos += ICP_HSSVOICEDRV_HEADER_SIZE; + + /*copy the data buffer into the user buffer */ + + /*use __copy_to_user() because we have already validated + * that the user space memory location is valid */ + ret_val = + __copy_to_user(buffer + buffer_pos, data_buf_ptr, rx_len); + if (ret_val) { + /*could not copy the data into the user space + * buffer - skip to the next channel */ + /*We need to rollback the buffer position + * here in order to remove the header for this + * channel, otherwise we will corrupt the returned + * data. + */ + buffer_pos -= ICP_HSSVOICEDRV_HEADER_SIZE; + printk(KERN_ERR + "%s - ERROR: Unable to copy data to " + "user space\n", __FUNCTION__); + hssvoicedrv_cleanup_rx_osalbuf(osal_buf_ptr); + continue; + } + + /*move the buffer position */ + buffer_pos += rx_len; + /**********END COPY TO USER SPACE**********/ + + /* + * We have copied the data out of the osal buf, + * so now clean it up (replenish the osal buf + * back to hss acc or deallocate) + */ + hssvoicedrv_cleanup_rx_osalbuf(osal_buf_ptr); + + /**********END PROCESS THE OSAL BUF**********/ + + } /*end of for loop */ + /**********END PROCESS THE READ FOR EACH CHANNEL**********/ + + /*Release the read mutex for this client - have to wait until + * all channels have been read */ + up(&(clients[client_id].client_read_mutex)); + + /*set the offset and return the amount of bytes read */ + return buffer_pos; +} + +module_init(hssvoicedrv_init_module); +module_exit(hssvoicedrv_cleanup_module); diff --git a/Acceleration/drivers/icp_tdm/hss_voice_driver/icp_hssvoicedrv_p.h b/Acceleration/drivers/icp_tdm/hss_voice_driver/icp_hssvoicedrv_p.h new file mode 100644 index 0000000..98cb4bc --- /dev/null +++ b/Acceleration/drivers/icp_tdm/hss_voice_driver/icp_hssvoicedrv_p.h @@ -0,0 +1,92 @@ +/****************************************************************************** + * @file icp_hssvoicedrv_p.h + * + * @description Content of this file provides the common header definitions + * used by the Analog FXO FXS Driver. + * + * @ingroup icp_hssvoicedrv + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + *****************************************************************************/ +#ifndef ICP_HSSVOICEDRV_P_H_ +#define ICP_HSSVOICEDRV_P_H_ + + + +/****************************************************************************** + * INCLUDE FILES + *****************************************************************************/ +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/fs.h> +#include <linux/poll.h> +#include <linux/cdev.h> +#include <linux/file.h> // fput() +#include <asm/uaccess.h> // copy_to/from_user +#include <linux/semaphore.h> // mutexes + +/*#define "icp.h"*/ +#include "icp_hssvoicedrv.h" + + +#endif /*ICP_HSSVOICEDRV_P_H_*/ diff --git a/Acceleration/drivers/icp_tdm/hss_voice_driver/linux_2.6_kernel_space.mk b/Acceleration/drivers/icp_tdm/hss_voice_driver/linux_2.6_kernel_space.mk new file mode 100644 index 0000000..7c1b8a2 --- /dev/null +++ b/Acceleration/drivers/icp_tdm/hss_voice_driver/linux_2.6_kernel_space.mk @@ -0,0 +1,77 @@ +################### +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# +################### + +#specific include directories in kernel space +#INCLUDES+= -I$(src)/common_platform/linux/include + +INCLUDES+= -I $(ICP_OSAL_DIR)/platforms/EP805XX/include \ + -I $(ICP_OSAL_DIR)/platforms/EP805XX/os/linux/include \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/core \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules/ddk \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules/ioMem \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules/bufferMgt + +#Extra Flags Specific in kernel space e.g. include path or debug flags etc. e.g to add an include path EXTRA_CFLAGS += -I$(src)/../include +EXTRA_CFLAGS += $(INCLUDES) -DEP805XX -D__ep805xx -DTOLAPAI -D__tolapai -DIX_HW_COHERENT_MEMORY=1 +EXTRA_LDFLAGS +=-whole-archive + +KBUILD_EXTRA_SYMBOLS+= $(ICP_ROOT)/Acceleration/library/icp_telephony/Module.symvers diff --git a/Acceleration/drivers/icp_tdm/include/icp_hssdrv_common.h b/Acceleration/drivers/icp_tdm/include/icp_hssdrv_common.h new file mode 100644 index 0000000..120e6b8 --- /dev/null +++ b/Acceleration/drivers/icp_tdm/include/icp_hssdrv_common.h @@ -0,0 +1,466 @@ +/****************************************************************************** + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + *****************************************************************************/ + +/* + ***************************************************************************** + * Doxygen group definitions + ****************************************************************************/ + +/** + ******************************************************************************* + * @defgroup icp_hssdrv Definitions common to the HSS voice and HSS data drivers. + * + * @purpose + * + * Common defines and structures used by voice and data drivers + * including the hss port configuration and the channel timeslot + * configuration. + * + ******************************************************************************/ + +#ifndef ICP_HSSDRV_COMMON_H +#define ICP_HSSDRV_COMMON_H + +#include <asm/types.h> + +#include "icp_hssdrv.h" +#include "icp_hssacc.h" + + +inline void port_config_create (unsigned int port_config, + icp_hssdrv_loopback_t loopbackMode, + icp_hssacc_port_config_params_t *configParams) +{ + + + switch (loopbackMode) + { + case ICP_HSSDRV_EXTERNAL_LOOPBACK: + { + + configParams->clkSpeed = ICP_HSSACC_CLK_SPEED_2048KHZ; + configParams->txPortConfig.frmSyncType = ICP_HSSACC_FRM_PULSE_SYNC_ACTIVE_LOW; + configParams->txPortConfig.frmSyncIO = + ICP_HSSACC_FRM_PULSE_SYNC_IO_TYPE_OUTPUT_FALLING; + configParams->txPortConfig.frmSyncClkEdge = ICP_HSSACC_CLK_EDGE_FALLING; + configParams->txPortConfig.dataClkEdge = ICP_HSSACC_CLK_EDGE_FALLING; + configParams->txPortConfig.clkMode = ICP_HSSACC_CLK_MODE_INPUT_EXTERNAL; + configParams->txPortConfig.frmPulseUsage = ICP_HSSACC_FRM_PULSE_USAGE_ENABLED; + + configParams->txPortConfig.dataPolarity = ICP_HSSACC_DATA_POLARITY_SAME; + configParams->txPortConfig.drainMode = ICP_HSSACC_TX_PINS_DRAIN_MODE_NORMAL; + configParams->txPortConfig.refFrame = ICP_HSSACC_REF_FRAME_SELECTED; + configParams->txPortConfig.dataPinsEnable = ICP_HSSACC_DATA_PINS_TRI_STATE; + configParams->txPortConfig.unassignedType = ICP_HSSACC_UNASSIGNED_DRIVE_LOW; + + configParams->txPortConfig.fBitType = ICP_HSSACC_TX_FBIT_TYPE_FIFO; + configParams->txPortConfig.frm_offset = 0; + configParams->txPortConfig.fBitEnable = FALSE; + configParams->txPortConfig.interleaving = ICP_HSSACC_INTERLEAVING_FRAME; + + + configParams->rxPortConfig.frmSyncType = ICP_HSSACC_FRM_PULSE_SYNC_ACTIVE_LOW; + configParams->rxPortConfig.frmSyncIO = + ICP_HSSACC_FRM_PULSE_SYNC_IO_TYPE_OUTPUT_FALLING; + configParams->rxPortConfig.frmSyncClkEdge = ICP_HSSACC_CLK_EDGE_FALLING; + configParams->rxPortConfig.dataClkEdge = ICP_HSSACC_CLK_EDGE_FALLING; + configParams->rxPortConfig.clkMode = ICP_HSSACC_CLK_MODE_INPUT_EXTERNAL; + configParams->rxPortConfig.frmPulseUsage = ICP_HSSACC_FRM_PULSE_USAGE_ENABLED; + configParams->rxPortConfig.dataPolarity = ICP_HSSACC_DATA_POLARITY_SAME; + configParams->rxPortConfig.drainMode = ICP_HSSACC_TX_PINS_DRAIN_MODE_NORMAL; + configParams->rxPortConfig.refFrame = ICP_HSSACC_REF_FRAME_SELECTED; + configParams->rxPortConfig.dataPinsEnable = ICP_HSSACC_DATA_PINS_TRI_STATE; + configParams->rxPortConfig.unassignedType = ICP_HSSACC_UNASSIGNED_DRIVE_LOW; + configParams->rxPortConfig.fBitType = ICP_HSSACC_TX_FBIT_TYPE_FIFO; + configParams->rxPortConfig.fBitEnable = FALSE; + configParams->rxPortConfig.frm_offset = 0; + configParams->rxPortConfig.interleaving = ICP_HSSACC_INTERLEAVING_FRAME; + + /*Loopback settings*/ + configParams->txPortConfig.loopback = TRUE; + configParams->rxPortConfig.loopback = FALSE; + break; + } + case ICP_HSSDRV_INTERNAL_LOOPBACK: + { + + configParams->clkSpeed = ICP_HSSACC_CLK_SPEED_2048KHZ; + configParams->txPortConfig.frmSyncType = ICP_HSSACC_FRM_PULSE_SYNC_RISING_EDGE; + configParams->txPortConfig.frmSyncIO = + ICP_HSSACC_FRM_PULSE_SYNC_IO_TYPE_OUTPUT_FALLING; + configParams->txPortConfig.frmSyncClkEdge = ICP_HSSACC_CLK_EDGE_FALLING; + configParams->txPortConfig.dataClkEdge = ICP_HSSACC_CLK_EDGE_FALLING; + configParams->txPortConfig.clkMode = ICP_HSSACC_CLK_MODE_OUTPUT_INTERNAL; + configParams->txPortConfig.frmPulseUsage = ICP_HSSACC_FRM_PULSE_USAGE_ENABLED; + + configParams->txPortConfig.dataPolarity = ICP_HSSACC_DATA_POLARITY_SAME; + configParams->txPortConfig.drainMode = ICP_HSSACC_TX_PINS_DRAIN_MODE_NORMAL; + configParams->txPortConfig.refFrame = ICP_HSSACC_REF_FRAME_NOT_SELECTED; + configParams->txPortConfig.dataPinsEnable = ICP_HSSACC_DATA_PINS_ENABLE; + configParams->txPortConfig.unassignedType = ICP_HSSACC_UNASSIGNED_HIGH_IMPEDANCE; + configParams->txPortConfig.fBitType = ICP_HSSACC_TX_FBIT_TYPE_FIFO; + configParams->txPortConfig.frm_offset = 0; + configParams->txPortConfig.fBitEnable = FALSE; + configParams->txPortConfig.interleaving = ICP_HSSACC_INTERLEAVING_FRAME; + + + configParams->rxPortConfig.frmSyncType = ICP_HSSACC_FRM_PULSE_SYNC_RISING_EDGE; + configParams->rxPortConfig.frmSyncIO = + ICP_HSSACC_FRM_PULSE_SYNC_IO_TYPE_OUTPUT_FALLING; + configParams->rxPortConfig.frmSyncClkEdge = ICP_HSSACC_CLK_EDGE_FALLING; + configParams->rxPortConfig.dataClkEdge = ICP_HSSACC_CLK_EDGE_FALLING; + configParams->rxPortConfig.clkMode = ICP_HSSACC_CLK_MODE_OUTPUT_INTERNAL; + configParams->rxPortConfig.frmPulseUsage = ICP_HSSACC_FRM_PULSE_USAGE_ENABLED; + + configParams->rxPortConfig.dataPolarity = ICP_HSSACC_DATA_POLARITY_SAME; + configParams->rxPortConfig.drainMode = ICP_HSSACC_TX_PINS_DRAIN_MODE_NORMAL; + configParams->rxPortConfig.refFrame = ICP_HSSACC_REF_FRAME_NOT_SELECTED; + configParams->rxPortConfig.dataPinsEnable = ICP_HSSACC_DATA_PINS_ENABLE; + configParams->rxPortConfig.unassignedType = ICP_HSSACC_UNASSIGNED_HIGH_IMPEDANCE; + configParams->rxPortConfig.fBitType = ICP_HSSACC_TX_FBIT_TYPE_FIFO; + configParams->rxPortConfig.fBitEnable = FALSE; + configParams->rxPortConfig.frm_offset = 0; + configParams->rxPortConfig.interleaving = ICP_HSSACC_INTERLEAVING_FRAME; + + /*Loopback settings*/ + configParams->txPortConfig.loopback = FALSE; + configParams->rxPortConfig.loopback = TRUE; + break; + } + case ICP_HSSDRV_NO_LOOPBACK: + { + switch (port_config) + { + case ICP_HSSDRV_PORT_E1_FRAMER_MEZZANINE_CONFIG: + { + + configParams->clkSpeed = ICP_HSSACC_CLK_SPEED_2048KHZ; + configParams->txPortConfig.frmSyncType = ICP_HSSACC_FRM_PULSE_SYNC_ACTIVE_LOW; + configParams->txPortConfig.frmSyncIO = + ICP_HSSACC_FRM_PULSE_SYNC_IO_TYPE_OUTPUT_FALLING; + configParams->txPortConfig.frmSyncClkEdge = ICP_HSSACC_CLK_EDGE_FALLING; + configParams->txPortConfig.dataClkEdge = ICP_HSSACC_CLK_EDGE_FALLING; + configParams->txPortConfig.clkMode = ICP_HSSACC_CLK_MODE_INPUT_EXTERNAL; + configParams->txPortConfig.frmPulseUsage = ICP_HSSACC_FRM_PULSE_USAGE_ENABLED; + + configParams->txPortConfig.dataPolarity = ICP_HSSACC_DATA_POLARITY_SAME; + configParams->txPortConfig.drainMode = ICP_HSSACC_TX_PINS_DRAIN_MODE_NORMAL; + configParams->txPortConfig.refFrame = ICP_HSSACC_REF_FRAME_SELECTED; + configParams->txPortConfig.dataPinsEnable = ICP_HSSACC_DATA_PINS_TRI_STATE; + configParams->txPortConfig.unassignedType = ICP_HSSACC_UNASSIGNED_DRIVE_LOW; + + configParams->txPortConfig.fBitType = ICP_HSSACC_TX_FBIT_TYPE_FIFO; + configParams->txPortConfig.frm_offset = 0; + configParams->txPortConfig.fBitEnable = FALSE; + configParams->txPortConfig.interleaving = ICP_HSSACC_INTERLEAVING_BYTE; + + + configParams->rxPortConfig.frmSyncType = ICP_HSSACC_FRM_PULSE_SYNC_ACTIVE_LOW; + configParams->rxPortConfig.frmSyncIO = + ICP_HSSACC_FRM_PULSE_SYNC_IO_TYPE_OUTPUT_FALLING; + configParams->rxPortConfig.frmSyncClkEdge = ICP_HSSACC_CLK_EDGE_FALLING; + configParams->rxPortConfig.dataClkEdge = ICP_HSSACC_CLK_EDGE_FALLING; + configParams->rxPortConfig.clkMode = ICP_HSSACC_CLK_MODE_INPUT_EXTERNAL; + configParams->rxPortConfig.frmPulseUsage = ICP_HSSACC_FRM_PULSE_USAGE_ENABLED; + configParams->rxPortConfig.dataPolarity = ICP_HSSACC_DATA_POLARITY_SAME; + configParams->rxPortConfig.drainMode = ICP_HSSACC_TX_PINS_DRAIN_MODE_NORMAL; + configParams->rxPortConfig.refFrame = ICP_HSSACC_REF_FRAME_SELECTED; + configParams->rxPortConfig.dataPinsEnable = ICP_HSSACC_DATA_PINS_TRI_STATE; + configParams->rxPortConfig.unassignedType = ICP_HSSACC_UNASSIGNED_DRIVE_LOW; + configParams->rxPortConfig.fBitType = ICP_HSSACC_TX_FBIT_TYPE_FIFO; + configParams->rxPortConfig.fBitEnable = FALSE; + configParams->rxPortConfig.frm_offset = 0; + configParams->rxPortConfig.interleaving = ICP_HSSACC_INTERLEAVING_BYTE; + + break; + } + case ICP_HSSDRV_PORT_T1_FRAMER_MEZZANINE_CONFIG: + { + configParams->clkSpeed = ICP_HSSACC_CLK_SPEED_1544KHZ; + configParams->txPortConfig.frmSyncType = ICP_HSSACC_FRM_PULSE_SYNC_ACTIVE_LOW; + configParams->txPortConfig.frmSyncIO = + ICP_HSSACC_FRM_PULSE_SYNC_IO_TYPE_OUTPUT_FALLING; + configParams->txPortConfig.frmSyncClkEdge = ICP_HSSACC_CLK_EDGE_FALLING; + configParams->txPortConfig.dataClkEdge = ICP_HSSACC_CLK_EDGE_FALLING; + configParams->txPortConfig.clkMode = ICP_HSSACC_CLK_MODE_INPUT_EXTERNAL; + configParams->txPortConfig.frmPulseUsage = ICP_HSSACC_FRM_PULSE_USAGE_ENABLED; + + configParams->txPortConfig.dataPolarity = ICP_HSSACC_DATA_POLARITY_SAME; + configParams->txPortConfig.drainMode = ICP_HSSACC_TX_PINS_DRAIN_MODE_NORMAL; + configParams->txPortConfig.refFrame = ICP_HSSACC_REF_FRAME_SELECTED; + configParams->txPortConfig.dataPinsEnable = ICP_HSSACC_DATA_PINS_TRI_STATE; + configParams->txPortConfig.unassignedType = ICP_HSSACC_UNASSIGNED_DRIVE_LOW; + configParams->txPortConfig.fBitType = ICP_HSSACC_TX_FBIT_TYPE_FIFO; + configParams->txPortConfig.frm_offset = 0; + configParams->txPortConfig.fBitEnable = TRUE; + configParams->txPortConfig.interleaving = ICP_HSSACC_INTERLEAVING_BYTE; + + + configParams->rxPortConfig.frmSyncType = ICP_HSSACC_FRM_PULSE_SYNC_ACTIVE_LOW; + configParams->rxPortConfig.frmSyncIO = + ICP_HSSACC_FRM_PULSE_SYNC_IO_TYPE_OUTPUT_FALLING; + configParams->rxPortConfig.frmSyncClkEdge = ICP_HSSACC_CLK_EDGE_FALLING; + configParams->rxPortConfig.dataClkEdge = ICP_HSSACC_CLK_EDGE_FALLING; + configParams->rxPortConfig.clkMode = ICP_HSSACC_CLK_MODE_INPUT_EXTERNAL; + configParams->rxPortConfig.frmPulseUsage = ICP_HSSACC_FRM_PULSE_USAGE_ENABLED; + + configParams->rxPortConfig.dataPolarity = ICP_HSSACC_DATA_POLARITY_SAME; + configParams->rxPortConfig.drainMode = ICP_HSSACC_TX_PINS_DRAIN_MODE_NORMAL; + configParams->rxPortConfig.refFrame = ICP_HSSACC_REF_FRAME_SELECTED; + configParams->rxPortConfig.dataPinsEnable = ICP_HSSACC_DATA_PINS_TRI_STATE; + configParams->rxPortConfig.unassignedType = ICP_HSSACC_UNASSIGNED_DRIVE_LOW; + configParams->rxPortConfig.fBitType = ICP_HSSACC_TX_FBIT_TYPE_FIFO; + configParams->rxPortConfig.fBitEnable = TRUE; + configParams->rxPortConfig.frm_offset = 0; + configParams->rxPortConfig.interleaving = ICP_HSSACC_INTERLEAVING_BYTE; + break; + } + case ICP_HSSDRV_PORT_ANALOG_VOICE_MEZZANINE_CONFIG: + { + configParams->clkSpeed = ICP_HSSACC_CLK_SPEED_2048KHZ; + configParams->txPortConfig.frmSyncType = ICP_HSSACC_FRM_PULSE_SYNC_RISING_EDGE; + configParams->txPortConfig.frmSyncIO = ICP_HSSACC_FRM_PULSE_SYNC_IO_TYPE_INPUT; + configParams->txPortConfig.frmSyncClkEdge = ICP_HSSACC_CLK_EDGE_FALLING; + configParams->txPortConfig.dataClkEdge = ICP_HSSACC_CLK_EDGE_RISING; + configParams->txPortConfig.clkMode = ICP_HSSACC_CLK_MODE_INPUT_EXTERNAL; + configParams->txPortConfig.frmPulseUsage = ICP_HSSACC_FRM_PULSE_USAGE_ENABLED; + + configParams->txPortConfig.dataPolarity = ICP_HSSACC_DATA_POLARITY_SAME; + configParams->txPortConfig.drainMode = ICP_HSSACC_TX_PINS_DRAIN_MODE_NORMAL; + configParams->txPortConfig.refFrame = ICP_HSSACC_REF_FRAME_NOT_SELECTED; + configParams->txPortConfig.dataPinsEnable = ICP_HSSACC_DATA_PINS_ENABLE; + configParams->txPortConfig.unassignedType = ICP_HSSACC_UNASSIGNED_HIGH_IMPEDANCE; + configParams->txPortConfig.fBitType = ICP_HSSACC_TX_FBIT_TYPE_FIFO; + configParams->txPortConfig.frm_offset = 0; + configParams->txPortConfig.fBitEnable = FALSE; + configParams->txPortConfig.interleaving = ICP_HSSACC_INTERLEAVING_FRAME; + + + configParams->rxPortConfig.frmSyncType = ICP_HSSACC_FRM_PULSE_SYNC_RISING_EDGE; + configParams->rxPortConfig.frmSyncIO = ICP_HSSACC_FRM_PULSE_SYNC_IO_TYPE_INPUT; + configParams->rxPortConfig.frmSyncClkEdge = ICP_HSSACC_CLK_EDGE_FALLING; + configParams->rxPortConfig.dataClkEdge = ICP_HSSACC_CLK_EDGE_FALLING; + configParams->rxPortConfig.clkMode = ICP_HSSACC_CLK_MODE_INPUT_EXTERNAL; + configParams->rxPortConfig.frmPulseUsage = ICP_HSSACC_FRM_PULSE_USAGE_ENABLED; + + configParams->rxPortConfig.dataPolarity = ICP_HSSACC_DATA_POLARITY_SAME; + configParams->rxPortConfig.drainMode = ICP_HSSACC_TX_PINS_DRAIN_MODE_NORMAL; + configParams->rxPortConfig.refFrame = ICP_HSSACC_REF_FRAME_NOT_SELECTED; + configParams->rxPortConfig.dataPinsEnable = ICP_HSSACC_DATA_PINS_ENABLE; + configParams->rxPortConfig.unassignedType = ICP_HSSACC_UNASSIGNED_HIGH_IMPEDANCE; + configParams->rxPortConfig.fBitType = ICP_HSSACC_TX_FBIT_TYPE_FIFO; + configParams->rxPortConfig.fBitEnable = FALSE; + configParams->rxPortConfig.frm_offset = 0; + configParams->rxPortConfig.interleaving = ICP_HSSACC_INTERLEAVING_FRAME; + break; + } + case ICP_HSSDRV_PORT_HMVIP_FRAMER_MEZZANINE_CONFIG: + { + configParams->clkSpeed = ICP_HSSACC_CLK_SPEED_8192KHZ; + configParams->txPortConfig.frmSyncType = ICP_HSSACC_FRM_PULSE_SYNC_ACTIVE_LOW; + configParams->txPortConfig.frmSyncIO = + ICP_HSSACC_FRM_PULSE_SYNC_IO_TYPE_INPUT; + configParams->txPortConfig.frmSyncClkEdge = ICP_HSSACC_CLK_EDGE_FALLING; + configParams->txPortConfig.dataClkEdge = ICP_HSSACC_CLK_EDGE_RISING; + configParams->txPortConfig.clkMode = ICP_HSSACC_CLK_MODE_INPUT_EXTERNAL; + configParams->txPortConfig.frmPulseUsage = ICP_HSSACC_FRM_PULSE_USAGE_ENABLED; + + configParams->txPortConfig.dataPolarity = ICP_HSSACC_DATA_POLARITY_SAME; + configParams->txPortConfig.drainMode = ICP_HSSACC_TX_PINS_DRAIN_MODE_NORMAL; + configParams->txPortConfig.refFrame = ICP_HSSACC_REF_FRAME_NOT_SELECTED; + configParams->txPortConfig.dataPinsEnable = ICP_HSSACC_DATA_PINS_ENABLE; + configParams->txPortConfig.unassignedType = ICP_HSSACC_UNASSIGNED_HIGH_IMPEDANCE; + configParams->txPortConfig.fBitType = ICP_HSSACC_TX_FBIT_TYPE_FIFO; + configParams->txPortConfig.frm_offset = 1023; + configParams->txPortConfig.fBitEnable = FALSE; + configParams->txPortConfig.interleaving = ICP_HSSACC_INTERLEAVING_BYTE; + + + configParams->rxPortConfig.frmSyncType = ICP_HSSACC_FRM_PULSE_SYNC_ACTIVE_LOW; + configParams->rxPortConfig.frmSyncIO = + ICP_HSSACC_FRM_PULSE_SYNC_IO_TYPE_INPUT; + configParams->rxPortConfig.frmSyncClkEdge = ICP_HSSACC_CLK_EDGE_FALLING; + configParams->rxPortConfig.dataClkEdge = ICP_HSSACC_CLK_EDGE_RISING; + configParams->rxPortConfig.clkMode = ICP_HSSACC_CLK_MODE_INPUT_EXTERNAL; + configParams->rxPortConfig.frmPulseUsage = ICP_HSSACC_FRM_PULSE_USAGE_ENABLED; + + configParams->rxPortConfig.dataPolarity = ICP_HSSACC_DATA_POLARITY_SAME; + configParams->rxPortConfig.drainMode = ICP_HSSACC_TX_PINS_DRAIN_MODE_NORMAL; + configParams->rxPortConfig.refFrame = ICP_HSSACC_REF_FRAME_NOT_SELECTED; + configParams->rxPortConfig.dataPinsEnable = ICP_HSSACC_DATA_PINS_ENABLE; + configParams->rxPortConfig.unassignedType = ICP_HSSACC_UNASSIGNED_HIGH_IMPEDANCE; + configParams->rxPortConfig.fBitType = ICP_HSSACC_TX_FBIT_TYPE_FIFO; + configParams->rxPortConfig.fBitEnable = FALSE; + configParams->rxPortConfig.frm_offset = 1023; + configParams->rxPortConfig.interleaving = ICP_HSSACC_INTERLEAVING_BYTE; + break; + } + case ICP_HSSDRV_PORT_XHFC_MEGREZ_PROTO_XIVO_CONFIG: + { + configParams->clkSpeed = ICP_HSSACC_CLK_SPEED_2048KHZ; + configParams->txPortConfig.frmSyncType = ICP_HSSACC_FRM_PULSE_SYNC_ACTIVE_HIGH; + configParams->txPortConfig.frmSyncIO = ICP_HSSACC_FRM_PULSE_SYNC_IO_TYPE_INPUT; + configParams->txPortConfig.frmSyncClkEdge = ICP_HSSACC_CLK_EDGE_RISING; + configParams->txPortConfig.dataClkEdge = ICP_HSSACC_CLK_EDGE_FALLING; + configParams->txPortConfig.clkMode = ICP_HSSACC_CLK_MODE_INPUT_EXTERNAL; + configParams->txPortConfig.frmPulseUsage = ICP_HSSACC_FRM_PULSE_USAGE_ENABLED; + + configParams->txPortConfig.dataPolarity = ICP_HSSACC_DATA_POLARITY_SAME; + configParams->txPortConfig.drainMode = ICP_HSSACC_TX_PINS_DRAIN_MODE_NORMAL; + configParams->txPortConfig.refFrame = ICP_HSSACC_REF_FRAME_NOT_SELECTED; + configParams->txPortConfig.dataPinsEnable = ICP_HSSACC_DATA_PINS_ENABLE; + configParams->txPortConfig.unassignedType = ICP_HSSACC_UNASSIGNED_DRIVE_HIGH; + + configParams->txPortConfig.fBitType = 0; + configParams->txPortConfig.frm_offset = 255; + configParams->txPortConfig.fBitEnable = FALSE; + configParams->txPortConfig.interleaving = 0; + + + configParams->rxPortConfig.frmSyncType = ICP_HSSACC_FRM_PULSE_SYNC_ACTIVE_HIGH; + configParams->rxPortConfig.frmSyncIO = ICP_HSSACC_FRM_PULSE_SYNC_IO_TYPE_INPUT; + configParams->rxPortConfig.frmSyncClkEdge = ICP_HSSACC_CLK_EDGE_RISING; + configParams->rxPortConfig.dataClkEdge = ICP_HSSACC_CLK_EDGE_RISING; + configParams->rxPortConfig.clkMode = ICP_HSSACC_CLK_MODE_INPUT_EXTERNAL; + configParams->rxPortConfig.frmPulseUsage = ICP_HSSACC_FRM_PULSE_USAGE_ENABLED; + configParams->rxPortConfig.dataPolarity = ICP_HSSACC_DATA_POLARITY_SAME; + configParams->rxPortConfig.drainMode = ICP_HSSACC_TX_PINS_DRAIN_MODE_NORMAL; + configParams->rxPortConfig.refFrame = ICP_HSSACC_REF_FRAME_NOT_SELECTED; + configParams->rxPortConfig.dataPinsEnable = ICP_HSSACC_DATA_PINS_ENABLE; + configParams->rxPortConfig.unassignedType = ICP_HSSACC_UNASSIGNED_DRIVE_HIGH; + configParams->rxPortConfig.fBitType = 0; + configParams->rxPortConfig.fBitEnable = FALSE; + configParams->rxPortConfig.frm_offset = 255; + configParams->rxPortConfig.interleaving = 0; + break; + } + case ICP_HSSDRV_PORT_LE89316_MEGREZ_PROTO_XIVO_CONFIG: + { + configParams->clkSpeed = ICP_HSSACC_CLK_SPEED_2048KHZ; + configParams->txPortConfig.frmSyncType = ICP_HSSACC_FRM_PULSE_SYNC_ACTIVE_HIGH; + configParams->txPortConfig.frmSyncIO = ICP_HSSACC_FRM_PULSE_SYNC_IO_TYPE_OUTPUT_RISING; + configParams->txPortConfig.frmSyncClkEdge = ICP_HSSACC_CLK_EDGE_FALLING; + configParams->txPortConfig.dataClkEdge = ICP_HSSACC_CLK_EDGE_RISING; + configParams->txPortConfig.clkMode = ICP_HSSACC_CLK_MODE_OUTPUT_REF; + configParams->txPortConfig.frmPulseUsage = ICP_HSSACC_FRM_PULSE_USAGE_ENABLED; + + configParams->txPortConfig.dataPolarity = ICP_HSSACC_DATA_POLARITY_SAME; + configParams->txPortConfig.drainMode = ICP_HSSACC_TX_PINS_DRAIN_MODE_NORMAL; + configParams->txPortConfig.refFrame = ICP_HSSACC_REF_FRAME_NOT_SELECTED; + configParams->txPortConfig.dataPinsEnable = ICP_HSSACC_DATA_PINS_ENABLE; + configParams->txPortConfig.unassignedType = ICP_HSSACC_UNASSIGNED_DRIVE_HIGH; + + configParams->txPortConfig.fBitType = 0; + configParams->txPortConfig.frm_offset = 255; + configParams->txPortConfig.fBitEnable = FALSE; + configParams->txPortConfig.interleaving = 0; + + + configParams->rxPortConfig.frmSyncType = ICP_HSSACC_FRM_PULSE_SYNC_ACTIVE_HIGH; + configParams->rxPortConfig.frmSyncIO = ICP_HSSACC_FRM_PULSE_SYNC_IO_TYPE_INPUT; + configParams->rxPortConfig.frmSyncClkEdge = ICP_HSSACC_CLK_EDGE_FALLING; + configParams->rxPortConfig.dataClkEdge = ICP_HSSACC_CLK_EDGE_RISING; + configParams->rxPortConfig.clkMode = ICP_HSSACC_CLK_MODE_INPUT_EXTERNAL; + configParams->rxPortConfig.frmPulseUsage = ICP_HSSACC_FRM_PULSE_USAGE_ENABLED; + configParams->rxPortConfig.dataPolarity = ICP_HSSACC_DATA_POLARITY_SAME; + configParams->rxPortConfig.drainMode = ICP_HSSACC_TX_PINS_DRAIN_MODE_NORMAL; + configParams->rxPortConfig.refFrame = ICP_HSSACC_REF_FRAME_NOT_SELECTED; + configParams->rxPortConfig.dataPinsEnable = ICP_HSSACC_DATA_PINS_ENABLE; + configParams->rxPortConfig.unassignedType = ICP_HSSACC_UNASSIGNED_DRIVE_HIGH; + configParams->rxPortConfig.fBitType = 0; + configParams->rxPortConfig.fBitEnable = FALSE; + configParams->rxPortConfig.frm_offset = 255; + configParams->rxPortConfig.interleaving = 0; + break; + } + default: + { + printk(KERN_ERR "invalid HSS Port Config Mode \n"); + return; + } + + } + /*Loopback settings*/ + configParams->txPortConfig.loopback = FALSE; + configParams->rxPortConfig.loopback = FALSE; + break; + } + default: + { + printk(KERN_ERR "invalid loopbackMode"); + break; + } + } +} + +inline void timeslot_map_translate (icp_hssdrv_timeslot_map_t * driver_map, + icp_hssacc_timeslot_map_t * acc_map) +{ + acc_map->line0_timeslot_bit_map = driver_map->line0_timeslot_bit_map; + acc_map->line1_timeslot_bit_map = driver_map->line1_timeslot_bit_map; + acc_map->line2_timeslot_bit_map = driver_map->line2_timeslot_bit_map; + acc_map->line3_timeslot_bit_map = driver_map->line3_timeslot_bit_map; +} + +#endif +/* ICP_HSSDRV_COMMON_H */ diff --git a/Acceleration/drivers/icp_tdm/tdm_setup_driver/Makefile b/Acceleration/drivers/icp_tdm/tdm_setup_driver/Makefile new file mode 100644 index 0000000..5a4f5e2 --- /dev/null +++ b/Acceleration/drivers/icp_tdm/tdm_setup_driver/Makefile @@ -0,0 +1,130 @@ +######################################################################### +# +# Targets supported +# all - builds everything and installs +# install - identical to all +# depend - build dependencies +# clean - clears derived objects except the .depend files +# distclean- clears all derived objects and the .depend file +# +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# +############################################################################ + + +####################Common variables and definitions######################## +# Ensure The ICP_ENV_DIR environmental var is defined. +ifndef ICP_ENV_DIR +$(error ICP_ENV_DIR is undefined. Please set the path to your environment makefile \ + "-> setenv ICP_ENV_DIR <path>") +endif + +#Add your project environment Makefile +include $(ICP_ENV_DIR)/environment.mk + + +#include the makefile with all the default and common Make variable definitions +include $(ICP_BUILDSYSTEM_PATH)/build_files/common.mk + +ifdef ICP_DEBUG + CFLAGS+= -DDEBUG +endif + +ifdef ICP_POLLING + CFLAGS+= -DTDM_NO_INTERRUPTS +endif + + +#Add the name for the executable, Library or Module output definitions +OUTPUT_NAME=tdm_setup_driver + +# List of Source Files to be compiled (to be in a single line or on different lines separated by a "\" and tab. +MODULE_SOURCES=$(ICP_COMMON_PLATFORM)$(ICP_SLASH)$(ICP_OS_TYPE)$(ICP_SLASH)tdm_setup_drv.c + + +#common includes between all supported OSes +INCLUDES+= -I $(ICP_TDM_SETUP_DRV_DIR)/$(ICP_COMMON_PLATFORM)$(ICP_SLASH)$(ICP_OS_TYPE)$(ICP_SLASH)include \ + -I $(ICP_API_DIR) \ + -I $(ICP_API_DIR)/hss \ + -I $(ICP_API_DIR)/accel_infra \ + -I $(ICP_TDM_DL_DIR)/include \ + -I $(ICP_OSAL_DIR)/common/include \ + -I $(ICP_OSAL_DIR)/common/include/modules \ + -I $(ICP_OSAL_DIR)/common/include/modules/ddk \ + -I $(ICP_OSAL_DIR)/common/include/modules/bufferMgt \ + -I $(ICP_OSAL_DIR)/common/include/modules/ioMem + + + + +#include your $(ICP_OS)_$(ICP_OS_LEVEL).mk file +#include $(ICP_TDM_SETUP_DRV_DIR)/$(ICP_OS)_$(ICP_OS_LEVEL).mk +include $(ICP_TDM_SETUP_DRV_DIR)/$(ICP_OS)_$(ICP_OS_LEVEL).mk + + +# On the line directly below list the outputs you wish to build for, +# e.g "lib_static lib_shared exe module" as show below +install: module + + + +###################Include rules makefiles######################## +include $(ICP_BUILDSYSTEM_PATH)/build_files/rules.mk +###################End of Rules inclusion######################### + diff --git a/Acceleration/drivers/icp_tdm/tdm_setup_driver/include/tdm_setup_drv_p.h b/Acceleration/drivers/icp_tdm/tdm_setup_driver/include/tdm_setup_drv_p.h new file mode 100644 index 0000000..b3b7b78 --- /dev/null +++ b/Acceleration/drivers/icp_tdm/tdm_setup_driver/include/tdm_setup_drv_p.h @@ -0,0 +1,162 @@ +/************************************************************************** + * @file tdm_setup_drv_p.h + * + * @description + * This file contains the TDM Setup Driver private declarations + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + **************************************************************************/ +#ifndef TDM_SETUP_DRV_P_H_ +#define TDM_SETUP_DRV_P_H_ + +/********************************** + * DEFINES + *********************************/ +#define PCI_DEVICE_TDM_UNIT 0x504C /*TDM Unit PCI Device ID */ + +#define MAX_PCI_BARS 6 /*Max No. of BARS for any device */ +#define TDM_UNIT_BARS 2 /*total No. of TDM unit BARS */ + +#define TDM_UNIT_CSR_BAR 0 +#define TDM_UNIT_CCP_BAR 1 + +/*These are the three types of interrupts that can be generated by the TDM + * IO Unit that have to be handled by this driver. + * FUNCTIONAL INTERRUPT: + * signals that the TDM IO Unit has responsed to a message sent down by the + * piuMh component. + * TRIGGER INTERRUPT: + * used to notify TDM IO Access Layer that packets are ready for processing + * ERROR INTERRUPT: + * reports a parity error in TDM IO Unit memory. + * There is no recovery from this situation*/ +#define PCI_SMIA_REG_OFFSET 0xE8 +#define PCI_INT_TARGET_REG_OFFSET 0xEC + +#define TDM_INT_FUNCTIONAL 0x01 +#define TDM_INT_ERROR 0x02 +#define TDM_INT_TRIGGER 0x04 + +/*the total number of minor numbers required + * when registering the driver*/ +#define MINOR_NUMS_REQ 1 + +#define TDM_SETUP_DEVICE(device_id) \ +{ \ +PCI_DEVICE(PCI_VENDOR_ID_INTEL, device_id)} + +#define AUTO_INIT_ENABLED 1 +#define AUTO_INIT_DISABLED 0 + +/*The number of mezzanine slots supported*/ +#define TDM_MAX_MEZZ_SLOTS 3 + +/*Debug tracing*/ +#ifdef DEBUG +#define TDM_SETUP_DEBUG printk +#else +#define NULL_TDM_SETUP_DEBUG(x, y...) +#define TDM_SETUP_DEBUG NULL_TDM_SETUP_DEBUG +#endif + +/********************************** + * TYPE DEFINITIONS + *********************************/ +/*BAR information*/ +struct _tdm_bar_s { + + uint64_t base_addr; /* read from PCI config */ + + uint64_t virt_addr; /* mapped to kernel VA */ + + uint32_t size; /* size of BAR */ + +}; + +/* + * PCI information + */ +struct tdm_pci_info_s { + + struct pci_dev *pdev; + + uint32_t device_id; + + uint32_t irq; + + uint32_t num_bars; + + struct _tdm_bar_s pci_bars[MAX_PCI_BARS]; + +}; + +struct tdm_dev_s { + + struct tdm_pci_info_s device; /* PCI Device */ + + /* Linked list of device_handles */ + struct tdm_dev_s *pnext; + + struct tdm_dev_s *pprev; + +}; + +#endif /*TDM_SETUP_DRV_P_H_ */ diff --git a/Acceleration/drivers/icp_tdm/tdm_setup_driver/linux_2.6_kernel_space.mk b/Acceleration/drivers/icp_tdm/tdm_setup_driver/linux_2.6_kernel_space.mk new file mode 100644 index 0000000..d6aad3a --- /dev/null +++ b/Acceleration/drivers/icp_tdm/tdm_setup_driver/linux_2.6_kernel_space.mk @@ -0,0 +1,75 @@ +################### +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# +################### + +INCLUDES+= -I $(ICP_OSAL_DIR)/platforms/EP805XX/include \ + -I $(ICP_OSAL_DIR)/platforms/EP805XX/os/linux/include \ + -I $(ICP_OSAL_DIR)/common/os/linux/include \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/core \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules/ddk \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules/ioMem \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules/bufferMgt + +#Extra Flags Specific in kernel space e.g. include path or debug flags etc. e.g to add an include path EXTRA_CFLAGS += -I$(src)/../include +EXTRA_CFLAGS += -D__tolapai -D__ep805xx -D_IX_HARDWARE_TYPE_=_IX_HW_TOLAPAI_ -DIX_HW_COHERENT_MEMORY=1 -D ENABLE_SPINLOCK $(INCLUDES) -D_IX_RM_IMPL_HARDWARE_ -DIOSTYLE=NOIOOP -D__LITTLE_ENDIAN -D__BYTE_ORDER=__LITTLE_ENDIAN -DIX_DEBUG -DENABLE_IOMEM -DENABLE_BUFFERMGT +EXTRA_LDFLAGS +=-whole-archive + +KBUILD_EXTRA_SYMBOLS+= $(ICP_ROOT)/Acceleration/library/icp_telephony/Module.symvers diff --git a/Acceleration/drivers/icp_tdm/tdm_setup_driver/tdm_setup_drv.c b/Acceleration/drivers/icp_tdm/tdm_setup_driver/tdm_setup_drv.c new file mode 100644 index 0000000..0efe37b --- /dev/null +++ b/Acceleration/drivers/icp_tdm/tdm_setup_driver/tdm_setup_drv.c @@ -0,0 +1,947 @@ +/************************************************************************** + * @file tdm_setup_drv.c + * + * @description + * This file contains the TDM Setup Driver Implementation code + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + **************************************************************************/ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/pci.h> +#include <linux/init.h> +#include <linux/types.h> +#include <linux/fs.h> +#include <linux/sched.h> +#include <linux/slab.h> +#include <linux/errno.h> + +#include <linux/cdev.h> +#include <linux/device.h> +#include <linux/interrupt.h> +#include <linux/workqueue.h> +#include <asm/uaccess.h> +#include <asm/io.h> +#include <linux/acpi.h> +#include <asm/acpi.h> +#include <asm/system.h> +#include <linux/delay.h> + +#include "icp.h" +#include "icp_tdmsetupdrv.h" +#include "IxPiuDl.h" +#include "IxPiuMicrocode.h" +#include "IxPiuMh.h" +#include "IxQMgr.h" +#include "icp_hssacc.h" +#include "tdm_setup_drv_p.h" + +/********************************** + * Module static variables + **********************************/ +/*System is automatically initialized on insmod if this variable is set*/ +static int auto_init = AUTO_INIT_ENABLED; + +/********************************** + * Module parameters + **********************************/ +module_param(auto_init, int, S_IRUGO); +MODULE_DESCRIPTION("TDM Setup Driver"); +MODULE_AUTHOR("Intel Corporation"); +MODULE_VERSION("1.0"); +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_DEVICE_TABLE(pci, tdm_pci_tbl); + +/************************************ + * Module function prototypes + ************************************/ + + /*to initialize the driver on insmod */ +static int tdmdrv_init(void); +/*to uninitialize the driver on rmmod*/ +static void tdmdrv_release(void); +/*handles open() call by a client*/ +static int tdmdrv_open(struct inode *inode, struct file *filep); +/*handles close() call by a client*/ +static int tdmdrv_close(struct inode *inode, struct file *filep); +/*handles ioctl() call by a client*/ +static int tdmdrv_ioctl(struct inode *inode, struct file *filep, + unsigned int cmd, unsigned long arg); +/*handles the registration of PCI hardware that the driver is + * configured to manage*/ +static int tdm_probe(struct pci_dev *pdev, const struct pci_device_id *ent); +/*handles the un-registration of PCI hardware that the driver is + * configured to manage*/ +static void __devexit tdm_remove(struct pci_dev *pdev); +/*binds an irq*/ +static int bind_irq(unsigned int *vector, char *name); +/*unbinds and irq*/ +static void unbind_irq(unsigned int *vector); +/*interrupt handler for TDM I/O interrupts*/ +static irqreturn_t tdm_interrupt_dispatcher(int irg, void *dev_id); +/*@function used to set to stop the TDM system*/ +static void tdm_stop_system(void); +/*used to process interrupts from the TDM I/O*/ +void tdm_work_queue_handler(struct work_struct *work); + + +/************************************ + * Globals + ************************************/ +/*Dynamic allocation of device driver major number*/ +static int tdmdrv_major = 0; +/*Dynamic allocation of device driver minor number*/ +static int tdmdrv_minor = 0; +static char tdm_driver_name[] = "tdm_setup"; + +static struct cdev *tdmdrv_cdev = NULL; /*driver cdev structure */ + +static struct file_operations tdmdrv_fops = { + .owner = THIS_MODULE, + .ioctl = tdmdrv_ioctl, /* ioctl method */ + .open = tdmdrv_open, /* open method */ + .release = tdmdrv_close, /* release method */ +}; + +static struct pci_device_id tdm_pci_tbl[] = { /*PCI device table */ + TDM_SETUP_DEVICE(PCI_DEVICE_TDM_UNIT), + {0,} +}; + +static struct pci_driver tdm_driver = { /*PCI driver setup structure */ + .name = tdm_driver_name, + .id_table = tdm_pci_tbl, + .probe = tdm_probe, + .remove = __devexit_p(tdm_remove), +}; + +/* Tracks the number of time that the driver has been initialized*/ +static unsigned int num_inits = 0; + +static struct workqueue_struct *tdmdrv_wq; + +/*work queue used to switch interrupt processing to context mode*/ +DECLARE_WORK(tdm_work_queue, tdm_work_queue_handler); + +/*Mutex to contol multiple accesses to the driver*/ +DECLARE_MUTEX(control_mutex); + +/*pointer to a linked list of PCI devices that the driver is managing*/ +static struct tdm_dev_s *tdm_table = NULL; + +/* + * TDM device table and functions + * + */ + + /*checks if the driver is configured to manage the given PCI device */ +static struct tdm_dev_s *tdm_table_check(struct pci_dev *pdev) +{ + struct tdm_dev_s *ptr = tdm_table; + while (ptr != NULL) { + + if (ptr->device.pdev == pdev) { + return ptr; + } + + ptr = ptr->pnext; + } + return ptr; +} + +/* + * tdm_table_get_device + * Check the device table for a structure suitable for the found PCI device. + * Return an device structure for the PCI device + */ +static struct tdm_dev_s *tdm_table_get_device(unsigned int device_id) +{ + struct tdm_dev_s *ptr = tdm_table; + + /* + *check for existing device + */ + while (ptr != NULL) { + if (ptr->device.device_id == device_id) { + return ptr; + } + + ptr = ptr->pnext; + } + + return NULL; +} + +/*Add a device to the TDM device table*/ +static void tdm_device_table_add(struct tdm_dev_s *tdm_dev) +{ + if (tdm_dev == NULL) { + printk(KERN_ERR "%s: NULL pointer provided\n", __FUNCTION__); + return; + } + + if (tdm_table == NULL) { + tdm_table = tdm_dev; + tdm_dev->pnext = NULL; + tdm_dev->pprev = NULL; + } else { + tdm_dev->pnext = tdm_table; + tdm_table->pprev = tdm_dev; + tdm_dev->pprev = NULL; + tdm_table = tdm_dev; + } + +} + +/*Remove a device from the TDM device table*/ +static int tdm_device_table_remove(struct tdm_dev_s *tdm_dev) +{ + struct tdm_dev_s *prev = NULL; + struct tdm_dev_s *next = NULL; + + if (!tdm_dev) { + return -ENODEV; + } + + prev = tdm_dev->pprev; + next = tdm_dev->pnext; + + if (prev) { + prev->pnext = tdm_dev->pnext; + if (next) + + next->pprev = prev; + } else { + tdm_table = tdm_dev->pnext; + if (next) + + next->pprev = NULL; + } + return 0; +} + +/*Release the memory regions that belong to a PCI Device and disable + * the device*/ +static void tdm_cleanup_device(struct tdm_dev_s *tdm_dev) +{ + int status = 0; + + if (tdm_dev == NULL) { + printk(KERN_ERR "%s: NULL pointer provided\n", __FUNCTION__); + return; + } + + if (tdm_dev->device.pdev) { + pci_release_regions(tdm_dev->device.pdev); + pci_disable_device(tdm_dev->device.pdev); + } + + /* Remove the device from the device table */ + status = tdm_device_table_remove(tdm_dev); + if (status != 0) { + printk(KERN_ERR + "%s: failed to remove tdm_dev from device table\n", + __FUNCTION__); + } + + kfree(tdm_dev); + + return; +} + +/* + * tdm_remove + * + * Remove a PCI device + * + */ +static void tdm_remove(struct pci_dev *pdev) +{ + struct tdm_dev_s *tdm_dev = NULL; + + /* Find the device structure */ + tdm_dev = tdm_table_check(pdev); + if (tdm_dev == NULL) { + printk(KERN_ERR "%s: failed to find tdm_dev\n", __FUNCTION__); + return; + } + + tdm_cleanup_device(tdm_dev); + + TDM_SETUP_DEBUG(KERN_DEBUG "%s: Device Removal Completed\n", + __FUNCTION__); + return; +} + +/* + * tdm_init_system + * + * Initializes the TDM system components + */ +static int tdm_init_system(void) +{ + struct tdm_pci_info_s *pci_info = NULL; + struct tdm_dev_s *tdm_dev = NULL; + + /*Get the control mutex */ + if (down_interruptible(&control_mutex)) { + printk(KERN_ERR "%s - ERROR: Unable to get control mutex \n", + __FUNCTION__); + return -ERESTARTSYS; + } + + /*if the TDM system has already been initialized then increment + * the number of initializations and return success*/ + if (num_inits > 0) { + TDM_SETUP_DEBUG(KERN_DEBUG + "%s: Already initialized - do nothing !!!\n", + __FUNCTION__); + num_inits++; + + /*increment the number of processes using the driver + * This prevents the driver from being removed if it is + * in use*/ + + try_module_get(THIS_MODULE); + up(&control_mutex); + return 0; + } + + /* get tdm unit structure */ + tdm_dev = tdm_table_get_device(PCI_DEVICE_TDM_UNIT); + if (tdm_dev == NULL) { + printk(KERN_ERR "%s: no TDM I/O Structure found\n", + __FUNCTION__); + up(&control_mutex); + return -ENODEV; + } + + pci_info = &tdm_dev->device; + + /*set the base addresses in piuMh and piuDl */ + if (IX_SUCCESS != ixPiuDlPhysicalAddressSet(IX_PIUDL_PIUID_PIU0, + pci_info-> + pci_bars[TDM_UNIT_CSR_BAR]. + base_addr)) { + printk(KERN_ERR "%s: failed to set piuDl base address\n", + __FUNCTION__); + tdm_stop_system(); + up(&control_mutex); + return -EIO; + } + + /*Download and initialize the TDM I/O */ + if (IX_SUCCESS != ixPiuDlPiuInitAndStart + (IX_PIUDL_PIUIMAGE_PIU_HSS_TOLAPAI)) { + printk(KERN_ERR "%s: failed to start PIU\n", __FUNCTION__); + tdm_stop_system(); + up(&control_mutex); + return -EIO; + } + + /*bind any interrupts needed */ + if (bind_irq(&pci_info->irq, "tdm_io_unit") != 0) { + printk(KERN_ERR "%s: failed to bind TDM I/O interrupt\n", + __FUNCTION__); + tdm_stop_system(); + up(&control_mutex); + return -EIO; + } + + if (IX_SUCCESS != ixPiuMhPhysicalAddressSet(IX_PIUMH_PIUID_PIU0, + pci_info-> + pci_bars[TDM_UNIT_CSR_BAR]. + base_addr)) { + printk(KERN_ERR "%s: failed to set piuMh base address\n", + __FUNCTION__); + tdm_stop_system(); + up(&control_mutex); + return -EIO; + } + + /*start the piu message handler with interrupts enabled */ + if (IX_SUCCESS != ixPiuMhInitialize(IX_PIUMH_PIUINTERRUPTS_YES)) { + printk(KERN_ERR "%s: failed to initialize piuMh\n", + __FUNCTION__); + tdm_stop_system(); + up(&control_mutex); + return -EIO; + } + + /*start the queue manager */ + if (ICP_STATUS_SUCCESS != ixQMgrInit()) { + printk(KERN_ERR "%s: failed to start QMgr\n", __FUNCTION__); + tdm_stop_system(); + up(&control_mutex); + return -EIO; + } + + /*start hssAcc */ + if (ICP_STATUS_SUCCESS != icp_HssAccInit()) { + printk(KERN_ERR "%s: failed to start hssAcc\n", __FUNCTION__); + tdm_stop_system(); + up(&control_mutex); + return -EIO; + } + + /*increment the number of times the driver has been initialized */ + num_inits++; + + if (auto_init == AUTO_INIT_DISABLED) { + /*increment the number of processes using the driver */ + try_module_get(THIS_MODULE); + } + + TDM_SETUP_DEBUG(KERN_DEBUG "%s: init has been completed\n", + __FUNCTION__); + up(&control_mutex); + return 0; +} + +/* + * tdm_uninit_system + * + * Uninitializes the TDM system components + */ +static int tdm_uninit_system(void) +{ + + /*Get the control mutex */ + if (down_interruptible(&control_mutex)) { + printk(KERN_ERR "%s - ERROR: Unable to get control mutex \n", + __FUNCTION__); + return -ERESTARTSYS; + } + + /*return success if the driver is not initialized */ + if (num_inits == 0) { + printk(KERN_ERR "%s: System already uninitialized !!!\n", + __FUNCTION__); + up(&control_mutex); + return 0; + } + + /*if the TDM system has been initialized mutiple times then decrement + * the number of initializations and return success*/ + if (num_inits > 1) { + TDM_SETUP_DEBUG(KERN_DEBUG + "%s: Uninit - System in use - do nothing !!!\n", + __FUNCTION__); + num_inits--; + /*decrement the number of processes using the driver */ + module_put(THIS_MODULE); + up(&control_mutex); + return 0; + } + + /*Stop the TDM System */ + tdm_stop_system(); + + num_inits--; + + /*if auto init is enabled then num_init is +1 compared to the + num processes using the driver */ + if (auto_init == AUTO_INIT_DISABLED) { + /*decrement the number of processes using the driver */ + module_put(THIS_MODULE); + } + + up(&control_mutex); + return 0; +} + +/*shuts down all loaded voice components*/ +static void tdm_stop_system(void) +{ + struct tdm_pci_info_s *pci_info = NULL; + struct tdm_dev_s *tdm_dev = NULL; + + /*unmask Trigger interrupts*/ + tdm_dev = tdm_table_get_device(PCI_DEVICE_TDM_UNIT); + if (tdm_dev != NULL) { + pci_info = &tdm_dev->device; + + if (pci_write_config_byte(pci_info->pdev, PCI_SMIA_REG_OFFSET, + (TDM_INT_FUNCTIONAL | TDM_INT_ERROR))) { + printk(KERN_ERR "%s: Failed to disable trigger \n" + "interrupt\n", __FUNCTION__); + } + } + + /*unload hssAcc */ + if (ICP_STATUS_SUCCESS != icp_HssAccShutdown()) { + printk(KERN_ERR "%s: failed to stop hssAcc\n", __FUNCTION__); + } + + /*unbind TDM IO Unit interrupt */ + if (tdm_dev != NULL) { + unbind_irq(&pci_info->irq); + } + + /*stop the queue manager */ + if (ICP_STATUS_SUCCESS != ixQMgrUnload()) { + printk(KERN_ERR "%s: failed to stop QMgr\n", __FUNCTION__); + } + + /*stop the message handler */ + if (IX_SUCCESS != ixPiuMhUnload()) { + printk(KERN_ERR "%s: failed to unload piuMh\n", __FUNCTION__); + } + + /*stop the TDM IO Unit */ + if (IX_SUCCESS != ixPiuDlPiuStopAndReset(IX_PIUMH_PIUID_PIU0)) { + printk(KERN_ERR "%s: failed to stop the TDM I/O\n", + __FUNCTION__); + } + + /*unload the TDM IO Unit code */ + if (IX_SUCCESS != ixPiuDlUnload()) { + printk(KERN_ERR "%s: failed to unload piuDl\n", __FUNCTION__); + } +} + +/* handles the registration of PCI hardware that the driver is + * configured to manage*/ +static int tdm_probe(struct pci_dev *pdev, const struct pci_device_id *ent) +{ + int i = 0; + struct tdm_dev_s *tdm_dev = NULL; + struct tdm_pci_info_s *pci_info = NULL; + int num_bars = 0; + int new_device = 0; + int status = 0; + + /* Ensure have valid device */ + switch (ent->device) { + case PCI_DEVICE_TDM_UNIT: + break; + default: + printk(KERN_ERR "%s: invalid device 0x%x found..!!\n", + __FUNCTION__, ent->device); + return -ENODEV; + } + + /*Check device Table for an existing device structure */ + tdm_dev = tdm_table_check(pdev); + if (tdm_dev == NULL) { + tdm_dev = kzalloc(sizeof(struct tdm_dev_s), GFP_KERNEL); + if (tdm_dev == NULL) { + printk(KERN_ERR + "%s: failed to allocate memory for device" + " structure\n", __FUNCTION__); + return -ENOMEM; + } + new_device = 1; + } else { + new_device = 0; + } + + /* enable PCI device */ + if (pci_enable_device(pdev)) { + tdm_cleanup_device(tdm_dev); + return -EIO; + } + + /* set dma identifier */ + if (pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { + if ((pci_set_dma_mask(pdev, DMA_32BIT_MASK))) { + printk(KERN_ERR + "%s: No usable DMA configuration, aborting\n", + __FUNCTION__); + tdm_cleanup_device(tdm_dev); + return -EIO; + } + } + + status = pci_request_regions(pdev, tdm_driver_name); + if (status) { + printk(KERN_ERR "%s: PCI request regions failed\n", + __FUNCTION__); + tdm_cleanup_device(tdm_dev); + return -EIO; + } + + switch (ent->device) { + case PCI_DEVICE_TDM_UNIT: + TDM_SETUP_DEBUG(KERN_DEBUG "%s: TDM Hardware found..\n", + __FUNCTION__); + num_bars = TDM_UNIT_BARS; + pci_info = &tdm_dev->device; + break; + + default: + printk(KERN_ERR "%s: invalid device 0x%x found.. !!\n", + __FUNCTION__, ent->device); + tdm_cleanup_device(tdm_dev); + return -ENODEV; + } + + /* + * Setup PCI Info structure + */ + pci_info->pdev = pdev; + pci_info->device_id = ent->device; + pci_info->irq = pdev->irq; + for (i = 0; i < num_bars; i++) { + pci_info->num_bars++; + pci_info->pci_bars[i].base_addr = pci_resource_start(pdev, i); + pci_info->pci_bars[i].size = pci_resource_len(pdev, i); + } + + TDM_SETUP_DEBUG(KERN_DEBUG "%s: IRQ_LEVEL: %i \n", __FUNCTION__, + pdev->irq); + + switch (ent->device) { + case PCI_DEVICE_TDM_UNIT: + pci_set_master(pdev); + + /* SET SMIA */ + if (pci_write_config_byte(pdev, PCI_SMIA_REG_OFFSET, + (TDM_INT_FUNCTIONAL | TDM_INT_TRIGGER + | TDM_INT_ERROR))) { + printk(KERN_ERR + "%s: Failed to write SMIA control for TDM \n", + __FUNCTION__); + return -EIO; + } + break; + + default: + printk(KERN_ERR "%s: invalid device 0x%x found..!!\n", + __FUNCTION__, ent->device); + tdm_cleanup_device(tdm_dev); + return -ENODEV; + } + + /* Add device to table */ + if (new_device) { + tdm_device_table_add(tdm_dev); + } + + return status; +} + + + /*********************** INTERRUPT HANDLING ******************************/ + /*There are three possible interrupts that can be generated by the TDM I/O + * Unit. Each interrupt is handled differently by the driver. In the case of + * the Error and Functional interrupts all processing takes place in the + * interrupt handler. The trigger interrupt is handled differently as hssAcc + * API cannot be called in interrupt context. For a trigger interrupt the + * interrupt handler just clears the interrupt and then schedules a work + * queue to handle the necessary hssAcc processing. + */ +void tdm_work_queue_handler(struct work_struct *work) +{ + /*call hssacc */ + icp_HssAccDataPathService(ICP_HSSACC_CHAN_TYPE_HDLC); + icp_HssAccDataPathService(ICP_HSSACC_CHAN_TYPE_VOICE); + +} + +static void tdm_dummy_trigger_handler(void) +{ + /* nothing */ +} + +static tdm_trigger_hardirq_handler trigger_handler = tdm_dummy_trigger_handler; + +/*interrupt handler for tdm I/O unit (ISR Top Half)*/ +static irqreturn_t tdm_interrupt_dispatcher(int irg, void *dev_id) +{ + + uint8_t reg_val = 0; + struct tdm_dev_s *tdm_dev = NULL; + + /* get piu structure */ + tdm_dev = tdm_table_get_device(PCI_DEVICE_TDM_UNIT); + if (tdm_dev == NULL) { + printk(KERN_ERR "%s: no TDM I/O Structure found\n", + __FUNCTION__); + return IRQ_NONE; + } + + pci_read_config_byte(tdm_dev->device.pdev, PCI_INT_TARGET_REG_OFFSET, + ®_val); + + /*If none of the interrupt bits are set then the + * TDM I/O Unit did not trigger an interrupt*/ + if (!(reg_val & (TDM_INT_FUNCTIONAL | TDM_INT_TRIGGER | + TDM_INT_ERROR))) { + return IRQ_NONE; + } + + if (reg_val & TDM_INT_FUNCTIONAL) { + /*call piuMh */ + ixPiuMhIsr(IX_PIUMH_PIUID_PIU0); + } + if (reg_val & TDM_INT_TRIGGER) { + ixPiuDlPiuMgrTriggerInterruptReset(); + trigger_handler(); + } + if (reg_val & TDM_INT_ERROR) { + printk(KERN_CRIT + "%s: TDM I/O Error Detected - Restart the system !\n", + __FUNCTION__); + } + + return IRQ_HANDLED; +} + +void tdm_register_trigger_hardirq_handler(tdm_trigger_hardirq_handler handler) +{ + mb(); + if (handler) + trigger_handler = handler; + else + trigger_handler = tdm_dummy_trigger_handler; + mb(); + msleep(10); // gruik hack +} +EXPORT_SYMBOL(tdm_register_trigger_hardirq_handler); + +/*Bind the interrupt handler for a slot */ +static int bind_irq(unsigned int * vector, char *name) +{ + if (request_irq + (*vector, tdm_interrupt_dispatcher, IRQF_SHARED, name, + vector)) { + printk(KERN_ERR + "%s: failed to bind TDM IRQ Level: %u\n", + __FUNCTION__, *vector); + return -EPERM; + } + + TDM_SETUP_DEBUG(KERN_DEBUG "%s: bind IRQ Level successful: %u\n", + __FUNCTION__, *vector); + return 0; + +} + +/*Unbind the interrupt handler for a slot */ +static void unbind_irq(unsigned int *vector) +{ + free_irq(*vector, vector); +} + +/************************************************************************* +* +* IOCTLS to Initialize the TDM Setup Driver +* +*************************************************************************/ +int tdmdrv_ioctl(struct inode *inode, struct file *filep, + unsigned int cmd, unsigned long arg) +{ + int ret_val = 0; + + switch (cmd) { + case ICP_TDMSETUPDRV_INIT: + ret_val = tdm_init_system(); + if (ret_val != 0) { + printk(KERN_ERR + "%s: TDM system initialization failed !!!\n", + __FUNCTION__); + } + break; + + case ICP_TDMSETUPDRV_UNINIT: + ret_val = tdm_uninit_system(); + if (ret_val != 0) { + printk(KERN_ERR + "%s: TDM system uninitialization failed !!!\n", + __FUNCTION__); + } + break; + + default: + printk(KERN_ERR "%s: Invalid IOCTL !!!\n", __FUNCTION__); + ret_val = -EINVAL; + break; + } + + return ret_val; +} + +/************************************************************************* +* +* Open the TDM Setup driver +* +*************************************************************************/ +int tdmdrv_open(struct inode *inode, struct file *filep) +{ + return 0; +} + +/************************************************************************* +* +* Close the TDM Setup driver +* +*************************************************************************/ +int tdmdrv_close(struct inode *inode, struct file *filep) +{ + return 0; +} + +/* + * Driver init/exit functions + */ +static void tdmdrv_destroy_workqueue(void) +{ + if (tdmdrv_wq) { + destroy_workqueue(tdmdrv_wq); + tdmdrv_wq = NULL; + } +} + +static int __init tdmdrv_init() +{ + int status = 0; + dev_t tdmdrv_dev = 0; + + tdmdrv_wq = create_singlethread_workqueue("tdmdrv"); + if (tdmdrv_wq == NULL) { + printk(KERN_ERR "%s: create_singlethread_workqueue returned " + "NULL\n", __func__); + return -ENOMEM; + } + + status = alloc_chrdev_region(&tdmdrv_dev, tdmdrv_minor, MINOR_NUMS_REQ, + "tdm_setup"); + tdmdrv_major = MAJOR(tdmdrv_dev); + + if (status < 0) { + printk(KERN_ERR "%s: can't get major number %d\n", + __FUNCTION__, tdmdrv_major); + tdmdrv_destroy_workqueue(); + return status; + } + + tdmdrv_dev = MKDEV(tdmdrv_major, tdmdrv_minor); + + /* Setup the cdev structure */ + tdmdrv_cdev = cdev_alloc(); + + cdev_init(tdmdrv_cdev, &tdmdrv_fops); + tdmdrv_cdev->owner = THIS_MODULE; + tdmdrv_cdev->ops = &tdmdrv_fops; + status = cdev_add(tdmdrv_cdev, tdmdrv_dev, MINOR_NUMS_REQ); + + /* Fail gracefully if needs be */ + if (status) { + printk(KERN_ERR "%s: Error %d adding tdmdrv", __FUNCTION__, + status); + unregister_chrdev_region(tdmdrv_dev, MINOR_NUMS_REQ); + tdmdrv_destroy_workqueue(); + return status; + } + + status = pci_register_driver(&tdm_driver); + if (status) { + printk(KERN_ERR "%s: failed call to pci_register_driver\n", + __FUNCTION__); + cdev_del(tdmdrv_cdev); + unregister_chrdev_region(tdmdrv_dev, MINOR_NUMS_REQ); + tdmdrv_destroy_workqueue(); + return status; + } + + if (auto_init == AUTO_INIT_ENABLED) { + status = tdm_init_system(); + if (status) { + printk(KERN_ERR "%s: failed call to tdm_init_devices\n", + __FUNCTION__); + pci_unregister_driver(&tdm_driver); + cdev_del(tdmdrv_cdev); + unregister_chrdev_region(tdmdrv_dev, MINOR_NUMS_REQ); + tdmdrv_destroy_workqueue(); + } + } + return status; +} + +static void __exit tdmdrv_release() +{ + dev_t tdmdrv_dev = MKDEV(tdmdrv_major, tdmdrv_minor); + + if (auto_init == AUTO_INIT_ENABLED) { + if (tdm_uninit_system()) { + printk(KERN_ERR "%s: TDM uninitialization failed\n", + __FUNCTION__); + } + } + + pci_unregister_driver(&tdm_driver); + + /* Remove the cdev and unregister */ + cdev_del(tdmdrv_cdev); + + unregister_chrdev_region(tdmdrv_dev, MINOR_NUMS_REQ); + + tdmdrv_destroy_workqueue(); + + TDM_SETUP_DEBUG(KERN_DEBUG "%s: TDM Driver Released\n", __FUNCTION__); + return; +} + +module_init(tdmdrv_init); +module_exit(tdmdrv_release); diff --git a/Acceleration/firmware/IxPiuMicrocode.dat b/Acceleration/firmware/IxPiuMicrocode.dat Binary files differnew file mode 100644 index 0000000..a8163b0 --- /dev/null +++ b/Acceleration/firmware/IxPiuMicrocode.dat diff --git a/Acceleration/firmware/license.txt b/Acceleration/firmware/license.txt new file mode 100644 index 0000000..ca06205 --- /dev/null +++ b/Acceleration/firmware/license.txt @@ -0,0 +1,11 @@ +Copyright (c) 2007,2008,2009 Intel Corporation. +All rights reserved. +Redistribution. Redistribution and use in binary form, without modification, are permitted provided that the following conditions are met: + + Redistributions must reproduce the above copyright notice and the following disclaimer in the documentation and/or other materials provided with the distribution. + Neither the name of Intel Corporation nor the names of its suppliers may be used to endorse or promote products derived from this software without specific prior written permission. + No reverse engineering, decompilation, or disassembly of this software is permitted. + +Limited patent license. Intel Corporation grants a world-wide, royalty-free, non-exclusive license under patents it now or hereafter owns or controls to make, have made, use, import, offer to sell and sell ("Utilize") this software, but solely to the extent that any such patent is necessary to Utilize the software alone. The patent license shall not apply to any combinations which include this software. No hardware per se is licensed hereunder. + +DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/Acceleration/include/accel_infra/IxPiuDl.h b/Acceleration/include/accel_infra/IxPiuDl.h new file mode 100644 index 0000000..8e0944c --- /dev/null +++ b/Acceleration/include/accel_infra/IxPiuDl.h @@ -0,0 +1,679 @@ +/** + * @file IxPiuDl.h + * + * @date 11 August 2003 + + * @brief This file contains the public API of the PIU Downloader + * component. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +/** + * @defgroup IxPiuDl PIU-Downloader (IxPiuDl) API + * + * @brief The Public API for the PIU Downloader + * + * @{ + */ + +#ifndef IXPIUDL_H +#define IXPIUDL_H + +/* + * Put the user defined include files required + */ +#include "IxOsal.h" + +#include "IxPiuTypes.h" + +/* + * #defines for function return types, etc. + */ + +/** + * @def IX_PIUDL_PARAM_ERR + * + * @brief PiuDl function return value for a parameter error + */ +#define IX_PIUDL_PARAM_ERR 2 + +/** + * @def IX_PIUDL_RESOURCE_ERR + * + * @brief PiuDl function return value for a resource error + */ +#define IX_PIUDL_RESOURCE_ERR 3 + +/** + * @def IX_PIUDL_CRITICAL_PIU_ERR + * + * @brief PiuDl function return value for a Critical PIU error occuring during + download. Assume PIU is left in unstable condition if this value is + returned. + */ +#define IX_PIUDL_CRITICAL_PIU_ERR 4 + +/** + * @def IX_PIUDL_CRITICAL_MICROCODE_ERR + * + * @brief PiuDl function return value for a Critical Microcode error + * discovered during download. Assume PIU is left in unstable condition + * if this value is returned. + */ +#define IX_PIUDL_CRITICAL_MICROCODE_ERR 5 + +/** + * @defgroup PIUImageID PIU Image ID Definition + * + * @ingroup IxPiuDl + * + * @brief Definition of PIU Image ID to be passed to ixPiuDlPiuInitAndStart() + * as input of type ix_uint32 which has the following fields format: + * + * Field [Bit Location] <BR> + * -------------------- <BR> + * PIU ID [31 - 24] <BR> + * PIU Functionality ID [23 - 16] <BR> + * Major Release Number [15 - 8] <BR> + * Minor Release Number [7 - 0] <BR> + * + * + * @{ + */ + + + +/***************************************************************************** + * End of PIU Image Definition * + *****************************************************************************/ +/** + * @} addtogroup PIUImageID + */ + + +/* + * Typedefs + */ + + +/* + * Enums + */ + +/** +* @enum IxPiuDlPiuId +* @brief PiuId numbers to identify PIU 0 or 1 +* @note In this context, For this processor, there is a single +* PIU for HSS functionality.<br> +*/ +typedef enum +{ + IX_PIUDL_PIUID_PIU0 = 0, /**< ID for PIU-0 */ +#if !defined(__tolapai) + IX_PIUDL_PIUID_PIU1, /**< ID for PIU-1 */ +#endif + IX_PIUDL_PIUID_MAX /**< Total Number of PIUs */ +} IxPiuDlPiuId; + +/* + * Typedefs + */ + +/** + * @typedef IxPiuDlFunctionalityId + * @brief Used to make up Functionality ID field of Image Id + * + * @warning <b>THIS typedef HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b> + * It will be removed in a future release. + * See @ref ixPiuDlPiuInitAndStart for more information. + */ +typedef ix_uint8 IxPiuDlFunctionalityId; + +/** + * @typedef IxPiuDlMajor + * @brief Used to make up Major Release field of Image Id + * + * @warning <b>THIS typedef HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b> + * It will be removed in a future release. + * See @ref ixPiuDlPiuInitAndStart for more information. + */ +typedef ix_uint8 IxPiuDlMajor; + +/** + * @typedef IxPiuDlMinor + * @brief Used to make up Minor Revision field of Image Id + * + * @warning <b>THIS typedef HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b> + * It will be removed in a future release. + * See @ref ixPiuDlPiuInitAndStart for more information. + */ +typedef ix_uint8 IxPiuDlMinor; + + +/* + * Structs + */ + +/** + * @brief Image Id to identify each image contained in an image library + * + * @warning <b>THIS struct HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b> + * It will be removed in a future release. + * See @ref ixPiuDlPiuInitAndStart for more information. + */ +typedef struct +{ + IxPiuDlPiuId piuId; /**< PIU ID */ + IxPiuDlFunctionalityId functionalityId; /**< Build ID indicates functionality of image */ + IxPiuDlMajor major; /**< Major Release Number */ + IxPiuDlMinor minor; /**< Minor Revision Number */ +} IxPiuDlImageId; + +#if defined(__tolapai) +/** + * @brief Coprocessor and Instruction decodes needed to define an application + * specific dual coprocessor instruction + */ +typedef struct +{ + ix_uint32 copr0; /**< coprocessor 0 decode */ + ix_uint32 inst0; /**< coprocessor 0 instruction decode */ + ix_uint32 copr1; /**< coprocessor 1 decode */ + ix_uint32 inst1; /**< coprocessor 1 instruction decode */ +} IxPiuDlAppDualInstruction; +#endif // #if defined(__tolapai) + +/* + * Prototypes for interface functions + */ + +#if defined(__tolapai) +/** + * @ingroup IxPiuDl + * + * @fn ix_error ixPiuDlPhysicalAddressSet ( + * IxPiuDlPiuId piuId, + * ix_uint32 address) + * + * @brief This function sets the physical base address for the given PIU. + * + * @param piuId @ref IxPiuDlPiuId [in] - The ID of the PIU whose physical base + * address will be set + * @param address ix_uint32 [in] - The address to set the physical address to + * + * This function sets the physical base address for the given PIU. It must be + * called when the piuDl component is not initialized i.e. prior to calling the + * @ref ixPiuDlPiuInitAndStart function (maps the physical address to a virtual + * address) or after calling the @ref ixPiuDlUnload function. + * + * @return + * - IX_SUCCESS if the address was set successfully + * - IX_PIUDL_PARAM_ERR if a parameter error occured + * - IX_FAIL if the function is called after memory has been initialised + */ +ix_error +ixPiuDlPhysicalAddressSet ( + IxPiuDlPiuId piuId, + ix_uint32 address); + +#endif // #if defined(__tolapai) + +/** + * @ingroup IxPiuDl + * + * @fn ix_error ixPiuDlPiuInitAndStart (ix_uint32 piuImageId) + * + * @brief Stop, reset, download microcode (firmware) and finally start PIU. + * + * @param piuImageId ix_uint32 [in] - Id of the microcode image to download. + * + * This function locates the image specified by the <i>imageId</i> parameter + * from the default microcode image library which is included internally by + * this component. + * It then stops and resets the PIU, loads the firmware image onto the PIU, + * and then restarts the PIU. + * + * <BR><B>Run-time behaviour:</B> This function is blocking and not re-entrant. + * + * @note A list of valid image IDs is included in this header file. + * See #defines with prefix IX_PIUDL_PIUIMAGE_... + * + * @pre + * - The Client is responsible for ensuring mutual access to the PIU. + * @post + * - The PIU Instruction Pipeline will be cleared if State Information + * has been downloaded. + * - If the download fails with a critical error, the PIU may + * be left in an ususable state. + * @return + * - IX_SUCCESS if the download was successful; + * - IX_PIUDL_PARAM_ERR if a parameter error occured + * - IX_PIUDL_CRITICAL_PIU_ERR if a critical PIU error occured during + * download + * - IX_PIUDL_CRITICAL_MICROCODE_ERR if a critical microcode error + * occured during download + * - IX_FAIL if PIU is not available or image is failed to be located. + * A warning is issued if the PIU is not present. + */ +ix_error +ixPiuDlPiuInitAndStart (ix_uint32 piuImageId); + +/** + * @ingroup IxPiuDl + * + * @fn ix_error ixPiuDlCustomImagePiuInitAndStart (ix_uint32 *imageLibrary, + ix_uint32 piuImageId) + * + * @brief Stop, reset, download microcode (firmware) and finally start PIU + * + * @param piuImageId ix_uint32 [in] - Id of the microcode image to download. + * @param imageLibrary ix_uint32* [in] - Pointer to the microcode image library. + * + * This function locates the image specified by the <i>imageId</i> parameter + * from the specified microcode image library which is pointed to by the + * <i>imageLibrary</i> parameter. + * It then stops and resets the PIU, loads the firmware image onto the PIU, + * and then restarts the PIU. + * + * This is a facility for users who wish to use an image from an external + * library of PIU firmware images. To use a standard image from the + * built-in library, see @ref ixPiuDlPiuInitAndStart instead. + * + * <BR><B>Run-time behaviour:</B> This function is blocking and not re-entrant. + * + * @note A list of valid image IDs is included in this header file. + * See #defines with prefix IX_PIUDL_PIUIMAGE_... + * + * @pre + * - The Client is responsible for ensuring mutual access to the PIU. + * - The image library supplied must be in the correct format for use + * by the PIU Downloader (IxPiuDl) component. Details of the library + * format are contained in the Functional Specification document for + * IxPiuDl. + * @post + * - The PIU Instruction Pipeline will be cleared if State Information + * has been downloaded. + * - If the download fails with a critical error, the PIU may + * be left in an ususable state. + * @return + * - IX_SUCCESS if the download was successful; + * - IX_PIUDL_PARAM_ERR if a parameter error occured + * - IX_PIUDL_CRITICAL_PIU_ERR if a critical PIU error occured during + * download + * - IX_PIUDL_CRITICAL_MICROCODE_ERR if a critical microcode error + * occured during download + * - IX_FAIL if PIU is not available or image is failed to be located. + * A warning is issued if the PIU is not present. + */ +ix_error +ixPiuDlCustomImagePiuInitAndStart (ix_uint32 *imageLibrary, + ix_uint32 piuImageId); + + +/** + * @ingroup IxPiuDl + * + * @fn ix_error ixPiuDlPiuStopAndReset (IxPiuDlPiuId piuId) + * + * @brief Stops and Resets an PIU + * + * @param IxPiuDlPiuId [in] piuId - Id of the target PIU. + * + * This function performs a soft PIU reset by writing reset values to + * particular PIU registers. Note that this does not reset PIU co-processors. + * This implicitly stops PIU code execution before resetting the PIU. + * + * @note It is not necessary to call this function before downloading a new + * image to the PIU. It is left on the API only to allow greater control of PIU + * execution if required. Where appropriate, use @ref ixPiuDlPiuInitAndStart + * or @ref ixPiuDlCustomImagePiuInitAndStart instead. + * + * @pre + * - The Client is responsible for ensuring mutual access to the PIU. + * + * @post + * + * @return + * - IX_SUCCESS if the operation was successful + * - IX_PIUDL_PARAM_ERR if a parameter error occured + * - IX_FAIL otherwise + */ +ix_error +ixPiuDlPiuStopAndReset (IxPiuDlPiuId piuId); + +/** + * @ingroup IxPiuDl + * + * @fn ix_error ixPiuDlUnload (void) + * + * @brief This function will uninitialise the IxPiuDl component. + * + * This function will uninitialise the IxPiuDl component. It should only be + * called once, and only if the IxPiuDl component has already been initialised by + * calling any of the following functions: + * - @ref ixPiuDlPiuInitAndStart + * - @ref ixPiuDlCustomImagePiuInitAndStart + * + * If possible, this function should be called before a soft reboot or unloading + * a kernel module to perform any clean up operations required for IxPiuDl. + * + * The following actions will be performed by this function: + * - Unmapping of any kernel memory mapped by IxPiuDl + * + * <BR><B>Run-time behaviour:</B> This function is not blocking and not re-entrant. + * + * @return + * - IX_SUCCESS if the operation was successful + * - IX_FAIL otherwise + */ + +ix_error ixPiuDlUnload (void); + +/** + * @ingroup IxPiuDl + * + * @fn void ixPiuDlStatsShow (void) + * + * @brief This function will display run-time statistics from the IxPiuDl + * component + * + * <BR><B>Run-time behaviour:</B> This function is blocking and not re-entrant. + * + * @return none + */ +void +ixPiuDlStatsShow (void); + +/** + * @ingroup IxPiuDl + * + * @fn void ixPiuDlStatsReset (void) + * + * @brief This function will reset the statistics of the IxPiuDl component + * + * <BR><B>Run-time behaviour:</B> This function is not blocking and is re-entrant. + * + * @return none + */ +void +ixPiuDlStatsReset (void); + + + +/** + * @ingroup IxPiuDl + * + * @fn ix_error ixPiuDlLoadedImageGet (IxPiuDlPiuId piuId, + IxPiuDlImageId *imageIdPtr) + * + * @brief Gets the Id of the image currently loaded on a particular PIU + * + * @param piuId IxPiuDlPiuId [in] - Id of the target PIU. + * @param imageIdPtr IxPiuDlImageId* [out] - Pointer to the where the + * image id should be stored. + * + * If an image of microcode was previously downloaded successfully to the PIU + * by PIU Downloader, this function returns in <i>imageIdPtr</i> the image + * Id of that image loaded on the PIU. + * + * <BR><B>Run-time behaviour:</B> This function is not blocking and is re-entrant. + * + * @pre + * - The Client has allocated memory to the <i>imageIdPtr</i> pointer. + * + * @post + * + * @return + * - IX_SUCCESS if the operation was successful + * - IX_PIUDL_PARAM_ERR if a parameter error occured + * - IX_FAIL if the PIU doesn't currently have a image loaded + */ +ix_error +ixPiuDlLoadedImageGet (IxPiuDlPiuId piuId, + IxPiuDlImageId *imageIdPtr); + + + +/** + * @ingroup IxPiuDl + * + * @fn ix_error ixPiuDlAvailableImagesListGet (IxPiuDlImageId *imageIdListPtr, + ix_uint32 *listSizePtr) + * + * @brief Get a list of the images available in a microcode image library + * + * @param imageIdListPtr IxPiuDlImageId* [out] - Array to contain list of + * image Ids (memory + * allocated by Client). + * @param listSizePtr ix_uint32* [inout] - As an input, this param should point + * to the max number of Ids the + * <i>imageIdListPtr</i> array can + * hold. PiuDl will replace the input + * value of this parameter with the + * number of image Ids actually filled + * into the array before returning. + * + * Finds list of images available in the microcode image library. + * Fills these into the array pointed to by <i>imageIdListPtr</i> + * + * <BR><B>Run-time behaviour:</B> This function is not blocking and is re-entrant. + * + * @pre + * - The Client should declare the variable to which numImagesPtr points + * - The Client should create an array (<i>imageIdListPtr</i>) large + * enough to contain all the image Ids in the image library + * + * @post + * + * @return + * - IX_SUCCESS if the operation was successful + * - IX_PIUDL_PARAM_ERR if a parameter error occured + * - IX_FAIL otherwise + */ +ix_error +ixPiuDlAvailableImagesListGet (IxPiuDlImageId *imageIdListPtr, + ix_uint32 *listSizePtr); + + + + +/** + * @ingroup IxPiuDl + * + * @fn ix_error ixPiuDlPiuMgrPiuResetAssert ( IxPiuDlPiuId piuId) + * + * @brief Puts the designated PIU into the reset state. + * any previously downloaded firmware image will be lost. + * + * @param piuId IxPiuDlPiuId [in] - Id of the target PIU. + * + * <BR><B>Run-time behaviour:</B> This function is not blocking and is re-entrant. + * + * @pre + * none + * + * @post + * + * @return + * - IX_SUCCESS if the operation was successful + * - IX_FAIL incorrect PIU Id. + */ +ix_error +ixPiuDlPiuMgrPiuResetAssert ( IxPiuDlPiuId piuId); + +/** + * @ingroup IxPiuDl + * + * @fn ix_error ixPiuDlPiuMgrPiuResetDeassert ( IxPiuDlPiuId piuId) + * + * @brief takes the designated PIU out of the reset state + * + * @param piuId IxPiuDlPiuId [in] - Id of the target PIU. + * + * <BR><B>Run-time behaviour:</B> This function is not blocking and is re-entrant. + * + * @pre + * none + * + * @post + * + * @return + * - IX_SUCCESS if the operation was successful + * - IX_FAIL incorrect PIU Id. + */ +ix_error +ixPiuDlPiuMgrPiuResetDeassert (IxPiuDlPiuId piuId); + + +/** + * @ingroup IxPiuDl + * + * @fn void ixPiuDlPiuMgrTriggerInterruptReset (void) + * + * @brief reset the PIU Trigger interrupt source (2). + * (this interrupt is triggered by PIU 1 firmware) + * + * <BR><B>Run-time behaviour:</B> This function is not blocking and is re-entrant. + * + * @return none + */ +void +ixPiuDlPiuMgrTriggerInterruptReset (void); + +#if defined(__tolapai) +/** + * @ingroup IxPiuDl + * + * @fn ix_error ixPiuDlAppDualSet ( + * IxPiuDlPiuId piuId, + * ix_uint32 appDualId, + * IxPiuDlAppDualInstruction *appDualInstruction ) + * + * @brief This function configures an PIU application specific dual coprocessor + * instruction + * + * @param piuId IxPiuDlPiuId [in] - Id of the target PIU. + * @param appDualId ix_uint32 [in] - The application specific dual coprocessor + * instruction Id + * @param IxPiuDlAppDualInstruction appDualInstruction [in] - pointer to an + * application specific dual coprocessor instruction structure + * + * This function configures an PIU application specific dual coprocessor + * instruction which allows 2 arbitrary coprocessor instructions to execute + * at the same time. + * + * @return + * - IX_SUCCESS if the dual instruction was set successfully + * - IX_PIUDL_PARAM_ERR if a parameter error occurred + * - IX_FAIL if the verification of the register write fails + */ +ix_error +ixPiuDlAppDualSet ( + IxPiuDlPiuId piuId, + ix_uint32 appDualId, + IxPiuDlAppDualInstruction *appDualInstruction +); + +/** + * @ingroup IxPiuDl + * + * @fn ix_error ixPiuDlAppDualGet ( + * IxPiuDlPiuId piuId, + * ix_uint32 appDualId, + * IxPiuDlAppDualInstruction *appDualInstruction + * ) + * + * @brief This function retrieves the fields of an PIU application specific + * dual coprocessor instruction register + * + * @param piuId IxPiuDlPiuId [in] - Id of the target PIU. + * @param appDualId ix_uint32 [in] - The application specific dual coprocessor + * instruction Id + * @param IxPiuDlAppDualInstruction appDualInstruction [out] - pointer to an + * application specific dual coprocessor instruction structure which will be + * filled by this function + * + * This function retrieves the fields of an PIU application specific dual + * coprocessor instruction. + * + * @return + * - IX_SUCCESS if the dual instruction was set successfully + * - IX_PIUDL_PARAM_ERR if a parameter error occurred + */ + +ix_error +ixPiuDlAppDualGet ( + IxPiuDlPiuId piuId, + ix_uint32 appDualId, + IxPiuDlAppDualInstruction *appDualInstruction +); + +#endif // #if defined(__tolapai) + +#endif /* IXPIUDL_H */ + +/** + * @} defgroup IxPiuDl + */ + + diff --git a/Acceleration/include/accel_infra/IxPiuMh.h b/Acceleration/include/accel_infra/IxPiuMh.h new file mode 100644 index 0000000..09a3efe --- /dev/null +++ b/Acceleration/include/accel_infra/IxPiuMh.h @@ -0,0 +1,603 @@ +/** + * @file IxPiuMh.h + * + * @date 14 Dec 2001 + * + * @brief This file contains the public API for the PIU Message + * Handler component. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + +/** + * @defgroup IxPiuMh Intel (R) Software PIU Message Handler (IxPiuMh) API + * + * @brief The public API for the PIU Message Handler component. + * + * @{ + */ + +#ifndef IXPIUMH_H +#define IXPIUMH_H + +#include "IxOsal.h" + +/* + * #defines for function return types, etc. + */ + +#define IX_PIUMH_MIN_MESSAGE_ID (0x00) /**< minimum valid message ID */ +#define IX_PIUMH_MAX_MESSAGE_ID (0xFF) /**< maximum valid message ID */ + +#define IX_PIUMH_SEND_RETRIES_DEFAULT (3) /**< default msg send retries */ + + +/** + * @def IX_PIUMH_CRITICAL_PIU_ERR + * + * @brief PiuMH function return value for a Critical PIU error occuring during + sending/receiving message. Assume PIU hang / halt if this value is + returned. + */ +#define IX_PIUMH_CRITICAL_PIU_ERR 2 + +/** + * @enum IxPiuMhPiuId + * + * @brief The ID of a particular PIU. + */ + +typedef enum +{ +#if defined(__ixp23xx) + IX_PIUMH_PIUID_PIU0 = 0, /**< ID for PIU-0 */ + IX_PIUMH_PIUID_PIU1, /**< ID for PIU-1 */ +#endif +#if defined(__tolapai) + IX_PIUMH_PIUID_PIU0 = 0, /**< ID for PIU-0 */ +#endif +#if defined(__ixp42X) || defined(__ixp46X) || defined(__ixp5XX) + IX_PIUMH_PIUID_PIUA = 0, /**< Identifies PIU A */ + IX_PIUMH_PIUID_PIUB, /**< Identifies PIU B */ +#endif +#if defined(__ixp42X) || defined(__ixp46X) && !defined(__ixp5XX) + IX_PIUMH_PIUID_PIUC, /**< Identifies PIU C */ +#endif /* defined(__ixp42X) || defined(__ixp46X) && !defined(__ixp5XX) */ + IX_PIUMH_NUM_PIUS /**< Number of PIUs */ +} IxPiuMhPiuId; + + +/** + * @enum IxPiuMhPiuInterrupts + * + * @brief Indicator specifying whether or not PIU interrupts should drive + * receiving of messages from the PIUs. + */ + +typedef enum +{ + IX_PIUMH_PIUINTERRUPTS_NO = 0, /**< Don't use PIU interrupts */ + IX_PIUMH_PIUINTERRUPTS_YES /**< Do use PIU interrupts */ +} IxPiuMhPiuInterrupts; + +/** + * @brief The 2-word message structure to send to and receive from the + * PIUs. + */ + +typedef struct +{ + UINT32 data[2]; /**< the actual data of the message */ +} IxPiuMhMessage; + +/** message ID */ +typedef UINT32 IxPiuMhMessageId; + +/** + * @typedef IxPiuMhCallback + * + * @brief This prototype shows the format of a message callback function. + * + * This prototype shows the format of a message callback function. The + * message callback will be passed the message to be handled and will also + * be told from which PIU the message was received. The message callback + * will either be registered by ixPiuMhUnsolicitedCallbackRegister() or + * passed as a parameter to ixPiuMhMessageWithResponseSend(). It will be + * called from within an ISR triggered by the PIU's "outFIFO not empty" + * interrupt (see ixPiuMhInitialize()). The parameters passed are the ID + * of the PIU that the message was received from, and the message to be + * handled.<P><B>Re-entrancy:</B> This function is only a prototype, and + * will be implemented by the client. It does not need to be re-entrant. + */ + +typedef void (*IxPiuMhCallback) (IxPiuMhPiuId, IxPiuMhMessage); + +/* + * Prototypes for interface functions. + */ + +#if defined(__tolapai) +/** + * @ingroup IxPiuMh + * + * @fn IX_STATUS ixPiuMhPhysicalAddressSet ( + * IxPiuMhPiuId piuId, + * UINT32 address) + * + * @brief This function sets the physical base address for the given PIU. + * + * @param piuId @ref IxPiuMhPiuId [in] - The ID of the PIU whose physical base + * address will be set + * @param address UINT32 [in] - The address to set the physical address to + * + * This function sets the physical base address for the given PIU. It must be + * called when the piuMh component is not initialized i.e. prior to calling the + * @ref ixPiuMhInitialize function (maps the physical address to a virtual + * address) or after calling the @ref ixPiuMhUnload function. + * + * @return The function returns a status indicating success or failure. + */ +PUBLIC IX_STATUS ixPiuMhPhysicalAddressSet ( + IxPiuMhPiuId piuId, + UINT32 address); + +/** + * @ingroup IxPiuMh + * + * @fn IX_STATUS ixPiuMhInterruptIdSet ( + * IxPiuMhPiuId piuId, + * UINT32 interruptId) + * + * @brief This function sets the interruptId for the given piu + * + * @param piuId @ref IxPiuMhPiuId [in] - The ID of the PIU whose physical base + * address will be set + * @param interruptId UINT32 [in] - The interrupt ID + * + * This function sets the interrupt ID for the given PIU. It must be + * called when the piuMh component is not initialized i.e. prior to calling the + * @ref ixPiuMhInitialize function or after calling the @ref ixPiuMhUnload + * function. + * + * @return The function returns a status indicating success or failure. + */ +PUBLIC IX_STATUS ixPiuMhInterruptIdSet ( + IxPiuMhPiuId piuId, + UINT32 interruptId); + +#endif // #if defined(__tolapai) + + + +/** + * @ingroup IxPiuMh + * + * @fn void ixPiuMhIsr (void *parameter) + * + * @brief This function is the piuMh interrupt handler which is called to + * receive messages from an PIU + * + * @param parameter void [in] - a parameter passed to the routine - in the case + * of piuMh the parameter is the piuId + * + * This function is called by an external component which has registered an + * interrupt handler for handling PIU interrupts - the PIU has multiple + * external interrupt lines, but in some platforms these are coalesced into + * a single interrupt as far as the main processor is concerned - in those + * cases it is better to register the interrupt handler in an external + * component which calls several components to handle each interrupt type + * with the piuMh component being on type + * + * @return nothing + */ +void ixPiuMhIsr (void *parameter); + + +/** + * @ingroup IxPiuMh + * + * @fn IX_STATUS ixPiuMhInitialize ( + IxPiuMhPiuInterrupts piuInterrupts) + * + * @brief This function will initialise the IxPiuMh component. + * + * @param piuInterrupts @ref IxPiuMhPiuInterrupts [in] - This parameter + * dictates whether or not the IxPiuMh component will service PIU "outFIFO + * not empty" interrupts to trigger receiving and processing of messages + * from the PIUs. If not then the client must use ixPiuMhMessagesReceive() + * to control message receiving and processing. + * + * This function will initialise the IxPiuMh component. It should only be + * called once, prior to using the IxPiuMh component. The following + * actions will be performed by this function:<OL><LI>Initialization of + * internal data structures (e.g. solicited and unsolicited callback + * tables).</LI><LI>Configuration of the interface with the PIUs (e.g. + * enabling of PIU "outFIFO not empty" interrupts).</LI><LI>Registration of + * ISRs that will receive and handle messages when the PIUs' "outFIFO not + * empty" interrupts fire (if piuInterrupts equals + * IX_PIUMH_PIUINTERRUPTS_YES).</LI></OL> + * + * @return The function returns a status indicating success or failure. + */ + +PUBLIC IX_STATUS ixPiuMhInitialize ( + IxPiuMhPiuInterrupts piuInterrupts); + +/** + * @ingroup IxPiuMh + * + * @fn IX_STATUS ixPiuMhUnload (void) + * + * @brief This function will uninitialise the IxPiuMh component. + * + * This function will uninitialise the IxPiuMh component. It should only be + * called once, and only if the IxPiuMh component has already been initialised. + * No other IxPiuMh API functions should be called until @ref ixPiuMhInitialize + * is called again. + * If possible, this function should be called before a soft reboot or unloading + * a kernel module to perform any clean up operations required for IxPiuMh. + * + * The following actions will be performed by this function: + * <OL><LI>Unmapping of kernel memory mapped by the function + * @ref ixPiuMhInitialize.</LI></OL> + * + * @return The function returns a status indicating success or failure. + */ + +PUBLIC IX_STATUS ixPiuMhUnload (void); + +/** + * @ingroup IxPiuMh + * + * @fn IX_STATUS ixPiuMhUnsolicitedCallbackRegister ( + IxPiuMhPiuId piuId, + IxPiuMhMessageId messageId, + IxPiuMhCallback unsolicitedCallback) + * + * @brief This function will register an unsolicited callback for a + * particular PIU and message ID. + * + * @param piuId @ref IxPiuMhPiuId [in] - The ID of the PIU whose messages + * the unsolicited callback will handle. + * @param messageId @ref IxPiuMhMessageId [in] - The ID of the messages the + * unsolicited callback will handle. + * @param unsolicitedCallback @ref IxPiuMhCallback [in] - The unsolicited + * callback function. A value of NULL will deregister any previously + * registered callback for this PIU and message ID. + * + * This function will register an unsolicited message callback for a + * particular PIU and message ID.<P>If an unsolicited callback is already + * registered for the specified PIU and message ID then the callback will + * be overwritten. Only one client will be responsible for handling a + * particular message ID associated with a PIU. Registering a NULL + * unsolicited callback will deregister any previously registered + * callback.<P>The callback function will be called from an ISR that will + * be triggered by the PIU's "outFIFO not empty" interrupt (see + * ixPiuMhInitialize()) to handle any unsolicited messages of the specific + * message ID received from the PIU. Unsolicited messages will be handled + * in the order they are received.<P>If no unsolicited callback can be + * found for a received message then it is assumed that the message is + * solicited.<P>If more than one client may be interested in a particular + * unsolicited message then the suggested strategy is to register a + * callback for the message that can itself distribute the message to + * multiple clients as necessary.<P>See also + * ixPiuMhUnsolicitedCallbackForRangeRegister().<P><B>Re-entrancy:</B> This + * function will be callable from any thread at any time. IxOsal + * will be used for any necessary resource protection. + * + * @return The function returns a status indicating success or failure. + */ + +PUBLIC IX_STATUS ixPiuMhUnsolicitedCallbackRegister ( + IxPiuMhPiuId piuId, + IxPiuMhMessageId messageId, + IxPiuMhCallback unsolicitedCallback); + +/** + * @ingroup IxPiuMh + * + * @fn IX_STATUS ixPiuMhUnsolicitedCallbackForRangeRegister ( + IxPiuMhPiuId piuId, + IxPiuMhMessageId minMessageId, + IxPiuMhMessageId maxMessageId, + IxPiuMhCallback unsolicitedCallback) + * + * @brief This function will register an unsolicited callback for a + * particular PIU and range of message IDs. + * + * @param piuId @ref IxPiuMhPiuId [in] - The ID of the PIU whose messages the + * unsolicited callback will handle. + * @param minMessageId @ref IxPiuMhMessageId [in] - The minimum message ID in + * the range of message IDs the unsolicited callback will handle. + * @param maxMessageId @ref IxPiuMhMessageId [in] - The maximum message ID in + * the range of message IDs the unsolicited callback will handle. + * @param unsolicitedCallback @ref IxPiuMhCallback [in] - The unsolicited + * callback function. A value of NULL will deregister any previously + * registered callback(s) for this PIU and range of message IDs. + * + * This function will register an unsolicited callback for a particular PIU + * and range of message IDs. It is a convenience function that is + * effectively the same as calling ixPiuMhUnsolicitedCallbackRegister() for + * each ID in the specified range. See + * ixPiuMhUnsolicitedCallbackRegister() for more + * information.<P><B>Re-entrancy:</B> This function will be callable from + * any thread at any time. IxOsal will be used for any necessary + * resource protection. + * + * @return The function returns a status indicating success or failure. + */ + +PUBLIC IX_STATUS ixPiuMhUnsolicitedCallbackForRangeRegister ( + IxPiuMhPiuId piuId, + IxPiuMhMessageId minMessageId, + IxPiuMhMessageId maxMessageId, + IxPiuMhCallback unsolicitedCallback); + +/** + * @ingroup IxPiuMh + * + * @fn IX_STATUS ixPiuMhMessageSend ( + IxPiuMhPiuId piuId, + IxPiuMhMessage message, + UINT32 maxSendRetries) + * + * @brief This function will send a message to a particular PIU. + * + * @param piuId @ref IxPiuMhPiuId [in] - The ID of the PIU to send the message + * to. + * @param message @ref IxPiuMhMessage [in] - The message to send. + * @param maxSendRetries UINT32 [in] - Max num. of retries to perform + * if the PIU's inFIFO is full. + * + * This function will send a message to a particular PIU. It will be the + * client's responsibility to ensure that the message is properly formed. + * The return status will signify to the client if the message was + * successfully sent or not.<P>If the message is sent to the PIU then this + * function will return a status of success. Note that this will only mean + * the message has been placed in the PIU's inFIFO. There will be no way + * of knowing that the PIU has actually read the message, but once in the + * incoming message queue it will be safe to assume that the PIU will + * process it. + * <P>The inFIFO may fill up sometimes if the Xscale is sending messages + * faster than the PIU can handle them. This forces us to retry attempts + * to send the message until the PIU services the inFIFO. The client should + * specify a ceiling value for the number of retries suitable to their + * needs. IX_PIUMH_SEND_RETRIES_DEFAULT can be used as a default value for + * the <i>maxSendRetries</i> parameter for this function. Each retry + * exceeding this default number will incur a blocking delay of 1 microsecond, + * to avoid consuming too much AHB bus bandwidth while performing retries. + * <P>Note this function <B>must</B> only be used for messages. + * that do not solicit responses. If the message being sent will solicit a + * response then the ixPiuMhMessageWithResponseSend() function <B>must</B> + * be used to ensure that the response is correctly + * handled. <P> This function will return timeout status if PIU hang / halt + * while sending message. The timeout error is not related to the + * <i>maxSendRetries</i> as mentioned above. The timeout error will only occur + * if the first word of the message has been sent to PIU (not exceeding + * <i>maxSendRetries</i> when sending 1st message word), but the second word of + * the message can't be written to PIU's inFIFO due to PIU hang / halt after + * maximum waiting time (IX_PIU_MH_MAX_NUM_OF_RETRIES). + * <P><B>Re-entrancy:</B> This function will be callable from any + * thread at any time. IxOsal will be used for any necessary + * resource protection. + * + * @return The function returns a status indicating success, failure or timeout. + */ + +PUBLIC IX_STATUS ixPiuMhMessageSend ( + IxPiuMhPiuId piuId, + IxPiuMhMessage message, + UINT32 maxSendRetries); + +/** + * @ingroup IxPiuMh + * + * @fn IX_STATUS ixPiuMhMessageWithResponseSend ( + IxPiuMhPiuId piuId, + IxPiuMhMessage message, + IxPiuMhMessageId solicitedMessageId, + IxPiuMhCallback solicitedCallback, + UINT32 maxSendRetries) + * + * @brief This function is equivalent to the ixPiuMhMessageSend() function, + * but must be used when the message being sent will solicited a response. + * + * @param piuId @ref IxPiuMhPiuId [in] - The ID of the PIU to send the message + * to. + * @param message @ref IxPiuMhMessage [in] - The message to send. + * @param solicitedMessageId @ref IxPiuMhMessageId [in] - The ID of the + * solicited response message. + * @param solicitedCallback @ref IxPiuMhCallback [in] - The function to use to + * pass the response message back to the client. A value of NULL will + * cause the response message to be discarded. + * @param maxSendRetries UINT32 [in] - Max num. of retries to perform + * if the PIU's inFIFO is full. + * + * This function is equivalent to the ixPiuMhMessageSend() function, but + * must be used when the message being sent will solicited a + * response.<P>The client must specify the ID of the solicited response + * message to allow the response to be recognised when it is received. The + * client must also specify a callback function to handle the received + * response. The IxPiuMh component will not offer the facility to send a + * message to a PIU and receive a response within the same context.<P>Note + * if the client is not interested in the response, specifying a NULL + * callback will cause the response message to be discarded.<P>The + * solicited callback will be stored and called some time later from an ISR + * that will be triggered by the PIU's "outFIFO not empty" interrupt (see + * ixPiuMhInitialize()) to handle the response message corresponding to the + * message sent. Response messages will be handled in the order they are + * received.<P> + * <P>The inFIFO may fill up sometimes if the Xscale is sending messages + * faster than the PIU can handle them. This forces us to retry attempts + * to send the message until the PIU services the inFIFO. The client should + * specify a ceiling value for the number of retries suitable to their + * needs. IX_PIUMH_SEND_RETRIES_DEFAULT can be used as a default value for + * the <i>maxSendRetries</i> parameter for this function. Each retry + * exceeding this default number will incur a blocking delay of 1 microsecond, + * to avoid consuming too much AHB bus bandwidth while performing retries. + * <P> This function will return timeout status if PIU hang / halt + * while sending message. The timeout error is not related to the + * <i>maxSendRetries</i> as mentioned above. The timeout error will only occur + * if the first word of the message has been sent to PIU (not exceeding + * <i>maxSendRetries</i> when sending 1st message word), but the second word of + * the message can't be written to PIU's inFIFO due to PIU hang / halt after + * maximum waiting time (IX_PIU_MH_MAX_NUM_OF_RETRIES). + * <P><B>Re-entrancy:</B> This function will be callable from any + * thread at any time. IxOsal will be used for any necessary + * resource protection. + * + * @return The function returns a status indicating success or failure. + */ + +PUBLIC IX_STATUS ixPiuMhMessageWithResponseSend ( + IxPiuMhPiuId piuId, + IxPiuMhMessage message, + IxPiuMhMessageId solicitedMessageId, + IxPiuMhCallback solicitedCallback, + UINT32 maxSendRetries); + +/** + * @ingroup IxPiuMh + * + * @fn IX_STATUS ixPiuMhMessagesReceive ( + IxPiuMhPiuId piuId) + * + * @brief This function will receive messages from a particular PIU and + * pass each message to the client via a solicited callback (for solicited + * messages) or an unsolicited callback (for unsolicited messages). + * + * @param piuId @ref IxPiuMhPiuId [in] - The ID of the PIU to receive and + * process messages from. + * + * This function will receive messages from a particular PIU and pass each + * message to the client via a solicited callback (for solicited messages) + * or an unsolicited callback (for unsolicited messages).<P>If the IxPiuMh + * component is initialised to service PIU "outFIFO not empty" interrupts + * (see ixPiuMhInitialize()) then there is no need to call this function. + * This function is only provided as an alternative mechanism to control + * the receiving and processing of messages from the PIUs.<P> This function + * will return timeout status if PIU hang / halt while receiving message. The + * timeout error will only occur if this function has read the first word of + * the message and can't read second word of the message from PIU's outFIFO + * after maximum retries (IX_PIU_MH_MAX_NUM_OF_RETRIES). + * <P>Note this function cannot be called from within + * an ISR as it will use resource protection mechanisms.<P><B>Re-entrancy:</B> + * This function will be callable from any thread at any time. IxOsal will be + * used for any necessary resource protection. + * + * @return The function returns a status indicating success, failure or timeout. + */ + +PUBLIC IX_STATUS ixPiuMhMessagesReceive ( + IxPiuMhPiuId piuId); + +/** + * @ingroup IxPiuMh + * + * @fn IX_STATUS ixPiuMhShow ( + IxPiuMhPiuId piuId) + * + * @brief This function will display the current state of the IxPiuMh + * component. + * + * <B>Re-entrancy:</B> This function will be callable from + * any thread at any time. However, no resource protection will be used + * so as not to impact system performance. As this function is only + * reading statistical information then this is acceptable. + * + * @param piuId @ref IxPiuMhPiuId [in] - The ID of the PIU to display state + * information for. + * + * @return The function returns a status indicating success or failure. + */ + +PUBLIC IX_STATUS ixPiuMhShow ( + IxPiuMhPiuId piuId); + +/** + * @ingroup IxPiuMh + * + * @fn IX_STATUS ixPiuMhShowReset ( + IxPiuMhPiuId piuId) + * + * @brief This function will reset the current state of the IxPiuMh + * component. + * + * <B>Re-entrancy:</B> This function will be callable from + * any thread at any time. However, no resource protection will be used + * so as not to impact system performance. As this function is only + * writing statistical information then this is acceptable. + * + * @param piuId @ref IxPiuMhPiuId [in] - The ID of the PIU to reset state + * information for. + * + * @return The function returns a status indicating success or failure. + */ + +PUBLIC IX_STATUS ixPiuMhShowReset ( + IxPiuMhPiuId piuId); + +#endif /* IXPIUMH_H */ + +/** + * @} defgroup IxPiuMh + */ diff --git a/Acceleration/include/accel_infra/IxPiuTypes.h b/Acceleration/include/accel_infra/IxPiuTypes.h new file mode 100644 index 0000000..aa92ede --- /dev/null +++ b/Acceleration/include/accel_infra/IxPiuTypes.h @@ -0,0 +1,141 @@ +/** + * @file IxPiuTypes.h + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + + +#ifndef IXPIUTYPES_INC +#define IXPIUTYPES_INC + +/** + * Put the system defined include files required. + */ + +#include "icp.h" + + +/** + * Boolean TRUE and FALSE definitions + */ +#if !defined(TRUE) || (TRUE != 1) +/* Basic type - wrapped as not to redefine them if VxWorks does */ +#ifndef __INCvxTypesOldh +#define TRUE 1 +#endif /* TRUE */ +#if !defined(FALSE) || (FALSE != 0) +#define FALSE 0 +#endif +#endif /* FALSE */ + +#if !defined(__tolapai) && !defined(__ixp23xx) +#if !defined(BOOL) +typedef int BOOL; +#endif +#endif + +/** + * definition of NULL + */ +#ifndef NULL +#define NULL 0L +#endif /* NULL */ + + +#if !defined( IX_SUCCESS ) +#define IX_SUCCESS (ICP_STATUS_SUCCESS) +#endif + +#if !defined( IX_FAIL ) +#define IX_FAIL (ICP_STATUS_FAIL) +#endif + +#if !defined(PIU_PRIVATE) +#define PIU_PRIVATE static +#else +#define PIU_PRIVATE +#endif + + +/* + * Mechanism to validate the upper (MAX) and lower (0) bounds + * of a positive enumeration + * + * param int [in] VALUE - the integer value to test + * param int [in] MAX - the maximum value to test against + * + * This macro returns TRUE if the bounds are invalid and FALSE if + * they are okay. NOTE: MAX will be an invalid value, so check >= + * + */ +#define IX_PIU_TYPE_ENUM_IS_INVALID(VALUE, MAX) ((((VALUE) < 0) || ((VALUE) >= (MAX))) ? TRUE : FALSE) + + +#define INLINE __inline__ + + +typedef uint8_t ix_uint8; + +typedef uint32_t ix_uint32; + +typedef icp_status_t ix_error; + +#endif /* ndef IXPIUTYPES_INC */ diff --git a/Acceleration/include/accel_infra/IxQMgr.h b/Acceleration/include/accel_infra/IxQMgr.h new file mode 100644 index 0000000..faf4666 --- /dev/null +++ b/Acceleration/include/accel_infra/IxQMgr.h @@ -0,0 +1,2563 @@ +/** + * @file IxQMgr.h + * + * + * @brief This file contains the Moher Software public API of IxQMgr component. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +/* ------------------------------------------------------ + Doxygen group definitions + ------------------------------------------------------ */ +/** + * @defgroup IxQMgrAPI Software Queue Manager (IxQMgr) API + * + * @brief The public API for the Software QMgr component. + * + * @{ + */ + +#ifndef IXQMGR_H +#define IXQMGR_H + +/* + * User defined include files + */ + + +#include "IxOsal.h" +#include "icp.h" +#include "IxSwQueue.h" + + +/** +* +* @ingroup IxQMgrAPI +* +* @def IX_COMPONENT_NAME +* +* @brief defines the name of this component +* +*/ +#define IX_COMPONENT_NAME IX_QMGR + + +/* + * #defines and macros + */ + +/** +* +* @ingroup IxQMgrAPI +* +* @def IX_QMGR_INLINE +* +* @brief Inline definition, for inlining of Queue Access functions on API +* +* Please read the header information in this file for more details on the +* use of function inlining in this component. +* +*/ +#ifdef IXQMGRQACCESS_C +/* If IXQMGRQACCESS_C is set then the IxQmgrQAccess.c is including this file + and must instantiate a concrete definition for each inlineable API function + whether or not that function actually gets inlined. */ +# ifdef NO_INLINE_APIS +# undef NO_INLINE_APIS +# endif +# define IX_QMGR_INLINE /* Empty Define */ +#else +# ifndef NO_INLINE_APIS +# define IX_QMGR_INLINE __inline__ extern +# else +# define IX_QMGR_INLINE /* Empty Define */ +# endif +#endif + + +/** +* +* @ingroup IxQMgrAPI +* +* @def IX_QMGR_MAX_NUM_QUEUES +* +* @brief Number of software queues supported by the QMgr component. +* +* This constant is used to indicate the number of queues +* +*/ +#define IX_QMGR_MAX_NUM_QUEUES (512) + + +/** +* +* @ingroup IxQMgrAPI +* +* @def IX_QMGR_MAX_QNAME_LEN +* +* @brief Maximum queue name length. +* +* This constant is used to indicate the maximum null terminated string length +* (excluding '\0') for a queue name +* +*/ +#define IX_QMGR_MAX_QNAME_LEN (16) + +/** + * + * @ingroup IxQMgrAPI + * + * @def IX_QMGR_Q_MAX_SIZE + * + * @brief Maximum Allowed Size for a Queue + * + * As Head and Tail are Max 16-bits this figure must be less than 2^16 + * If this size is ever increased > 2^16, additional overflow checks will be + * required during config. + */ +#define IX_QMGR_Q_MAX_SIZE (32768) + + +/** + * + * @ingroup IxQMgrAPI + * + * @def IX_QMGR_Q_MAX_ENTRY_SIZE + * + * @brief Maximum Allowed Entry Size for a Queue in words + * + * Entry Size will also be limited to 2^n values: 1,2,4,8. + * + */ +#define IX_QMGR_Q_ENTRY_MAX_SIZE (8) + +/** + * + * @ingroup IxQMgrAPI + * + * @def IX_QMGR_MAX_BYTE_COUNT + * + * @brief Max count value of 8-bits + * + */ +#define IX_QMGR_MAX_BYTE_COUNT (256) + + +/** + * + * @ingroup IxQMgrAPI + * + * @def IX_QMGR_SIZEOF_WORD + * + * @brief The sizeof() a 32-bit word. value in bytes. + * + */ +#define IX_QMGR_SIZEOF_WORD (4) + +/** + * + * @ingroup IxQMgrAPI + * + * @def IX_QMGR_SIZEOF_BYTE + * + * @brief The sizeof() a 8-bit byte. value in bytes. + * + */ +#define IX_QMGR_SIZEOF_BYTE (1) + +/* + * Mechanism to validate the upper (MAX) and lower (0) bounds + * of a positive enumeration + * + * param int [in] VALUE - the integer value to test + * param int [in] MAX - the maximum value to test against + * + * This macro returns TRUE if the bounds are invalid and FALSE if + * they are okay. NOTE: MAX will be an invalid value, so check >= + * + */ +#define IX_QMGR_ENUM_IS_INVALID(VALUE, MAX) \ + ((((VALUE) < 0) || ((VALUE) >= (MAX))) ? TRUE : FALSE) + + +/** + * + * @ingroup IxQMgrAPI + * + * @def IX_QMGR_MASK_8BIT + * + * @brief A mask for 8-bits. + * + */ +#define IX_QMGR_MASK_8BIT (0xFF) + + +/** + * + * @ingroup IxQMgrAPI + * + * @def IX_QMGR_MASK_16BIT + * + * @brief A mask for 16-bits. + * + */ +#define IX_QMGR_MASK_16BIT (0xFFFF) + +/* + * Typedefs + */ + +/** + * + * @typedef IxQMgrQId + * + * @ingroup IxQMgrAPI + * + * @brief Generic identifiers for queues. + * + * This defines generic identifiers for the queues. + */ +typedef UINT32 IxQMgrQId; + + +/** + * + * @typedef IxQMgrQEntryType + * + * @ingroup IxQMgrAPI + * + * @brief Entry Type for all Queue Entries + * + * This defines generic Entry for the queues. + */ +typedef UINT32 IxQMgrQEntryType; + + +/** + * @enum IxQMgrNotificationCondition + * + * @ingroup IxQMgrAPI + * + * @brief Queue interrupt condition. + * + * This enum defines the different conditions on a queue that the client can register for + * a callback notification by the dispatcher. + * + */ +typedef enum +{ + IX_QMGR_Q_SOURCE_ID_E = 0, /**< Queue Empty due to last read */ + IX_QMGR_Q_SOURCE_ID_NOT_E, /**< Queue Not Empty */ + IX_QMGR_Q_SOURCE_ID_BW, /**< Queue Number of entries Below Watermark */ + IX_QMGR_Q_SOURCE_ID_AW, /**< Queue Number of entries Above Watermark */ + IX_QMGR_Q_SOURCE_ID_NOT_F, /**< Queue Not Full */ + IX_QMGR_Q_SOURCE_ID_F, /**< Queue Full */ + IX_QMGR_Q_SOURCE_INVALID /**< For Parameter validation purposes only */ +} IxQMgrNotificationCondition; + +/** + * @typedef IxQMgrQState + * + * @ingroup IxQMgrAPI + * + * @brief Queue state. + * + * A queues status is defined by its relative fullness or relative emptiness. + * Each of the queues can be in the following states: Below Watermark, + * Above Watermark, Empty, Full. + * + */ +typedef enum +{ + IX_QMGR_Q_STATE_E = IX_QMGR_Q_SOURCE_ID_E, /**< Queue Empty */ + IX_QMGR_Q_STATE_BW = IX_QMGR_Q_SOURCE_ID_BW, /**< Queue Number of Entries Below Watermark */ + IX_QMGR_Q_STATE_AW = IX_QMGR_Q_SOURCE_ID_AW, /**< Queue Number of entries Above Watermark */ + IX_QMGR_Q_STATE_F = IX_QMGR_Q_SOURCE_ID_F /**< Queue Full */ +} IxQMgrQState; + +/** + * @typedef IxQMgrQSize + * + * @ingroup IxQMgrAPI + * + * @brief QMgr queue sizes. + * + * These values define the allowed queue sizes for a queue. The sizes are + * specified in words, 1 word per entry. The Queue Size must be equal to 2^n. + * the theoritical maximum size for a queue will be 2^15 as the last bit + * is reserved and the queue counter used to manipulate the queues are 16 bits long. + * however native size for xscale is 32 bits, so for better efficiency 32 bit + * long variables are used. + * + */ +typedef UINT32 IxQMgrQSize; + + +/** + * @typedef IxQMgrQEntrySizeInWords + * + * @ingroup IxQMgrAPI + * + * @brief QMgr queue entry sizes in owrds. + * + * These values define the allowed queue entry sizes for a queue. The Entry Size + * must be equal to 2^n. The maximum size for a queue will be + * IX_QMGR_Q_ENTRY_MAX_SIZE + * + */ +typedef UINT32 IxQMgrQEntrySizeInWords; + + +/** + * @typedef IxQMgrWMLevel + * + * @ingroup IxQMgrAPI + * + * @brief QMgr watermark levels. + * + * defines the watermark level for queues, + * the level will be limited to a range from 1 to the Queue Size minus 1. + * This restriction will be enforced when setting the watermark level. + */ +typedef UINT32 IxQMgrWMLevel; + + +/** + * @ingroup IxQMgrAPI + * + * @typedef IxQMgrDispatchGroup + * + * @brief QMgr dispatch group identifiers. + * + * This type defines the logical groups of queues which the dispatcher should + * process when called. each queue belongs to a single group. A group will be + * used as an input to ixQMgrDispatcherLoopRun().When configuring a Queue, + * the client will specify the group which it belongs to. + * valid group ID will be between 0 and MAX_DISPATCH_GRP_ID. + * + */ +typedef UINT32 IxQMgrDispatchGroup; + + +/** + * + * @ingroup IxQMgrAPI + * + * @def IX_QMGR_DISPATCH_ETH + * + * @brief Reserved Dispatch Group ID for Ethernet 10/100 feature + * + */ +#define IX_QMGR_DISPATCH_ETH (0) + + + +/** + * + * @ingroup IxQMgrAPI + * + * @def IX_QMGR_DISPATCH_HSS + * + * @brief Reserved Dispatch Group ID for HSS feature Transmit Queues + * + */ +#define IX_QMGR_DISPATCH_TX_HSS (1) + + + +/** + * + * @ingroup IxQMgrAPI + * + * @def IX_QMGR_DISPATCH_HSS + * + * @brief Reserved Dispatch Group ID for HSS feature Voice Receive Queues + * + */ +#define IX_QMGR_DISPATCH_VOICE_RX_HSS (2) + + +/** + * + * @ingroup IxQMgrAPI + * + * @def IX_QMGR_DISPATCH_HSS + * + * @brief Reserved Dispatch Group ID for HSS feature HDLC Receive Queues + * + */ +#define IX_QMGR_DISPATCH_HDLC_RX_HSS (3) + + + +/** + * + * @ingroup IxQMgrAPI + * + * @def IX_QMGR_MAX_DISPATCH_GRP_ID + * + * @brief Maximum Dispatch group ID authorised + * + */ +#define IX_QMGR_MAX_NUM_DISPATCH_GRP (IX_QMGR_MAX_NUM_QUEUES) + + +/** + * @ingroup IxQMgrAPI + * + * @typedef IxQMgrCallbackId + * + * @brief Uniquely identifies a callback function. + * + * A unique callback identifier associated with each callback + * registered by clients. + * + */ +typedef UINT32 IxQMgrCallbackId; + + +/** + * + * @ingroup IxQMgrAPI + * + * @typedef IxQMgrCallback + * + * @brief QMgr notification callback type. + * + * This defines the interface to all client callback functions. + * + * @param IxQMgrQId qId(in) - the queue identifier + * @param IxQMgrCallbackId cbId(in) - the callback identifier + */ +typedef void (*IxQMgrCallback)(IxQMgrQId qId, + IxQMgrCallbackId cbId); + +/** + * @ingroup IxQMgrAPI + * + * @typedef IxSwQueueOfType_IxQMgrQEntryType + * + * @brief the macro used here creates the Software Queue Type used + * throughout the Queue Manager. + */ +IX_SWQ_TYPE(IxQMgrQEntryType,IxQMgrSwQueue); + + +/** + * @ingroup IxQMgrAPI + * + * @typedef IxQMgrHeadAndTailCountFormat + * + * @brief The count type of the Head and Tail pointer + * + * This enum is used to indicate whether the Head and Tail pointers for a queue + * count by the number of bytes or by the number of entries. + */ +typedef enum +{ + IX_QMGR_Q_COUNT_BYTES = 0, + IX_QMGR_Q_COUNT_ENTRIES, + IX_QMGR_Q_COUNT_INVALID + +} IxQMgrHeadAndTailCountFormat; + +/** + * @ingroup IxQMgrAPI + * + * @typedef IxQMgrHeadAndTailAlignment + * + * @brief The alignment of the Head and Tail + * + * This enum is used to indicate the alignment of the Head and Tail pointers of + * a queue. Note that in the case of Word alignment, only 16-bits are actually + * used for counting. + */ +typedef enum +{ + IX_QMGR_Q_ALIGN_BYTE = 0, + IX_QMGR_Q_ALIGN_WORD, + IX_QMGR_Q_ALIGN_INVALID +} IxQMgrHeadAndTailAlignment; + + +/** + * @ingroup IxQMgrAPI + * + * @typedef IxQMgrShadowCounter + * + * @brief Data Structure containing the shadowing information (the shadow tail + * and the real tail counters) for a queue. + * + */ + +typedef struct +{ + union + { + UINT8 byteShadowTailCounter; + UINT32 wordShadowTailCounter; + }; + union + { + volatile UINT8 *byteRealTailCounter; + volatile UINT32 *wordRealTailCounter; + }; + +} IxQMgrShadowCounter; + + + +/** + * @ingroup IxQMgrAPI + * + * @typedef IxQMgrHeadAndTailShadowing + * + * @brief The shadowing of the queue counters + * + * This enum is used to indicate the type of shadowing that should be usd for a + * queue. + */ +typedef enum +{ + IX_QMGR_Q_NO_SHADOWING = 0, + IX_QMGR_Q_SHADOW_TAIL_ONLY, + IX_QMGR_Q_SHADOW_HEAD_ONLY, + IX_QMGR_Q_SHADOW_HEAD_TAIL, + IX_QMGR_Q_SHADOW_INVALID +} IxQMgrHeadAndTailShadowing; +/** + * @ingroup IxQMgrAPI + * + * @typedef IxQMgrQueue + * + * @brief Data Structure containing all the relevant information regarding a queue + * + */ +typedef struct +{ + char qName[IX_QMGR_MAX_QNAME_LEN]; /**< name of the queue */ + IxQMgrQSize qSize; /**< queue size in entries */ + IxQMgrQEntrySizeInWords qEntrySize; /**< queue entry size in words */ + IxQMgrSwQueue queue; /**< the queue */ + IxQMgrDispatchGroup group; /**< the group the queue belongs to*/ + IxQMgrQId nextQId; /**< the next Q in the list for + the group the Q belongs to, only + set once notification is enabled */ + IxQMgrQId prevQId; /**< the previous Q in the list */ + IxQMgrCallback callback; /**< the callback function to be + used in case of notification */ + IxQMgrCallbackId callbackId; /**< the Id to be used when using + the callback */ + IxQMgrWMLevel waterMark; /**< the watermark level for this queue */ + IxQMgrNotificationCondition notifCond; /**< The condition that will + trigger a notif by the dispatcher*/ + IxQMgrHeadAndTailCountFormat htCountFormat; /**<the head (write) and tail + (read) count format*/ + IxQMgrHeadAndTailAlignment htAlignment; /**<the head (write) and tail + (read) alignment */ + IxQMgrHeadAndTailShadowing shadowing; /**<the head (write) and tail + (read) shadowing */ + IxQMgrShadowCounter shadowInfo; /**<the shadowing data struct */ +} IxQMgrQueue; + + +/* for inline function include the private queue data */ +#ifndef NO_INLINE_APIS +extern IxQMgrQueue ixQMgrQueues [IX_QMGR_MAX_NUM_QUEUES]; +#endif + + +/* + * Function Prototypes + */ + + +/* ------------------------------------------------------------ + Initialisation related functions + ---------------------------------------------------------- */ +/** + * + * @ingroup IxQMgrAPI + * + * @fn ixQMgrInit (void) + * + * @brief Initialise the QMgr. + * + * This function must be called before any other QMgr function. It + * sets up internal data structures. + * + * - Reentrant - no + * - ISR Callable - no + * + * @return @li ICP_STATUS_SUCCESS, the IxQMgr successfully initialised + * @return @li ICP_STATUS_FAIL, failed to initialize the QMgr + * + */ +icp_status_t +ixQMgrInit (void); + +/** + * + * @ingroup IxQMgrAPI + * + * @fn ixQMgrUnload (void) + * + * @brief Uninitialise the QMgr. + * + * This function will perform the tasks required to unload the QMgr component + * cleanly. This should be called before a soft reboot or unloading of a + * kernel module. + * It is normal behaviour for this function to return a fail if it cannot be + * unloaded due to it being still used by another client. + * + * @pre It should only be called if @ref ixQMgrInit has already been called. It + * will only be successful if all groups of queues that were configured have + * been unconfigured using the ixQMgrUnconfigGroup() function. + * + * + * @post No QMgr functions should be called until ixQMgrInit is called again. + * + * - Reentrant - no + * - ISR Callable - no + * + * @return @li ICP_STATUS_SUCCESS, the IxQMgr successfully uninitialised + * @return @li ICP_STATUS_FAIL, failed to uninitialize the Qmgr + * @return @li ICP_STATUS_RESOURCE, A configure queue operation is in progress, + * IxQMgr cannot be unloaded at this time + * + */ + +icp_status_t +ixQMgrUnload (void); + +/** + * + * @ingroup IxQMgrAPI + * + * @fn ixQMgrShow (void) + * + * @brief Describe queue configuration and statistics. + * + * This function shows configured queues, their configurations and overall statistics. + * + * - Reentrant - no + * - ISR Callable - no + * + * @return @li void + * + */ + void +ixQMgrShow (void); + +/** + * + * @ingroup IxQMgrAPI + * + * @fn ixQMgrQShow (IxQMgrQId qId) + * + * @brief Display a queue configuration and current state. + * + * This function shows queue configuration. + * + * @param IxQMgrQId (in)qId - the queue identifier. + * + * - Reentrant - no + * - ISR Callable - no + * + * @return @li ICP_STATUS_SUCCESS, success + * @return @li ICP_STATUS_INVALID_PARAM, queue not configured for this QId + * + */ +icp_status_t +ixQMgrQShow (IxQMgrQId qId); + + +/** + * + * @ingroup IxQMgrAPI + * + * @fn ixQMgrGroupMemoryConfig (IxQMgrDispatchGroup group, void * baseAddressToFlush, void * baseAddressToInvalidate, UINT32 size) + * + * @brief Sets the base address and the size of the memory area that will be invalidated when the dispatch loop function will run. + * + * @param IxQMgrDispatchGroup (in)group - the Dispatch Group Identifier + * @param void * (in)baseAddress - address of the start of the cached memory + * @param UINT32 (in)size - size of cache. + * + * - Reentrant - no + * - ISR Callable - no + * + * @return @li ICP_STATUS_SUCCESS, success + * @return @li ICP_STATUS_INVALID_PARAMOR, invalid parameter + * + */ +icp_status_t +ixQMgrGroupMemoryConfig (IxQMgrDispatchGroup group, + void * baseAddressToFlush, + void * baseAddressToInvalidate, + UINT32 size); + + +/* ------------------------------------------------------------ + Configuration related functions + ---------------------------------------------------------- */ +/** + * + * @ingroup IxQMgrAPI + * + * @fn ixQMgrQConfig (char *qName, + IxQMgrQId *qId, + IxQMgrQSize qSize, + IxQMgrQEntrySizeInWords qEntrySize, + IxQMgrHeadAndTailCountFormat htCountFormat, + IxQMgrHeadAndTailAlignment htAlignment, + IxQMgrDispatchGroup group, + IxQMgrHeadAndTailShadowing shadowing, + void *qBaseAddress, + void *qHeadCountPtr, + void *qTailCountPtr) + * + * @brief Configure a Software queue. + * + * This function is called by a client to setup a queue, the queue stores + * entries in memory, each entry will be of size qEntrySize words. All parameters + * are checked for valid values. This function must be called for each queue, + * before any queue accesses are made and after ixQMgrInit() has been called. + * qName is assumed to be a '\0' terminated array of 16 characters or less. + * The Queue Manager component allocates a QId on configuration and returns + * it to the client. Both Head and Tail Counter are 16bits, the queue manager component + * will only support these counters in Big Endian mode, there will be no support + * for Little Endian. + * + * @param char(in) *qName - is the name provided by the client and is associated + * with a QId by the QMgr. + * @param IxQMgrQId(out) *qId - the returned qId of this queue + * @param IxQMgrQSize(in) qSize - the 2^n number of entries of the queue. + * @param IxQMgrQEntrySizeInWords(in) qEntrySize - the 2^n size of the queue entry + * can be up to 8 words (i.e. must be 1,2,4 or 8 words in size). + * @param IxQMgrHeadAndTailCountFormat(in) htCountFormat - the format that Head + * and Tail counters will use. Either count by bytes or count by entries. + * @param IxQMgrHeadAndTailAlignment(in) htAlignment - the alignment of the Head + * and Tail Counters. Either Word or byte aligned. + * @param IxQMgrDispatchGroup(in) group - the group this queue belongs to. this + * will be used by the dispatcher to determine which queues to service. + * @param IxQMgrHeadAndTailShadowing(in) shadowing - the counters that should be + * shadowed + * @param void*(in) qBaseAddress - The address of the area of memory to use for the + * Queue entries, the client allocates the memory, it will need to + * allocate "qSize" words of data. + * @param void* (in)qHeadCountPtr - the pointer to the area of memory for the + * Head Counter, the client should allocate a single word, its location + * must be word-aligned. + * @param void* (in)qTailCountPtr - the pointer to the area of memory for + * the Tail Counter, the client should allocate a single word, its location + * must be word aligned. + * + * @Note The total size of a queue (number of entries * size of each entry) + * can be up to 32768 words. + * + * @Note the head and tail counters are 16 bits in size (lower part of a word), + * however the QMgr is NOT designed to be able to handle non-word aligned pointers + * + * @Note the head and tail counters will be stored in big endian format + * + * - Reentrant - yes + * - ISR Callable - no + * + * @return @li ICP_STATUS_SUCCESS, a specified queue has been successfully configured. + * @return @li ICP_STATUS_FAIL, component not initialised. + * @return @li ICP_RESOURCE_ERR, all available queues are already configured, a + * different queue configure operation is in progress - please retry., + * @return @li ICP_STATUS_INVALID_PARAM, invalid queue size + * @return @li ICP_STATUS_INVALID_PARAM invalid queue entry size + * @return @li ICP_STATUS_INVALID_PARAM, queue already configured + * @return @li ICP_STATUS_INVALID_PARAM, Base Address is invalid + * @return @li ICP_STATUS_INVALID_PARAM, Counter Ptr is invalid + * + */ +icp_status_t +ixQMgrQConfig (char *qName, + IxQMgrQId *qId, + IxQMgrQSize qSize, + IxQMgrQEntrySizeInWords qEntrySize, + IxQMgrHeadAndTailCountFormat htCountFormat, + IxQMgrHeadAndTailAlignment htAlignment, + IxQMgrDispatchGroup group, + IxQMgrHeadAndTailShadowing shadowing, + void *qBaseAddress, + void *qHeadCountPtr, + void *qTailCountPtr); + +/** + * + * @ingroup IxQMgrAPI + * + * @fn ixQMgrQSizeReconfig (IxQMgrQId qId, + IxQMgrQSize qSize) + + * + * @brief Reconfigures the max number of entries in a Software queue. + * + * + * This function is called by the client in order to resize the max number of + * entries in an existing queue. + * + * Preconditions to successfully calling this function are as follows: + * 1. The QMgr must be initialised + * 2. The queue must have been successfully configured using ixQMgrQConfig() + * 3. The queue must be empty + * 4. The queue must have it's Notifications disabled. (default) + * 5. The memory pool allocated by the client for ixQMgrQConfig should be big + * enough to accomodate the new number of entries. + * + * Conditions 1-4 are checked and the function will return with an + * appropriate error code should any of conditions not be met. + * Condition 5 is not checked. It is the clients responsiblity to ensurse the + * buffer it allcoated for this queue that was passed as an argument to + * ixQMgrQConfig() is of sufficient size for this queue. + * + * The qSize will be checked against the selected Head and Tail alignment and + * counting format (entries or bytes). It will return an error if it is possible + * that the qSize could be greater than the Head and Tail can count. + * + * Postconditions to successfully calling this function are as follows: + * 1. The queue will have a max number of entries as specified by qSize. + * 2. The Head and Tail pointers for the queue will be reset. + * 3. The watermark for the queue will be reset. + * 4. Any registered queue callbacks and callbackId's will be unchanged. + * + * + * @param IxQMgrQId(in) qId - the qId + * @param IxQMgrQSize(in) qSize - the new amount of entries in the queue. + * qSize must = 2^n, where n is a positive integer. + * + * @Note The total size of a queue (number of entries * size of each entry) + * can be up to 32768 words. + * + * @Note The queue entry size cannot be reconfigured using this function + * + * - Reentrant - yes + * - ISR Callable - no + * + * @return @li ICP_STATUS_SUCCESS, a specified queue has been successfully configured. + * @return @li ICP_STATUS_FAIL, component not initialised. + * @return @li ICP_STATUS_INVALID_PARAM , invalid queue, invalid queue size + * @return @li ICP_STATUS_RESOURCE, Q is not empty, Q Notifications are not disabled + * + */ +icp_status_t +ixQMgrQSizeReconfig (IxQMgrQId qId, + IxQMgrQSize qSize); + + + + +/** + * + * @ingroup IxQMgrAPI + * + * @fn ixQMgrUnconfigGroup (IxQMgrDispatchGroup group) + * + * @brief Unconfigures the queues in a group + * + * This function is called by the client in order to unconfigure a group of + * queues. It should be called when a group of queues are no longer needed by + * the client. + * + * Preconditions to successfully calling this function are as follows: + * 1. The QMgr must be initialised + * + * It is not explicitly checked but this function is only useful if the there + * are queues configured in the group that is being unconfigured. + * + * Postconditions to successfully calling this function are as follows: + * 1. All queues that had their group set to the parameter will be completely + * reset. Reseting means that the all counters will be cleared and the QMgr + * will remove it's association with queue buffer. The qId of each queue will + * be available for reuse through the ixQMgrQConfig function. + * + * @param IxQMgrDispatchGroup(in) group - the queue group + * + * @Note This function should be called before calling ixQMgrUnload + * + * @Note Memory allocation/freeing is the clients responsiblity. + * + * - Reentrant - no + * - ISR Callable - no + * + * @return @li ICP_STATUS_SUCCESS, the group has been unconfigured + * @return @li ICP_STATUS_FAIL, component not initialised. + * @return @li ICP_STATUS_INVALID_PARAM , invalid group + * + */ + icp_status_t +ixQMgrUnconfigGroup(IxQMgrDispatchGroup group); + + + +/** + * + * @ingroup IxQMgrAPI + * + * @fn ixQMgrQSizeGet (IxQMgrQId qId, + IxQMgrQSize *qSize) + * + * @brief Return the size of a queue. + * + * This function returns the the size of the queue in entries. + * + * @param IxQMgrQId(in) qId - the queue identifier + * @param IxQMgrQSize(out) *qSize - queue size in entries + * + * - Reentrant - no + * - ISR Callable - no + * + * @return @li ICP_STATUS_SUCCESS, successfully retrieved the size + * @return @li ICP_STATUS_INVALID_PARAM, invalid queue id + * @return @li ICP_STATUS_INVALID_PARAM, queue not configured for this QId + * @return @li ICP_STATUS_INVALID_PARAM, invalid parameter(s). + * + */ + icp_status_t +ixQMgrQSizeGet (IxQMgrQId qId, + IxQMgrQSize *qSize); + + + + +/** + * + * @ingroup IxQMgrAPI + * + * @fn ixQMgrWatermarkSet (IxQMgrQId qId, + IxQMgrWMLevel waterM) + * + * @brief Set the Watermark of a queue. + * + * This function is called by a client to set the watermark for the + * queue specified by qId. + * The queue must be empty at the time this function is called, it is the clients + * responsibility to ensure that the queue is empty. + * + * @param IxQMgrQId(in) qId - the QId of the queue. + * @param IxQMgrWMLevel(in) waterM - range (1..qSize-1) the watermark for this queue. + * + * - Reentrant - no + * - ISR Callable - no + * + * @return @li ICP_STATUS_SUCCESS, watermark have been set for the queue + * @return @li ICP_STATUS_INVALID_PARAM, invalid queue id + * @return @li ICP_STATUS_INVALID_PARAM, queue not configured for this QId + * @return @li ICP_STATUS_INVALID_PARAM, invalid watermark + * + */ + icp_status_t +ixQMgrWatermarkSet (IxQMgrQId qId, + IxQMgrWMLevel waterM); + + +/* ------------------------------------------------------------ + Queue access related functions + ---------------------------------------------------------- */ + +/** + * + * @ingroup IxQMgrAPI + * + * @fn ixQMgrQReadWithChecks (IxQMgrQId qId, + IxQMgrQEntryType *entryPtr) + * + * @brief Read an entry from a queue. + * + * This function reads an entire entry from a queue returning it in *entryPtr. + * + * + * @param IxQMgrQId(in) qId - the queue identifier. + * @param IxQMgrQEntryType(out) *entryPtr - array to copy the entry word(s) into. + * + * - Reentrant - no + * - ISR Callable - yes + * + * @return @li ICP_STATUS_SUCCESS, entry was successfully read. + * @return @li ICP_STATUS_INVALID_PARAM, invalid paramter(s). + * @return @li ICP_STATUS_INVALID_PARAM, queue not configured for this QId + * @return @li ICP_STATUS_UNDERFLOW, attempt to read from an empty queue + * + */ +icp_status_t +ixQMgrQReadWithChecks (IxQMgrQId qId, + IxQMgrQEntryType *entryPtr); + + +/** + * + * @ingroup IxQMgrAPI + * + * @fn ixQMgrQRead (IxQMgrQId qId, + IxQMgrQEntryType *entryPtr) + * + * @brief Fast read of an entry from a queue. + * + * This function is a heavily streamlined version of ixQMgrQReadWithChecks(), + * This function reads an entire entry from a queue returning it in *entryPtr. + * + * + * @note - This function is inlined, to reduce unnecessary function call + * overhead. It does not perform any parameter checks, or update any statistics. + * Also, it does not check that the queue specified by qId has been configured. + * or is in range. It simply checks for underflow and reads an entry from the queue. + * + * + * @param IxQMgrQId(in) qId - the queue identifier. + * @param IxQMgrQEntryType(out) *entryPtr - pointer to the entry word(s). + * + * - Reentrant - no + * - ISR Callable - yes + * + * @return @li ICP_STATUS_SUCCESS, entry was successfully read. + * @return @li ICP_STATUS_UNDERFLOW, attempt to read from an empty queue + * + */ +IX_QMGR_INLINE icp_status_t +ixQMgrQRead (IxQMgrQId qId, + IxQMgrQEntryType *entryPtr) +#ifdef NO_INLINE_APIS + ; +#else +{ + IxQMgrQueue *info = &ixQMgrQueues[qId]; + + + if (info->htCountFormat == IX_QMGR_Q_COUNT_BYTES) + { + /* + * Currently the only layer using this type of queue will have + * invalidate and flush done in the dispatcher + */ + + if (IX_SWQ_WA_CB_QUEUE_EMPTY(info->queue)) + { + return ICP_STATUS_UNDERFLOW; + } + IX_SWQ_WA_CB_ENTRY_DEQUEUE(info->queue, entryPtr); + + + } + else + { + + + if(info->htAlignment == IX_QMGR_Q_ALIGN_WORD) + { + IX_SWQ_WA_HEAD_INVALIDATE(info->queue); + + if (IX_SWQ_WA_CE_QUEUE_EMPTY(info->queue)) + { + return ICP_STATUS_UNDERFLOW; + } + IX_SWQ_WA_CE_ENTRY_DEQUEUE(info->queue, entryPtr); + + IX_SWQ_WA_TAIL_FLUSH(info->queue); + } + else + { + IX_SWQ_BA_HEAD_INVALIDATE(info->queue); + + if (IX_SWQ_BA_CE_QUEUE_EMPTY(info->queue)) + { + return ICP_STATUS_UNDERFLOW; + } + IX_SWQ_BA_CE_ENTRY_DEQUEUE(info->queue, entryPtr); + + IX_SWQ_BA_TAIL_FLUSH(info->queue); + } + + + } + + + return ICP_STATUS_SUCCESS; +} +#endif + + + + +/** + * + * @ingroup IxQMgrAPI + * + * @fn ixQMgrQBurstRead (IxQMgrQId qId, + UINT32 numEntries, + IxQMgrQEntryType *entriesPtr) + * + * @brief Read a number of entries from a software queue. + * + * This function will burst read a number of entries from the specified queue. + * The function will attempt to read as many entries as specified by the + * numEntries parameter and will return an UNDERFLOW if the sufficient number + * of entries is not in the queue at the start of the function. + * This function reads a number of entries from a queue returning them in entriesPtr. + * + * @note + * This function is intended for fast draining of queues, so to make it + * as efficient as possible, it has the following features: + * - This function is inlined, to reduce unnecessary function call overhead. + * - It does not perform any parameter checks apart from underflow, + * or update any statistics. + * - It does not check that the queue specified by qId has been configured. + * - It will only check there are enough entries to fulfill the clients request + * + * @param IxQMgrQId(in) qId - the queue identifier. + * @param UINT32(in) numEntries - the number of entries to read. + * This number should be greater than 0 + * @param IxQMgrQEntryType(out) *entriesPtr - array with the entries read. + * + * - Reentrant - no + * - ISR Callable - yes + * + * @return @li ICP_STATUS_SUCCESS, entries were successfully read. + * @return @li ICP_STATUS_UNDERFLOW, the component will check before read any + * entries that there are enough entries in teh queue to satisfy the burst read. + * + */ +IX_QMGR_INLINE icp_status_t +ixQMgrQBurstRead (IxQMgrQId qId, + UINT32 numEntries, + IxQMgrQEntryType *entriesPtr) +#ifdef NO_INLINE_APIS +; +#else +{ + IxQMgrQueue *info = &ixQMgrQueues[qId]; + VUINT32 *qEntry = NULL; +#ifndef NDEBUG + UINT32 qEntries = 0; +#endif + UINT32 xfrSizeWords = 0; + VUINT32 *lastEntry = NULL; + + + if (info->htCountFormat == IX_QMGR_Q_COUNT_BYTES) + { + /* + * This code is specific to queues which Head and Tails are + * word aligned and count in bytes + */ + qEntry = &IX_SWQ_WA_CB_TAIL_ENTRY_GET((info->queue)); + +#ifndef NDEBUG + IX_SWQ_WA_CB_NUM_ENTRIES_GET(info->queue, qEntries); + if (numEntries > qEntries) + { + return ICP_STATUS_UNDERFLOW; + } +#endif + + /* preload the first cache line */ + IX_OSAL_CACHE_PRELOAD((void *)qEntry, 0); + + /* Compare head and tail, if head is greater than tail then there is + no wrap around and the all entries to be read are situated in the + same block of memory that can be read in one go. if head is not + greater than tail then the head counter has wrapped around and the + entries will have to be read one at a time as they are not situated + in consecutives addresses in memory.*/ + if ( IX_SWQ_WA_CB_HEAD(info->queue) > IX_SWQ_WA_CB_TAIL(info->queue) ) + { + xfrSizeWords = numEntries * info->qEntrySize; + lastEntry = qEntry + xfrSizeWords; + + /* preload */ + IX_OSAL_CACHE_PRELOAD(qEntry, xfrSizeWords << IX_SWQ_BYTES_POW_IN_WORD); + + /* memcpy */ + while( lastEntry != qEntry ) + { + *entriesPtr++ = *qEntry++; + } + + /* invalidate the queue memory just being read */ + IX_SWQ_WA_CB_TAIL_INVALIDATE_AFTER_DEQUEUE(info->queue, numEntries); + /* move the queue counter */ + IX_SWQ_WA_CB_TAIL_ADVANCE(info->queue, numEntries); + } + else + { + while(numEntries > 0) + { + numEntries--; + IX_SWQ_WA_CB_ENTRY_DEQUEUE(info->queue, entriesPtr); + entriesPtr = entriesPtr + (info->qEntrySize); + } + } + } + else + { + if(info->htAlignment == IX_QMGR_Q_ALIGN_WORD) + { + IX_SWQ_WA_HEAD_INVALIDATE(info->queue); + /* + * This code is specific to queues which Head and Tails are + * word aligned and count in entries + */ + qEntry = &IX_SWQ_WA_CE_TAIL_ENTRY_GET((info->queue)); + +#ifndef NDEBUG + IX_SWQ_WA_CE_NUM_ENTRIES_GET(info->queue, qEntries); + if (numEntries > qEntries) + { + return ICP_STATUS_UNDERFLOW; + } +#endif + + /* preload the first cache line */ + IX_OSAL_CACHE_PRELOAD((void *)qEntry, 0); + + /* Compare head and tail, if head is greater than tail then there + is no wrap around and the all entries to be read are situated + in the same block of memory that can be read in one go. if head + is not greater than tail then the head counter has wrapped around + and the entries will have to be read one at a time as they are + not situated in consecutives addresses in memory.*/ + if (IX_SWQ_WA_CE_HEAD(info->queue) > IX_SWQ_WA_CE_TAIL(info->queue)) + { + xfrSizeWords = numEntries * info->qEntrySize; + lastEntry = qEntry + xfrSizeWords; + + /* preload */ + IX_OSAL_CACHE_PRELOAD(qEntry, xfrSizeWords << IX_SWQ_BYTES_POW_IN_WORD); + + /* memcpy */ + while( lastEntry != qEntry ) + { + *entriesPtr++ = *qEntry++; + } + + /* invalidate the queue memory just being read */ + IX_SWQ_WA_CE_TAIL_INVALIDATE_AFTER_DEQUEUE(info->queue, numEntries); + /* move the queue counter */ + IX_SWQ_WA_CE_TAIL_ADVANCE(info->queue, numEntries); + } + else + { + while(numEntries > 0) + { + numEntries--; + IX_SWQ_WA_CE_ENTRY_DEQUEUE(info->queue, entriesPtr); + entriesPtr = entriesPtr + (info->qEntrySize); + } + } + IX_SWQ_WA_TAIL_FLUSH(info->queue); + } + else + { + IX_SWQ_BA_HEAD_INVALIDATE(info->queue); + /* + * This code is specific to queues which Head and Tails are + * byte aligned and count in entries + */ + qEntry = &IX_SWQ_BA_CE_TAIL_ENTRY_GET((info->queue)); + +#ifndef NDEBUG + IX_SWQ_BA_CE_NUM_ENTRIES_GET(info->queue, qEntries); + if (numEntries > qEntries) + { + return ICP_STATUS_UNDERFLOW; + } +#endif + + /* preload the first cache line */ + IX_OSAL_CACHE_PRELOAD((void *)qEntry, 0); + + /* Compare head and tail, if head is greater than tail then there + is no wrap around and the all entries to be read are situated + in the same block of memory that can be read in one go. if head + is not greater than tail then the head counter has wrapped around + and the entries will have to be read one at a time as they are + not situated in consecutives addresses in memory.*/ + if (IX_SWQ_BA_CE_HEAD(info->queue) > IX_SWQ_BA_CE_TAIL(info->queue)) + { + xfrSizeWords = numEntries * info->qEntrySize; + lastEntry = qEntry + xfrSizeWords; + + /* preload */ + IX_OSAL_CACHE_PRELOAD(qEntry, xfrSizeWords << IX_SWQ_BYTES_POW_IN_WORD); + + /* memcpy */ + while( lastEntry != qEntry ) + { + *entriesPtr++ = *qEntry++; + } + + /* invalidate the queue memory just being read */ + IX_SWQ_BA_CE_TAIL_INVALIDATE_AFTER_DEQUEUE(info->queue, numEntries); + /* move the queue counter */ + IX_SWQ_BA_CE_TAIL_ADVANCE(info->queue, numEntries); + } + else + { + while(numEntries > 0) + { + numEntries--; + IX_SWQ_BA_CE_ENTRY_DEQUEUE(info->queue, entriesPtr); + entriesPtr = entriesPtr + (info->qEntrySize); + } + } + IX_SWQ_BA_TAIL_FLUSH(info->queue); + } + + } + + return ICP_STATUS_SUCCESS; +} +#endif + +/** + * + * @ingroup IxQMgrAPI + * + * @fn ixQMgrQReadAdvance (IxQMgrQId qId, + UINT32 numEntries) + * + * @brief Advance the Queue Read pointer a number of entries + * + * This function will advance the tail pointer of a specific Queue. In doing so + * it will seem like numEntries entries have been read from queue. The benefits + * of this is that the overhead of actually reading the Queue entries is avoided + * It will return an UNDERFLOW if the sufficient number of entries is not in the + * queue at the start of the function. + * + * @note + * This function is intended for very fast draining of queues, so to make it + * as efficient as possible, it has the following features: + * - This function is inlined, to reduce unnecessary function call overhead. + * - It does not perform any parameter checks apart from underflow, + * or update any statistics. + * - It does not check that the queue specified by qId has been configured. + * - It doesn't bother reading the Queue Entries themselves + * - It will only check there are enough entries to fulfill the clients request + * + * @param IxQMgrQId(in) qId - the queue identifier. + * @param UINT32(in) numEntries - the number of entries to advance the tail + * count by. This number should be greater than 0 + * + * - Reentrant - no + * - ISR Callable - yes + * + * @return @li ICP_STATUS_SUCCESS, entries were successfully read. + * @return @li ICP_STATUS_UNDERFLOW, the component will check before read any + * entries that there are enough entries in teh queue to satisfy the burst read. + * + */ +IX_QMGR_INLINE icp_status_t +ixQMgrQReadAdvance (IxQMgrQId qId, + UINT32 numEntries) +#ifdef NO_INLINE_APIS +; +#else +{ + IxQMgrQueue *info = &ixQMgrQueues[qId]; + UINT32 qEntries; + + + if (info->htCountFormat == IX_QMGR_Q_COUNT_BYTES) + { + IX_SWQ_WA_CB_NUM_ENTRIES_GET(info->queue, qEntries); + if (numEntries > qEntries) + { + return ICP_STATUS_UNDERFLOW; + } + IX_SWQ_WA_CB_TAIL_ADVANCE((info->queue), numEntries); + } + else + { + if(info->htAlignment == IX_QMGR_Q_ALIGN_WORD) + { + IX_SWQ_WA_HEAD_INVALIDATE(info->queue); + + IX_SWQ_WA_CE_NUM_ENTRIES_GET(info->queue, qEntries); + if (numEntries > qEntries) + { + return ICP_STATUS_UNDERFLOW; + } + IX_SWQ_WA_CE_TAIL_ADVANCE((info->queue), numEntries); + + IX_SWQ_WA_TAIL_FLUSH(info->queue); + } + else + { + IX_SWQ_BA_HEAD_INVALIDATE(info->queue); + + IX_SWQ_BA_CE_NUM_ENTRIES_GET(info->queue, qEntries); + if (numEntries > qEntries) + { + return ICP_STATUS_UNDERFLOW; + } + IX_SWQ_BA_CE_TAIL_ADVANCE((info->queue), numEntries); + IX_SWQ_BA_TAIL_FLUSH(info->queue); + } + } + + return ICP_STATUS_SUCCESS; +} +#endif + + +/** + * + * @ingroup IxQMgrAPI + * + * @fn ixQMgrQWriteWithChecks (IxQMgrQId qId, + IxQMgrQEntryType *entry) + * + * @brief Write an entry to a Software Queue. + * + * This function will write the entry to the queue specified by qId. + * + * @param IxQMgrQId(in) qId - the queue identifier. + * @param IxQMgrQEntryType(in) entry - Pointer to the entry word(s) to write. + * + * - Reentrant - no + * - ISR Callable - yes + * + * @return @li ICP_STATUS_SUCCESS, value was successfully written. + * @return @li ICP_STATUS_INVALID_PARAM, invalid paramter(s). + * @return @li ICP_STATUS_INVALID_PARAM, queue not configured for this QId + * @return @li ICP_STATUS_OVERFLOW, attempt to write to a full queue + * + */ +icp_status_t +ixQMgrQWriteWithChecks (IxQMgrQId qId, + IxQMgrQEntryType *entry); + + +/** + * + * @ingroup IxQMgrAPI + * + * @fn ixQMgrQWrite (IxQMgrQId qId, + IxQMgrQEntryType *entry) + * + * @brief Fast write of an entry to a queue. + * + * This function is a heavily streamlined version of ixQMgrQWriteWithChecks(), + * but performs essentially the same task. It will write the entry word(s) + * to the queue specified by qId. + * + * @note - This function is inlined, to reduce unnecessary function call + * overhead. It does not perform any parameter checks, or update any + * statistics. Also, it does not check that the queue specified by qId has + * been configured. It simply writes an entry to the queue, and checks for + * overflow. + * + * + * @param IxQMgrQId(in) qId - the queue identifier. + * @param IxQMgrQEntryType(in) *entry - array holding entry word(s) to be written + * - Reentrant - no + * - ISR Callable - yes + * + * + * @return @li ICP_STATUS_SUCCESS, entry was successfully read. + * @return @li ICP_STATUS_OVERFLOW, attempt to write to a full queue + * + */ + +IX_QMGR_INLINE icp_status_t +ixQMgrQWrite (IxQMgrQId qId, + IxQMgrQEntryType *entry) +#ifdef NO_INLINE_APIS + ; +#else +{ + IxQMgrQueue *info = &ixQMgrQueues[qId]; + if (info->htCountFormat == IX_QMGR_Q_COUNT_BYTES) + { + if ( IX_SWQ_WA_CB_QUEUE_FULL(info->queue) ) + { + return ICP_STATUS_OVERFLOW; + } + IX_SWQ_WA_CB_ENTRY_ENQUEUE(info->queue, entry); + } + else + { + + + if(info->htAlignment == IX_QMGR_Q_ALIGN_WORD) + { + IX_SWQ_WA_TAIL_INVALIDATE(info->queue); + + if ( IX_SWQ_WA_CE_QUEUE_FULL(info->queue) ) + { + return ICP_STATUS_OVERFLOW; + } + IX_SWQ_WA_CE_ENTRY_ENQUEUE(info->queue, entry); + + IX_SWQ_WA_HEAD_FLUSH(info->queue); + } + else + { + IX_SWQ_BA_TAIL_INVALIDATE(info->queue); + + if ( IX_SWQ_BA_CE_QUEUE_FULL(info->queue) ) + { + return ICP_STATUS_OVERFLOW; + } + IX_SWQ_BA_CE_ENTRY_ENQUEUE(info->queue, entry); + + IX_SWQ_BA_HEAD_FLUSH(info->queue); + } + } + + return ICP_STATUS_SUCCESS; +} +#endif + +/** + * + * @ingroup IxQMgrAPI + * + * @fn ixQMgrQBurstWrite (IxQMgrQId qId, + UINT32 numEntries, + IxQMgrQEntryType *entriesPtr) + * + * @brief Write a number of entries to a Software queue. + * + * This function will burst write a number of entries to the specified queue. + * The function will attempt to write as many entries as specified + * by the numEntries parameter and will return an OVERFLOW if + * there isnt sufficient space in the queue. + * + * @note + * This function is intended for fast population of queues, so to make it + * as efficient as possible, it has the following features: + * - This function is inlined, to reduce unnecessary function call overhead. + * - It does not perform any parameter checks, or update any statistics. + * - It does not check that the queue specified by qId has been configured. + * - It only checks that the queue has enough free space to hold the entries + * before writing performed.Therefore, the client should ensure before calling this function + * that there is enough free space in the queue to hold the number of entries + * to be written. ixQMgrQWrite() or ixQMgrQWriteWithChecks(), which only writes + * a single queue entry per call, should be used instead if the user requires + * checks for OVERFLOW before each entry written. + * + * @param IxQMgrQId(in) qId - the queue identifier. + * @param UINT32(in) numEntries - the number of entries to write. + * @param IxQMgrQEntryType(in) *entriesPtr - the list of entries to write. + * + * - Reentrant - no + * - ISR Callable - yes + * + * @return @li ICP_STATUS_SUCCESS, value was successfully written. + * @return @li ICP_STATUS_OVERFLOW, attempt to write to a queue with an + * insufficient number of free entries + * + */ +IX_QMGR_INLINE icp_status_t +ixQMgrQBurstWrite (IxQMgrQId qId, + UINT32 numEntries, + IxQMgrQEntryType *entriesPtr) +#ifdef NO_INLINE_APIS +; +#else +{ + + IxQMgrQueue* info = &ixQMgrQueues[qId]; + UINT32 qEntries; + + if (info->htCountFormat == IX_QMGR_Q_COUNT_BYTES) + { + IX_SWQ_WA_CB_NUM_ENTRIES_GET(info->queue, qEntries); + if (numEntries > (IX_SWQ_SIZE(info->queue) - qEntries)) + { + return ICP_STATUS_OVERFLOW; + } + + /* write each queue entry */ + while (numEntries) + { + numEntries--; + IX_SWQ_WA_CB_ENTRY_ENQUEUE(info->queue, entriesPtr); + entriesPtr = entriesPtr + (info->qEntrySize); + } + } + else + { + if(info->htAlignment == IX_QMGR_Q_ALIGN_WORD) + { + IX_SWQ_WA_TAIL_INVALIDATE(info->queue); + + IX_SWQ_WA_CE_NUM_ENTRIES_GET(info->queue, qEntries); + if (numEntries > (IX_SWQ_SIZE(info->queue) - qEntries)) + { + return ICP_STATUS_OVERFLOW; + } + + /* write each queue entry */ + while (numEntries) + { + numEntries--; + IX_SWQ_WA_CE_ENTRY_ENQUEUE(info->queue, entriesPtr); + entriesPtr = entriesPtr + (info->qEntrySize); + } + /*Head flush done in IX_SWQ_WA_CE_ENTRY_ENQUEUE macro*/ + + } + else + { + IX_SWQ_BA_TAIL_INVALIDATE(info->queue); + + IX_SWQ_BA_CE_NUM_ENTRIES_GET(info->queue, qEntries); + if (numEntries > (IX_SWQ_SIZE(info->queue) - qEntries)) + { + return ICP_STATUS_OVERFLOW; + } + + /* write each queue entry */ + while (numEntries) + { + numEntries--; + IX_SWQ_BA_CE_ENTRY_ENQUEUE(info->queue, entriesPtr); + entriesPtr = entriesPtr + (info->qEntrySize); + } + + /*Head flush done in IX_SWQ_WA_CE_ENTRY_ENQUEUE macro*/ + } + } + + return ICP_STATUS_SUCCESS; +} +#endif + + +/** + * + * @ingroup IxQMgrAPI + * + * @fn ixQMgrQNumEntriesGetWithChecks (IxQMgrQId qId, + UINT32 *numEntries) + * + * @brief Get a snapshot of the number of entries in a queue. + * + * This function gets the number of entries in a queue. + * + * @param IxQMgrQId(in) qId - the queue idenfifier + * @param UINT32(out) *numEntries - the number of entries in a queue + * + * - Reentrant - no + * - ISR Callable - yes + * + * @return @li ICP_STATUS_SUCCESS, got the number of entries for the queue + * @return @li ICP_STATUS_INVALID_PARAM, invalid paramter(s). + * @return @li ICP_STATUS_INVALID_PARAM, the specified qId has not been configured + * + */ +icp_status_t +ixQMgrQNumEntriesGetWithChecks (IxQMgrQId qId, + UINT32 *numEntries); + + +/** + * + * @ingroup IxQMgrAPI + * + * @fn ixQMgrQNumEntriesGet (IxQMgrQId qId, + UINT32 *numEntries) + * + * @brief Get a snapshot of the number of entries in a queue. this + * is an inlined version of ixQMgrQNumEntriesGetWithChecks. it does + * not perform any checks on the parameters given, the client must + * ensure that these are correct. + * + * This function gets the number of entries in a queue. + * + * @param IxQMgrQId(in) qId - the queue idenfifier + * @param UINT32(out) *numEntries - the number of entries in a queue + * + * - Reentrant - no + * - ISR Callable - yes + * + * @return @li ICP_STATUS_SUCCESS, got the number of entries for the queue + * + */ +IX_QMGR_INLINE icp_status_t +ixQMgrQNumEntriesGet (IxQMgrQId qId, + UINT32 *numEntries) +#ifdef NO_INLINE_APIS +; +#else +{ + IxQMgrQueue *info = &ixQMgrQueues[qId]; +if (info->htCountFormat == IX_QMGR_Q_COUNT_BYTES) + { + IX_SWQ_WA_CB_NUM_ENTRIES_GET(info->queue, (*numEntries)); + } + else + { + if(info->htAlignment == IX_QMGR_Q_ALIGN_WORD) + { + IX_SWQ_WA_HEAD_INVALIDATE(info->queue); + IX_SWQ_WA_TAIL_INVALIDATE(info->queue); + IX_SWQ_WA_CE_NUM_ENTRIES_GET(info->queue, (*numEntries)); + } + else + { + IX_SWQ_BA_HEAD_INVALIDATE(info->queue); + IX_SWQ_BA_TAIL_INVALIDATE(info->queue); + IX_SWQ_BA_CE_NUM_ENTRIES_GET(info->queue, (*numEntries)); + } + } + return ICP_STATUS_SUCCESS; +} +#endif + +/** + * + * @ingroup IxQMgrAPI + * + * @fn ixQMgrQStatusGetWithChecks (IxQMgrQId qId, + IxQMgrQState *qState) + * + * @brief Get a queues status. + * + * This function computes the specified queues status using its head and tail counters. + * A queues status is defined as E,AW,BW,or F. + * + * @param IxQMgrQId(in) qId - the queue identifier. + * @param IxQMgrQState(out) *qState - the status of the specified queue. + * + * - Reentrant - no + * - ISR Callable - yes + * + * @return @li ICP_STATUS_SUCCESS, queue status was successfully read. + * @return @li ICP_STATUS_INVALID_PARAM, the specified qId has not been configured + * @return @li ICP_STATUS_INVALID_PARAM, invalid paramter. + * + */ +icp_status_t +ixQMgrQStatusGetWithChecks (IxQMgrQId qId, + IxQMgrQState *qState); + +/** + * + * @ingroup IxQMgrAPI + * + * @fn ixQMgrQStatusGet (IxQMgrQId qId, + IxQMgrQState *qState) + * + * @brief Fast get of a queue's status. + * + * This function is a streamlined version of ixQMgrQStatusGetWithChecks(), but + * performs essentially the same task. It computes the specified queue's status. + * A queues status is defined by its Head and Tail Counters. The Queue's state + * can be E,AW,BW,F. + * + * @note - This function is inlined, to reduce unnecessary function call + * overhead. It does not perform any parameter checks, or update any + * statistics. Also, it does not check that the queue specified by qId has + * been configured. It simply returns the specified queue's status. + * + * @param IxQMgrQId(in) qId - the queue identifier. + * @param IxQMgrQState(out) *qState - the status of the specified queue. + * + * - Reentrant - no + * - ISR Callable - yes + * + * @return @li ICP_STATUS_SUCCESS, queue status was successfully read. + * + */ + +#ifdef NO_INLINE_APIS +icp_status_t +ixQMgrQStatusGet (IxQMgrQId qId, + IxQMgrQState *qState); +#else +IX_QMGR_INLINE icp_status_t +ixQMgrQStatusGet (IxQMgrQId qId, + IxQMgrQState *qState) +{ + IxQMgrQueue *info = &ixQMgrQueues[qId]; + UINT32 num_entries; + + if (info->htCountFormat == IX_QMGR_Q_COUNT_BYTES) + { + IX_SWQ_WA_CB_NUM_ENTRIES_GET(info->queue, num_entries); + + } + else + { + if(info->htAlignment == IX_QMGR_Q_ALIGN_WORD) + { + IX_SWQ_WA_HEAD_INVALIDATE(info->queue); + IX_SWQ_WA_TAIL_INVALIDATE(info->queue); + IX_SWQ_WA_CE_NUM_ENTRIES_GET(info->queue, num_entries); + + } + else + { + IX_SWQ_BA_HEAD_INVALIDATE(info->queue); + IX_SWQ_BA_TAIL_INVALIDATE(info->queue); + IX_SWQ_BA_CE_NUM_ENTRIES_GET(info->queue, num_entries); + } + } + + /* Calculate number of enqueued entries */ + /* Compare to E,F and W to get status */ + if (num_entries == info->qSize) + { + *qState = IX_QMGR_Q_STATE_F; + } + else if (num_entries == 0) + { + *qState = IX_QMGR_Q_STATE_E; + } + else if ( num_entries < info->waterMark) + { + *qState = IX_QMGR_Q_STATE_BW; + } + else + { + *qState = IX_QMGR_Q_STATE_AW; + } + + return ICP_STATUS_SUCCESS; +} +#endif + + + + +/* ------------------------------------------------------------ + Queue dispatch related functions + ---------------------------------------------------------- */ +/** + * + * @ingroup IxQMgrAPI + * + * @fn ixQMgrNotificationEnable (IxQMgrQId qId, + IxQMgrNotificationCondition sourceId) + * + * @brief Enable notification on a queue for a specified queue State. + * + * This function is called by a client of the QMgr to enable notifications on a + * specified condition. + * + * + * This function is re-entrant. and can be used from an interrupt context + * + * - Reentrant - yes + * - ISR Callable - yes + * + * @param IxQMgrQId(in) qId - the queue identifier + * @param IxQMgrNotificationCondition(in) sourceId - the notification condition identifier + * + * @return @li ICP_STATUS_SUCCESS, the notification has been enabled for the specified condition + * @return @li ICP_STATUS_INVALID_PARAM, the specified qId has not been configured + * @return @li ICP_STATUS_INVALID_PARAM, interrupt source invalid for this queue + * + */ +icp_status_t +ixQMgrNotificationEnable (IxQMgrQId qId, + IxQMgrNotificationCondition sourceId); + +/** + * @ingroup IxQMgrAPI + * + * @fn ixQMgrNotificationDisable (IxQMgrQId qId) + * + * @brief Disable notifications on a queue. + * + * This function is called to disable notifications on a specified queue. + * + * This function is re-entrant. and can be used from an interrupt context + * + * - Reentrant - yes + * - ISR Callable - yes + * + * @param IxQMgrQId(in) qId - the queue identifier + * + * @return @li ICP_STATUS_SUCCESS, the notification has been disabled + * @return @li ICP_STATUS_INVALID_PARAM, the specified qId has not been configured + * + */ +icp_status_t +ixQMgrNotificationDisable (IxQMgrQId qId); + +/** + * + * @ingroup IxQMgrAPI + * + * @fn ixQMgrDispatcherLoopRun (IxQMgrDispatchGroup group) + * + * @brief Run the callback dispatcher, + * service the first queue enabled in the group first. + * + * The function runs the dispatcher for a group of queues. + * Callbacks are made for conditions fulfilled on queues within + * the group that have registered callbacks. The order in which queues are + * serviced is fixed. + * This function may be called from interrupt or task context. the function + * could be called within the context of a polling mechanism based on a timer + * interrupt or could be called in the context of an ISR called in the event + * of a HW interrupt. However, for optimal performance the choice of context + * depends also on the operating system used. + * + * This function is not re-entrant. + * + * - Reentrant - no + * - ISR Callable - yes + * + * @param IxQMgrDispatchGroup(in) group - the group of queues over which the + * dispatcher will run + * + * @return @li void + * + */ +void +ixQMgrDispatcherLoopRun (IxQMgrDispatchGroup group); + +/** + * + * @ingroup IxQMgrAPI + * + * @fn ixQMgrDispatcherLoopRunReverse (IxQMgrDispatchGroup group) + * + * @brief Run the callback dispatcher, + * service the last Queue Enabled in the group first. + * + * The function runs the dispatcher for a group of queues. + * Callbacks are made for conditions fulfilled on queues within + * the group that have registered callbacks. The order in which queues are + * serviced is fixed. + * This function may be called from interrupt or task context. the function + * could be called within the context of a polling mechanism based on a timer + * interrupt or could be called in the context of an ISR called in the event + * of a HW mailbox interrupt + * + * This function is not re-entrant. This function may be called from interrupt + * or task context. + * However, for optimal performance the choice of context depends also on the + * operating system used. + * + * - Reentrant - no + * - ISR Callable - yes + * + * @param IxQMgrDispatchGroup(in) group - the group of queues over which the + * dispatcher will run + * + * @return @li void + * + */ +void +ixQMgrDispatcherLoopRunReverse (IxQMgrDispatchGroup group); + + + +/** + * + * @ingroup IxQMgrAPI + * + * @fn ixQMgrNotificationCallbackSet (IxQMgrQId qId, + IxQMgrCallback callback, + IxQMgrCallbackId callbackId) + * + * @brief Set the notification callback for a queue. + * + * This function sets the callback for the specified queue. This callback will + * be called by the dispatcher, and may be called in the context of a interrupt + * If callback has a value of NULL the previously registered callback, if one + * exists will be unregistered. + * + * It is possible to change the callback function 'on the fly' at any time, + * and from any context (interrupt or task) when the application needs to + * register a new callback function which has a different behaviour than + * the current one. Typical scenarios include dropping received data or + * handling transmission timeouts. + * + * - Reentrant - yes + * - ISR Callable - yes + * + * @param IxQMgrQId(in) qId - the queue idenfifier + * @param IxQMgrCallback(in) callback - the callback registered for this queue + * @param IxQMgrCallbackId(in) callbackid - the callback identifier + * + * @return @li ICP_STATUS_SUCCESS, the callback for the specified queue has been set + * @return @li ICP_STATUS_INVALID_PARAM, the specified qId has not been configured + * + */ +icp_status_t +ixQMgrNotificationCallbackSet (IxQMgrQId qId, + IxQMgrCallback callback, + IxQMgrCallbackId callbackId); + +/** + * + * @ingroup IxQMgrAPI + * + * @fn ixQMgrShadowAdvanceWithChecks(IxQMgrQId qId, + IxQMgrHeadAndTailShadowing shadowingCounterType, + UINT32 numEntries) + * + * @brief Advances the shadow counter by the specifed number of entries. + * + * + * This function is called by the client in order to advance a shadow counter. + * At present only a shadow tail is supported. This function will only ever + * advance the head or tail shadow counter. Seperate call would be required to + * advance both. + * + * This function is a non-inline version of ixQMgrShadowAdvance. + * + * Preconditions to successfully calling this function are as follows: + * 1. The QMgr must be initialised + * 2. The queue must have been successfully configured using ixQMgrQConfig() + * 3. The queue must have configured to use an shadow counter config that is + * equal or a superset of of shadowingCounter. + * 4. When the queue was configured using the ixQMgrQConfig() function, it + * must have been configured to queue whose head and tail counters count by + * entries, as shadowing is only supported on these types of queues. + * + * Conditions 1-4 are checked in this function. + * Also checked in this function are + * 1. That numEntries is greater than 0. + * 2. That numEntries is not greater then the max amount of entries. + * + * Postconditions to successfully calling this function are as follows: + * 1. If there is at least numEntries delta between the shadow and real counter, + * the shadow counter will be advanced by numEntries. + * 2. If there is less then numEntries delta between the shadow and real + * counters, the shadow counter will not be advanced. + * + * + * @param IxQMgrQId(in) qId - the qId + * @param IxQMgrHeadAndTailShadowing(in) shadowingCounterType - the counter to be + * advanced + * @param UINT32(in) numEntries - the amount of entries to advance the + * shadow counter + * + * @Note At present tail shadowing only is supported + * + * - Reentrant - no + * - ISR Callable - no + * + * @return @li ICP_STATUS_INVALID_PARAM, the specified queue is not configured, + * numEntries ==0, numEntries > max amount of entries. + * @return @li ICP_STATUS_RESOURCE, the queue does not use shadowing, the queue uses + * a count by bytes format for it's counters. + * @return @li ICP_STATUS_SUCCESS, the queue's counter has been advanced by numEntries + * @return @li ICP_STATUS_FAIL, the ixQMgr is not initialised, or it was not possible + * to advance shadow counter by numEntries as the delta between the shadow and + * real counters was less then numEntries. + * + */ +icp_status_t +ixQMgrShadowAdvanceWithChecks(IxQMgrQId qId, + IxQMgrHeadAndTailShadowing shadowingCounterType, + UINT32 numEntries); + + + +/** + * + * @ingroup IxQMgrAPI + * + * @fn ixQMgrShadowAdvance(IxQMgrQId qId, + IxQMgrHeadAndTailShadowing shadowingCounterType, + UINT32 numEntries) + * + * @brief Advances the shadow counter by the specifed number of entries. + * + * + * This function is called by the client in order to advance a shadow counter. + * + * + * Preconditions to successfully calling this function are as follows: + * 1. The QMgr must be initialised + * 2. The queue must have been successfully configured using ixQMgrQConfig() + * 3. The queue must have configured to use an shadow counter config that is + * equal or a superset of shadowingCounter. + * 4. The queue must have been configured to have its head and tail counters to + * count by entries. + * + * Conditions 1-4 are not checked in this function. + * This function is expected to be called on the data path and such it does not + * contain checks. A non-inline version of this function which includes checks + * can used by calling ixQMgrShadowAdvanceWithChecks instead. + * + * + * Postconditions to successfully calling this function are as follows: + * 1. If there is at least numEntries delta between the shadow and real counter, + * the shadow counter will be advance by numEntries. + * 2. If there is less then numEntries delta between the shadow and real + * counters, the shadow counter will not be advanced. + * + * + * @param IxQMgrQId(in) qId - the qId + * @param IxQMgrHeadAndTailShadowing(in) shadowingCounterType - the counter to be + * advanced + * @param UINT32(in) numEntries - the amount of entries to advance the + * shadow counter + * + * @Note At present tail shadowing only is supported + * + * @Note The shadowingCounterType parameter is not used in this function. It is + * a parameter in this function so that ixQMgrShadowAdvance() and + * ixQMgrShadowAdvanceWithChecks() have the same signatures. + * + * - Reentrant - no + * - ISR Callable - no + * + * @return @li ICP_STATUS_SUCCESS, the queue's counter has been advanced by numEntries + * @return @li ICP_STATUS_FAIL, it was not possible to advance shadow counter by + * numEntries as the delta between the shadow and real counters was less then numEntries. + * + */ +IX_QMGR_INLINE icp_status_t +ixQMgrShadowAdvance(IxQMgrQId qId, + IxQMgrHeadAndTailShadowing shadowingCounterType, + UINT32 numEntries) +#ifdef NO_INLINE_APIS +; +#else +{ + IxQMgrQueue *info = &ixQMgrQueues[qId]; + UINT32 shadowRealDelta = 0; + + if (info->htAlignment == IX_QMGR_Q_ALIGN_BYTE) + { + /*Invalidate the real tail*/ + IX_SWQ_CACHE_INVALIDATE((info->shadowInfo.byteRealTailCounter),IX_QMGR_SIZEOF_BYTE); + /* + * Test the delta between the shadow tail and the real tail up until + * the number of entries + */ + shadowRealDelta = + (IX_OSAL_READ_BE_SHARED_BYTE(info->shadowInfo.byteRealTailCounter)) - + (IX_OSAL_READ_BE_SHARED_BYTE(&(info->shadowInfo.byteShadowTailCounter))); + /* + * shadowRealDelta is an unsigned => overflow implicitly handled + * IX_QMGR_Q_ALIGN_BYTE means we must only use 8-bits + */ + if ((shadowRealDelta & IX_QMGR_MASK_8BIT) >= numEntries) + { + IX_SWQ_BA_CE_TAIL_ADVANCE(info->queue,numEntries); + + return ICP_STATUS_SUCCESS; + } + else + { + return ICP_STATUS_UNDERFLOW; + } + } + else + { + /*Invalidate the real tail*/ + IX_SWQ_CACHE_INVALIDATE((info->shadowInfo.wordRealTailCounter),IX_QMGR_SIZEOF_WORD); + /* + * Test the delta between the shadow tail and the real tail up until + * the number of entries + */ + shadowRealDelta = + (IX_OSAL_READ_BE_SHARED_LONG(info->shadowInfo.wordRealTailCounter)) - + (IX_OSAL_READ_BE_SHARED_LONG(&(info->shadowInfo.wordShadowTailCounter))); + + /* + * shadowRealDelta is an unsigned => overflow implicitly handled + * IX_QMGR_Q_ALIGN_WORD, but we only use 16-bits for counters + */ + if ((shadowRealDelta & IX_QMGR_MASK_16BIT) >= numEntries) + { + IX_SWQ_WA_CE_TAIL_ADVANCE(info->queue,numEntries); + + return ICP_STATUS_SUCCESS; + } + else + { + return ICP_STATUS_UNDERFLOW; + } + } +} +#endif + +/** + * + * @ingroup IxQMgrAPI + * + * @fn ixQMgrShadowDeltaGetWithChecks(IxQMgrQId qId, + IxQMgrHeadAndTailShadowing shadowingCounterType, + UINT32 *numEntries) + * + * @brief Gets the amount of entries that the shadow counter is behind the real + * counter + * + * This function is a non-inline version of ixQMgrShadowDeltaGet. + * + * This function is called by the client in order to get the amount of entries + * that the shadow is behind the real counter + * + * Preconditions to successfully calling this function are as follows: + * 1. The QMgr must be initialised + * 2. The queue must have been successfully configured using ixQMgrQConfig() + * 3. The queue must have configured to use a shadow counter config that is + * equal or a superset of of shadowingCounter. + * 4. The queue must have been configured to have its head and tail counters to + * count by entries. + * 5. That numEntries is a valid pointer. + * + * Conditions 1-4 are checked in this function. + * Also checked in this function are + * 1. That numEntries is a valid pointer + * + * Postconditions to successfully calling this function are as follows: + * 1. The numEntries parameter will be set to the the amount of entires that + * the shadow counter trails behind the real counter. + * + * + * @param IxQMgrQId(in) qId - the qId + * @param IxQMgrHeadAndTailShadowing(in) shadowingCounterType - the counter to be + * checked + * @param UINT32(out) *numEntries - the amount of entries the shadow + * counter trails the real counter by + * + * @Note At present tail shadowing only is supported + * + * - Reentrant - no + * - ISR Callable - no + * + * @return @li ICP_STATUS_INVALID_PARAM, the queue manager is not initialised, + * the specified queue is not configured, numEntries ==0, numEntries > max + * amount of entries. + * @return @li ICP_STATUS_RESOURCE, the queue does not use shadowing, the queue + * uses a count by bytes format for it's counters. + * @return @li ICP_STATUS_SUCCESS, numEntries has been updated with to indicate the + * amount of entries that the shadow counter trails the real counter by. + * @return @li ICP_STATUS_FAIL, the ixQMgr is not initialised. + * + */ +icp_status_t +ixQMgrShadowDeltaGetWithChecks(IxQMgrQId qId, + IxQMgrHeadAndTailShadowing shadowingCounterType, + UINT32 *numEntries); + +/** + * + * @ingroup IxQMgrAPI + * + * @fn ixQMgrShadowDeltaGet(IxQMgrQId qId, + IxQMgrHeadAndTailShadowing shadowingCounterType, + UINT32 *numEntries) + + * + * @brief Gets the amount of entries that the shadow counter is behind the real + * counter + * + * + * This function is called by the client in order to get the amount of entries + * that the shadow is behind the real counter + * + * Preconditions to successfully calling this function are as follows: + * 1. The QMgr must be initialised + * 2. The queue must have been successfully configured using ixQMgrQConfig() + * 3. The queue must have configured to use a shadow counter config that is + * equal or a superset of of shadowingCounter. + * 4. The queue must have been configured to have its head and tail counters to + * count by entries. + * + * Conditions 1-4 are not checked in this function. + * This function is expected to be called on the data path and such it does not + * contain checks. A non-inline version of this function which includes checks + * can used by calling ixQMgrShadowDeltaGetWithChecks instead. + * + * + * Postconditions to successfully calling this function are as follows: + * 1. The numEntries parameter will be set to the the amount of entires that + * the shadow counter trails behind the real counter. + * + * + * @param IxQMgrQId(in) qId - the qId + * @param IxQMgrHeadAndTailShadowing(in) shadowingCounterType - the counter to be + * checked + * @param UINT32(out) *numEntries - the amount of entries the shadow + * counter trails the real counter by + * + * @Note At present tail shadowing only is supported + * + * @Note The shadowingCounterType parameter is not used in this function. It is + * a parameter in this function so that ixQMgrShadowDeltaGet() and + * ixQMgrShadowDeltaGetWithChecks() have the same signatures. + * + * - Reentrant - no + * - ISR Callable - no + * + * @return @li ICP_STATUS_SUCCESS, this function always return this value, but it + * used so that the inline and non-inline versions of this function will have + * the same signature + * + */ +IX_QMGR_INLINE icp_status_t +ixQMgrShadowDeltaGet(IxQMgrQId qId, + IxQMgrHeadAndTailShadowing shadowingCounterType, + UINT32 *numEntries) +#ifdef NO_INLINE_APIS +; +#else +{ + IxQMgrQueue *info = &ixQMgrQueues[qId]; + UINT32 temp =0; + + if (info->htAlignment == IX_QMGR_Q_ALIGN_BYTE) + { + /*Invalidate the real tail*/ + IX_SWQ_CACHE_INVALIDATE((info->shadowInfo.byteRealTailCounter),IX_QMGR_SIZEOF_BYTE); + + /* Get the delta between the shadow tail and the real tail. */ + temp = + (IX_OSAL_READ_BE_SHARED_BYTE(info->shadowInfo.byteRealTailCounter)) - + (IX_OSAL_READ_BE_SHARED_BYTE(&(info->shadowInfo.byteShadowTailCounter))); + /*In case of overflow, this is byte aligned */ + *numEntries = (temp & 0xFF); + return ICP_STATUS_SUCCESS; + } + else + { + /*Invalidate the real tail*/ + IX_SWQ_CACHE_INVALIDATE((info->shadowInfo.wordRealTailCounter),IX_QMGR_SIZEOF_WORD); + + /* Get the delta between the shadow tail and the real tail. */ + temp = + (IX_OSAL_READ_BE_SHARED_LONG(info->shadowInfo.wordRealTailCounter)) - + (IX_OSAL_READ_BE_SHARED_LONG(&(info->shadowInfo.wordShadowTailCounter))); + /*In case of overflow, this is 4 byte (word) aligned, but only 16-bits are used */ + *numEntries = (temp & 0xFFFF); + return ICP_STATUS_SUCCESS; + } +} +#endif + + +/** + * + * @ingroup IxQMgrAPI + * + * @fn ixQMgrQWriteRollbackWithChecks (IxQMgrQId qId, + UINT32 numEntries) + * + * @brief Rollback the last entries written to the specified queue. + * + * This function moves back the write/head counter by the specfied number of + * entries. + * + * This function is a non-inline version of ixQMgrQWriteRollback. + * + * Preconditions to successfully calling this function: + * 1. The QMgr must be initialised + * 2. The queue must have been successfully configured using ixQMgrQConfig() + * 3. The queue must have configured to use an shadow counter. + * 4. The queue must have been configured to have its head and tail counters to + * count by entries. + * + * Conditions 1-4 are checked in this function. + * + * Postconditions to successfully calling this function are as follows: + * 1. If there is at least numEntries delta between the head counter and + * the shadow tail counter, the head counter will have numEntries + * subtracted from it. + * 2. If there is less then numEntries delta between the head counter and the + * shadow tail counter, the head counter will not be modified. + * + * @param IxQMgrQId(in) qId - the queue identifier. + * @param UINT32(in) numEntries - the number of entries that should be rolled back + * + * - Reentrant - no + * - ISR Callable - no + * + * @return @li ICP_STATUS_INVALID_PARAM, the queue manager is not initialised, + * the specified queue is not configured, the queue does not use shadowing, + * numEntries ==0, numEntries > max possible amount of entries, + * . + * @return @li ICP_STATUS_SUCCESS, queue status was successfully read. + * @return @li ICP_STATUS_RESOURCE, the queue uses a count by bytes format for it's + * counters, shadowing is not enabled on the queue, + * @return @li ICP_STATUS_FAIL, the number of entries to rollback would corrupt the queue + * + */ +IX_QMGR_INLINE icp_status_t +ixQMgrQWriteRollbackWithChecks (IxQMgrQId qId, + UINT32 numEntries); + + + +/** + * + * @ingroup IxQMgrAPI + * + * @fn ixQMgrQWriteR (IxQMgrQId qId, + UINT32 numEntries) + * + * @brief Rollback the last entries written to the specified queue. + * + * This function moves back the write/head counter by the specfied number of + * entries. + * + * Preconditions to successfully calling this function: + * 1. The QMgr must be initialised + * 2. The queue must have been successfully configured using ixQMgrQConfig() + * 3. The queue must have been configured to have its head and tail counters to + * count by entries. + * + * Conditions 1-3 are not checked in this function. + * This function is expected to be called on the data path and such it does not + * contain checks for these preconditions. A non-inline version of this function + * which includes checks can used by calling ixQMgrQWriteRollbackWithChecks instead. + * + * Postconditions to successfully calling this function are as follows: + * 1. If there is at least numEntries delta between the write/head counter and + * the shadow tail counter, the head counter will be will have numEntries + * subtracted from it. + * 2. If there is less then numEntries delta between the head counter and the + * shadow tail counter, the head counter will not be modified. + * + * @param IxQMgrQId(in) qId - the queue identifier. + * @param UINT32(in) numEntries - the number of entries that should be rolled back + * + * - Reentrant - no + * - ISR Callable - yes + * + * @return @li ICP_STATUS_SUCCESS, queue status was successfully read. + * @return @li ICP_STATUS_FAIL, the number of entries to rollback would corrupt the queue + * + * + * @Note this function checks that the rollback will not go beyond the real + * tail counter as to do so would corrupt the queue. + * + * + */ +IX_QMGR_INLINE icp_status_t +ixQMgrQWriteRollback (IxQMgrQId qId, UINT32 numEntries) +#ifdef NO_INLINE_APIS +; +#else +{ + IxQMgrQueue *info = &ixQMgrQueues[qId]; + UINT32 entryCount = 0; + + if (info->htAlignment == IX_QMGR_Q_ALIGN_BYTE) + { + IX_SWQ_BA_TAIL_INVALIDATE(info->queue); + + /* Get the current number of entries */ + IX_SWQ_BA_CE_NUM_ENTRIES_GET(info->queue,entryCount); + + if((UINT8) numEntries > (UINT8) entryCount) + { + /*not enough entries to rollback by numEntries*/ + return ICP_STATUS_FAIL; + } + else + { + /*rollback the head. set it to (present head val - numEntries)*/ + IX_SWQ_BA_CE_HEAD_SET(info->queue,(IX_SWQ_BE_SHARED_BYTE_READ(IX_SWQ_BA_CE_HEAD_PTR(info->queue))) - (UINT8) numEntries); + + IX_SWQ_BA_HEAD_FLUSH(info->queue); + return ICP_STATUS_SUCCESS; + } + } + else + { + + /*invalidate real tail counter*/ + IX_SWQ_WA_TAIL_INVALIDATE(info->queue); + + /* Get the current number of entries */ + IX_SWQ_WA_CE_NUM_ENTRIES_GET(info->queue,entryCount); + + if(numEntries > entryCount) + { + /*not enough entries to rollback by numEntries*/ + return ICP_STATUS_FAIL; + } + else + { + + /*rollback the head. set it to (present head val - numEntries)*/ + IX_SWQ_WA_CE_HEAD_SET(info->queue,((IX_SWQ_BE_SHARED_LONG_READ(IX_SWQ_WA_CE_HEAD_PTR(info->queue))) - numEntries)); + IX_SWQ_WA_HEAD_FLUSH(info->queue); + return ICP_STATUS_SUCCESS; + } + } +} +#endif + + + +/* Restore IX_COMPONENT_NAME */ +#undef IX_COMPONENT_NAME +#define IX_COMPONENT_NAME IX_QMGR_SAVED_COMPONENT_NAME + +#endif /* IXQMGR_H */ + +/** + * @} defgroup IxQMgrAPI + */ + + diff --git a/Acceleration/include/accel_infra/IxSwQueue.h b/Acceleration/include/accel_infra/IxSwQueue.h new file mode 100644 index 0000000..d263043 --- /dev/null +++ b/Acceleration/include/accel_infra/IxSwQueue.h @@ -0,0 +1,979 @@ +/** + * @file IxSwQueue.h + * + * @author Intel Corporation + * + * @brief This file contains the implementation of A Fast Software Queue + * + * @note This file can be broken into 4 sections. + * 1. Macros common to all types of queue + * 2. Macros for queues whose Head (Write) and Tail (Read) counters + * are Word Aligned and Count in Bytes. These have the IX_SWQ_WA_CB_* prefix + * 3. Macros for queues whose Head (Write) and Tail (Read) counters + * are Word Aligned and Count in Entries. These have the IX_SWQ_WA_CE_* + * prefix + * 4. Macros for queues whose Head (Write) and Tail (Read) counters + * are Byte Aligned and Count in Entries. These have the IX_SWQ_BA_CE_* + * prefix + * + * @note A Word as used in this file refers to a 32-bit value. + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +#ifndef IX_SW_QUEUE_H +#define IX_SW_QUEUE_H + +#ifdef SW_SWAPPING + +#define IX_SWQ_BE_SHARED_LONG_READ IX_OSAL_READ_BE_SHARED_LONG +#define IX_SWQ_BE_SHARED_LONG_WRITE IX_OSAL_WRITE_BE_SHARED_LONG + +#define IX_SWQ_BE_SHARED_BYTE_READ IX_OSAL_READ_BE_SHARED_BYTE +#define IX_SWQ_BE_SHARED_BYTE_WRITE IX_OSAL_WRITE_BE_SHARED_BYTE + +#else + +#define IX_SWQ_BE_SHARED_LONG_READ IX_OSAL_READ_LONG_RAW +#define IX_SWQ_BE_SHARED_LONG_WRITE IX_OSAL_WRITE_LONG_RAW + +#define IX_SWQ_BE_SHARED_BYTE_READ IX_OSAL_READ_BYTE_RAW +#define IX_SWQ_BE_SHARED_BYTE_WRITE IX_OSAL_WRITE_BYTE_RAW + +#endif + + + +/* + * Word Aligned Head and Tail Counters only use 16 active bits. + * Byte Aligned Head and Tail Counters use 8 active bits. + */ +#define IX_SWQ_WA_COUNTER_MASK (0xFFFF) +#define IX_SWQ_BA_COUNTER_MASK (0xFF) + +/* Mask for cache line boundary computations */ +#define IX_SWQ_CACHE_LINE_MASK (0x1f) + +/* conversion from bytes to words */ +#define IX_SWQ_BYTES_POW_IN_WORD (0x2) + +/** +* @def IX_SWQ_TYPE +* @brief Define the type of a software queue +* +* @note The head/tail of a queue is pointer that the queue stores to a +* shared (typically with NPE) location in memory that is used to count the +* latest Write/Read. Depending on the type of queue the count will either by +* Entries or Bytes. This value is converted to words to access the queue. +*/ +#define IX_SWQ_TYPE(TYPE,NAME) \ +typedef struct \ +{ \ + volatile TYPE *content; \ + UINT32 sizeInBytes; \ + UINT32 entrySizeInBytes; \ + UINT32 entrySizeBytePow; \ + UINT32 entrySizeWordPow; \ + UINT32 mask; \ + union \ + { \ + volatile UINT32 *wordHead; \ + volatile UINT8 *byteHead; \ + }; \ + union \ + { \ + volatile UINT32 *wordTail; \ + volatile UINT8 *byteTail; \ + }; \ +} \ +NAME + +/* The following macros are common for all queues, regardless of the */ +/* head and tail alignment and count format that are used */ + +/** +* @def IX_SWQ_STATIC_INIT +* @brief Initialise a Queue of a specified type and size, using a preallocated +* buffer +* +* @note - The requested size will be adjusted to the nearest larger +* size that is a power of 2. +* +* @note - User code that needs to reference the queue size should +* take care to query the queue to obtain the actual rounded +* up queue size, and not to use the requested queue size. +* +* @note - After initialisation use IX_SWQ_SIZE to obtain +* the actual size. +* +* @note - Memory for the queue is allocated from a buffer passed as parameter +* After initialisation use IX_SWQ_INITIALISED to check +* that the queue was initialised correctly. +* @note - due to optimisations, it is assumed at this point that the entry +* TYPE of a queue will always be a word +* +* @note - A queue whose head and tail counters are byte aligned and count in +* bytes is forbidden. This is not checked in this macro. The client +* should not call this function with this queue configuration. +* @note - Checking of max sizes is not done in this macro. They should be done +* by the client prior to using this macro. +* +* @note - Input parameters are:- +* +* @li queue - a pointer to a queue +* @li TYPE - the specific queue entry type +* @li requestedSize - the requested queue size +* @li reqEntrySize - the requested queue entry size +* @li queueBuffer - the location of the queue contents +* @li head - the location of the head counter +* @li tail - the location of the tail counter +* @li htCountFormat - the count format of the head and tail counters +* @li htAlignment - the alignment of the head and tail counters +*/ +#define IX_SWQ_STATIC_INIT(queue, \ + TYPE, \ + requestedSize, \ + reqEntrySize, \ + queueBuffer, \ + head, \ + tail, \ + htCountFormat, \ + htAlignment) \ + do { \ + (queue).entrySizeInBytes = (reqEntrySize) * sizeof (TYPE); \ + (queue).sizeInBytes = (requestedSize) * (queue).entrySizeInBytes; \ + (queue).entrySizeBytePow = 0; \ + while ((queue).entrySizeInBytes > 1) \ + { \ + (queue).entrySizeInBytes >>= 1; \ + (queue).entrySizeBytePow++; \ + } \ + (queue).entrySizeWordPow = (queue).entrySizeBytePow - 2; \ + (queue).entrySizeInBytes = (reqEntrySize) * sizeof (TYPE); \ + if (htAlignment == IX_QMGR_Q_ALIGN_WORD) \ + { \ + if (htCountFormat == IX_QMGR_Q_COUNT_BYTES) \ + { \ + (queue).mask = (queue).sizeInBytes - 1; \ + } \ + else \ + { \ + (queue).mask = (requestedSize) - 1; \ + } \ + (queue).wordHead = (head); \ + (queue).wordTail = (tail); \ + IX_SWQ_BE_SHARED_LONG_WRITE((queue).wordHead, 0); \ + IX_SWQ_BE_SHARED_LONG_WRITE((queue).wordTail, 0); \ + IX_SWQ_CACHE_FLUSH(((queue).wordHead),IX_QMGR_SIZEOF_WORD); \ + IX_SWQ_CACHE_FLUSH(((queue).wordTail),IX_QMGR_SIZEOF_WORD); \ + IX_SWQ_CACHE_INVALIDATE(((queue).wordHead),IX_QMGR_SIZEOF_WORD); \ + IX_SWQ_CACHE_INVALIDATE(((queue).wordTail),IX_QMGR_SIZEOF_WORD); \ + } \ + else \ + { \ + (queue).mask = (requestedSize) - 1; \ + (queue).byteHead = (head); \ + (queue).byteTail = (tail); \ + IX_SWQ_BE_SHARED_BYTE_WRITE((queue).byteHead, 0); \ + IX_SWQ_BE_SHARED_BYTE_WRITE((queue).byteTail, 0); \ + IX_SWQ_CACHE_FLUSH(((queue).byteHead),IX_QMGR_SIZEOF_BYTE); \ + IX_SWQ_CACHE_FLUSH(((queue).byteTail),IX_QMGR_SIZEOF_BYTE); \ + IX_SWQ_CACHE_INVALIDATE(((queue).byteHead),IX_QMGR_SIZEOF_BYTE); \ + IX_SWQ_CACHE_INVALIDATE(((queue).byteTail),IX_QMGR_SIZEOF_BYTE); \ + } \ + (queue).content = (volatile TYPE *)(queueBuffer); \ + memset ((void*)((queue).content), 0, (queue).sizeInBytes ); \ + IX_SWQ_CACHE_FLUSH(((queue).content),(queue).sizeInBytes);\ + IX_SWQ_CACHE_INVALIDATE(((queue).content),(queue).sizeInBytes);\ + } while(0) + +/** +* @def IX_SWQ_INITIALISED +* @brief Check that the Initialisation of a Queue was successfull +*/ +#define IX_SWQ_INITIALISED(queue) \ + ((queue).content != 0) + +/** +* @def IX_SWQ_CONTENT_PTR +*/ +#define IX_SWQ_CONTENT_PTR(queue) \ + ((queue).content) + +/** +* @def IX_SWQ_ENTRY_IDXGET +* @brief return an entry directly from the specified index in a queue +*/ +#define IX_SWQ_ENTRY_IDXGET(queue,index) \ + ((queue).content[(index)]) + +/** +* @def IX_SWQ_SIZE +* @brief return the size of a queue in entries +*/ +#define IX_SWQ_SIZE(queue) \ + ((queue).sizeInBytes >> (queue).entrySizeBytePow) + +/** +* @def IX_SWQ_ENTRY_SIZE_WORDS +* @brief return the size in words of a queue entry +*/ +#define IX_SWQ_ENTRY_SIZE_WORDS(queue) \ + ((queue).entrySizeInBytes >> IX_SWQ_BYTES_POW_IN_WORD) + + +/** +* @def IX_SWQ_WA_HEAD_FLUSH +* @brief flushes a word aligned head pointer +*/ +#ifdef SW_CACHE_MGMT +#define IX_SWQ_WA_HEAD_FLUSH(queue) do{ \ + IX_OSAL_CACHE_FLUSH((queue).wordHead,IX_QMGR_SIZEOF_WORD); \ + } while(0) +#else +#define IX_SWQ_WA_HEAD_FLUSH(queue) do{} while(0) +#endif + +/** +* @def IX_SWQ_WA_HEAD_INVALIDATE +* @brief invalidates a word aligned head pointer +*/ +#ifdef SW_CACHE_MGMT +#define IX_SWQ_WA_HEAD_INVALIDATE(queue) do{ \ + IX_OSAL_CACHE_INVALIDATE((queue).wordHead,IX_QMGR_SIZEOF_WORD); \ + } while(0) +#else +#define IX_SWQ_WA_HEAD_INVALIDATE(queue) do{} while(0) +#endif +/** +* @def IX_SWQ_WA_TAIL_FLUSH +* @brief flushes a word aligned tail pointer +*/ +#ifdef SW_CACHE_MGMT +#define IX_SWQ_WA_TAIL_FLUSH(queue) do{ \ + IX_OSAL_CACHE_FLUSH((queue).wordTail,IX_QMGR_SIZEOF_WORD); \ + } while(0) +#else +#define IX_SWQ_WA_TAIL_FLUSH(queue) do{} while(0) +#endif +/** +* @def IX_SWQ_WA_TAIL_INVALIDATE +* @brief invalidates a word aligned tail pointer +*/ +#ifdef SW_CACHE_MGMT +#define IX_SWQ_WA_TAIL_INVALIDATE(queue) do{ \ + IX_OSAL_CACHE_INVALIDATE((queue).wordTail,IX_QMGR_SIZEOF_WORD); \ + } while(0) +#else +#define IX_SWQ_WA_TAIL_INVALIDATE(queue) do{} while(0) +#endif + +/** +* @def IX_SWQ_BA_HEAD_FLUSH +* @brief flushes a byte aligned head pointer +*/ +#ifdef SW_CACHE_MGMT +#define IX_SWQ_BA_HEAD_FLUSH(queue) do{ \ + IX_OSAL_CACHE_FLUSH((queue).byteHead,IX_QMGR_SIZEOF_BYTE); \ + } while(0) +#else +#define IX_SWQ_BA_HEAD_FLUSH(queue) do{} while(0) +#endif + +/** +* @def IX_SWQ_WA_HEAD_INVALIDATE +* @brief invalidates a byte aligned head pointer +*/ +#ifdef SW_CACHE_MGMT +#define IX_SWQ_BA_HEAD_INVALIDATE(queue) do{ \ + IX_OSAL_CACHE_INVALIDATE((queue).byteHead,IX_QMGR_SIZEOF_BYTE); \ + } while(0) +#else +#define IX_SWQ_BA_HEAD_INVALIDATE(queue) do{} while(0) +#endif + +/** +* @def IX_SWQ_WA_TAIL_FLUSH +* @brief flushes a byte aligned tail pointer +*/ +#ifdef SW_CACHE_MGMT +#define IX_SWQ_BA_TAIL_FLUSH(queue) do{ \ + IX_OSAL_CACHE_FLUSH((queue).byteTail,IX_QMGR_SIZEOF_BYTE); \ + } while(0) +#else +#define IX_SWQ_BA_TAIL_FLUSH(queue) do{} while(0) +#endif + +/** +* @def IX_SWQ_WA_TAIL_INVALIDATE +* @brief invalidates a byte aligned tail pointer +*/ +#ifdef SW_CACHE_MGMT +#define IX_SWQ_BA_TAIL_INVALIDATE(queue) do{ \ + IX_OSAL_CACHE_INVALIDATE((queue).byteTail,IX_QMGR_SIZEOF_BYTE); \ + } while(0) +#else +#define IX_SWQ_BA_TAIL_INVALIDATE(queue) do{} while(0) +#endif + +#ifdef SW_CACHE_MGMT +#define IX_SWQ_CACHE_INVALIDATE(pointer,size) do{ \ + IX_OSAL_CACHE_INVALIDATE(pointer,size); \ + } while(0) +#else +#define IX_SWQ_CACHE_INVALIDATE(pointer,size) do{} while(0) +#endif + +#ifdef SW_CACHE_MGMT +#define IX_SWQ_CACHE_FLUSH(pointer,size) do{ \ + IX_OSAL_CACHE_FLUSH(pointer,size); \ + } while(0) +#else +#define IX_SWQ_CACHE_FLUSH(pointer,size) do{} while(0) +#endif + + + + +/* + * The following macros are specific for queues that have head and tail + * pointers that are word aligned and count in bytes + */ +/** +* @def IX_SWQ_WA_CB_QUEUE_EMPTY +* @brief tests whether the queue is empty +*/ +#define IX_SWQ_WA_CB_QUEUE_EMPTY(queue) \ + (IX_SWQ_WA_CB_QUEUE_BYTE_COUNT(queue) == 0) +/** +* @def IX_SWQ_WA_CB_QUEUE_FULL +* @brief tests whether the queue is full +*/ +#define IX_SWQ_WA_CB_QUEUE_FULL(queue) \ + (IX_SWQ_WA_CB_QUEUE_BYTE_COUNT(queue) == (queue).sizeInBytes) + +/** +* @def IX_SWQ_WA_CB_NUM_ENTRIES_GET +* @brief gets the number of entries currently queued +*/ +#define IX_SWQ_WA_CB_NUM_ENTRIES_GET(queue, numberOfEntries) do { \ + (numberOfEntries) = (IX_SWQ_WA_CB_QUEUE_BYTE_COUNT(queue) >> \ + (queue).entrySizeBytePow); \ + } while(0) +/** +* @def IX_SWQ_WA_CB_HEAD_PTR +*/ +#define IX_SWQ_WA_CB_HEAD_PTR(queue) \ + ((queue).wordHead) + +/** +* @def IX_SWQ_WA_CB_TAIL_PTR +*/ +#define IX_SWQ_WA_CB_TAIL_PTR(queue) \ + ((queue).wordTail) + +/** +* @def IX_SWQ_WA_CB_TAIL +* @brief Get the Tail pointer of a Queue +*/ +#define IX_SWQ_WA_CB_TAIL(queue) \ + ((IX_SWQ_BE_SHARED_LONG_READ((queue).wordTail) & (queue).mask) \ + >> IX_SWQ_BYTES_POW_IN_WORD) + +/** +* @def IX_SWQ_WA_CB_TAIL_INCR +* @brief Increment the Tail pointer of a Queue +*/ +#define IX_SWQ_WA_CB_TAIL_INCR(queue) do { \ + IX_SWQ_BE_SHARED_LONG_WRITE((queue).wordTail, \ + (IX_SWQ_BE_SHARED_LONG_READ((queue).wordTail) + \ + (queue).entrySizeInBytes)); \ + } while (0) + +/** +* @def IX_SWQ_WA_CB_TAIL_ADVANCE +* @brief Advance the Tail pointer of a Queue +*/ +#define IX_SWQ_WA_CB_TAIL_ADVANCE(queue,numberOfEntries) do { \ + IX_SWQ_BE_SHARED_LONG_WRITE((queue).wordTail, \ + (IX_SWQ_BE_SHARED_LONG_READ((queue).wordTail) + \ + ((numberOfEntries) << (queue).entrySizeBytePow))); \ + } while (0) + +/** +* @def IX_SWQ_WA_CB_TAIL_RESET +* @brief Reset the Tail pointer +*/ +#define IX_SWQ_WA_CB_TAIL_RESET(queue) \ + (IX_SWQ_BE_SHARED_LONG_WRITE((queue).wordTail,0)) + +/** +* @def IX_SWQ_WA_CB_HEAD +* @brief Get the Head pointer of a Queue +*/ +#define IX_SWQ_WA_CB_HEAD(queue) \ + ((IX_SWQ_BE_SHARED_LONG_READ((queue).wordHead) & (queue).mask) \ + >> IX_SWQ_BYTES_POW_IN_WORD) + +/** +* @def IX_SWQ_WA_CB_HEAD_INCR +* @brief Increment the Head pointer of a Queue +*/ +#define IX_SWQ_WA_CB_HEAD_INCR(queue) do { \ + IX_SWQ_BE_SHARED_LONG_WRITE((queue).wordHead, \ + (IX_SWQ_BE_SHARED_LONG_READ((queue).wordHead) + \ + (queue).entrySizeInBytes)); \ + } while (0) + +/** +* @def IX_SWQ_WA_CB_HEAD_RESET +* @brief Reset the Head pointer +*/ +#define IX_SWQ_WA_CB_HEAD_RESET(queue) \ + (IX_SWQ_BE_SHARED_LONG_WRITE((queue).wordHead,0)) + + +/** +* @def IX_SWQ_WA_CB_TAIL_ENTRY_GET +* @brief Get the entry at the tail of a Queue +*/ +#define IX_SWQ_WA_CB_TAIL_ENTRY_GET(queue) \ + (queue).content[(IX_SWQ_WA_CB_TAIL(queue))] + +/** +* @def IX_SWQ_WA_CB_HEAD_ENTRY_GET +* @brief Get the entry at the head of a Queue +*/ +#define IX_SWQ_WA_CB_HEAD_ENTRY_GET(queue) \ + (queue).content[(IX_SWQ_WA_CB_HEAD(queue))] + + +/** +* @def IX_SWQ_WA_CB_TAIL_CACHE_INVALIDATE_AFTER_DEQUEUE +* @brief Invalidate the memory at the entry at the tail of a Queue +* +* This macro assumes the memory does not wrap around the queue boundaries. +* It invalidates the memory used by the queue entries just being read. +* This macro should be used after reading a certain amount of queue +* entries and before incrementing the tail pointer. +* Memory pointer and length are modified to round down and up to +* cache line boundaries, for efficiency. +*/ +#define IX_SWQ_WA_CB_TAIL_INVALIDATE_AFTER_DEQUEUE(queue,numberOfEntries) do { \ + UINT32 start = (UINT32)&IX_SWQ_WA_CB_TAIL_ENTRY_GET(queue); \ + UINT32 end = start + ((numberOfEntries) << (queue).entrySizeBytePow); \ + start &= ~IX_SWQ_CACHE_LINE_MASK; \ + end = (end + IX_SWQ_CACHE_LINE_MASK) & ~IX_SWQ_CACHE_LINE_MASK; \ + IX_SWQ_CACHE_INVALIDATE(start, end - start); \ + } while(0) + +/** +* @def IX_SWQ_WA_CB_ENTRY_ENQUEUE +* @brief puts an entry at the head of the queue and increments head counter +* and flush the queue memory at head counter +*/ +#define IX_SWQ_WA_CB_ENTRY_ENQUEUE(queue,entry) do { \ + UINT32 entrySize = IX_SWQ_ENTRY_SIZE_WORDS(queue); \ + volatile UINT32 *qEntry = &IX_SWQ_WA_CB_HEAD_ENTRY_GET(queue); \ + UINT32 *tmpPtr = (UINT32 *)(entry); \ + for(;entrySize>0;entrySize--) \ + { \ + *qEntry = *tmpPtr; \ + qEntry++; \ + tmpPtr++; \ + } \ + qEntry -= IX_SWQ_ENTRY_SIZE_WORDS(queue); \ + IX_SWQ_CACHE_FLUSH ((UINT32 *)qEntry,(queue).entrySizeInBytes); \ + IX_SWQ_WA_CB_HEAD_INCR(queue); \ + IX_SWQ_CACHE_FLUSH ((queue).wordHead,IX_QMGR_SIZEOF_WORD); \ + } while (0) + + +/** +* @def IX_SWQ_WA_CB_ENTRY_DEQUEUE +* @brief gets an entry from the tail of the queue, clean the corresponding +* cache line and increments tail counter. +*/ +#define IX_SWQ_WA_CB_ENTRY_DEQUEUE(queue,entry) do { \ + UINT32 entrySize = IX_SWQ_ENTRY_SIZE_WORDS(queue); \ + VUINT32 *qEntry = &IX_SWQ_WA_CB_TAIL_ENTRY_GET(queue); \ + UINT32 *tmpPtr = (UINT32 *)(entry); \ + for(;entrySize>0;entrySize--) \ + { \ + *tmpPtr = *qEntry; \ + tmpPtr++; \ + qEntry++; \ + } \ + IX_SWQ_WA_CB_TAIL_INVALIDATE_AFTER_DEQUEUE(queue,1); \ + IX_SWQ_WA_CB_TAIL_INCR((queue)); \ + } while(0) + + +/** +* @def IX_SWQ_WA_CB_QUEUE_BYTE_COUNT +* @brief number of bytes in a queue +*/ +#define IX_SWQ_WA_CB_QUEUE_BYTE_COUNT(queue) \ + ((IX_SWQ_BE_SHARED_LONG_READ((queue).wordHead) - \ + IX_SWQ_BE_SHARED_LONG_READ((queue).wordTail)) & IX_SWQ_WA_COUNTER_MASK) + +/* + *The following macros are specific for queues that have head and tail + * pointers that are word aligned and count in entries + */ + + +/** +* @def IX_SWQ_WA_CE_QUEUE_EMPTY +* @brief tests whether the queue is empty +*/ +#define IX_SWQ_WA_CE_QUEUE_EMPTY(queue) \ + (IX_SWQ_WA_CE_QUEUE_BYTE_COUNT(queue) == 0) + +/** +* @def IX_SWQ_WA_CE_QUEUE_FULL +* @brief tests whether the queue is full +*/ +#define IX_SWQ_WA_CE_QUEUE_FULL(queue) \ + (IX_SWQ_WA_CE_QUEUE_BYTE_COUNT(queue) == (queue).sizeInBytes) + + +/** +* @def IX_SWQ_WA_CE_NUM_ENTRIES_GET +* @brief gets the number of entries currently queued +*/ +#define IX_SWQ_WA_CE_NUM_ENTRIES_GET(queue, numberOfEntries) do { \ + (numberOfEntries) = (IX_SWQ_WA_CE_QUEUE_ENTRY_COUNT(queue)); \ + } while(0) + +/** +* @def IX_SWQ_WA_CE_HEAD_PTR +*/ +#define IX_SWQ_WA_CE_HEAD_PTR(queue) \ + ((queue).wordHead) + +/** +* @def IX_SWQ_WA_CE_TAIL_PTR +*/ +#define IX_SWQ_WA_CE_TAIL_PTR(queue) \ + ((queue).wordTail) + + +/** +* @def IX_SWQ_WA_CE_TAIL +* @brief Get the Tail pointer of a Queue +* +*/ +#define IX_SWQ_WA_CE_TAIL(queue) \ + ((IX_SWQ_BE_SHARED_LONG_READ((queue).wordTail) & (queue).mask) \ + << (queue).entrySizeWordPow) + +/** +* @def IX_SWQ_WA_CE_TAIL_INCR +* @brief Increment the Tail pointer of a Queue +*/ +#define IX_SWQ_WA_CE_TAIL_INCR(queue) do { \ + IX_SWQ_BE_SHARED_LONG_WRITE((queue).wordTail, \ + (IX_SWQ_BE_SHARED_LONG_READ((queue).wordTail) + 1)); \ + } while (0) + +/** +* @def IX_SWQ_WA_CE_TAIL_ADVANCE +* @brief Advance the Tail pointer of a Queue +*/ +#define IX_SWQ_WA_CE_TAIL_ADVANCE(queue,numberOfEntries) do { \ + IX_SWQ_BE_SHARED_LONG_WRITE((queue).wordTail, \ + (IX_SWQ_BE_SHARED_LONG_READ((queue).wordTail) + (numberOfEntries))); \ + } while (0) + +/** +* @def IX_SWQ_WA_CE_TAIL_RESET +* @brief Reset the Tail pointer +*/ +#define IX_SWQ_WA_CE_TAIL_RESET(queue) do { \ + IX_SWQ_BE_SHARED_LONG_WRITE((queue).wordTail,0); \ + } while (0) + + +/** +* @def IX_SWQ_WA_CE_HEAD +* @brief Get the Head pointer of a Queue +*/ +#define IX_SWQ_WA_CE_HEAD(queue) \ + ((IX_SWQ_BE_SHARED_LONG_READ((queue).wordHead) & (queue).mask) \ + << (queue).entrySizeWordPow) + + +/** +* @def IX_SWQ_WA_CE_HEAD_INCR +* @brief Increment the Head pointer of a Queue +*/ +#define IX_SWQ_WA_CE_HEAD_INCR(queue) do { \ + IX_SWQ_BE_SHARED_LONG_WRITE((queue).wordHead, \ + (IX_SWQ_BE_SHARED_LONG_READ((queue).wordHead) + 1)); \ + } while (0) + +/** +* @def IX_SWQ_WA_CE_HEAD_RESET +* @brief Reset the Head pointer +*/ +#define IX_SWQ_WA_CE_HEAD_RESET(queue) do { \ + IX_SWQ_BE_SHARED_LONG_WRITE((queue).wordHead,0); \ + } while (0) + +/** +* @def IX_SWQ_WA_CE_HEAD_SET +* @brief Set the Head pointer +*/ +#define IX_SWQ_WA_CE_HEAD_SET(queue,value) \ + (IX_SWQ_BE_SHARED_LONG_WRITE((queue).wordHead,value)) + +/** +* @def IX_SWQ_WA_CE_TAIL_ENTRY_GET +* @brief Get the entry at the tail of a Queue +*/ +#define IX_SWQ_WA_CE_TAIL_ENTRY_GET(queue) \ + (queue).content[(IX_SWQ_WA_CE_TAIL(queue))] + +/** +* @def IX_SWQ_WA_CE_HEAD_ENTRY_GET +* @brief Get the entry at the head of a Queue +*/ +#define IX_SWQ_WA_CE_HEAD_ENTRY_GET(queue) \ + (queue).content[(IX_SWQ_WA_CE_HEAD(queue))] + +/** +* @def IX_SWQ_WA_CE_TAIL_INVALIDATE_AFTER_DEQUEUE +* @brief Invalidate the memory at the entry at the tail of a Queue +* +* This macro assumes the memory does not wrap around the queue boundaries. +* It invalidates the memory used by the queue entries just being read. +* This macro should be used after reading a certain amount of queue +* entries and before incrementing the tail pointer. +* Memory pointer and length are modified to round down and up to +* cache line boundaries, for efficiency. +*/ +#define IX_SWQ_WA_CE_TAIL_INVALIDATE_AFTER_DEQUEUE(queue,numberOfEntries) do { \ + UINT32 start = (UINT32)&IX_SWQ_WA_CE_TAIL_ENTRY_GET(queue); \ + UINT32 end = start + ((numberOfEntries) << (queue).entrySizeBytePow); \ + start &= ~IX_SWQ_CACHE_LINE_MASK; \ + end = (end + IX_SWQ_CACHE_LINE_MASK) & ~IX_SWQ_CACHE_LINE_MASK; \ + IX_SWQ_CACHE_INVALIDATE(start, end - start); \ + } while(0) + +/** +* @def IX_SWQ_WA_CE_ENTRY_ENQUEUE +* @brief puts an entry at the head of the queue and increments head counter +* and flush the queue memory at head counter +*/ +#define IX_SWQ_WA_CE_ENTRY_ENQUEUE(queue,entry) do { \ + UINT32 entrySize = IX_SWQ_ENTRY_SIZE_WORDS(queue); \ + VUINT32 *qEntry = &IX_SWQ_WA_CE_HEAD_ENTRY_GET(queue); \ + UINT32 *tmpPtr = (UINT32 *)(entry); \ + for(;entrySize>0;entrySize--) \ + { \ + *qEntry = *tmpPtr; \ + qEntry++; \ + tmpPtr++; \ + } \ + qEntry -= IX_SWQ_ENTRY_SIZE_WORDS(queue); \ + IX_SWQ_CACHE_FLUSH ((UINT32 *)qEntry,(queue).entrySizeInBytes); \ + IX_SWQ_WA_CE_HEAD_INCR(queue); \ + IX_SWQ_CACHE_FLUSH ((queue).wordHead,IX_QMGR_SIZEOF_WORD); \ + } while (0) + +/** +* @def IX_SWQ_WA_CE_ENTRY_DEQUEUE +* @brief gets an entry from the tail of the queue, clean the corresponding +* cache line and increments tail counter. +* @note an invalidate of the head counter must be done before this macro +*/ +#define IX_SWQ_WA_CE_ENTRY_DEQUEUE(queue,entry) do { \ + UINT32 entrySize = IX_SWQ_ENTRY_SIZE_WORDS(queue); \ + VUINT32 *qEntry = &IX_SWQ_WA_CE_TAIL_ENTRY_GET(queue); \ + UINT32 *tmpPtr = (UINT32 *)(entry); \ + for(;entrySize>0;entrySize--) \ + { \ + *tmpPtr = *qEntry; \ + tmpPtr++; \ + qEntry++; \ + } \ + IX_SWQ_WA_CE_TAIL_INVALIDATE_AFTER_DEQUEUE(queue,1); \ + IX_SWQ_WA_CE_TAIL_INCR((queue)); \ + } while(0) + +/** +* @def IX_SWQ_WA_CE_QUEUE_BYTE_COUNT +* @brief number of bytes in a queue +*/ +/* +#define IX_SWQ_WA_CE_QUEUE_BYTE_COUNT(queue) \ + (((IX_SWQ_BE_SHARED_LONG_READ((queue).wordHead) - \ + IX_SWQ_BE_SHARED_LONG_READ((queue).wordTail)) & \ + IX_SWQ_WA_COUNTER_MASK) * (queue).entrySizeInBytes) +*/ +#define IX_SWQ_WA_CE_QUEUE_BYTE_COUNT(queue) \ + (IX_SWQ_WA_CE_QUEUE_ENTRY_COUNT(queue) * (queue).entrySizeInBytes) + +/** +* @def IX_SWQ_WA_CE_QUEUE_ENTRY_COUNT +* @brief number of entries in a queue +*/ +#define IX_SWQ_WA_CE_QUEUE_ENTRY_COUNT(queue) \ + ((IX_SWQ_BE_SHARED_LONG_READ((queue).wordHead) - \ + IX_SWQ_BE_SHARED_LONG_READ((queue).wordTail)) & IX_SWQ_WA_COUNTER_MASK) + +/* + * The following macros are specific for queues that have head and tail + * pointers that are byte aligned and count in entries + */ + +/** +* @def IX_SWQ_BA_CE_QUEUE_EMPTY +* @brief tests whether the queue is empty +*/ +#define IX_SWQ_BA_CE_QUEUE_EMPTY(queue) \ + (IX_SWQ_BA_CE_QUEUE_BYTE_COUNT(queue) == 0) +/** +* @def IX_SWQ_BA_CE_QUEUE_FULL +* @brief tests whether the queue is full +*/ +/* +#define IX_SWQ_BA_CE_QUEUE_FULL(queue) \ + (IX_SWQ_BA_CE_QUEUE_BYTE_COUNT(queue) == (queue).sizeInBytes) +*/ +#define IX_SWQ_BA_CE_QUEUE_FULL(queue) \ + (IX_SWQ_BA_CE_QUEUE_BYTE_COUNT(queue) == (queue).sizeInBytes) + + + /** +* @def IX_SWQ_BA_CE_NUM_ENTRIES_GET +* @brief gets the number of entries currently queued +*/ +#define IX_SWQ_BA_CE_NUM_ENTRIES_GET(queue, numberOfEntries) do { \ + (numberOfEntries) = (IX_SWQ_BA_CE_QUEUE_ENTRY_COUNT(queue)); \ + } while(0) + +/** +* @def IX_SWQ_BA_CE_HEAD_PTR +*/ +#define IX_SWQ_BA_CE_HEAD_PTR(queue) \ + ((queue).byteHead) + +/** +* @def IX_SWQ_BA_CE_TAIL_PTR +*/ +#define IX_SWQ_BA_CE_TAIL_PTR(queue) \ + ((queue).byteTail) + +/** +* @def IX_SWQ_BA_CE_TAIL +* @brief Get the Tail pointer of a Queue +*/ +#define IX_SWQ_BA_CE_TAIL(queue) \ + ((IX_SWQ_BE_SHARED_BYTE_READ((queue).byteTail) & \ + (queue).mask) << (queue).entrySizeWordPow) + +/** +* @def IX_SWQ_BA_CE_TAIL_INCR +* @brief Increment the Tail pointer of a Queue +*/ +#define IX_SWQ_BA_CE_TAIL_INCR(queue) do { \ + IX_SWQ_BE_SHARED_BYTE_WRITE((queue).byteTail, \ + (IX_SWQ_BE_SHARED_BYTE_READ((queue).byteTail) + 1)); \ + } while (0) +/** +* @def IX_SWQ_BA_CE_TAIL_ADVANCE +* @brief Advance the Tail pointer of a Queue +*/ +#define IX_SWQ_BA_CE_TAIL_ADVANCE(queue,numberOfEntries) do { \ + IX_SWQ_BE_SHARED_BYTE_WRITE((queue).byteTail, \ + (IX_SWQ_BE_SHARED_BYTE_READ((queue).byteTail) + (numberOfEntries))); \ + } while (0) + +/** +* @def IX_SWQ_BA_CE_TAIL_RESET +* @brief Reset the Tail pointer +*/ +#define IX_SWQ_BA_CE_TAIL_RESET(queue) \ + (IX_SWQ_BE_SHARED_BYTE_WRITE((queue).byteTail,0)) + +/** +* @def IX_SWQ_BA_CE_HEAD +* @brief Get the Head pointer of a Queue +*/ +#define IX_SWQ_BA_CE_HEAD(queue) \ + ((IX_SWQ_BE_SHARED_BYTE_READ((queue).byteHead) & \ + (queue).mask) << (queue).entrySizeWordPow) +/** +* @def IX_SWQ_BA_CE_HEAD_INCR +* @brief Increment the Head pointer of a Queue +*/ +#define IX_SWQ_BA_CE_HEAD_INCR(queue) do { \ + IX_SWQ_BE_SHARED_BYTE_WRITE((queue).byteHead, \ + (IX_SWQ_BE_SHARED_BYTE_READ((queue).byteHead) + 1)); \ + } while (0) + +/** +* @def IX_SWQ_BA_CE_HEAD_RESET +* @brief Reset the Head pointer +*/ +#define IX_SWQ_BA_CE_HEAD_RESET(queue) \ + (IX_SWQ_BE_SHARED_BYTE_WRITE((queue).byteHead,0)) + +/** +* @def IX_SWQ_BA_CE_HEAD_SET +* @brief Set the Head pointer +*/ +#define IX_SWQ_BA_CE_HEAD_SET(queue,value) \ + (IX_SWQ_BE_SHARED_BYTE_WRITE((queue).byteHead,value)) + +/** +* @def IX_SWQ_BA_CE_TAIL_ENTRY_GET +* @brief Get the entry at the tail of a Queue +*/ +#define IX_SWQ_BA_CE_TAIL_ENTRY_GET(queue) \ + (queue).content[(IX_SWQ_BA_CE_TAIL(queue))] +/** +* @def IX_SWQ_BA_CE_HEAD_ENTRY_GET +* @brief Get the entry at the head of a Queue +*/ +#define IX_SWQ_BA_CE_HEAD_ENTRY_GET(queue) \ + (queue).content[(IX_SWQ_BA_CE_HEAD(queue))] + +/** +* @def IX_SWQ_BA_CE_TAIL_INVALIDATE_AFTER_DEQUEUE +* @brief Invalidate the memory at the entry at the tail of a Queue +* +* This macro assumes the memory does not wrap around the queue boundaries. +* It invalidates the memory used by the queue entries just being read. +* This macro should be used after reading a certain amount of queue +* entries and before incrementing the tail pointer. +* Memory pointer and length are modified to round down and up to +* cache line boundaries, for efficiency. +*/ +#define IX_SWQ_BA_CE_TAIL_INVALIDATE_AFTER_DEQUEUE(queue,numberOfEntries) do { \ + UINT32 start = (UINT32)&IX_SWQ_BA_CE_TAIL_ENTRY_GET(queue); \ + UINT32 end = start + ((numberOfEntries) << (queue).entrySizeBytePow); \ + start &= ~IX_SWQ_CACHE_LINE_MASK; \ + end = (end + IX_SWQ_CACHE_LINE_MASK) & ~IX_SWQ_CACHE_LINE_MASK; \ + IX_SWQ_CACHE_INVALIDATE(start, end - start); \ + } while(0) + +/** +* @def IX_SWQ_BA_CE_ENTRY_ENQUEUE +* @brief puts an entry at the head of the queue and increments head counter +* and flush the queue memory at head counter +*/ +#define IX_SWQ_BA_CE_ENTRY_ENQUEUE(queue,entry) do { \ + UINT32 entrySize = IX_SWQ_ENTRY_SIZE_WORDS(queue); \ + VUINT32 *qEntry = &IX_SWQ_BA_CE_HEAD_ENTRY_GET(queue); \ + UINT32 *tmpPtr = (UINT32 *)(entry); \ + for(;entrySize>0;entrySize--) \ + { \ + *qEntry = *tmpPtr; \ + qEntry++; \ + tmpPtr++; \ + } \ + qEntry -= IX_SWQ_ENTRY_SIZE_WORDS(queue); \ + IX_SWQ_CACHE_FLUSH ((UINT32 *)qEntry,(queue).entrySizeInBytes); \ + IX_SWQ_BA_CE_HEAD_INCR(queue); \ + IX_SWQ_CACHE_FLUSH ((queue).byteHead,IX_QMGR_SIZEOF_BYTE); \ + } while (0) + +/** +* @def IX_SWQ_BA_CE_ENTRY_DEQUEUE +* @brief gets an entry from the tail of the queue, clean the corresponding +* cache line and increments tail counter. +*/ + #define IX_SWQ_BA_CE_ENTRY_DEQUEUE(queue,entry) do { \ + UINT32 entrySize = IX_SWQ_ENTRY_SIZE_WORDS(queue); \ + VUINT32 *qEntry = &IX_SWQ_BA_CE_TAIL_ENTRY_GET(queue); \ + UINT32 *tmpPtr = (UINT32 *)(entry); \ + for(;entrySize>0;entrySize--) \ + { \ + *tmpPtr = *qEntry; \ + tmpPtr++; \ + qEntry++; \ + } \ + IX_SWQ_BA_CE_TAIL_INVALIDATE_AFTER_DEQUEUE(queue,1); \ + IX_SWQ_BA_CE_TAIL_INCR((queue)); \ + } while(0) + + +/** +* @def IX_SWQ_BA_CE_QUEUE_BYTE_COUNT +* @brief number of bytes in a queue +*/ +#define IX_SWQ_BA_CE_QUEUE_BYTE_COUNT(queue) \ + (IX_SWQ_BA_CE_QUEUE_ENTRY_COUNT(queue) * (queue).entrySizeInBytes) + +/** +* @def IX_SWQ_BA_CE_QUEUE_ENTRY_COUNT +* @brief number of entries in a queue +*/ +#define IX_SWQ_BA_CE_QUEUE_ENTRY_COUNT(queue) \ + ((IX_SWQ_BE_SHARED_BYTE_READ((queue).byteHead) - \ + IX_SWQ_BE_SHARED_BYTE_READ((queue).byteTail)) & IX_SWQ_BA_COUNTER_MASK) + + +#endif /* IX_SW_QUEUE_H */ + diff --git a/Acceleration/include/hss/icp_hssacc.h b/Acceleration/include/hss/icp_hssacc.h new file mode 100644 index 0000000..8728070 --- /dev/null +++ b/Acceleration/include/hss/icp_hssacc.h @@ -0,0 +1,3017 @@ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +/* + ***************************************************************************** + * Doxygen group definitions + ****************************************************************************/ + +/** + ****************************************************************************** + * @defgroup icp_HssAcc Public API for the HSS TDM I/O Unit + * + * @purpose + * + * The High Speed Serial (HSS) I/O Access Library is the + * software that provides an interface to the Time Division + * Multiplexing (TDM) I/O Unit to higher level software such as + * device drivers. The TDM I/O Unit provides the majority of + * the HSS data processing (e.g. segmentation, encoding, + * decoding, reassembly) and contains coprocessors to assist + * with these functions. + * + * An example of clients of the access library are the HSS + * Voice driver and the HSS PPP Data driver. + *****************************************************************************/ + +/** + ****************************************************************************** + * @defgroup icp_HssAccInitShutdown HSS API for init/shutdown operations + * @ingroup icp_HssAcc + * Initialization and shutdown functions for the HSS TDM I/O Unit. + * + * @purpose + * The functions in this group are responsible for all initialization + * and shutdown of the HSS TDM I/O Unit. + *****************************************************************************/ + +/** + ****************************************************************************** + * @defgroup icp_HssAccPortConfig HSS API for port operations + * @ingroup icp_HssAcc + * Port configuration functions for the HSS TDM I/O Unit. + * + * @purpose + * The functions in this group are responsible for all aspects of the + * HSS TDM I/O Unit port configuration. + *****************************************************************************/ + +/** + ****************************************************************************** + * @defgroup icp_HssAccChannelConfig HSS API for channel operations + * @ingroup icp_HssAcc + * Channel configuration functions for the HSS TDM I/O Unit. + * These functions apply to both types of channels, where a function + * is type specific it will be clearly stated. + * + * @purpose + * The functions in this group are responsible for all aspects of the + * HSS TDM I/O Unit channel configuration. + *****************************************************************************/ + +/** + ****************************************************************************** + * @defgroup icp_HssAccDataPath HSS data path API + * @ingroup icp_HssAcc + * Data path functions for the HSS TDM I/O Unit. + * + * @purpose + * The functions in this group are responsible for all aspects of the + * HSS TDM I/O Unit data path. + *****************************************************************************/ + +/** + ****************************************************************************** + * @defgroup icp_HssAccDataPathCallbackMode HSS callback API + * @ingroup icp_HssAccDataPath + * Data path functions that work in callback mode for the HSS TDM + * I/O Unit. + * + * @purpose + * The functions in this group are responsible for all aspects of the + * HSS TDM I/O Unit data path. These are designed to callback the + * client. + *****************************************************************************/ + +/** + ****************************************************************************** + * @defgroup icp_HssAccDataPathPolledMode HSS polling API + * @ingroup icp_HssAccDataPath + * Data path functions that work in polled mode for the HSS TDM + * I/O Unit. These APIs could be called by the client as a + * result of a callback. + * + * @purpose + * The functions in this group are responsible for all aspects of the + * HSS TDM I/O Unit data path. These are designed to work in + * polled mode. + *****************************************************************************/ + +/** + ****************************************************************************** + * @defgroup icp_HssAccVoiceBypass HSS voice channel bypass API + * @ingroup icp_HssAccDataPath + * Voice Bypass functions (timeslot switching) for the HSS TDM I/O Unit. + * + * @purpose + * The functions in this group are responsible for all aspects + * of HSS TDM I/O Unit voice bypass. This includes setting up + * the gain control tables as well as enabling and disabling voice + * bypasses. + *****************************************************************************/ + +/** + ****************************************************************************** + * @defgroup icp_HssAccErrors HSS API Error callback definition and registration + * @ingroup icp_HssAcc + * Functions and type definitions for the HSS TDM I/O Unit Error + * reporting. + * + * @purpose + * The functions and type definitions in this group are responsible + * for facilitating the error reporting of all errors from the + * HSS TDM I/O Unit. + *****************************************************************************/ + + +/** + ****************************************************************************** + * @defgroup icp_HssAccStats HSS API statistics and show operations + * @ingroup icp_HssAcc + * Statistics and show functions for the HSS TDM I/O Unit. + * + * @purpose + * The functions in this group are responsible for all statistics and + * show functions for the HSS TDM I/O Unit. + *****************************************************************************/ + +#ifndef ICP_HSSACC_H +#define ICP_HSSACC_H + + +#include "IxOsal.h" + +#include "icp.h" + +/* ---------------------------------------------------------------------------- + * Defines + * --------------------------------------------------------------------------- + */ +/** + * @ingroup icp_HssAccVoiceBypass + * Size of the Gain Control Table (GCT). + * @description + * Used to define the size of the client gain control table byte array. + */ +#define ICP_HSSACC_BYPASS_GCT_SIZE 256 + +/* ---------------------------------------------------------------------------- + * Enumerated Types + * --------------------------------------------------------------------------- + */ + +/** + * @ingroup icp_HssAccPortConfig + * HSS Clock Speed setting. + * @description + * Used to set the HSS clock speed. + */ +typedef enum +{ + ICP_HSSACC_CLK_SPEED_1544KHZ = 0, + /**< 1.544MHz - Needed for single T1 Mode. */ + ICP_HSSACC_CLK_SPEED_2048KHZ, + /**< 2.048MHz - Needed for Single E1 Mode. */ + ICP_HSSACC_CLK_SPEED_8192KHZ, + /**< 8.192MHz - Needed for Quad MVIP. */ + ICP_HSSACC_CLK_SPEED_DELIMITER + /**< Delimiter for error checking. */ +} icp_hssacc_clk_speed_t; + +/** + * @ingroup icp_HssAccPortConfig + * HSS frame sync type. + * @description + * Used to identify how the frame synchronization is triggered. + */ +typedef enum +{ + ICP_HSSACC_FRM_PULSE_SYNC_ACTIVE_LOW = 0, + /**< Frame sync is sampled low. */ + ICP_HSSACC_FRM_PULSE_SYNC_ACTIVE_HIGH, + /**< Frame sync is sampled high. */ + ICP_HSSACC_FRM_PULSE_SYNC_FALLING_EDGE, + /**< Frame sync sampled on a falling edge. */ + ICP_HSSACC_FRM_PULSE_SYNC_RISING_EDGE, + /**< Frame sync sampled on a rising edge. */ + ICP_HSSACC_FRM_PULSE_SYNC_TYPE_DELIMITER + /**< Delimiter for error checks. */ +} icp_hssacc_frm_pulse_sync_type_t; + +/** + * @ingroup icp_HssAccPortConfig + * Frame Sync I/O usage. + * @description + * Used to specify how the frame pulse is used. + */ +typedef enum +{ + ICP_HSSACC_FRM_PULSE_SYNC_IO_TYPE_INPUT = 0, + /**< Frame sync is detected as an input. */ + ICP_HSSACC_FRM_PULSE_SYNC_IO_TYPE_INVALID_VALUE = 1, + /**< This value is a place holder in the enum and is not used. */ + ICP_HSSACC_FRM_PULSE_SYNC_IO_TYPE_OUTPUT_FALLING = 2, + /**< Frame sync is an output generated off a falling clock edge. */ + ICP_HSSACC_FRM_PULSE_SYNC_IO_TYPE_OUTPUT_RISING = 3, + /**< Frame sync is an output generated off a rising clock edge. */ + ICP_HSSACC_FRM_PULSE_SYNC_IO_TYPE_DELIMITER + /**< Delimiter for error checks. */ +} icp_hssacc_frm_pulse_sync_io_type_t; + +/** + * @ingroup icp_HssAccPortConfig + * Frame Sync clock edge. + * @description + * Used to specify how the frame pulse is sampled, i.e. based on the + * rising or falling clock edge. + */ +typedef enum +{ + ICP_HSSACC_CLK_EDGE_FALLING = 0, + /**< Clock is sampled off a falling clock edge. */ + ICP_HSSACC_CLK_EDGE_RISING, + /**< Clock is sampled off a rising clock edge. */ + ICP_HSSACC_CLK_EDGE_TYPE_DELIMITER + /**< Delimiter for error checks. */ +} icp_hssacc_clk_edge_t; + + +/** + * @ingroup icp_HssAccPortConfig + * HSS Frame pulse setting. + * @description + * Used to enable/disable the HSS frame pulse usage. + */ +typedef enum +{ + ICP_HSSACC_FRM_PULSE_USAGE_ENABLED = 0, + /**< Generate/Receive frame pulses. */ + ICP_HSSACC_FRM_PULSE_USAGE_DISABLED, + /**< Disregard frame pulses. */ + ICP_HSSACC_FRM_PULSE_USAGE_TYPE_DELIMITER + /**< Delimiter for error checks. */ +} icp_hssacc_frm_pulse_usage_t; + + + +/** + * @ingroup icp_HssAccPortConfig + * HSS clock internal/external input/output settings. + * @description + * Used to specify how the clock is driven for each + * direction. This setting MUST be specified for both Receive and + * Transmit directions. Some options are only available in a specific + * direction and some options may not be supported on specific + * platforms. Invalid options will be rejected during + * configuration.*/ +typedef enum +{ + ICP_HSSACC_CLK_MODE_INPUT_EXTERNAL = 0, + /**< Clock is an input from external clock. */ + ICP_HSSACC_CLK_MODE_OUTPUT_REF, + /**< Clock is an output derived from ref clock (port 0 Receive Clock). */ + ICP_HSSACC_CLK_MODE_OUTPUT_INTERNAL, + /**< Clock is an output derived from the internal clock. */ + ICP_HSSACC_CLK_MODE_DELIMITER + /**< Delimiter for error checks. */ +} icp_hssacc_clk_mode_t; + + +/** + * @ingroup icp_HssAccPortConfig + * HSS Data polarity. + * @description + * Used to invert the HSS data polarity. + */ +typedef enum +{ + ICP_HSSACC_DATA_POLARITY_SAME = 0, + /**< No inversion of data coming to/from the line */ + ICP_HSSACC_DATA_POLARITY_INVERT, + /**< Invert data coming to/from the line */ + ICP_HSSACC_DATA_POLARITY_DELIMITER + /* Delimiter for error checks. */ +} icp_hssacc_data_polarity_t; + +/** + * @ingroup icp_HssAccPortConfig + * HSS Transmit pin operation. + * @description + * Used to set the HSS Transmit pins into normal or open drain mode. + */ +typedef enum +{ + ICP_HSSACC_TX_PINS_DRAIN_MODE_NORMAL = 0, + /**< Normal mode. */ + ICP_HSSACC_TX_PINS_DRAIN_MODE_OPEN_DRAIN, + /**< Open Drain mode. */ + ICP_HSSACC_TX_PINS_DRAIN_MODE_TYPE_DELIMITER + /**< Delimiter for error checks. */ +} icp_hssacc_tx_pins_drain_mode_t; + +/** + * @ingroup icp_HssAccPortConfig + * HSS Reference Frame In. + * @description + + * Used to specify if frame and clock synchronization is + * performed from port 0 Receive or not. This option can simplify + * the board design. Note: @ref + * icp_hssacc_frm_pulse_sync_io_type_t needs to be an output, + * i.e. ICP_HSSACC_FRM_PULSE_SYNC_IO_TYPE_OUTPUT_FALLING/RISING. */ +typedef enum +{ + ICP_HSSACC_REF_FRAME_NOT_SELECTED = 0, + /**< Reference Frame not used. */ + ICP_HSSACC_REF_FRAME_SELECTED, + /**< Reference Frame selected. */ + ICP_HSSACC_REF_FRAME_DELIMITER + /**< Delimiter for error checks. */ +} icp_hssacc_ref_frame_t; + +/** + * @ingroup icp_HssAccPortConfig + * HSS Data Pin setting. + * @description + * Used to enable the data transmission. The data pins are tri-stated + * when data transmission is stopped. + */ +typedef enum +{ + ICP_HSSACC_DATA_PINS_TRI_STATE = 0, + /**< Tri-state the data pins. */ + ICP_HSSACC_DATA_PINS_ENABLE, + /**< Push data out the data pins. */ + ICP_HSSACC_DATA_PINS_TYPE_DELIMITER + /**< Delimiter for error checks. */ +} icp_hssacc_data_pins_enable_t; + + +/** + * @ingroup icp_HssAccPortConfig + * Specifies how to drive the idle (unassigned/unsynchronized) data. + * @description + * Used to specify how to drive the data pins when transmitting + * idle (unassigned/unsynchronized) data. + */ +typedef enum +{ + ICP_HSSACC_UNASSIGNED_DRIVE_LOW = 0, + /**< Drive the data pins low. */ + ICP_HSSACC_UNASSIGNED_DRIVE_HIGH, + /**< Drive the data pins high. */ + ICP_HSSACC_UNASSIGNED_HIGH_IMPEDANCE, + /**< Drive the data pins with high impedance. */ + ICP_HSSACC_UNASSIGNED_DATA_DRIVE_DELIMITER + /**< Delimiter for error checks. */ +} icp_hssacc_unassigned_data_drive_type_t; + + +/** + * @ingroup icp_HssAccPortConfig + * HSS Framing Bit setting. + * @description + * Used to specify how to drive the F-Bit when it is enabled. + * Note: This will only be used for T1 @ 1.544MHz. + */ +typedef enum +{ + ICP_HSSACC_TX_FBIT_TYPE_FIFO = 0, + /**< F-Bit is dictated in FIFO. */ + ICP_HSSACC_TX_FBIT_TYPE_HIGH_IMP, + /**< F-Bit is high impedance. */ + ICP_HSSACC_TX_FBIT_TYPE_DELIMITER + /**< Delimiter for error checks. */ +} icp_hssacc_tx_fbit_type_t; + +/** + * @ingroup icp_HssAccPortConfig + * HSS Interleaving Mode setting. + * @description + * Used to describe if frame interleaving or byte + * interleaving mode is enabled. + */ +typedef enum + { + ICP_HSSACC_INTERLEAVING_FRAME = 0, + /**< Frame Interleaving. */ + ICP_HSSACC_INTERLEAVING_BYTE, + /**< Byte Interleaving. */ + ICP_HSSACC_INTERLEAVING_TYPE_DELIMITER + /**< Delimiter for error checks. */ +} icp_hssacc_interleaving_t; + + +/** + * @ingroup icp_HssAccChannelConfig + * Channel bit endianness setting. For Transmit, the LSb means that the Least + * Significant Bit is transmitted first on the serial line. MSb + * signifies the Most Significant Bit is transmitted first. + * For Receive, LSb means that the Least Significant bit is received + * first from the Line. MSb signifies the Most Significant Bit is + * received first. + * @description + * Used to set the Channel bit endianness. + */ +typedef enum +{ + ICP_HSSACC_BIT_ENDIAN_LSB = 0, + /**< Transmit/Receive Least Significant bit first. */ + ICP_HSSACC_BIT_ENDIAN_MSB, + /**< Transmit/Receive Most Significant bit first. */ + ICP_HSSACC_BIT_ENDIAN_DELIMITER + /**< Delimiter for the purposes of error checks. */ +} icp_hssacc_bit_endian_t; + + +/** + * @ingroup icp_HssAccChannelConfig + * HSS channel type. + * @description + * Used to specify the type of HSS channel. + */ +typedef enum +{ + ICP_HSSACC_CHAN_TYPE_HDLC = 0, + /**< HDLC Channel. */ + ICP_HSSACC_CHAN_TYPE_VOICE, + /**< Voice Channel. */ + ICP_HSSACC_CHAN_TYPE_DELIMITER + /**< Delimiter for error checks. */ +} icp_hssacc_channel_type_t; + + +/** + * @ingroup icp_HssAccChannelConfig + * HSS Bit Robbing Enable. + * @description + * Used to specify whether Bit Robbing is used or not. + */ +typedef enum + { + ICP_HSSACC_BIT_ROBBING_OFF = 0, + /**< Bit Robbing is off, this is a 64k channel. */ + ICP_HSSACC_BIT_ROBBING_ONE_BIT, + /**< One Bit is robbed, this is a 56k channel. */ + ICP_HSSACC_BIT_ROBBING_DELIMITER + /**< Bit Robbing error check delimiter. */ + } icp_hssacc_bit_robbing_t; + +/** + * @ingroup icp_HssAccChannelConfig + * HSS Robbed Bit value. + * @description + * Used to specify the value of the robbed bit with 56k Mode. + */ +typedef enum +{ + ICP_HSSACC_ROBBED_BIT_ZERO = 0, + /**< Robbed Bit set to zero. */ + ICP_HSSACC_ROBBED_BIT_ONE, + /**< Robbed Bit set to one. */ + ICP_HSSACC_ROBBED_BIT_DELIMITER + /**< Delimiter for error checks. */ +} icp_hssacc_robbed_bit_value_t; + +/** + * @ingroup icp_HssAccChannelConfig + * HSS robbed bit position. + * @description + * Used to specify the position of the unused bit in a 56k channel. + */ +typedef enum +{ + ICP_HSSACC_ROBBED_BIT_POS_7 = 0, + /**< Bit 7 is used as the robbed bit. */ + ICP_HSSACC_ROBBED_BIT_POS_0, + /**< Bit 0 is used as the robbed bit. */ + ICP_HSSACC_ROBBED_BIT_POS_DELIMITER + /**< Delimiter for error checks. */ +} icp_hssacc_robbed_bit_location_t; + +/** + * @ingroup icp_HssAccChannelConfig + * HSS HDLC Channel idle pattern. + * @description + * Used to set the HDLC channel idle transmission pattern. + */ +typedef enum +{ + ICP_HSSACC_HDLC_IDLE_PATTERN_FLAG = 0, + /**< Idle Transmit/Receive is repeated '0x7E' flag. */ + ICP_HSSACC_HDLC_IDLE_PATTERN_ONES, + /**< Idle Transmit/Receive is all ones. */ + ICP_HSSACC_HDLC_IDLE_PATTERN_DELIMITER + /**< Delimiter for error checks. */ +} icp_hssacc_hdlc_idle_pattern_t; + +/** + * @ingroup icp_HssAccChannelConfig + * HSS CRC Bit Width. + * @description + * Used to set the HSS HDLC Channel's CRC bit width. + */ +typedef enum +{ + ICP_HSSACC_HDLC_CRC_BIT_WIDTH_16 = 0, + /**< 16 bit CRC is being used. */ + ICP_HSSACC_HDLC_CRC_BIT_WIDTH_32, + /**< 32 bit CRC is being used. */ + ICP_HSSACC_HDLC_CRC_BIT_WIDTH_DELIMITER + /**< Delimiter for error checks. */ +} icp_hssacc_hdlc_crc_bit_width_t; + +/** + * @ingroup icp_HssAccChannelConfig + * HSS Start Of Frame (SOF) flag type. + * @description + * Used to decide if flag sharing is enabled. Choices are that + * the SOF flag is the same as the previous frame's End Of + * Frame (EOF) flag, or there is one SOF flag at the start of + * the frame, or there are two SOF flags at the start of the + * frame. + */ +typedef enum +{ + ICP_HSSACC_HDLC_SOF_SHARED_FLAG = 0, + /**< EOF and SOF shared. */ + ICP_HSSACC_HDLC_SOF_ONE_FLAG, + /**< One SOF flag at start of frame. */ + ICP_HSSACC_HDLC_SOF_TWO_FLAGS, + /**< Two SOF flags at start of frame. */ + ICP_HSSACC_HDLC_SOF_FLAG_TYPE_DELIMITER + /**< Delimiter for error check. */ +} icp_hssacc_hdlc_sof_flag_type_t; + + + +/** + * @ingroup icp_HssAccChannelConfig + * HSS Voice Transmit Idling Action. + * @description + * Used to specify if the TDM I/O Unit repeats the last frame when + * there is no new data to transmit or transmit an idle pattern instead. + */ + +typedef enum + { + ICP_HSSACC_VOICE_TX_IDLE_REPEAT_LAST_FRAME = 0, + /**< Repeat the last frame transmitted. */ + ICP_HSSACC_VOICE_TX_IDLE_PATTERN, + /**< Transmit an idle Pattern. */ + ICP_HSSACC_VOICE_TX_IDLE_DELIMITER + /**< Delimiter for error checks. */ + } icp_hssacc_channel_voice_tx_idle_action_t; + + +/** + * @ingroup icp_HssAccErrors + * HSS Error Type. + * @description + * Used to identify HSS TDM I/O Unit errors. + */ +typedef enum +{ + ICP_HSSACC_ERROR_RX_OVERFLOW = 0, + /**< Receive queuing Overflow. This error is service specific: + only the affected service (voice or data) will get + notified. */ + ICP_HSSACC_ERROR_RX_FREE_UNDERFLOW, + /**< Receive Free Queuing underflow. This error is service + specific: only the affected service(voice or data) will get + notified. */ + ICP_HSSACC_ERROR_MESSAGE_FIFO_OVERFLOW, + /**< Message FIFO overflow between the TDM I/O Unit and + HSS Acceleration. Both voice and data services will get notified of this + error. */ + ICP_HSSACC_ERROR_DELIMITER + /**< Delimiter for error checks. */ +} icp_hssacc_error_t; + + +/** + * @ingroup icp_HssAccErrors + * HSS Port Error Type. + * @description + * Used to identify HSS TDM I/O Unit errors. + */ +typedef enum +{ + ICP_HSSACC_PORT_ERROR_TX_LOS = 0, + /**< Transmit loss of sync - unexpected frame pulse seen on Transmit. */ + ICP_HSSACC_PORT_ERROR_RX_LOS, + /**< Receive loss of sync - unexpected frame pulse seen on Receive. */ + ICP_HSSACC_PORT_ERROR_TX_UNDERFLOW, + /**< Transmit underflow - Transmit port could not get access to HSS TDM I/O Unit + * internal memory fast enough. */ + ICP_HSSACC_PORT_ERROR_RX_OVERFLOW, + /**< Receive overflow - Receive port could not get access to HSS TDM I/O Unit + * internal memory fast enough. */ + ICP_HSSACC_PORT_ERROR_TX_PARITY, + /**< Parity Error within the HSS TDM I/O Unit Transmit internal memory */ + ICP_HSSACC_PORT_ERROR_RX_PARITY, + /**< Parity Error within the HSS TDM I/O Unit Receive internal memory */ + ICP_HSSACC_PORT_ERROR_DELIMITER + /**< Delimiter for port error checks. */ +} icp_hssacc_port_error_t; + +/* ---------------------------------------------------------------------------- + * Call-back definitions + * ---------------------------------------------------------------------------- + */ + +/** + * @ingroup icp_HssAccDataPathCallbackMode + * HSS Receive Callback. + * @description + * Prototype of the client's function to accept notification of received + * data. This function is registered through the channel callback + * registration function @ref icp_HssAccChannelCallbacksRegister(). + * Client can retrieve the buffer(s) through @ref icp_HssAccReceive() + * + * @context + * Calling context of @ref icp_HssAccDataPathService(). + * @assumptions + * None + * @sideEffects + * None + * + * @param + * userContext [OUT] Opaque value provided by user during callback + * registration via @ref icp_HssAccChannelCallbacksRegister(). + * @return + * void + * @pre + * None + * @post + * None + * @note + * None + * @see + * @ref icp_HssAccChannelCallbacksRegister() \n + * @ref icp_HssAccDataPathService() + */ +typedef void (*icp_hssacc_rx_callback_t) ( + icp_user_context_t userContext); + + +/** + * @ingroup icp_HssAccDataPathCallbackMode + * HSS transmit done callback. + * @description + * Callback used to notify the client's function of completion with + * Transmit buffers. This function is registered through the + * @ref icp_HssAccChannelCallbacksRegister(). + * Client can retrieve the buffer(s) through + * @ref icp_HssAccTxDoneRetrieve() + * + * @context + * Task context. This is invoked from the same context as that + * which the transmit function runs in. That is, near the end of the + * transmit processing function, this callback is invoked to return + * buffers to the client. + * @assumptions + * None + * @sideEffects + * None + * + * @param + * userContext [OUT] Opaque value provided by user during callback + * registration via @ref icp_HssAccChannelCallbacksRegister(). + * + * @return + * Void + * @pre + * None + * @post + * None + * @note + * None + * @see + * @ref icp_HssAccChannelCallbacksRegister() \n + * @ref icp_HssAccDataPathService() + */ +typedef void (*icp_hssacc_tx_done_callback_t) ( + icp_user_context_t userContext); + + +/** + * @ingroup icp_HssAccErrors + * HSS Error callback. + * @description + * Prototype of the client's function to accept notification of general + * internal errors, e.g. internal Receive queue overflow. + * This function is registered through + * @ref icp_HssAccErrorCallbackRegister(). + * + * @context + * None + * @assumptions + * None + * @sideEffects + * None + * + * @param + * userContext [OUT] Opaque value provided by user during callback + * registration via @ref icp_HssAccErrorCallbackRegister(). + * + * @param + * errorType @ref icp_hssacc_error_callback_t [IN] - This is + * error type that has triggered the callback. + * + * @return + * Void + * @pre + * None + * @post + * None + * @note + * None + * @see + * @ref icp_HssAccErrorCallbackRegister() + */ +typedef void (*icp_hssacc_error_callback_t) ( + icp_user_context_t userContext, + icp_hssacc_error_t errorType); + + +/** + * @ingroup icp_HssAccErrors + * HSS Port Error callback. + * @description + * Prototype of the client's function to accept notification of an error + * condition on a port. E.g. a Transmit/Receive loss of sync error. + * This function is registered through + * @ref icp_HssAccPortErrorCallbackRegister(). + * + * @context + * None + * @assumptions + * None + * @sideEffects + * None + * + * @param + * userContext [OUT] Opaque value provided by user during callback + * registration via @ref icp_HssAccPortErrorCallbackRegister(). + * + * @param + * errorType @ref icp_hssacc_port_error_callback_t [IN] - This is + * error type that has triggered the callback. + * + * @return + * Void + * @pre + * None + * @post + * None + * @note + * None + * @see + * @ref icp_HssAccPortErrorCallbackRegister() + */ +typedef void (*icp_hssacc_port_error_callback_t) ( + icp_user_context_t userContext, + icp_hssacc_port_error_t errorType); + +/* ---------------------------------------------------------------------------- + * Structure definitions + * ---------------------------------------------------------------------------- + */ + +/** + * @ingroup icp_HssAccPortConfig + * Receive or Transmit Port configuration parameters. + * @purpose + * Structure containing HSS port configuration parameters. + * Note: All of these are used for Transmit. + * Only some are specific to Receive. + * + * @see + * @ref icp_hssacc_port_config_params_t \n + * @ref icp_HssAccPortConfig() + * + */ +typedef struct +{ + icp_hssacc_frm_pulse_sync_type_t frmSyncType; /**< Frame sync pulse type + (Transmit/Receive). */ + icp_hssacc_frm_pulse_sync_io_type_t frmSyncIO; /**< How the frame sync + pulse is used + (Transmit/Receive). */ + icp_hssacc_clk_edge_t frmSyncClkEdge; /**< Frame sync clock edge + type (Transmit/Receive). */ + icp_hssacc_clk_edge_t dataClkEdge; /**< Data clock edge type + (Transmit/Receive)*/ + icp_hssacc_clk_mode_t clkMode; /**< Clock Mode + (Transmit/Receive). */ + icp_hssacc_frm_pulse_usage_t frmPulseUsage; /**< Whether to use the frame + sync pulse or not + (Transmit/Receive).*/ + icp_hssacc_data_polarity_t dataPolarity; /**< Data polarity type + (Transmit/Receive). */ + icp_hssacc_tx_pins_drain_mode_t drainMode; /**< Transmit pin open drain + mode (Transmit). */ + icp_hssacc_ref_frame_t refFrame; /**< Enable or disable the + reference frame + (Transmit).*/ + + icp_hssacc_unassigned_data_drive_type_t unassignedType;/**< How to drive the data + pins for unassigned type + (Transmit). */ + icp_hssacc_data_pins_enable_t dataPinsEnable; /**< Whether or not to drive + the data pins (Transmit).*/ + icp_boolean_t loopback; /**< Enable loopback. When set + for Transmit, this is + external loopback + (Receive->Transmit). + When set for Receive, this + is internal loopback + (Transmit->Receive). + Should be exclusively set + for Receive or Transmit. */ + icp_boolean_t fBitEnable; /**< Enable F-Bit + (Transmit/Receive), only + valid for T1 configurations. */ + icp_hssacc_tx_fbit_type_t fBitType; /**< How to drive the F-Bit + (Transmit). */ + + unsigned frm_offset; /**< Frame pulse offset in bits + with respect to the first + timeslot (0-1023) + (Transmit/Receive). */ + icp_hssacc_interleaving_t interleaving; /**< Specifies Byte or Frame + interleaving + (Transmit/Receive). */ +} icp_hssacc_port_config_t; + + + +/** + * @ingroup icp_HssAccPortConfig + * Port configuration parameters + * @purpose + * This structure contains the Transmit and Receive port config parameters + * and other port configuration. + * + * @see + * @ref icp_hssacc_port_config_t \n + * @ref icp_HssAccPortConfig() + * + */ +typedef struct +{ + icp_hssacc_port_config_t txPortConfig; /**< HSS Transmit port + configuration. */ + icp_hssacc_port_config_t rxPortConfig; /**< HSS Receive port + configuration. */ + icp_hssacc_clk_speed_t clkSpeed; /**< HSS clock speed. */ +} icp_hssacc_port_config_params_t; + +/** + * @ingroup icp_HssAccChannelConfig + * Timeslot map for a channel onto a HSS port. + * @purpose + * This structure contains the timeslot map information a channel onto + * a HSS port. + * Setting a bit high (1) indicates that timeslot is required. The + * timeslot bit map for E1/T1 lines 1, 2 and 3 are only relevant if Quad MVIP + * is enabled. + * + * @see + * @ref icp_HssAccChannelAllocate() + */ +typedef struct +{ + uint32_t line0_timeslot_bit_map; + /**< Timeslot bit map for line 0. + * A bit mask representing the timeslots [0...31] the given HSS + * line. LSb represents timeslot #0, MSb represents timeslot + * #31. + * Set the appropriate bits to select the timeslots to + * link to the given channel. \n + * E.g. To bind to timeslots + * 1,2,11,22,30, timeslotMask = 0x40400806. \n + * E.g. To bind to + * timeslot 31, timeslotMask = 0x80000000. \n + * E.g. To bind to + * timeslots 1-31, timeslotMask = 0xFFFFFFFE. */ + uint32_t line1_timeslot_bit_map; + /**< Timeslot bit map for line 1. */ + uint32_t line2_timeslot_bit_map; + /**< Timeslot bit map for line 2. */ + uint32_t line3_timeslot_bit_map; + /**< Timeslot bit map for line 3. */ +} icp_hssacc_timeslot_map_t; + + +/* ---------------------------------------------------------------------------- + * Interface Definition + * --------------------------------------------------------------------------- + */ + +/** + * @ingroup icp_HssAccInitShutdown + * Initializes the HssAcc component for the HSS TDM I/O Unit. + * @description + * This function is responsible for initializing internal resources for + * use by this component. It should be called before any other HSS Access + * function is called. This function should only be called once, subsequent + * calls will fail. + * + * @context + * Calling function thread + * @assumptions + * None + * @sideEffects + * None + * @blocking + * Yes + * @reentrant + * No + * @threadSafe + * Yes + * @retval + * ICP_STATUS_SUCCESS The function executed successfully. + * @retval + * ICP_STATUS_FAIL The function did not execute successfully. + * @pre + * None + * @post + * None + * @note + * None + * @see + * @ref icp_HssAccShutdown() + */ +icp_status_t +icp_HssAccInit ( void ); + +/** + * @ingroup icp_HssAccInitShutdown + * Initializes the HDLC service for the HSS TDM I/O Unit. + * @description + * This function is responsible for initializing HDLC resources for use + * by this component. It should be called before any other HDLC + * function is called. This function should only be called once. Only + * one HDLC service is supported at a time. This implies only one + * HDLC application in the system. + * + * @context + * Calling function thread. + * @assumptions + * None + * @sideEffects + * None + * @blocking + * Yes + * @reentrant + * No + * @threadSafe + * Yes + * @param + * maxRxFrameSize (IN) Maximum receive frame size (inclusive of CRC) + * that can be configured for any HDLC channel. The individual per + * channel hdlcMaxRxFrameSize values passed in calls to + * @ref icp_HssAccChannelHdlcServiceConfigure() must be less than this. + * All HDLC buffers supplied with @ref icp_HssAccRxFreeReplenish() must + * be at least this size. + * @param + * intGenerationEnable (IN) set to ICP_TRUE will enable interrupts + * from the TDM I/O unit for notification of received HDLC packets + * and successful HDLC packet transmission. Interrupts are coalesced + * by the TDM I/O Unit between receive and transmit as well as Voice + * traffic if interrupts are enabled for the Voice service. If HDLC + * is functioning in polled mode then this parameter should be set to + * ICP_FALSE to avoid spurious interrupts. + * + * @retval + * ICP_STATUS_SUCCESS The function executed successfully. + * @retval + * ICP_STATUS_FAIL The function did not execute successfully. + * @pre + * HSS Initialization has completed successfully. + * @post + * None + * @note + * None + * @see + * @ref icp_HssAccVoiceInit() \n + * @ref icp_HssAccChannelHdlcServiceConfigure() \n + * @ref icp_HssAccRxFreeReplenish() + */ +icp_status_t +icp_HssAccHdlcInit(unsigned maxRxFrameSize, + icp_boolean_t intGenerationEnable); + +/** + * @ingroup icp_HssAccInitShutdown + * Initializes the voice service for the HSS TDM I/O Unit. + * @description + * This function is responsible for initializing voice resources for use + * by this component. It should be called before any other voice + * function is called. This function should only be called once. Only + * one Voice service is supported at a time. This implies only one + * Voice application in the system. + * + * @context + * Calling function thread. + * @assumptions + * None + * @sideEffects + * None + * @blocking + * Yes + * @reentrant + * No + * @threadSafe + * Yes + * @param + * maxRxFrameSize (IN) Maximum receive frame size (inclusive of + * CRC) that can be configured for any voice channel. The + * individual per channel voicePacketSize values passed in + * calls to @ref icp_HssAccChannelVoiceServiceConfigure() must + * be at most this size. All voice buffers supplied with @ref + * icp_HssAccRxFreeReplenish() must be at least this size. + * @param + * intGenerationEnable (IN) set to ICP_TRUE will enable interrupts + * from the TDM I/O unit for notification of received Voice samples + * and successful Voice sample transmission. Interrupts are coalesced + * by the TDM I/O Unit between receive and transmit as well as HDLC + * traffic if interrupts are enabled for the HDLC service. If the Voice + * is functioning in polled mode then this parameter should be set to + * ICP_FALSE to avoid spurious interrupts. + * + * @retval + * ICP_STATUS_SUCCESS The function executed successfully. + * @retval + * ICP_STATUS_FAIL The function did not execute successfully. + * @pre + * HSS Initialization has completed successfully. + * @post + * None + * @note + * None + * @see + * @ref icp_HssAccHdlcInit() \n + * @ref icp_HssAccChannelVoiceServiceConfigure() \n + * @ref icp_HssAccRxFreeReplenish() + */ +icp_status_t +icp_HssAccVoiceInit(unsigned maxRxFrameSize, + icp_boolean_t intGenerationEnable); + +/** + * @ingroup icp_HssAccInitShutdown + * Un-initializes the HssAcc component. + * @description + * This function is responsible for freeing all resources that + * were allocated to this component. It performs all + * un-initialization type functionality such as disable and + * delete all channels, ensure all buffers have been freed and + * reset pointers. Buffers that are in the transmit queues are + * sent before being freed. Buffers in the receive queue are + * freed and not sent to the client. + * @context + * Calling function thread. + * @assumptions + * None + * @sideEffects + * None + * @blocking + * Yes + * @reentrant + * No + * @threadSafe + * Yes + * @retval + * ICP_STATUS_SUCCESS The function executed successfully. + * @retval + * ICP_STATUS_FAIL The function did not execute successfully. + * @pre + * HSS Initialization has completed successfully. + * @post + * None + * @note + * None + * @see + * @ref icp_HssAccInit() + */ +icp_status_t +icp_HssAccShutdown (void); + +/* HSS Port Configuration Functions. */ + +/** + * @ingroup icp_HssAccPortConfig + * Get number of ports supported. + * @description + * This function returns the number of ports that the HSS TDM + * I/O Access Library supports. + * + * @context + * Calling function thread. + * @assumptions + * None + * @sideEffects + * None + * @blocking + * Yes + * @reentrant + * No + * @threadSafe + * Yes + * + * @retval + * unsigned Number of ports supported by the HSS TDM I/O Access Library. + * + * @pre + * HSS Initialization has completed successfully. + * @post + * None + * @note + * None + * @see + * @ref icp_HssAccPortConfig() \n + * @ref icp_HssAccPortUp() \n + * @ref icp_HssAccPortDown() + */ +unsigned +icp_HssAccNumSupportedPortsGet ( void ); + +/** + * @ingroup icp_HssAccPortConfig + * HSS Transmit and Receive Port parameters. + * @description + * This function is used to setup common configuration + * parameters of both Receive and Transmit directions for a HSS port. The + * function configures the clock speed, the data rate + * setting compared to the clock rate, the data bit polarity + * setting, whether or not the framing bit is enabled, the data + * bit endianness of the port, configuration of the reference + * frame, and the interleaving mode type (either byte or + * frame). Each port can only be configured once using this function; + * subsequent calls to configure a specific port with different + * settings will fail. Multiple calls to configure a port with the same + * settings will succeed, this is to accommodate multiple services using + * the same port. This behavior is implemented following the + * assumption that it is not a normal usage model to be changing the + * port configuration "on the fly". + * + * @context + * Calling function thread. + * @assumptions + * None + * @sideEffects + * None + * @blocking + * Yes + * @reentrant + * No + * @threadSafe + * Yes + * + * @param + * portId [IN] - The HSS port ID (0 to icp_HssAccNumSupportedPortsGet()-1). + * @param + * *configParams @ref icp_hssacc_port_config_params_t [in] - A pointer + * to the HSS configuration structure. + * + * @retval + * ICP_STATUS_SUCCESS The function executed successfully. + * @retval + * ICP_STATUS_FAIL The function did not execute successfully. + * @retval + * ICP_STATUS_MUTEX An error occurred while grabbing or releasing the + * internal lock. + * @retval + * ICP_STATUS_INVALID_PARAM One of the parameters provided was invalid. + * + * @pre + * HSS Initialization function has completed successfully. + * @post + * @ref icp_HssAccPortUp() needs to be called before this + * setting takes effect. + * @note + * None + * @see + * @ref icp_HssAccPortUp() \n + * @ref icp_HssAccPortDown() + */ +icp_status_t +icp_HssAccPortConfig ( + unsigned portId, + icp_hssacc_port_config_params_t *configParams ); + +/** + * @ingroup icp_HssAccPortConfig + * HSS Port Up. + * @description + * This function is used to apply all of the port configuration + * parameters and bring up the port. Should the port be already up, + * this function will do nothing and return ICP_STATUS_SUCCESS. + * + * @context + * Calling function thread. + * @assumptions + * None + * @sideEffects + * None + * @blocking + * Yes + * @reentrant + * No + * @threadSafe + * Yes + * + * @param + * portId [IN] - The HSS port ID (0 to icp_HssAccNumSupportedPortsGet()-1). + * + * @retval + * ICP_STATUS_SUCCESS The function executed successfully. + * @retval + * ICP_STATUS_FAIL The function did not execute successfully. + * @retval + * ICP_STATUS_MUTEX An error occurred while grabbing or releasing the + * internal lock. + * @retval + * ICP_STATUS_INVALID_PARAM One of the parameters provided was invalid. + * + * @pre + * HSS Initialization function has completed successfully. + * @ref icp_HssAccPortConfig must be called before this + * function. + * @post + * In order to enable channels on this port, + * @ref icp_HssAccChannelAllocate() and + * @ref icp_HssAccChannelConfigure(), as well as either + * @ref icp_HssAccChannelVoiceServiceConfigure() or + * @ref icp_HssAccChannelVoiceServiceConfigure() + * functions need to be called after successful completion of this + * function. + * @note + * None + * @see + * @ref icp_HssAccPortDown() + */ +icp_status_t +icp_HssAccPortUp ( + unsigned portId); + +/** + * @ingroup icp_HssAccPortConfig + * HSS Port Down. + * @description + * This function is used to disable a HSS port. Should this port + * not be up when this function is called, it will do nothing and + * return ICP_STATUS_SUCCESS. This function will check that there are no + * channels allocated on this port, if any are found the function will + * return an error. This function does not unconfigure the port, all + * configuration settings are retained for the client to make a + * subsequent call to @ref icp_HssAccPortUp(). + * + * @context + * Calling function thread + * @assumptions + * None + * @sideEffects + * None + * @blocking + * Yes + * @reentrant + * No + * @threadSafe + * Yes + * + * @param + * portId [IN] - The HSS port ID (0 to + * icp_HssAccNumSupportedPortsGet()-1). + * + * @retval + * ICP_STATUS_SUCCESS The function executed successfully. + * @retval + * ICP_STATUS_FAIL The function did not execute successfully. + * @retval + * ICP_STATUS_RESOURCE There are still channels allocated on this port. + * + * @pre + * A HSS port has been successfully configured and enabled. + * @post + * None + * @note + * None + * @see + * @ref icp_HssAccPortUp() + */ +icp_status_t +icp_HssAccPortDown ( + unsigned portId); + + +/* HSS Channel Configuration. */ +/** + * @ingroup icp_HssAccChannelConfig + * Get number of channels supported. + * @description + * This function returns the number of channels that the HSS TDM + * I/O Access Library supports. + * + * @context + * Calling function thread. + * @assumptions + * None + * @sideEffects + * None + * @blocking + * Yes + * @reentrant + * No + * @threadSafe + * Yes + * + * @retval + * unsigned Number of channels supported by the HSS TDM I/O Access Library. + * + * @pre + * HSS Initialization has completed successfully. + * @post + * None + * @note + * None + * @see + * @ref icp_HssAccChannelConfigure() \n + * @ref icp_HssAccChannelHdlcServiceConfigure() \n + * @ref icp_HssAccChannelVoiceServiceConfigure() + */ +unsigned +icp_HssAccNumSupportedChannelsGet ( void ); + +/** + * @ingroup icp_HssAccChannelConfig + * HSS Channel Allocate. + * @description + * This function is used to allocate a channel ID for the requested + * set of timeslots, for the requested channel type and on the requested + * port. The returned channel ID is the only handle needed to + * perform all possible operations on the channel such as configure, + * start, stop, and delete.\n + * + * Multiple HDLC and Voice channels can be allocated on the + * same port. Voice and HDLC channels can span multiple + * noncontiguous timeslots in a single E1/T1 line. \n + * + * Timeslots for a channel cannot span across + * multiple E1/T1 lines; ie All Timeslots allocated to + * a channel must be on the same E1/T1 line.\n + * + * When allocating a channel on a T1 line, please note that + * timeslot 0 is reserved for the FBit, valid timeslots will + * be 1 to 24. + * + * + * @context + * Calling function thread. + * @assumptions + * None + * @sideEffects + * None + * @blocking + * Yes + * @reentrant + * No + * @threadSafe + * Yes + * + * @param + * pChannelId [OUT] - The allocated HSS channel ID. + * @param + * portId [IN] - The HSS port ID (0 to icp_HssAccNumSupportedPortsGet()-1). + * @param + * tsMap @ref icp_hssacc_timeslot_map_t [IN] - A structure which contains + * the requested timeslot map for the channel. + + * @param + * channelType @ref icp_hssacc_channel_type_t [IN] - Setting which + * configures the type of channel requested, i.e. HDLC or Voice. + * + * @retval + * ICP_STATUS_SUCCESS The function executed successfully. + * @retval + * ICP_STATUS_FAIL The function did not execute successfully. + * @retval + * ICP_STATUS_INVALID_PARAM One of the parameters provided was incorrect. + * @retval + * ICP_STATUS_MUTEX An error occurred while grabbing or releasing the + * internal lock. + * @retval + * ICP_STATUS_RESOURCE One of the resources to be used by the newly allocated + * channel is not available for use. + * + * @pre + * HSS Initialization and port configuration has completed successfully. + * @post + * icp_HssAccChannel*** functions need to be called after this + * function to configure the channel. The channel is then + * enabled via the @ref icp_HssAccChannelUp() function. + * @note + * None + * @see + * @ref icp_HssAccChannelConfigure() \n + * @ref icp_HssAccChannelHdlcServiceConfigure() \n + * @ref icp_HssAccChannelVoiceServiceConfigure() \n + * @ref icp_HssAccChannelUp() \n + * @ref icp_HssAccChannelDown() \n + * @ref icp_HssAccChannelDelete() */ +icp_status_t +icp_HssAccChannelAllocate ( + unsigned *pChannelId, + unsigned portId, + icp_hssacc_timeslot_map_t tsMap, + icp_hssacc_channel_type_t channelType); + + +/** + * @ingroup icp_HssAccChannelConfig + * HSS Channel Common configuration. + * @description + * This function is used to apply channel configuration + * parameters that are common to both a HDLC channel and a voice channel, + * or specific to only one of the service type. Parameters not relevant + * to a specific type of channel are ignored on configuration. + * Incompatibilities between channel parameter settings are checked + * before this function applies these to the underlying hardware. + * + * @context + * Calling function thread. + * @assumptions + * None + * @sideEffects + * None + * @blocking + * Yes + * @reentrant + * No + * @threadSafe + * Yes + * + * @param + * channelId [IN] - The allocated HSS channel ID. + * @param + * channelDataPolarity @ref icp_hssacc_data_polarity_t [IN] - + * Used to select whether or not one's complement inversion is + * performed on the channel data before any other processing + * occurs. Applies to both Voice and HDLC Channels. + * @param + * channelBitEndianness @ref icp_hssacc_bit_endian_t [IN] - Used to + * configure the bit endianness of a channel. The permitted settings are + * the most or least significant bit first on a per byte basis. + * Applies to both Voice and HDLC Channels. + * @param + * channelByteSwapping [IN] - Used to enable the byte swapping of a + * channel within each half-word (2 bytes) transmitted and received: + * if this setting is enabled, the 2 bytes of each half-word will + * be swapped. This setting is for Voice channels only and will be + * ignored for HDLC channels. + * @param + * rBitEnable [IN] - Enable or disable optional robbed bit on this + * channel. Robbed Bit is only supported for HDLC Channels. + * @param + * rBitValue @ref icp_hssacc_robbed_bit_value_t [IN] - Configures the + * value of the unused bit for 56 Kbps channels. This sets the + * robbed bit in each timeslot (that the channel has allocated) to + * either zero or one. Ignored if rBitEnable is FALSE. + * @param + * rBitLocation @ref icp_hssacc_robbed_bit_location_t [IN] - + * Used to configure which bit (bit 7 or bit 0) of each + * timeslot is used for robbed-bit signaling when a channel is + * configured in 56 Kbps mode. Ignored if rBitEnable is FALSE. + * + * @retval + * ICP_STATUS_SUCCESS The function executed successfully. + * @retval + * ICP_STATUS_FAIL The function did not execute successfully. + * @retval + * ICP_STATUS_INVALID_PARAM One of the parameters provided was incorrect. + * @retval + * ICP_STATUS_MUTEX An error occurred while grabbing or releasing the + * internal lock. + * @retval + * ICP_STATUS_RESOURCE One of the resources used in this operation was + * not available. + * + * @pre + * The @ref icp_HssAccChannelAllocate() has completed successfully for + * the specified channel ID. + * @post + * @ref icp_HssAccChannelHdlcServiceConfigure() or + * @ref icp_HssAccChannelVoiceServiceConfigure() must be called before + * the channel can be enabled.\n + * In order to enable channels on this port, the + * @ref icp_HssAccChannelUp() function needs to be called after + * successful completion of this function and the subsequent service + * configuration function. + * @note + * None + * @see + * @ref icp_HssAccChannelAllocate() + */ +icp_status_t +icp_HssAccChannelConfigure ( + unsigned channelId, + icp_hssacc_data_polarity_t channelDataPolarity, + icp_hssacc_bit_endian_t channelBitEndianness, + icp_boolean_t channelByteSwapping, + icp_hssacc_bit_robbing_t rBitEnable, + icp_hssacc_robbed_bit_value_t rBitValue, + icp_hssacc_robbed_bit_location_t rBitLocation); + + +/** + * @ingroup icp_HssAccChannelConfig + * HSS Channel HDLC-specific configuration. + * @description + * This function is used to configure all necessary parameters for an + * HDLC channel. + * + * @context + * Calling function thread. + * @assumptions + * None + * @sideEffects + * None + * @blocking + * Yes + * @reentrant + * No + * @threadSafe + * Yes + * + * @param + * channelId [IN] - The allocated HSS channel ID. + * @param + * hdlcCrcBitWidth @ref icp_hssacc_hdlc_crc_bit_width_t [IN] - Used to + * select the length of the CRC appended to each frame on transmit. Can + * be one of 16-bits or 32-bits. + * @param + * hdlcSofFlagType @ref icp_hssacc_hdlc_sof_flag_type_t [IN] - Used to + * specify the number of flags placed at the start of each frame. + * Can be flag sharing with the end of frame flag of the preceding frame, + * one flag per frame, or two flags per frame. + * @param + * hdlcRxIdlePattern @ref icp_hssacc_hdlc_idle_pattern_t [IN] - Used to + * specify the HDLC Receive idle pattern. The idle pattern is either + * set to a repeated flag (0x7E) or all ones (0xFF). + * @param + * hdlcTxIdlePattern @ref icp_hssacc_hdlc_idle_pattern_t [IN] - Used to + * specify the HDLC Transmit idle pattern. The idle pattern is either + * set to a repeated flag (0x7E) or all ones (0xFF). + * @param + * hdlcMaxRxFrameSize [IN] - The maximum frame size on Receive for this + * channel. Any frames larger than hdlcMaxRxFrameSize are dropped + * by the TDM I/O Unit and an error counter incremented. This value is + * inclusive of the CRC. A value of 0 will cause this function to return + * an error. + * + * @retval + * ICP_STATUS_SUCCESS The function executed successfully. + * @retval + * ICP_STATUS_FAIL The function did not execute successfully. + * @retval + * ICP_STATUS_INVALID_PARAM One of the parameters provided was incorrect. + * @retval + * ICP_STATUS_MUTEX An error occurred while grabbing or releasing the + * internal lock. + * @retval + * ICP_STATUS_RESOURCE One of the resources used in this operation was + * not available. + * + * @pre + * @ref icp_HssAccChannelAllocate() has completed successfully for the + * specified channel ID.\n + * @ref icp_HssAccChannelConfigure() has completed successfully + * for the specified channel ID.\n + * @post + * In order to enable channels on this port, the + * @ref icp_HssAccChannelUp() function needs to be called after + * successful completion of this function. + * @note + * None + * @see + * @ref icp_HssAccChannelConfigure() + */ +icp_status_t +icp_HssAccChannelHdlcServiceConfigure ( + unsigned channelId, + icp_hssacc_hdlc_crc_bit_width_t hdlcCrcBitWidth, + icp_hssacc_hdlc_sof_flag_type_t hdlcSofFlagType, + icp_hssacc_hdlc_idle_pattern_t hdlcRxIdlePattern, + icp_hssacc_hdlc_idle_pattern_t hdlcTxIdlePattern, + unsigned hdlcMaxRxFrameSize); + +/** + * @ingroup icp_HssAccChannelConfig + * HSS Channel voice-specific configuration. + * @description + * This function is used to configure all necessary parameters for a + * voice channel, including the idle pattern to Transmit when there's + * no data on the channel and the size of the packet (in bytes). + * + * Here are some examples of common voice channel bit widths and + * sampling frequencies: + * - HSS Narrowband Voice Channel (G.711). A Narrowband G.711 + * channel is defined as 1 x DS0 @ 8KHz transporting 8-bit + * G.711 PCM sampled @ 8KHz. + * - HSS Narrowband Voice Channel 16-bit Linear. A Narrowband 16-bit + * channel is defined as 2 x DS0 @ 8KHz transporting 16-bit Linear + * PCM sampled @ 8KHz. + * - HSS Wideband Voice Channel. A Wideband channel is defined as 4 + * x DS0 @ 8KHz transporting 16-bit Linear PCM sampled @ 16KHz. + * + * @context + * Calling function thread. + * @assumptions + * None + * @sideEffects + * None + * @blocking + * Yes + * @reentrant + * No + * @threadSafe + * Yes + * + * @param + * channelId [IN] - The allocated HSS channel ID. + * @param txIdleAction [IN] - The action to perform when there is no data to + * transmit, see @ref icp_hssacc_channel_voice_tx_idle_action_t. + * @param + * voiceIdlePattern [IN] - Set this argument to configure the idle + * pattern as a value from 0 to 0xFF. + * @param + * voicePacketSize [IN] - Set this argument to configure the size of the + * voice packets for this channel. When voicePacketSize bytes have been + * received for this channel on the timeslots reserved by + * @ref icp_HssAccChannelAllocate() the TDM I/O Unit passes the packet + * to the HssAcc I/O Access library. A packet Size of 0 will generate + * an ICP_STATUS_INVALID_PARAM error. + * + * @retval + * ICP_STATUS_SUCCESS The function executed successfully. + * @retval + * ICP_STATUS_FAIL The function did not execute successfully. + * @retval + * ICP_STATUS_INVALID_PARAM One of the parameters provided was incorrect. + * @retval + * ICP_STATUS_MUTEX An error occurred while grabbing or releasing the + * internal lock. + * @retval + * ICP_STATUS_RESOURCE One of the resources used in this operation was + * not available. + * + * @pre + * @ref icp_HssAccChannelAllocate() has completed successfully for the + * specified channel ID.\n + * @ref icp_HssAccChannelConfigure() has completed successfully + * for the specified channel ID. + * @post + * In order to enable channels on this port, the + * @ref icp_HssAccChannelUp() function needs to be called after + * successful completion of this function. + * @note + * None + * @see + * @ref icp_HssAccChannelConfigure() + */ +icp_status_t +icp_HssAccChannelVoiceServiceConfigure ( + unsigned channelId, + icp_hssacc_channel_voice_tx_idle_action_t txIdleAction, + uint8_t voiceIdlePattern, + unsigned voicePacketSize); + + + +/** + * @ingroup icp_HssAccChannelConfig + * HSS Channel callback register. + * @description + * This function is used to set the callback configuration of a + * HSS channel. Once the configuration has been completed, the + * client needs to call the enable function. + * + * @context + * Calling function thread. + * @assumptions + * None + * @sideEffects + * None + * @blocking + * Yes + * @reentrant + * No + * @threadSafe + * Yes + * + * @param + * channelId [IN] - The channel ID allocated by HSS. + * @param + * userContext [IN] - Opaque user context provided by the client. + * The access library returns this value unmodified when it invokes the + * callback function. This value can be used by the client to store + * any type of data that it may require when the callback function + * it is registering is called. For instance, a client might register + * the same callback function for several events, it can use the user + * context to determine which event triggered the callback. + * @param + * rxCallback @ref icp_hssacc_rx_callback_t [IN] - Receive callback + * invoked by the access library when a packet is received. + * @param + * txDoneCallback @ref icp_hssacc_tx_done_callback_t [IN] Transmit done + * callback invoked by the access library when a packet has been + * transmitted. + * + * @retval + * ICP_STATUS_SUCCESS The function executed successfully. + * @retval + * ICP_STATUS_FAIL The function did not execute successfully. + * @retval + * ICP_STATUS_INVALID_PARAM One of the parameters provided was incorrect. + * @retval + * ICP_STATUS_MUTEX An error occurred while grabbing or releasing the + * internal lock. + * @retval + * ICP_STATUS_RESOURCE One of the resources used in this operation was + * not available. + * + * @pre + * @ref icp_HssAccChannelAllocate() has completed successfully for the + * specified channel ID.\n + * @post + * None + * @note + * None + * @see + * @ref icp_HssAccChannelAllocate() + */ +icp_status_t +icp_HssAccChannelCallbacksRegister ( + unsigned channelId, + icp_user_context_t userContext, + icp_hssacc_rx_callback_t rxCallback, + icp_hssacc_tx_done_callback_t txDoneCallback); + + +/** + * @ingroup icp_HssAccErrors + * HSS error callback register. + * @description + * This function is used to register the error callback. These + * errors indicate serious internal errors in TDM I/O + * Acceleration unit relating to channel processing. See + * @ref icp_hssacc_error_t for details on the errors that will + * trigger the callback being registered here. Errors notified can + * apply to all channels associated to a specific service, or all + * channels in the system. Parameters will be set accordingly in the + * callback function upon the occurrence of the error.\n + * The error callback shall only be generated once per error type. + * Subsequent calls to this API, for a particular channelType, + * overwrites the previous registered callback. + * The client can call icp_HssAccAllStatsShow() to dump error + * statistics (and other statistics) at any time. + * + * @context + * Calling function thread + * @assumptions + * None + * @sideEffects + * None + * @blocking + * Yes + * @reentrant + * No + * @threadSafe + * Yes + * + * @param + * channelType @ref icp_hssacc_channel_type_t [IN] - specifies + * the type of service this callback is for. + * Errors specific to a service are only notified to that + * service. + * @param + * userContext [IN] - Opaque user context provided by the client. + * The access library returns this value when it invokes the + * callback function. This value can be used by the client to store + * any type of data that it may require when the callback function + * it is registering is called. + * @param + * errorCallback @ref icp_hssacc_error_callback_t [IN] - The + * error callback. + * + * @retval + * ICP_STATUS_SUCCESS The function executed successfully. + * @retval + * ICP_STATUS_FAIL The function did not execute successfully. + * + * @pre + * HSS Initialization has completed successfully. + * @post + * None + * @note + * None + * @see + * @ref icp_HssAccAllStatsShow() + */ +icp_status_t +icp_HssAccErrorCallbackRegister ( + icp_hssacc_channel_type_t channelType, + icp_user_context_t userContext, + icp_hssacc_error_callback_t errorCallback); + +/** + * @ingroup icp_HssAccErrors + * HSS port error callback register. + * @description + * This function is used to register the port error callback. + * This callback is used to notify the client of serious errors + * that have occurred on the specified TDM port and that will impact + * any channel with timeslots on that port.\n + * Subsequent calls to this API for a particular port and + * channelType overwrites the previous registered callback. + * The client can call icp_HssAccAllStatsShow() to dump error + * statistics (and other statistics) at any time.\n + * It is recommended that the client register the callback before any + * port is enabled. No error can occur on a port until it is enabled, + * however port misconfiguration can trigger immediate error reporting + * upon port enabling. + * + * @context + * Calling function thread. + * @assumptions + * None + * @sideEffects + * None + * @blocking + * Yes + * @reentrant + * No + * @threadSafe + * Yes + * + * @param + * portId [IN] - specifies the port for which the client is + * registering the error callback. + * @param + * channelType @ref icp_hssacc_channel_type_t [IN] - specifies + * the type of service this callback is for. + * @param + * userContext [IN] - Opaque user context provided by the client. + * The access library returns this value when it invokes the + * callback function. This value can be used by the client to store + * any type of data that it may require when the callback function + * it is registering is called. + * @param + * portErrorCallback @ref icp_hssacc_port_error_callback_t [IN] - The + * HSS port error callback. + * + * @retval + * ICP_STATUS_SUCCESS The function executed successfully. + * @retval + * ICP_STATUS_FAIL The function did not execute successfully. + * + * @pre + * HSS Initialization has completed successfully. + * @post + * None + * @note + * None + * @see + * @ref icp_HssAccAllStatsShow() + */ +icp_status_t +icp_HssAccPortErrorCallbackRegister ( + unsigned portId, + icp_hssacc_channel_type_t channelType, + icp_user_context_t userContext, + icp_hssacc_port_error_callback_t portErrorCallback); + + +/** + * @ingroup icp_HssAccVoiceBypass + * Get number of gain control tables (GCTs) supported. + * @description + * This function returns the number of gain control tables that the + * HSS TDM I/O Access Library supports. + * + * @context + * Calling function thread. + * @assumptions + * None + * @sideEffects + * None + * @blocking + * Yes + * @reentrant + * No + * @threadSafe + * Yes + * + * @retval + * unsigned Number of gain control tables supported by the HSS + * TDM I/O Access Library. + * + * @pre + * HSS Initialization has completed successfully. + * @post + * None + * @note + * None + * @see + * @ref icp_HssAccVoiceBypassGctDownload() \n + * @ref icp_HssAccVoiceBypassEnable() + */ +unsigned +icp_HssAccNumSupportedGCTsGet ( void ); + +/** + * @ingroup icp_HssAccVoiceBypass + * Get number of voice bypasses supported. + * @description + * This function returns the number of voice bypasses that the + * HSS TDM I/O Access Library supports. + * + * @context + * Calling function thread. + * @assumptions + * None + * @sideEffects + * None + * @blocking + * Yes + * @reentrant + * No + * @threadSafe + * Yes + * + * @retval + * unsigned Number of voice bypasses supported by the HSS TDM I/O Access + * Library. + * + * @pre + * HSS Initialization has completed successfully. + * @post + * None + * @note + * None + * @see + * @ref icp_HssAccVoiceBypassGctDownload() \n + * @ref icp_HssAccVoiceBypassEnable() \n + * @ref icp_HssAccVoiceBypassDisable() + */ +unsigned +icp_HssAccNumSupportedVoiceBypassesGet ( void ); + +/** + * @ingroup icp_HssAccVoiceBypass + * Gain control table download. + * @description + * This function is responsible for downloading a gain control table + * (256 bytes) to TDM I/O acceleration unit. There are up to + * icp_HssAccNumSupportedGCTsGet()-1 gain control tables. + * A gain control table is associated to a timeslot switch channel in + * a later call to @ref icp_HssAccVoiceBypassEnable(). + * A Gain Control Table is an array of @ref ICP_HSSACC_BYPASS_GCT_SIZE + * bytes. + * The Gain Control table is used to convert a single byte voice sample + * to its new value. The old byte value is used as an index into the + * GCT, the new value is the data at that index. Below is an example of + * a linear gain control table that will multiply by 2 until saturation + * at the max value. It is by no means a usable valid GCT but is + * just used for demonstration purposes:\n + * 0 -> 0\n + * 1 -> 2\n + * 2 -> 4\n + * ...\n + * 126 -> 252\n + * 127 -> 254\n + * 128 -> 255\n + * 129 -> 255\n + * ...\n + * 254 -> 255\n + * 255 -> 255\n + * \n + * Gain control tables default to a 1:1 mapping between source and + * destination voice channel timeslots. + * If the client wishes to change the default for this gain control + * table, the client should call this API before enabling a voice + * bypass channel with this table. See @ref icp_HssAccVoiceBypassEnable. + * This Function call will return an error if the Gain Control Table + * being configured is already in use by one or more bypasses. + * + * + * @context + * Calling function thread. + * @assumptions + * None + * @sideEffects + * None + * @blocking + * Yes + * @reentrant + * No + * @threadSafe + * Yes + * @param + * voiceBypassGct [IN] - The bypass gain control table index (0 to + * icp_HssAccNumSupportedGCTsGet()-1). + * @param + * *gainCtrlTable [IN] - A pointer to an array of size + * @ref ICP_HSSACC_BYPASS_GCT_SIZE, defining each entry for a gain + * control table for the specified bypass voice channel. + * The memory location should be 4 byte aligned, e.g. the 5 least + * significant bits of the address are 0. The HSS I/O + * Access library will reject any pointer that does not fit this + * criteria. + * + * @retval + * ICP_STATUS_SUCCESS The function executed successfully. + * @retval + * ICP_STATUS_FAIL The function did not execute successfully. + * @retval + * ICP_STATUS_INVALID_PARAM One of the parameters of the function + * call was invalid. + * @retval + * ICP_STATUS_MUTEX An error occurred while grabbing or releasing the + * internal lock. + * @retval + * ICP_STATUS_RESOURCE The designated Gain Control Table is already + * used by one or more enabled bypasses. + * @pre + * None + * @post + * None + * @note + * None + * @see + * @ref icp_HssAccVoiceBypassEnable() + * + */ +icp_status_t +icp_HssAccVoiceBypassGctDownload ( + unsigned voiceBypassGct, + uint8_t *gainCtrlTable); + +/** + * @ingroup icp_HssAccVoiceBypass + * Voice bypass enable. + * @description + * This function is responsible for enabling low latency voice channel + * bypass (timeslot switching) between two voice channels for the + * specified HSS port. + * The bypass takes place in the TDM I/O acceleration unit. + * The voice channels must have already been configured as a single + * timeslot voice channel (narrowband channel) for the specific HSS port. + * Up to 4 bypasses can be enabled at any one time. + * In timeslot switching mode, data received on source channel is + * transmitted onto destination. A copy of the received data on + * srcTimeslot is also sent to client via HssAccess component. + * Both Source and Destination timeslots must be on the same HSS port. + * Using 2 Voice bypasses, the client can implement an in-chip low + * latency cross-connect between 2 narrowband Voice channels. The + * receive data on both channels would be passed on to the client + * for potential inspection. + * + * @context + * Calling function thread. + * @assumptions + * None + * @sideEffects + * None + * @blocking + * Yes + * @reentrant + * No + * @threadSafe + * Yes + * @param + * portId [IN] - The HSS port ID (0 to icp_HssAccNumSupportedPortsGet()-1). + * @param + * voiceBypassId [IN] - The voice bypass id + * to enable voice bypass between 2 voice channels. + * The voiceBypassId shall be used for a subsequent call to disable the + * bypass. + * @param + * voiceBypassGct [IN] - The bypass gain control table index + * (0 to icp_HssAccNumSupportedGCTsGet()-1). + * @param + * srcChannelId [IN] - The source channel whose receive timeslot shall + * be used in the bypass. + * @param + * destChannelId [IN] - The destination channel whose transmit timeslot + * shall be used in the bypass. + * @retval + * ICP_STATUS_SUCCESS The function executed successfully. + * @retval + * ICP_STATUS_FAIL The function did not execute successfully. + * @retval + * ICP_STATUS_INVALID_PARAM One of the parameters provided was invalid. + * @retval + * ICP_STATUS_MUTEX An error occurred while grabbing or releasing the + * internal lock. + * @retval + * ICP_STATUS_RESOURCE At least resource requested for the success of this + * operation was not available. + * @pre + * The channels have been configured successfully and enabled. + * @post + * None + * @note + * None + * @see + * @ref icp_HssAccVoiceBypassGctDownload \n + * @ref icp_HssAccVoiceBypassDisable + * + */ +icp_status_t +icp_HssAccVoiceBypassEnable ( + unsigned portId, + unsigned voiceBypassId, + unsigned voiceBypassGct, + unsigned srcChannelId, + unsigned destChannelId); + +/** + * @ingroup icp_HssAccVoiceBypass + * Voice bypass disable. + * @description + * This function is responsible for disabling voice bypass + * (timeslot switching) between 2 voice channels. The voice + * bypass to be disabled must have already been enabled. + * + * @context + * Calling function thread. + * @assumptions + * None + * @sideEffects + * None + * @blocking + * Yes + * @reentrant + * No + * @threadSafe + * Yes + * @param + * voiceBypassId [IN] - The voice bypass to disable. This is the same id used in the call + * to @ref icp_HssAccVoiceBypassEnable during voice bypass enabling + * operation. + * @retval + * ICP_STATUS_SUCCESS The function executed successfully. + * @retval + * ICP_STATUS_FAIL The function did not execute successfully. + * @pre + * The voice bypass has been enabled. + * @post + * None + * @note + * None + * @see + * @ref icp_HssAccVoiceBypassEnable + * + */ +icp_status_t +icp_HssAccVoiceBypassDisable ( + unsigned voiceBypassId); + +/** + * @ingroup icp_HssAccDataPath + * HSS Channel Up. + * @description + * This function is used to enable packet processing for the + * specified channel. + * + * @context + * Calling function thread + * @assumptions + * None + * @sideEffects + * None + * @blocking + * Yes + * @reentrant + * No + * @threadSafe + * Yes + * + * @param + * channelId [IN] - The channel ID allocated by HSS. + * + * @retval + * ICP_STATUS_SUCCESS The function executed successfully. + * @retval + * ICP_STATUS_FAIL The function did not execute successfully. + * + * @pre + * @ref icp_HssAccChannelConfigure() must have completed successfully.\n + * @ref icp_HssAccChannelHdlcServiceConfigure() or \n + * @ref icp_HssAccChannelVoiceServiceConfigure() must have completed + * successfully. + * @post + * None + * @note + * None + * @see + * @ref icp_HssAccChannelConfigure() \n + * @ref icp_HssAccChannelHdlcServiceConfigure() \n + * @ref icp_HssAccChannelVoiceServiceConfigure() \n + * @ref icp_HssAccChannelDown() + */ +icp_status_t +icp_HssAccChannelUp ( + unsigned channelId); + +/** + * @ingroup icp_HssAccDataPath + * HSS Channel Down. + * @description + * This function is used to disable packet processing for the + * specified channel. No new data is added to the transmit HSS + * queues after this function completes. + * + * Pending completed transmissions and pending completed + * receptions continue to be recycled back to the client + * through normal polling and callback mechanisms. The client + * must call @ref icp_HssAccAllBuffersRetrieve() to ensure all + * outstanding buffers are recycled. + * + * @context + * Calling function thread. + * @assumptions + * None + * @sideEffects + * None + * @blocking + * Yes + * @reentrant + * No + * @threadSafe + * Yes + * + * @param + * channelId [IN] - The channel ID allocated by HSS. + * + * @retval + * ICP_STATUS_SUCCESS The function executed successfully. + * @retval + * ICP_STATUS_FAIL The function did not execute successfully. + * + * @pre + * The channel has been brought up. + * @post + * Call @ref icp_HssAccAllBuffersRetrieve to retrieve + * outstanding buffers. + * @note + * None + * @see + * @ref icp_HssAccChannelUp() + */ +icp_status_t +icp_HssAccChannelDown ( + unsigned channelId); + +/** + * @ingroup icp_HssAccChannelConfig + * HSS Channel Delete. + * @description + * This function is used to delete a channel. The timeslots + * allocated to a channel are freed by this call. For this function + * call to succeed, the function @ref icp_HssAccAllBuffersRetrieve + * should have been called beforehand. + * + * @context + * Calling function thread. + * @assumptions + * None + * @sideEffects + * None + * @blocking + * Yes + * @reentrant + * No + * @threadSafe + * Yes + * + * @param + * channelId [IN] - The channel ID allocated by HSS. + * + * @retval + * ICP_STATUS_SUCCESS The function executed successfully. + * @retval + * ICP_STATUS_FAIL The function did not execute successfully. + * @retval + * ICP_STATUS_INVALID_PARAM The channelId provided was invalid. + * @retval + * ICP_STATUS_RESOURCE The channel was not available for deletion, + * for example, there are still buffers left in the system for + * this channel. + * @retval + * ICP_STATUS_MUTEX An error occurred while grabbing or releasing the + * internal lock. + * + * @pre + * Traffic has been disabled on this channel first with @ref + * icp_HssAccChannelDown() and @ref icp_HssAccAllBuffersRetrieve + * should have been called beforehand. + * @post + * None + * @note + * None + * @see + * @ref icp_HssAccChannelConfigure() \n + * @ref icp_HssAccChannelDown() \n + * @ref icp_HssAccAllBuffersRetrieve() + */ +icp_status_t +icp_HssAccChannelDelete ( + unsigned channelId); + +/** + * @ingroup icp_HssAccDataPathPolledMode + * HSS Channel Transmit. + * @description + * Function which the client calls when it wants to transmit data on a + * channel. The specified channel should not be in a disabled state. + * + * @context + * Calling function thread. + * @assumptions + * None + * @sideEffects + * None + * @blocking + * Yes + * @reentrant + * No + * @threadSafe + * Yes + * + * @param + * channelId [IN] - The channel ID allocated by HSS. + * @param + * *buffer @ref IX_OSAL_MBUF[IN] - A pointer to an OSAL memory buffer + * which the client has filled with the payload for transmission. A + * successful transmission will depend on:\n + * - IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR being set to NULL as buffer + * chaining is not supported in this case;\n + * - IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR also being set to NULL as packet + * chaining is also not supported on Transmit, it is only used for + * Buffer recycling; \n + * - IX_OSAL_MBUF_PKT_LEN and IX_OSAL_MBUF_MLEN must be equal and set + * to the non-zero length of the packet submitted for transmission; + * In the case of Voice samples submitted for Transmission, + * IX_OSAL_MBUF_PKT_LEN must be a multiple of 4 bytes (e.g. 80 bytes + * is a correct size, 82 is not). + * - IX_OSAL_MBUF_MDATA should be set to the location in memory of the + * packet submitted for transmission. + * + * @retval + * ICP_STATUS_SUCCESS The function executed successfully. + * @retval + * ICP_STATUS_INVALID_PARAM One of the parameters provided was incorrect. + * @retval + * ICP_STATUS_RESOURCE The selected channel is not available for this + * operation. + * @retval + * ICP_STATUS_MUTEX An error occurred while grabbing or releasing the + * internal lock. + * @retval + * ICP_STATUS_OVERFLOW There was no room in the Channel Buffer for the data + * submitted. + * @retval + * ICP_STATUS_FAIL The function did not execute successfully. + * + * @pre + * The channel has been successfully configured and in the enabled + * state. + * @post + * None + * @note + * None + * @see + * @ref icp_HssAccReceive() \n + * @ref icp_hssacc_rx_callback_t() + */ +icp_status_t +icp_HssAccTransmit ( + unsigned channelId, + IX_OSAL_MBUF *buffer); + +/** + * @ingroup icp_HssAccDataPathPolledMode + * HSS Receive function. + * @description + * Function which the client calls when it wants to receive data on a + * channel. The specified channel should not be in a disabled state. + * + * @context + * Calling function thread. + * @assumptions + * None + * @sideEffects + * None + * @blocking + * Yes + * @reentrant + * No + * @threadSafe + * Yes + * + * @param + * channelId [IN] - The channel ID allocated by HSS. + * @param + * **buffer @ref IX_OSAL_MBUF[OUT] - A pointer to an OSAL memory buffer + * that has been filled with receive payload. IX_OSAL_MBUF_PKT_LEN and + * IX_OSAL_MBUF_MLEN will both contain the length of the received + * payload. + * + * @retval + * ICP_STATUS_SUCCESS The function executed successfully. + * @retval + * ICP_STATUS_UNDERFLOW There was no data to receive. +* @retval + * ICP_STATUS_MUTEX An error occurred while grabbing or releasing the + * internal lock. +* @retval + * ICP_STATUS_INVALID_PARAM One of the parameters was invalid in the + * current state. +* @retval + * ICP_STATUS_FAIL The function did not execute successfully. + * + * @pre + * The channel has been successfully configured and in the enabled + * state. + * @post + * None + * @note + * None + * @see + * @ref icp_HssAccTransmit() + */ +icp_status_t +icp_HssAccReceive ( + unsigned channelId, + IX_OSAL_MBUF **buffer); + +/** + * @ingroup icp_HssAccDataPathPolledMode + * HSS Receive Free Buffer Replenish function. + * @description + * Function which the client calls at regular intervals to provide memory + * buffers to the HSS TDM I/O Access Library for receive. The specific + * service about to be replenished should have been configured before + * attempting to call this function. + * + * @context + * Calling function thread + * @assumptions + * None + * @sideEffects + * None + * @blocking + * Yes + * @reentrant + * No + * @threadSafe + * Yes + * + * @param + * channelType @ref icp_hssacc_channel_type_t [IN] - Channel type to + * replenish buffers on. + * @param + * *buffer @ref IX_OSAL_MBUF[IN] - A pointer to a free OSAL memory buffer + * to be filled with payload. The buffer capacity must be at least + * as large as the maxRxFrameSize in the call to + * @ref icp_HssAccVoiceInit() or @ref icp_HssAccHdlcInit() depending on + * the channelType. A successful replenish will depend on:\n + * - IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR being set to NULL as buffer + * chaining is not supported in this case;\n + * - IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR also being set to NULL as packet + * chaining is also not supported on Receive, it is only used for + * Buffer recycling; \n + * - IX_OSAL_MBUF_MLEN must be set to the buffer capacity as detailed + * above; \n + * - IX_OSAL_MBUF_MDATA should be set to the location in memory of the + * data block allocated for packet reception. + * + * @retval + * ICP_STATUS_SUCCESS The function executed successfully. + * @retval + * ICP_STATUS_FAIL The function did not execute successfully. + * + * @pre + * At least one channel must be configured and in the enabled state + * before calling this function. + * + * @post + * None + * @note + * None + * @see + * icp_HssAccHdlcInit() \n + * icp_HssAccVoiceInit() \n + * icp_HssAccReceive() \n + * icp_hssacc_rx_callback_t() + */ +icp_status_t +icp_HssAccRxFreeReplenish ( + icp_hssacc_channel_type_t channelType, + IX_OSAL_MBUF *buffer); + +/** + * @ingroup icp_HssAccDataPathPolledMode + * HSS Transmit Done Buffer Retrieve function. + * @description + * Function which the client calls at regular intervals to retrieve + * buffers from the transmit done queue. The channel should have been + * configured and should not be in the disabled state before attempting + * to call this function. Also, the connection should not be in a + * deleting state. It is the responsibility of the client to ensure that + * it is only retrieving buffers from channels that it sent buffers to. + * + * @context + * Calling function thread. + * @assumptions + * None + * @sideEffects + * None + * @blocking + * Yes + * @reentrant + * No + * @threadSafe + * Yes + * + * @param + * channelId [IN] - The channel ID allocated by HSS. + * @param + * **buffer @ref IX_OSAL_MBUF[OUT] - A pointer to a buffer taken from + * the transmit-done queue, the contents of which had been transmitted. + * + * @retval + * ICP_STATUS_SUCCESS The function executed successfully. + * @retval + * ICP_STATUS_INVALID_PARAM One of the input parameters was incorrect. + * @retval + * ICP_STATUS_RESOURCE The Selected channel is not available for Data + * transmission. + * @retval + * ICP_STATUS_MUTEX An error occurred while grabbing or releasing the + * internal lock. + * @retval + * ICP_STATUS_UNDERFLOW There were no TxDone buffers to retrieve. + * @retval + * ICP_STATUS_FAIL The function did not execute successfully. + * + * @pre + * The channel has been configured successfully. Transmission may have + * been initiated. + * @post + * None + * @note + * None + * @see + * @ref icp_hssacc_tx_done_callback_t() + */ +icp_status_t +icp_HssAccTxDoneRetrieve ( + unsigned channelId, + IX_OSAL_MBUF **buffer); + +/** + * @ingroup icp_HssAccDataPathPolledMode + * HSS All Buffers Retrieve for a channel ID. + * @description + * Function that the client calls to retrieve all the buffers + * contained in the HSS TDM I/O Access Library and TDM I/O Unit + * for a specific channel. The function combines all of the + * buffers that it gathers into a single chain and returns that + * chain of buffers to the client. The channel must be disabled + * with @ref icp_HssAccChannelDown() before this function can + * be called. + * + * Due to the nature of the receive path and the shared pool of + * Free buffers for a specific service, the free buffers are + * not recycled back to the client when this function is + * called unless this is the only channel for this service. + * + * However, the free buffers can be recycled back to the client + * if the channelId is set to the return value of + * @ref icp_HssAccNumSupportedChannelsGet(). For each service that has + * no enabled channels, all Receive Free buffers pertaining to that + * service will be provided back to the calling client. Only the free + * buffers are recycled and this is only intended as a means to recover + * free buffers in specific error scenarios such as an invalid setup. + * + * For instance, the HDLC service may have been setup successfully in + * the system but the application providing the Voice service may have + * encountered at error during Voice channel setup. this function could + * be called here to recover the buffers that were provisioned for the + * Voice service without impacting the HDLC service and without having to + * restart the system. + * + * @context + * Calling function thread. + * @assumptions + * None + * @sideEffects + * None + * @blocking + * Yes + * @reentrant + * No + * @threadSafe + * Yes + * + * @param + * channelId [IN] - The channel ID allocated by HSS + * or the return value of @ref icp_HssAccNumSupportedChannelsGet() + * @param + * **buffer @ref IX_OSAL_MBUF [OUT] - A pointer to a chain of all the + * voice buffers that HSS has. Chaining will be achieved using the + * IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR field. + * + * @retval + * ICP_STATUS_SUCCESS The function executed successfully. + * @retval + * ICP_STATUS_FAIL The function did not execute successfully. + * + * @pre + * HSS Initialization has completed successfully. + * @post + * None + * @note + * None + * @see + * @ref icp_hssacc_tx_done_callback_t() \n + * @ref icp_hssacc_rx_callback_t() + */ +icp_status_t +icp_HssAccAllBuffersRetrieve (unsigned channelId, + IX_OSAL_MBUF **buffer); + + + +/** + * @ingroup icp_HssAccDataPathCallbackMode + * HSS HDLC or Voice Data Path Servicing for callback mode of operation. + * @description + * This function should be called regularly in order to service the + * datapath for the specified channel type (HDLC or Voice) when HSS + * is operated in callback mode. + * The client should bind this function to a periodic event (e.g. timer + * interrupt or a task that sleeps and wakes up periodically). + * Callbacks are made for receive @ref icp_hssacc_rx_callback_t + * and transmit done @ref icp_hssacc_tx_done_callback_t events that + * have occurred for the channel type (HDLC or Voice). + * This function may be called from interrupt or task context. + * However, for optimal performance the choice of context depends also + * on the operating system used. + * + * @context + * Calling function context - could be interrupt or task context. + * @assumptions + * None + * @sideEffects + * None + * @blocking + * No + * @reentrant + * No + * @threadSafe + * Yes + * + * @param + * channelType @ref icp_hssacc_channel_type_t [IN] - Specifies + * what type of channels are to be serviced in this call. + * + * @retval + * ICP_STATUS_SUCCESS The function executed successfully. + * @retval + * ICP_STATUS_FAIL The function did not execute successfully. + * + * @pre + * Channels have been configured successfully. + * @post + * None + * @note + * None + * @see + * icp_hssacc_tx_done_callback_t \n + * icp_hssacc_rx_callback_t \n + */ +icp_status_t +icp_HssAccDataPathService (icp_hssacc_channel_type_t channelType); + + + +/** + * @ingroup icp_HssAccStats + * HSS Channel Statistics Show. + * @description + * Function which the client calls to see the statistics that have been + * gathered for the specified channel. The output is sent to the + * standard output (stdout). + * + * @context + * Calling function thread. + * @assumptions + * None + * @sideEffects + * None + * @blocking + * Yes + * @reentrant + * No + * @threadSafe + * Yes + * + * @param + * channelId [IN] - The channel ID allocated by HSS. + * + * @retval + * ICP_STATUS_SUCCESS The function executed successfully. + * @retval + * ICP_STATUS_FAIL The function did not execute successfully. + * + * @pre + * HSS Initialization has completed successfully. + * @post + * None + * @note + * None + * @see + * @ref icp_HssAccChannelStatsReset() + */ +icp_status_t +icp_HssAccChannelStatsShow (unsigned channelId); + +/** + * @ingroup icp_HssAccStats + * HSS Channel Statistics reset. + * @description + * Function which the client calls to reset the statistics that have been + * gathered for the specified channel. + * + * @context + * Calling function thread. + * @assumptions + * None + * @sideEffects + * None + * @blocking + * Yes + * @reentrant + * No + * @threadSafe + * Yes + * + * @param + * channelId [IN] - The channel ID allocated by HSS. + * + * @retval + * ICP_STATUS_SUCCESS The function executed successfully. + * @retval + * ICP_STATUS_FAIL The function did not execute successfully. + * @pre + * HSS Initialization has completed successfully. + * @post + * None + * @note + * None + * @see + * @ref icp_HssAccChannelStatsShow() + */ +icp_status_t +icp_HssAccChannelStatsReset (unsigned channelId); + +/** + * @ingroup icp_HssAccStats + * HSS Per Port All Statistics Show. + * @description + * Function which the client calls to see the statistics that have been + * gathered for all of the channels for the given port. The output is + * be sent to the standard output (stdout). + * + * @context + * Calling function thread. + * @assumptions + * None + * @sideEffects + * None + * @blocking + * Yes + * @reentrant + * No + * @threadSafe + * Yes + * + * @param + * portId [IN] - The HSS port ID (0 to + * @ref icp_HssAccNumSupportedPortsGet()-1). + * + * @retval + * ICP_STATUS_SUCCESS The function executed successfully. + * @retval + * ICP_STATUS_FAIL The function did not execute successfully. + * @pre + * The port has been configured successfully. + * @post + * None + * @note + * None + * @see + * @ref icp_HssAccPortStatsReset() + */ +icp_status_t +icp_HssAccPortStatsShow ( + unsigned portId); + + +/** + * @ingroup icp_HssAccStats + * HSS Port Statistics Reset. + * @description + * Function which the client calls to reset the statistics that have been + * gathered for the specified port. + * + * @context + * Calling function thread. + * @assumptions + * None + * @sideEffects + * None + * @blocking + * Yes + * @reentrant + * No + * @threadSafe + * Yes + * + * @param + * portId [IN] - The HSS port ID (0 to + * @ref icp_HssAccNumSupportedPortsGet()-1). + * + * @retval + * ICP_STATUS_SUCCESS The function executed successfully. + * @retval + * ICP_STATUS_FAIL The function did not execute successfully. + * + * @pre + * HSS Initialization has completed successfully. + * @post + * None + * @note + * None + * @see + * @ref icp_HssAccPortStatsShow() + */ +icp_status_t +icp_HssAccPortStatsReset ( + unsigned portId); + +/** + * @ingroup icp_HssAccStats + * HSS Show All Statistics function. + * @description + * This function displays all the statistics for the HSS component as + * well as the current state of the component. The output is sent to + * the standard output (stdout). The output includes a report on all + * allocated channels for all ports as well as internal configuration + * statistics for the component. + * + * @context + * Calling function thread. + * @assumptions + * None + * @sideEffects + * None + * @blocking + * Yes + * @reentrant + * No + * @threadSafe + * Yes + * @retval + * None + * @pre + * HSS Initialization has completed successfully. + * @post + * None + * @note + * None + * @see + * @ref icp_HssAccStatsReset() + */ +void +icp_HssAccStatsShow (void); + + + + + +/** + * @ingroup icp_HssAccStats + * HSS All Statistics Reset function. + * @description + * This function resets all the statistics for the HSS component. + * + * @context + * Calling function thread. + * @assumptions + * None + * @sideEffects + * None + * @blocking + * Yes + * @reentrant + * No + * @threadSafe + * Yes + * @retval + * None + * @pre + * HSS Initialization has completed successfully. + * @post + * None + * @note + * None + * @see + * @ref icp_HssAccStatsShow() + */ +void +icp_HssAccStatsReset (void); + +#endif /* ICP_HSSACC_H */ + +/** + * @} defgroup icp_HssAcc + */ + + + diff --git a/Acceleration/include/hss/icp_hssdrv.h b/Acceleration/include/hss/icp_hssdrv.h new file mode 100644 index 0000000..b660e70 --- /dev/null +++ b/Acceleration/include/hss/icp_hssdrv.h @@ -0,0 +1,233 @@ +/****************************************************************************** + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + *****************************************************************************/ + +/* + ***************************************************************************** + * Doxygen group definitions + ****************************************************************************/ + +/** + ******************************************************************************* + * @defgroup icp_hssdrv Definitions common to the HSS voice and HSS data drivers. + * + * @purpose + * + * Common defines and structures used by voice and data drivers + * including the HSS port configuration and the channel timeslot + * configuration. + * + ******************************************************************************/ + +#ifndef ICP_HSSDRV_H +#define ICP_HSSDRV_H + +#include <asm/types.h> + + +#define ICP_HSSDRV_PORT_E1_FRAMER_MEZZANINE_CONFIG 0 +/**< @ingroup icp_hssdrv + * Configuration for the reference platform E1 framer mezzanine. + */ +#define ICP_HSSDRV_PORT_T1_FRAMER_MEZZANINE_CONFIG 1 +/**< @ingroup icp_hssdrv + * Configuration for the reference platform T1 framer mezzanine. + */ +#define ICP_HSSDRV_PORT_HMVIP_FRAMER_MEZZANINE_CONFIG 2 +/**< @ingroup icp_hssdrv + * Configuration for the reference platform in H-MVIP mode. + */ +#define ICP_HSSDRV_PORT_ANALOG_VOICE_MEZZANINE_CONFIG 3 +/**< @ingroup icp_hssdrv + * Configuration for the reference platform analog voice mezzanine. + */ +#define ICP_HSSDRV_PORT_XHFC_MEGREZ_PROTO_XIVO_CONFIG 4 +/**< @ingroup icp_hssdrv + * Configuration for the XiVO IPBX OpenHardware prototype + * with Megrez/Mizar board and ad-hoc wiring to XHFC-4SU EVB. + */ +#define ICP_HSSDRV_PORT_LE89316_MEGREZ_PROTO_XIVO_CONFIG 5 +/**< @ingroup icp_hssdrv + * Configuration for the XiVO IPBX OpenHardware prototype + * with Megrez/Mizar board and ad-hoc wiring to XHFC-4SU EVB. + */ +#define ICP_HSSDRV_PORT_CONFIG_DELIMITER 6 + + +/** + * @ingroup icp_hssdrv + * HSS Loopback Setting + * @description + * Used to enable/disable internal/external loop back. + * When the internal or external loopback settings are selected + * the pre-defined configuration + * e.g. ICP_HSSDRV_PORT_HMVIP_FRAMER_MEZZANINE_CONFIG is ignored + * and an E1 port speed is set. + * Please note that for internal loopback a mezzanine card must + * not be connected to the HSS port. + */ + +typedef enum +{ + ICP_HSSDRV_EXTERNAL_LOOPBACK, + /**< Enable the external loop back, all received data looped to + transmit. */ + ICP_HSSDRV_INTERNAL_LOOPBACK, + /**< Enable the internal loop back, all transmitted data looped to + receive. This Setting is incompatible with any peripheral connected + to the port configured in this mode. */ + ICP_HSSDRV_NO_LOOPBACK, + /**< No loopback enabled on the port. */ + ICP_HSSDRV_EXTERNAL_LOOPBACK_DELIMITER + /**<Enum delimiter for error checks. */ +} icp_hssdrv_loopback_t; + + +/** + * @ingroup icp_hssdrv + * Port up configuration + * @description + * This structure contains the data required to configure and + * enable a HSS port. + * + * @purpose + * Parameter to the voice and data driver PORT_UP IOCTLs. + * @see + * None */ + +typedef struct icp_hssdrv_portup_s +{ + unsigned int portId; + /**< HSS port ID 0 -> 2. */ + unsigned int port_config; + /**< Selects a predefined port configuration for a particular + * mezzanine card, one of ICP_HSSDRV_PORT_E1_FRAMER_MEZZANINE_CONFIG, + * ICP_HSSDRV_PORT_T1_FRAMER_MEZZANINE_CONFIG, + * ICP_HSSDRV_PORT_HMVIP_FRAMER_MEZZANINE_CONFIG, + * ICP_HSSDRV_PORT_ANALOG_VOICE_MEZZANINE_CONFIG. \n These configurations + * are hard coded in the driver and can be modified for a customer + * specific mezzanine card. */ + icp_hssdrv_loopback_t loopbackMode; + /**< Loopback mode for this port. */ +} icp_hssdrv_portup_t; + +/** + * @ingroup icp_hssdrv + * Timeslot map for a channel onto a HSS port. + * + * @description + * This structure contains the timeslot map information + * for each port. Setting a bit high (1) indicates that timeslot + * is required. The timeslot bit map for E1/T1 lines 1, 2 and 3 are + * only relevant if the HSS Frame contains > 32 timeslots, i.e. + * MVIP is enabled and we have 4 E1 lines on a single port. + * + * + * This series of bit masks represents the timeslots [0 -> 31] for each HSS + * line. LSb represents timeslot #0, MSb represents timeslot #31 for a line. + * + * Sample configurations: + * + * - 0x00000000, 0x00000000, 0x00000002, 0x0000000 corresponds to + * timeslots 1 on line 2. + * + * - 0x00000000, 0x00000000, 0x03000300, 0x0000000 corresponds to + * timeslots 8,9 on line 2 and timeslots 24,25 on line 2. This example is + * a wideband voice channel configuration for the Si3220 SLIC/CODEC + * (16 bit @ 16khz, i.e. 2 sets of 2 timeslots separated by 16 timeslots). + * + * - 0x00000000, 0x00000030, 0x00000000, 0x0000000 corresponds to + * timeslots 4 and 5 on line 1. This example could be a 16 bit linear + * narrowband voice channel. + * + * - 0x00000000, 0xFFFFFFFE, 0x00000000, 0x0000000 corresponds to + * timeslots 1 to 31 on line 1. + * + * @purpose + * Channel timeslot configuration. + * @see + * None */ +typedef struct icp_hssdrv_timeslot_map_s +{ + __u32 line0_timeslot_bit_map; + /**< Timeslot bit map for line 0. */ + __u32 line1_timeslot_bit_map; + /**< Timeslot bit map for line 1. */ + __u32 line2_timeslot_bit_map; + /**< Timeslot bit map for line 2. */ + __u32 line3_timeslot_bit_map; + /**< Timeslot bit map for line 3. */ +} icp_hssdrv_timeslot_map_t; + + + + +#endif +/* ICP_HSSDRV_H */ + + + + + + + + diff --git a/Acceleration/include/hss/icp_hssvoicedrv.h b/Acceleration/include/hss/icp_hssvoicedrv.h new file mode 100644 index 0000000..e26a202 --- /dev/null +++ b/Acceleration/include/hss/icp_hssvoicedrv.h @@ -0,0 +1,376 @@ +/****************************************************************************** + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + *****************************************************************************/ + +/* + ***************************************************************************** + * Doxygen group definitions + ****************************************************************************/ + +/** + ***************************************************************************** + * @defgroup icp_hssvoicedrv HSS voice device driver API + * + * @purpose + * + * This device driver can be called from user space. A character + * device can be opened using the system call open(). The file + * name is "/dev/hss-voice". This device can + * be poll(), read(), write(), and release() like a standard character + * device. This device driver can be called from user space + * using the standard ioctl interface. + * + * A channel is configured on the device using ioctl calls. Up + * to 128 channels can be configured. One limitation is that + * no more than 64 channels can be associated to any one file + * descriptor. + * + * Since standard POSIX file poll/read/write operations do not allow + * the inclusion of extra (custom) parameters (such as the + * channel ID), the Voice channel ID is embedded in the user + * buffer passed in read/write calls. + * + * When reading/writing voice data to/from the device with + * calls to read() and write(), the format of the user buffer + * is as follows: + * + * | len | channelId | payload || len | channelId | payload || etc. \n + * + * - len (16 bit) is the length in bytes of the voice packet + * payload. The voice packet payload is a multiple of 4 bytes. + * 16 bits are used for future proofing. Additionally, when + * combined with the 16 bit channelId, the payload is always + * 32 bit aligned. As the user buffer is a char array the + * order of the len bytes needs to be specified. It is passed + * in the order | MSB | LSB |. + * + * - channelId (16 bit) is the channel ID of the voice packet + * payload. Passing len and channelId in the user buffer for + * each packet can simplify the client code - it doesn't have to + * remember fixed offsets for each packet in a buffer. As the + * user buffer is a char array the order of the channelId bytes + * needs to be specified. It is passed in the order | MSB | LSB |. + * + * - payload (len bytes) is the voice packet payload for the + * channelId. + * + * With the above user buffer format, write() gives the client + * the options to 1) submit a single packet for a single channel + * 2) submit multiple packets for a single channel or 3) submit + * multiple packets for multiple channels. + * + * read() on a file descriptor returns multiple packets together + * in the user buffer, with up to one packet for each registered + * channel for the file descriptor. + * The client can choose to open() multiple file descriptors and + * register a single channel per descriptor, thus receiving a + * single packet per read() on a descriptor. Alternatively the + * client can register multiple channels for multiple + * descriptors, thus receiveing multiple packets per read() on a + * particular descriptor. + * + * File descriptors can be opened in blocking or non-blocking + * mode. At any given time, all open file descriptors must be of + * the same mode. Attempts to open file descriptors in + * different modes at the same time will result in a fail. For + * example, a first file descriptor could be opened in blocking + * mode. All subsequent opens should be in blocking mode. All current + * open file descriptors in blocking mode should be closed for + * an open to succeed in non-blocking mode. + * + * By default the driver operates in blocking mode. Calls to + * read() blocks until received packets are available for all + * registered channels. Calls to write() do not block. + * + * When configured for non blocking mode (O_NONBLOCK), calls to + * read() immediately return available received packets (one + * packet per registered channel). If there are no packets + * available it returns 0. + * + * Calls to write() buffer as many full packets as there is + * space internally for transmission. The returned length + * indicates the number of bytes written (including the length + * and channelId fields). + * + * The voicePacketSize and number of timeslots in the tsMap + * configured at channel setup defines the read() block rate for + * a channel. e.g. 1 timeslot for a voicePacketSize of 80 + * bytes for an E1 @ 2.048MHz corresponds to a packet read() + * every 10msec. + * If the client configures multiple channels for the same file + * descriptor, calls to read() for that file descriptor will + * block until data is available for the slowest channel. + * The client must not process channels with different codec + * intervals on the same file descriptor. + * + * In blocking mode, the poll() method may be used to determine whether + * the read()function will block when called. The poll() method + * should not be used in non-blocking mode. + * + * HSS Voice Driver allows clients to utilize multiple threading. + * There are some restrictions that apply: poll() methods + * can only be called simultaneously if they are on different file + * descriptors. read() methods can only be called simultaneously if + * they are on different file descriptors. poll() and read() methods + * can only be called simultaneously if they are on different file + * descriptors. write() methods can be called simultaneously. + * ioctl() methods can not be called simultaneously. + * + * It is recommended that the client synchronizes data path methods such + * as poll()/read()/write() with control ioctl() commands on a file + * descriptor. However, the client can use both simultaneously as long as + * it can handle the race conditions (examples below) that may be + * introduced by dynamically changing the state of channels simultaneous + * with performing data path operations on those same channels. + * + * Example 1: poll() is called on a file descriptor that has 2 channels + * associated with it. It returns that data is ready on both channels and + * therefore a call to read() will not block. ioctl() commands are used + * to add another channel on which receive data is not ready. read() is + * called and is expected to not block as poll() has indicated this. As + * there is no data ready on the newly added channel, read() blocks. + * + * Example 2: A blocking read() is called on a file descriptor that has 2 + * channels associated with it. At this point an ioctl() command to + * delete 1 channel is run. Depending on the stage of the read() when + * the ioctl command is run, the read() may return data for both channels, + * or just the channel that is enabled. + * + * Please note that for blocking read(), any channel that is causing the + * read() to block will have its state checked every 10mS to ensure that + * it is still enabled and therefore data is expected on it. The poll() + * method should be given a timeout by the client in order that it does + * not block indefinitely if there is a state change. + * + * The release() method should only be called after any other calls are + * completed. It should not be attempted simultaneously with other + * methods. + * + * None of the methods provided by the HSS Voice Driver are callable as + * part of an Interrupt Service Routine. + * + *****************************************************************************/ + +#ifndef ICP_HSSVOICEDRV_H +#define ICP_HSSVOICEDRV_H + +#include <linux/ioctl.h> +#include "icp_hssdrv.h" + +/** + * @ingroup icp_hssvoicedrv + * Channel add parameter. + * @description + * This structure contains the configuration for adding a voice channel. + * + * @purpose + * Parameter to the ICP_HSSVOICEDRV_CHAN_ADD ioctl(). + * @see + * None */ + +typedef struct icp_hssvoicedrv_channeladd_s +{ + unsigned int channelId; + /**< Client provided channel ID from 0 -> 127. Value must be unique per + * call to open(). */ + unsigned int portId; + /**< HSS port ID 0 -> 3. */ + unsigned int voicePacketSize; + /**< Set this argument to configure the size of the voice packets + * in bytes for this channel. + */ + icp_hssdrv_timeslot_map_t tsMap; + /**< Timeslot Map. This argument, when combined with the voicePacketSize, + * defines the read() rate when in blocking mode. e.g. If 1 + * timeslot is enabled in the timeslot map for a channel and the + * voicePacketSize is set to 80 bytes at a HSS port rate of at + * 2.048MHz, this corresponds a voice packet every 10msec. */ + unsigned int voiceIdleAction; + /**< This argument is used to configure the Tx idle action to (0) transmit + * the pattern set in the voiceIdlePattern argument or (1) to repeat the + * last frame. */ + unsigned int voiceIdlePattern; + /**< If the voiceIdleAction argument is set to (0) this argument is used + * to configure the Tx idle pattern as a value from 0 to 0xFF. This Idle + * pattern will also be used when configured to repeat the last frame + * before the first frame is transmitted. */ + unsigned int channelDataInvert; + /**< Used to select whether or not one's complement inversion is + * performed on the channel data before any other + * processing occurs. Set this argument to (1) in + * order to enable one's complement inversion of the + * bits. Set this argument to (0) to disable the bit + * order inversion. */ + unsigned int channelBitEndianness; + /**< Used to configure the bit endianness of a channel. Set this + * argument to (1) for MSb first, (0) for LSb first. */ + unsigned int channelByteSwap; + /**< Used to configure whether bytes within each half-word (2 bytes) of + * data are swapped (1) or not (0) before transmitting out on the line + * and after receiving from the line. */ +} icp_hssvoicedrv_channeladd_t; + + +/** + * @ingroup icp_hssvoicedrv + * Channel Bypass parameter. + * @description + * This structure contains the configuration for creating a + * unidirectional channel bypass. Packets on the Rx path for + * srcChannelId will be routed to the Tx path of destChannelId. + * + * @purpose + * Parameter to the ICP_HSSVOICEDRV_CHAN_BYPASS ioctl(). + * @see + * None */ + +typedef struct icp_hssvoicedrv_channelbypass_s +{ + unsigned int srcChannelId; + /**< Client provided channel ID from 0 -> 127. This channel will + * be the source of data in the bypass. */ + unsigned int destChannelId; + /**< Client provided channel ID from 0 -> 127. This channel will + * be the destination of the data in the bypass. */ + unsigned char * gainControlTable; + /**< Pointer to the Gain Control Table to be used for this bypass, + * the table must be 256 bytes in size. */ +} icp_hssvoicedrv_channelbypass_t; + +#define ICP_HSSVOICEDRV_IOC_MAGIC 'q' +/**< @ingroup icp_hssvoicedrv + * Seed for ioctl commands. + */ + +#define ICP_HSSVOICEDRV_PORT_UP _IOW(ICP_HSSVOICEDRV_IOC_MAGIC, 0, int) +/**< @ingroup icp_hssvoicedrv + * ioctl command to bring up the port. The parameter is a + * pointer to a data structure of type @ref icp_hssdrv_portup_s + * containing port number, the predefined mezzanine card + * configuration and loopback mode. */ + +#define ICP_HSSVOICEDRV_PORT_DOWN _IO(ICP_HSSVOICEDRV_IOC_MAGIC, 1) +/**< @ingroup icp_hssvoicedrv + * ioctl command to bring down the port. The port may then be + * brought up again with a new configuration. The parameter + * is an integer indicating the port number to bring down (0-3). */ + + +#define ICP_HSSVOICEDRV_CHAN_ADD _IOW(ICP_HSSVOICEDRV_IOC_MAGIC, 2, int) +/**< @ingroup icp_hssvoicedrv + * ioctl command to add and configure a voice channel. The + * parameter is a pointer to data structure of type @ref + * icp_hssvoicedrv_channeladd_s. Data flow must be enabled by + * a subsequent call to the ICP_HSSVOICEDRV_CHAN_UP IOCTL. */ + +#define ICP_HSSVOICEDRV_CHAN_REMOVE _IO(ICP_HSSVOICEDRV_IOC_MAGIC, 3) +/**< @ingroup icp_hssvoicedrv + * ioctl command to remove (delete) the + * channel, specified by the channelId in the parameter. The + * client shall put the channel down before calling this. */ + +#define ICP_HSSVOICEDRV_CHAN_UP _IO(ICP_HSSVOICEDRV_IOC_MAGIC, 4) +/**< @ingroup icp_hssvoicedrv + * ioctl command to enable data flow on the channelId, + * specified by the channelId on the parameter. + */ + +#define ICP_HSSVOICEDRV_CHAN_DOWN _IO(ICP_HSSVOICEDRV_IOC_MAGIC, 5) +/**< @ingroup icp_hssvoicedrv + * ioctl command to disable data flow for the channel id + * specified in the parameter. */ + +#define ICP_HSSVOICEDRV_CHAN_BYPASS_ENABLE _IOW(ICP_HSSVOICEDRV_IOC_MAGIC, 6, int) +/**< @ingroup icp_hssvoicedrv + * ioctl command to create a unidirectional channel bypass between + * the channels specified in the data structure of type + * @ref icp_hssvoicedrv_channelbypass_s passed as parameter. Two + * calls to this ioctl are required to setup bi-directional bypass. + * */ + +#define ICP_HSSVOICEDRV_CHAN_BYPASS_DISABLE _IOW(ICP_HSSVOICEDRV_IOC_MAGIC, 7, int) +/**< @ingroup icp_hssvoicedrv + * ioctl command to remove a unidirectional channel bypass between + * the channels specified in the data structure of type + * @ref icp_hssvoicedrv_channelbypass_s passed as parameter. Two + * calls to this ioctl are required to remove a bi-directional bypass. + * */ + +#define ICP_HSSVOICEDRV_STATS _IO(ICP_HSSVOICEDRV_IOC_MAGIC, 8) +/**< @ingroup icp_hssvoicedrv + * ioctl command to display the stats for the HSS Voice Driver. Stats + * displayed are HSS Voice Driver representation of clients, channels + * and their associated information. + * */ + + +#endif +/* ICP_HSSVOICEDRV_H */ + + + + + + + + diff --git a/Acceleration/include/hss/icp_sspacc.h b/Acceleration/include/hss/icp_sspacc.h new file mode 100644 index 0000000..45dc118 --- /dev/null +++ b/Acceleration/include/hss/icp_sspacc.h @@ -0,0 +1,1777 @@ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +/* + ***************************************************************************** + * Doxygen group definitions + ****************************************************************************/ + +/** + ****************************************************************************** + * @defgroup icp_SspAcc Public API for the SSP I/O Unit + * + * @purpose + * + * The Synchronous Serial Port (SSP) I/O Access Library is the + * software that provides an interface to the SSP hardware to higher + * level software such as device drivers. This is a kernel space + * interface. + * + * The SSP hardware is a full-duplex synchronous serial interface. + * The SSP hardware can connect to a variety of external + * analog-to-digital (A/D) converters, audio and telecom codecs, and + * many other devices that use serial protocols for transferring data. + * It supports Microwire, synchronous serial protocol (SSP), and serial + * peripheral interface (SPI) protocol. + * + * The SSP hardware supports serial bit rates from 7.2 KHz to 1.84 MHzs. + * Serial data formats may range from 4 to 16 bits in length. Two on-chip + * FIFOs are used for data, one for Rx and one for Tx. The buffers are + * 16 entries deep x 16 bits wide. + * + ******************************************************************************/ + +#ifndef ICPSSPACC_H +#define ICPSSPACC_H + + +#include "icp.h" + + +/* ---------------------------------------------------------------------------- + * Enumerated Types + * --------------------------------------------------------------------------- + */ +/** + * @ingroup icp_SspAcc + * The Data Size. + * + * @description + * The data sizes in bits that are supported by the protocol. + */ +typedef enum +{ + ICP_SSPACC_DATA_SIZE_TOO_SMALL = 2, + /**<Data size of too small. */ + ICP_SSPACC_DATA_SIZE_4 = 3, + /**<Data size of 4. */ + ICP_SSPACC_DATA_SIZE_5, + /**<Data size of 5 */ + ICP_SSPACC_DATA_SIZE_6, + /**<Data size of 6. */ + ICP_SSPACC_DATA_SIZE_7, + /**<Data size of 7. */ + ICP_SSPACC_DATA_SIZE_8, + /**<Data size of 8. */ + ICP_SSPACC_DATA_SIZE_9, + /**<Data size of 9. */ + ICP_SSPACC_DATA_SIZE_10, + /**<Data size of 10. */ + ICP_SSPACC_DATA_SIZE_11, + /**<Data size of 11. */ + ICP_SSPACC_DATA_SIZE_12, + /**<Data size of 12. */ + ICP_SSPACC_DATA_SIZE_13, + /**<Data size of 13. */ + ICP_SSPACC_DATA_SIZE_14, + /**<Data size of 14. */ + ICP_SSPACC_DATA_SIZE_15, + /**<Data size of 15. */ + ICP_SSPACC_DATA_SIZE_16, + /**<Data size of 16. */ + ICP_SSPACC_DATA_SIZE_TYPE_DELIMITER + /**<Data size of too big. */ +} icp_sspacc_data_size_t; + +/** + * @ingroup icp_SspAcc + * The Port Status. + * + * @description + * The status of the SSP port to be set to enable/disable. + */ +typedef enum +{ + ICP_SSPACC_PORT_DISABLE = 0, + /**<Port Disable. */ + ICP_SSPACC_PORT_ENABLE, + /**<Port Enable. */ + ICP_SSPACC_PORT_TYPE_DELIMITER + /**<Invalid Status. */ +} icp_sspacc_port_status_t; + +/** + * @ingroup icp_SspAcc + * The Frame Format. + * + * @description + * The frame format that is to be used - SPI, SSP, or Microwire. + */ +typedef enum +{ + ICP_SSPACC_FRAME_FORMAT_SPI = 0, + /**<SPI Format. */ + ICP_SSPACC_FRAME_FORMAT_SSP, + /**<SSP Format. */ + ICP_SSPACC_FRAME_FORMAT_MICROWIRE, + /**<Microwire Format. */ + ICP_SSPACC_FRAME_FORMAT_TYPE_DELIMITER + /**<Invalid Format. */ +} icp_sspacc_frame_format_t; + +/** + * @ingroup icp_SspAcc + * The Clock Source. + * + * @description + * The source to produce the SSP serial clock. + */ +typedef enum +{ + ICP_SSPACC_CLK_SOURCE_ON_CHIP = 0, + /**<On Chip Clock. */ + ICP_SSPACC_CLK_SOURCE_EXTERNAL, + /**<External Clock. */ + ICP_SSPACC_CLK_SOURCE_TYPE_DELIMITER + /**<Invalid Clock source. */ +} icp_sspacc_clk_source_t; + +/** + * @ingroup icp_SspAcc + * The SPI SClock Phase. + * + * @description + * The SPI Serial Clock Phase: + * 0 - SCLK is inactive one cycle at the start of a frame and 1/2 cycle at the + * end of a frame. + * 1 - SCLK is inactive 1/2 cycle at the start of a frame and one cycle at the + * end of a frame. + */ +typedef enum +{ + ICP_SSPACC_SPI_SCLK_PHASE_START_ONE_END_HALF = 0, + /**<SCLK is inactive one cycle at the start of a frame and 1/2 cycle at the + end of a frame. */ + ICP_SSPACC_SPI_SCLK_PHASE_START_HALF_END_ONE, + /**< SCLK is inactive 1/2 cycle at the start of a frame and one cycle at the + end of a frame. */ + ICP_SSPACC_SPI_SCLK_PHASE_TYPE_DELIMITER + /**< Invalid SPI phase. */ +} icp_sspacc_spi_sclk_phase_t; + +/** + * @ingroup icp_SspAcc + * The SPI SClock Polarity. + * + * @description + * The SPI SCLK Polarity can be set to either low or high. + */ +typedef enum +{ + ICP_SSPACC_SPI_SCLK_POLARITY_LOW = 0, + /**< Low Polarity. */ + ICP_SSPACC_SPI_SCLK_POLARITY_HIGH, + /**< High Polarity. */ + ICP_SSPACC_SPI_SCLK_POLARITY_TYPE_DELIMITER + /**<Invalid Polarity. */ +} icp_sspacc_spi_sclk_polarity_t; + +/** + * @ingroup icp_SspAcc + * The Microwire Control Word Size. + * + * @description + * The Microwire control word can be either 8 or 16 bit. + */ +typedef enum +{ + ICP_SSPACC_MICROWIRE_CTL_WORD_8_BIT = 0, + /**<8-bit Microwire. */ + ICP_SSPACC_MICROWIRE_CTL_WORD_16_BIT, + /**<16-bit Microwire. */ + ICP_SSPACC_MICROWIRE_CTL_WORD_TYPE_DELIMITER + /**<Invalid Microwire Control Word. */ +} icp_sspacc_microwire_ctl_word_t; + +/** + * @ingroup icp_SspAcc + * The FIFO Threshold. + * + * @description + * The threshold in frames (each frame is defined by icp_sspacc_DataSize) + * that can be set for the FIFO to trigger a threshold exceed when + * checking with the ThresholdCheck functions or an interrupt + * when it is enabled. + */ +typedef enum +{ + ICP_SSPACC_FIFO_TSHLD_1 = 0, + /**<FIFO threshold of 1. */ + ICP_SSPACC_FIFO_TSHLD_2, + /**<FIFO threshold of 2. */ + ICP_SSPACC_FIFO_TSHLD_3, + /**<FIFO threshold of 3. */ + ICP_SSPACC_FIFO_TSHLD_4, + /**<FIFO threshold of 4. */ + ICP_SSPACC_FIFO_TSHLD_5, + /**<FIFO threshold of 5. */ + ICP_SSPACC_FIFO_TSHLD_6, + /**<FIFO threshold of 6. */ + ICP_SSPACC_FIFO_TSHLD_7, + /**<FIFO threshold of 7. */ + ICP_SSPACC_FIFO_TSHLD_8, + /**<FIFO threshold of 8. */ + ICP_SSPACC_FIFO_TSHLD_9, + /**<FIFO threshold of 9. */ + ICP_SSPACC_FIFO_TSHLD_10, + /**<FIFO threshold of 10. */ + ICP_SSPACC_FIFO_TSHLD_11, + /**<FIFO threshold of 11. */ + ICP_SSPACC_FIFO_TSHLD_12, + /**<FIFO threshold of 12. */ + ICP_SSPACC_FIFO_TSHLD_13, + /**<FIFO threshold of 13. */ + ICP_SSPACC_FIFO_TSHLD_14, + /**<FIFO threshold of 14. */ + ICP_SSPACC_FIFO_TSHLD_15, + /**<FIFO threshold of 15. */ + ICP_SSPACC_FIFO_TSHLD_16, + /**<FIFO threshold of 16. */ + ICP_SSPACC_FIFO_TSHLD_TYPE_DELIMITER + /**<Invalid FIFO threshold. */ +} icp_sspacc_fifo_threshold_t; + +/* ---------------------------------------------------------------------------- + * Call-back definitions + * ---------------------------------------------------------------------------- + */ + +/** + * @ingroup icp_SspAcc + * SSP Rx FIFO Overrun Handler. + * @description + * Prototype of the client's function to accept notification of an SSP + * hardware Rx FIFO Overrun. The calling of this function occurs + * in an exception case. An Rx FIFO Overrun can occur if the client + * does not service the Rx FIFO quickly enough and more Rx data arrives. + * The data lost is not recoverable. + * + * + * + * This function is registered through the + * SSP I/O Access Library initialization function @ref icp_SspAccInit(). + * + * @context + * This function is called in interrupt context. + * @assumptions + * None. + * @sideEffects + * None. + * + * @param + * None. + * @return + * void. + * @pre + * None. + * @post + * None. + * @note + * None. + * @see + * @ref icp_SspAccInit() \n + * @ref icp_SspAccRxFifoOverrunCheck() + */ +typedef void (*icp_sspacc_rx_fifo_overrun_handler_t)(void); + +/** + * @ingroup icp_SspAcc + * SSP Rx FIFO high threshold hit or above handler. + * @description + * Prototype of the client's function to accept notification of an SSP + * hardware Rx FIFO high threshold hit or above. The calling of this + * function occurs during normal operation and indicates that the user + * configured amount of data has been received by the SSP hardware, and + * is available for the client. When this callback is called by the SSP + * I/O Acc Lib, the client will typically call + * @ref icp_SspAccFifoDataReceive() to receive the data. This function + * is registered through the SSP I/O Access Library initialization + * function @ref icp_SspAccInit() or @ref icp_SspAccRxFifoIntEnable() . + * + * @context + * This function is called in interrupt context. + * @assumptions + * None. + * @sideEffects + * None. + * + * @param + * None. + * @return + * void. + * @pre + * None. + * @post + * None. + * @note + * None. + * @see + * @ref icp_SspAccInit() \n + * @ref icp_SspAccRxFifoIntEnable() \n + * @ref icp_SspAccRxFifoIntDisable() + */ +typedef void (*icp_sspacc_rx_fifo_threshold_handler_t)(void); + +/** + * @ingroup icp_SspAcc + * SSP Tx FIFO low threshold hit or below handler. + * @description + * Prototype of the client's function to accept notification of an SSP + * hardware Tx FIFO low threshold hit or below. + * The calling of this function occurs during normal operation and + * indicates that the user configured amount of data to be transmitted + * is not available to the SSP hardware. When this callback is called + * by the SSP I/O Acc Lib, the client will typically call + * @ref icp_SspAccFifoDataSubmit() to make more data available for + * the SSP hardware to transmit. This function is registered through + * the SSP I/O Access Library initialization function + * @ref icp_SspAccInit() or @ref icp_SspAccTxFifoIntEnable() . + * + * @context + * This function is called in interrupt context. + * @assumptions + * None. + * @sideEffects + * None. + * + * @param + * None. + * @return + * void. + * @pre + * None. + * @post + * None. + * @note + * None. + * @see + * @ref icp_SspAccInit() \n + * @ref icp_SspAccTxFifoIntEnable() \n + * @ref icp_SspAccTxFifoIntDisable() \n + * @ref icp_SspAccFifoDataSubmit() + */ +typedef void (*icp_sspacc_tx_fifo_threshold_handler_t)(void); + + +/* ---------------------------------------------------------------------------- + * Structure definitions + * ---------------------------------------------------------------------------- + */ +/** + * @ingroup icp_SspAcc + * SSP initialization structure. + * + * @purpose + * This structure contains all the variables required to initialize the SSP + * serial port hardware. Structure to be filled and used for calling + * initialization. + * + * @see + * @ref icp_SspAccInit() + */ +typedef struct +{ + icp_sspacc_frame_format_t frameFormatSelected; + /**<Select between SPI, SSP and Microwire. */ + icp_sspacc_data_size_t dataSizeSelected; + /**<Select between 4 and 16. */ + icp_sspacc_clk_source_t clkSourceSelected; + /**<Select clock source to be on-chip or external. */ + icp_sspacc_fifo_threshold_t txFIFOThresholdSelected; + /**<Select Tx FIFO threshold between 1 to 16. */ + icp_sspacc_fifo_threshold_t rxFIFOThresholdSelected; + /**<Select Rx FIFO threshold between 1 to 16. */ + icp_boolean_t rxFIFOIntrEnable; + /**<Enable/disable Rx FIFO threshold interrupt. If disabled, + the client will have to use the polling function + RxFIFOExceedThresholdCheck. */ + icp_boolean_t txFIFOIntrEnable; + /**<Enable/disable Tx FIFO threshold interrupt. If disabled, + the client will have to use the polling function + TxFIFOExceedThresholdCheck. */ + icp_sspacc_rx_fifo_threshold_handler_t rxFIFOThsldHdlr; + /**<Pointer to function to handle a Rx FIFO interrupt. */ + icp_sspacc_tx_fifo_threshold_handler_t txFIFOThsldHdlr; + /**<Pointer to function to handle a Tx FIFO interrupt. */ + icp_sspacc_rx_fifo_overrun_handler_t rxFIFOOverrunHdlr; + /**<Pointer to function to handle a Rx FIFO overrun interrupt. */ + icp_boolean_t loopbackEnable; + /**<Select operation mode to be normal or loopback mode. */ + icp_sspacc_spi_sclk_phase_t spiSclkPhaseSelected; + /**<Select SPI SCLK phase to start with one inactive cycle and end with 1/2 + inactive cycle or start with 1/2 inactive cycle and end with one + inactive cycle. (Only used in SPI format). */ + icp_sspacc_spi_sclk_polarity_t spiSclkPolaritySelected; + /**<Select SPI SCLK idle state to be low or high. + (Only used in SPI format). */ + icp_sspacc_microwire_ctl_word_t microwireCtlWordSelected; + /**<Select Microwire control format to be 8 or 16-bit. + (Only used in Microwire format). */ + uint32_t serialClkRateSelected; + /**<Select between 0 (1.8432Mbps) and 255 (7.2Kbps). The formula used is + Bit rate = 3.6864x10^6 / (2 x (SerialClkRateSelect + 1)) */ +} icp_sspacc_init_vars_t; + +/** + * @ingroup icp_SspAcc + * SSP statistic counters. + * + * @purpose + * This structure contains SSP statistic counters. + * + * @see + * @ref icp_SspAccStatsGet() + */ +typedef struct +{ + uint32_t rcvCounter; + /**<Total frames received. */ + uint32_t xmitCounter; + /**<Total frames transmitted. */ + uint32_t overflowCounter; + /**<Total occurrences of overflow. */ +} icp_sspacc_stats_counters_t; + + +/* ---------------------------------------------------------------------------- + * Interface Definition + * --------------------------------------------------------------------------- + */ + + + /** + * @ingroup icp_SspAcc + * Sets the interrupt number of SSP unit hardware. + * + * @description + * This API will set the interrupt number of the SSP unit hardware. + * + * @context + * Calling function thread. + * @assumptions + * None + * @sideEffects + * None + * @blocking + * Yes + * @reentrant + * No + * @param + * unsigned int [in] interruptNumber - the interrupt number to used for the + * SSP unit. + * + * @retval + * ICP_STATUS_SUCCESS Successfully set the interrupt number. + * @retval + * ICP_STATUS_FAIL Failed to set the interrupt number, as SSP is already initialized. + * + * @pre + * SSP must be uninitialized when this function is called. + * @post + * none + * @note + * The interrupt number must be set before SSP is initialized. This + * function does not bind the interrupt. + * @see + * @ref icp_SspAcc_Init() + */ +icp_status_t +icp_SspAccInterruptSet ( + unsigned int interruptNumber); + + +/** + * @ingroup icp_SspAcc + * Sets the physical address of SSP unit hardware. + * + * @description + * This API will set the physical address of the SSP unit hardware. + * + * @context + * Calling function thread. + * @assumptions + * None + * @sideEffects + * None + * @blocking + * Yes + * @reentrant + * No + * @param + * uint32_t [in] address - the physical address of the SSP unit hardare. + * + * @retval + * ICP_STATUS_SUCCESS Successfully set the physical address. + * @retval + * ICP_STATUS_FAIL Failed to set the physical address, as SSP is already initialized. + * + * @pre + * SSP must be uninitialized when this function is called. + * @post + * none + * @note + * The physical address must be set before SSP is initialized. + * @see + * @ref icp_SspAcc_Init() + */ +icp_status_t +icp_SspAccPhysicalAddressSet ( + uint32_t address); + + +/** + * @ingroup icp_SspAcc + * Initializes the SSP Access module. + * + * @description + * This API will initialize the SSP Serial Port hardware to the user specified + * configuration. Then it will enable the SSP Serial Port. + * + * @context + * Calling function thread. + * @assumptions + * None + * @sideEffects + * None + * @blocking + * Yes + * @reentrant + * No + * @param + * icp_sspacc_init_vars_t [in] *initVarsSelected - struct containing required + * variables for initialization. + * + * + * + * @retval + * ICP_STATUS_SUCCESS Successfully initialize and enable the SSP serial port. + * + * @retval + * ICP_STATUS_NULL_PARAM One of or a combination of: The Parameter passed in is + * NULL, The interrupt mode is selected but RX FIFO /Tx FIFO + * or the Rx FIFO Overrun handler pointer is NULL. + * + * @retval + * ICP_STATUS_INVALID_PARAM One of or combination of: frame format is invalid, + * data size is invalid, clock source is invalid, Tx FIFO + * threshold level is invalid, Rx FIFO threshold level + * is invalid, SPI phase is invalid, SPI polarity is + * invalid, microwire control command size is invalid. + * + * @retval + * ICP_STATUS_RESOURCE One of or a combination of: Rx or Tx FIFO is not empty and + * therefore the data size change is not allowed, interrupt + * handler failed to unbind SSP interrupt, interrupt handler + * failed to bind to SSP interrupt hardware trigger. + * + * @retval + * ICP_STATUS_NOT_SUPPORTED The hardware does not support SSP. + * + * @pre + * The physical address of the SSP unit hardware needs to be set using + * the icp_SspAccPhysicalAddressSet() function before a first call to + * icp_SspAccInit(). + * @post + * none + * @note + * Once interrupt or polling mode is selected, the mode cannot be + * changed via the interrupt enable/disable function. The initialization + * function needs to be called again to change it. + * @see + * @ref icp_SspAccInit() + * @ref icp_SspAccPhysicalAddressSet() + */ +icp_status_t +icp_SspAccInit ( + icp_sspacc_init_vars_t *initVarsSelected); + +/** + * @ingroup icp_SspAcc + * Un-initializes the SSP Serial Port Access component. + * + * @description + * This API will disable the SSP Serial Port hardware. The client can call + * @ref icp_SspAccInit() again if they wish to enable SSP. + * + * @context + * Calling function thread. + * @assumptions + * None. + * @sideEffects + * None. + * @blocking + * Yes. + * @reentrant + * No. + * @param + * None. + * + * @retval + * ICP_STATUS_SUCCESS Successfully uninitialzed the SSP component. + * @retval + * ICP_STATUS_FAIL Interrupt handler failed to unbind SSP interrupt. + * + * @pre + * SSP needs to be initialized. + * @post + * None. + * @note + * None. + * @see + * @ref icp_SspAccInit() + * + */ +icp_status_t +icp_SspAccUninit ( + void); + +/** + * @ingroup icp_SspAcc + * Inserts data into the SSP Serial Port's FIFO. + * + * @description + * This API will insert the amount of data specified by "amtOfData" from buffer + * pointed to by "data" into the FIFO to be transmitted by the hardware. + * + * @context + * Calling function thread. + * @assumptions + * None. + * @sideEffects + * None. + * @blocking + * Yes. + * @reentrant + * No. + * + * @param + * uint16_t [in] *data - pointer to the location to transmit the data from. + * @param + * uint32_t [in] amtOfData - number of data to be transmitted. + * + * @retval + * ICP_STATUS_SUCCESS Data inserted successfully into FIFO. + * @retval + * ICP_STATUS_FAIL FIFO insufficient space. + * @retval + * ICP_STATUS_NULL_PARAM Data pointer passed by client is NULL. + * @retval + * ICP_STATUS_RESOURCE SSP not initialized. SSP init needs to be called. + * + * @pre + * SSP needs to be initialized. + * @post + * None. + * @note + * None. + * @see + * @ref icp_SspAccFifoDataReceive() + */ +icp_status_t +icp_SspAccFifoDataSubmit ( + uint16_t *data, + uint32_t amtOfData); + +/** + * @ingroup icp_SspAcc + * Extracts data from the SSP Serial Port's FIFO. + * + * @description + * This API will extract the amount of data specified by "amtOfData" from the + * FIFO already received by the hardware into the buffer pointed to by "data". + * @context + * Calling function thread. + * @assumptions + * None. + * @sideEffects + * None. + * @blocking + * Yes. + * @reentrant + * No. + * @param + * uint16_t [in] *data - pointer to the location to receive the data into. + * @param + * uint32_t [in] amtOfData - number of data to be received. + * + * + * @retval + * ICP_STATUS_SUCCESS Data extracted successfully from FIFO. + * @retval + * ICP_STATUS_FAIL FIFO has no data. + * @retval + * ICP_STATUS_NULL_PARAM Data pointer passed by client is NULL. + * @retval + * ICP_STATUS_RESOURCE SSP not initialized. SSP init needs to be called. + * + * @pre + * SSP needs to be initialized. + * @post + * None. + * @note + * None. + * @see + * none. + */ +icp_status_t +icp_SspAccFifoDataReceive ( + uint16_t *data, + uint32_t amtOfData); + + +/** + * Polling Functions + */ + +/** + * @ingroup icp_SspAcc + * Checks if the Tx FIFO is above or below the low threshold. + * + * @description + * This API will return whether the Tx FIFO is above or below the low threshold. + * + * @context + * Calling function thread. + * @assumptions + * None. + * @sideEffects + * None. + * @blocking + * Yes. + * @reentrant + * No. + * @param + * None. + * + * @retval + * ICP_STATUS_SUCCESS Tx FIFO is hit or below the low threshold. + * @retval + * ICP_STATUS_FAIL Tx FIFO is above the low threshold. + * @retval + * ICP_STATUS_RESOURCE SSP not initialized. SSP init needs to be called. + * + * @pre + * SSP needs to be initialized. + * @post + * None. + * @note + * None. + * @see + * None. + */ +icp_status_t +icp_SspAccTxFifoHitLowThresholdCheck ( + void); + +/** + * @ingroup icp_SspAcc + * Checks if the Rx FIFO is above or below the high threshold. + * + * @description + * This API will return whether the Rx FIFO is currently above or below the + * high threshold. + * @context + * Calling function thread. + * @assumptions + * None. + * @sideEffects + * None. + * @blocking + * Yes. + * @reentrant + * No. + * @param + * None. + * + * @retval + * ICP_STATUS_SUCCESS Rx FIFO is hit or above the high threshold. + * @retval + * ICP_STATUS_FAIL Rx FIFO is below the high threshold. + * @retval + * ICP_STATUS_RESOURCE SSP not initialized. SSP init needs to be called. + * + * @pre + * SSP needs to be initialized. + * @post + * None. + * @note + * None. + * @see + * None. + */ +icp_status_t +icp_SspAccRxFifoHitHighThresholdCheck ( + void); + + +/** + * Configuration functions + * + * NOTE: These configurations are not required to be called once init is called + * unless configurations need to be changed on the fly. + */ + +/** + * @ingroup icp_SspAcc + * Enables/disables the SSP Serial Port hardware. + * + * @description + * This API will enable/disable the SSP Serial Port hardware. + * + * @context + * Calling function thread. + * @assumptions + * None. + * @sideEffects + * None. + * @blocking + * Yes. + * @reentrant + * No. + * @param + * icp_sspacc_port_status_t [in] portStatusSelected - Set the SSP port to + * enable or disable. + * + * + * @retval + * ICP_STATUS_SUCCESS Port status set with valid enum value. + * @retval + * ICP_STATUS_INVALID_PARAM Invalid enum value. + * @retval + * ICP_STATUS_RESOURCE SSP not initialized. SSP init needs to be called. + * + * @pre + * SSP needs to be initialized. + * @post + * None. + * @note + * This function is called by @ref icp_SspAccInit() to enable the + * SSP after setting up the configurations and by @ref icp_SspAccUninit() + * to disable the SSP. + * @see + * None. + */ +icp_status_t +icp_SspAccSspPortStatusSet ( + icp_sspacc_port_status_t portStatusSelected); + +/** + * @ingroup icp_SspAcc + * Sets the frame format for the SSP Serial Port hardware. + * + * @description + * This API will set the format for the transfers via user input. + * + * @context + * Calling function thread. + * @assumptions + * None. + * @sideEffects + * None. + * @blocking + * Yes. + * @reentrant + * No. + * @param + * icp_sspacc_frame_format_t [in] frameFormatSelected - The frame format of + * SPI, SSP or Microwire can be selected as the format. + * + * + * @retval + * ICP_STATUS_SUCCESS Frame format set with valid enum value. + * @retval + * ICP_STATUS_INVALID_PARAM Invalid frame format value. + * @retval + * ICP_STATUS_RESOURCE SSP not initialized. SSP init needs to be called. + * + * @pre + * SSP needs to be initialized. + * @post + * None. + * @note + * The SSP hardware will be disabled to clear the FIFOs. Then its + * previous state (enabled/disabled) will be restored after changing + * the format. + * @see + * None. + */ +icp_status_t +icp_SspAccFrameFormatSelect ( + icp_sspacc_frame_format_t frameFormatSelected); + +/** + * @ingroup icp_SspAcc + * Sets the data size for transfers. + * + * @description + * This API will set the data size for the transfers via user input. It will + * disallow the change of the data size if either of the Rx/Tx FIFO is not + * empty to prevent data loss. + + * @context + * Calling function thread. + * @assumptions + * None. + * @sideEffects + * None. + * @blocking + * Yes. + * @reentrant + * No. + * @param + * icp_sspacc_data_size_t [in] dataSizeSelected - The data size between 4 + * and 16 that can be selected for data transfers. + * + * @retval + * ICP_STATUS_SUCCESS Data size set with valid enum value. + * @retval + * ICP_STATUS_INVALID_PARAM Invalid enum value. + * @retval + * ICP_STATUS_RESOURCE Rx or Tx FIFO not empty, so data size change is not + * allowed or SSP not initialized - SSP init needs to be called. + * + * @pre + * SSP needs to be initialized. + * @post + * None. + * @note + * The SSP port will be disabled if the FIFOs are found to be empty. + * If data is received into the FIFO between the check and disabling + * of the SSP (which clears the FIFOs), it might be lost. + * @note + * The FIFOs can be cleared by disabling the SSP Port if necessary to + * force the data size change. + * @see + * None. + */ +icp_status_t +icp_SspAccDataSizeSelect ( + icp_sspacc_data_size_t dataSizeSelected); + +/** + * @ingroup icp_SspAcc + * Sets the clock source of the SSP Serial Port hardware + * + * @description + * This API will set the clock source for data transfer. + * @context + * Calling function thread. + * @assumptions + * None. + * @sideEffects + * None. + * @blocking + * Yes. + * @reentrant + * No. + * @param + * icp_sspacc_clk_source_t [in] clkSourceSelected - The clock source from + * either external source on on-chip can be selected as the source. + * + * @retval + * ICP_STATUS_SUCCESS Clock source set with valid enum value. + * @retval + * ICP_STATUS_INVALID_PARAM Invalid enum value. + * @retval + * ICP_STATUS_RESOURCE SSP not initialized. SSP init needs to be called. + * + * @pre + * SSP needs to be initialized. + * @post + * None. + * @note + * None. + * @see + * None. + */ +icp_status_t +icp_SspAccClockSourceSelect ( + icp_sspacc_clk_source_t clkSourceSelected); + +/** + * @ingroup icp_SspAcc + * Sets the on-chip Serial Clock Rate of the SSP Serial Port hardware. + * + * @description + * This API will set the serial clock rate for data transfer. + * @context + * Calling function thread. + * @assumptions + * None. + * @sideEffects + * None. + * @blocking + * Yes. + * @reentrant + * No. + * @param + * uint8_t [in] serialClockRateSelected - The serial clock rate that can + * be set is between 7.2Kbps and 1.8432Mbps. The formula used is + * Bit rate = 3.6864x10^6 / (2 x (SerialClockRateSelected + 1)). + * + * @retval + * ICP_STATUS_SUCCESS Serial clock rate configured successfully. + * @retval + * ICP_STATUS_RESOURCE SSP not initialized. SSP init needs to be called. + * + * @pre + * SSP needs to be initialized. + * @post + * None. + * @note + * None. + * @see + * None. + */ +icp_status_t +icp_SspAccSerialClockRateConfigure ( + uint8_t serialClockRateSelected); + +/** + * @ingroup icp_SspAcc + * Enables service request interrupt whenever the Rx FIFO hits its threshold. + * + * @description + * This API will enable the service request interrupt for the Rx FIFO. + * @context + * Calling function thread. + * @assumptions + * None. + * @sideEffects + * None. + * @blocking + * Yes. + * @reentrant + * No. + * @param + * void [in] *rxFIFOIntrHandler(uint32_t) - function pointer to the + * interrupt handler for the Rx FIFO exceeded. + * + * @retval + * ICP_STATUS_SUCCESS Rx FIFO level interrupt enabled successfully. + * @retval + * ICP_STATUS_NULL_PARAM Missing handler for Rx FIFO level + * interrupt. + * @retval + * ICP_STATUS_FAIL Poll mode is selected at init, interrupt + * cannot be enabled. Use init to enable interrupt mode. + * @retval + * ICP_STATUS_RESOURCE SSP not initialized. SSP init needs to be called. + * + * @pre + * SSP needs to be initialized. + * @post + * None. + * @note + * None. + * @see + * None. + */ +icp_status_t +icp_SspAccRxFifoIntEnable ( + icp_sspacc_rx_fifo_threshold_handler_t rxFIFOIntrHandler); + +/** + * @ingroup icp_SspAcc + * Disables service request interrupt of the Rx FIFO. + * + * @description + * This API will disable the service request interrupt of the Rx FIFO. + * @context + * Calling function thread. + * @assumptions + * None. + * @sideEffects + * None. + * @blocking + * Yes. + * @reentrant + * No. + * @param + * None. + * + * @retval + * ICP_STATUS_SUCCESS Rx FIFO Interrupt disabled successfully. + * @retval + * ICP_STATUS_RESOURCE SSP not initialized. SSP init needs to be called. + * + * @pre + * SSP needs to be initialized. + * @post + * None. + * @note + * None. + * @see + * None. + */ +icp_status_t +icp_SspAccRxFifoIntDisable ( + void); + +/** + * @ingroup icp_SspAcc + * Enables service request interrupt of the Tx FIFO. + * + * @description + * This API will enable the service request interrupt of the Tx FIFO. + * @context + * Calling function thread. + * @assumptions + * None. + * @sideEffects + * None. + * @blocking + * Yes. + * @reentrant + * No. + * @param + * void [in] *txFIFOIntrHandler(uint32_t) - function pointer to the + * interrupt handler for the Tx FIFO exceeded. + * + * + * + * @retval + * ICP_STATUS_SUCCESS Tx FIFO level interrupt enabled successfully. + * @retval + * ICP_STATUS_NULL_PARAM Missing handler for Tx FIFO level + * interrupt. + * @retval + * ICP_STATUS_FAIL Poll mode is selected at init, interrupt + * not allowed to be enabled. Use init to enable interrupt mode. + * @retval + * ICP_STATUS_RESOURCE SSP not initialized. SSP init needs to be called. + * + * @pre + * SSP needs to be initialized. + * @post + * None. + * @note + * None. + * @see + * None. + */ +icp_status_t +icp_SspAccTxFifoIntEnable ( + icp_sspacc_tx_fifo_threshold_handler_t txFIFOIntrHandler); + +/** + * @ingroup icp_SspAcc + * Disables service request interrupt of the Tx FIFO. + * + * @description + * This API will disable the service request interrupt of the Tx FIFO. + * @context + * Calling function thread. + * @assumptions + * None. + * @sideEffects + * None. + * @blocking + * Yes. + * @reentrant + * No. + * @param + * None. + * + * @retval + * ICP_STATUS_SUCCESS Tx FIFO Interrupt disabled successfully. + * @retval + * ICP_STATUS_RESOURCE SSP not initialized. SSP init needs to be called. + * + * @pre + * SSP needs to be initialized. + * @post + * None. + * @note + * None. + * @see + * None. + */ +icp_status_t +icp_SspAccTxFifoIntDisable ( + void); + +/** + * @ingroup icp_SspAcc + * Enables/disables the loopback mode. + * + * @description + * This API will set the mode of operation to either loopback or normal mode + * according to the user input. + * + * @context + * Calling function thread. + * @assumptions + * None. + * @sideEffects + * None. + * @blocking + * Yes. + * @reentrant + * No. + * @param + * icp_boolean_t [in] loopbackEnable - True to enable and false to disable. + * + * + * @retval + * ICP_STATUS_SUCCESS Loopback enabled successfully. + * @retval + * ICP_STATUS_RESOURCE SSP not initialized. SSP init needs to be called. + * + * @pre + * SSP needs to be initialized. + * @post + * None. + * @note + * None. + * @see + * None. + */ +icp_status_t +icp_SspAccLoopbackEnable ( + icp_boolean_t loopbackEnable); + +/** + * @ingroup icp_SspAcc + * Sets the SPI SCLK Polarity to Low or High. + * + * @description + * This API is only used for the SPI frame format and will set the SPI SCLK + * polarity to either low or high. + * @context + * Calling function thread. + * @assumptions + * None. + * @sideEffects + * None. + * @blocking + * Yes. + * @reentrant + * No. + * @param + * icp_sspacc_spi_sclk_polarity_t [in] spiSclkPolaritySelected - SPI SCLK + * polarity that can be selected to either high or low. + * + * + * @retval + * ICP_STATUS_SUCCESS SPI SCLK polarity set with valid enum value. + * @retval + * ICP_STATUS_INVALID_PARAM Invalid SPI polarity value. + * @retval + * ICP_STATUS_RESOURCE SSP not initialized. SSP init needs to be called. + * + * @pre + * SSP needs to be initialized. + * @post + * None. + * @note + * None. + * @see + * None. + */ +icp_status_t +icp_SspAccSpiSclkPolaritySet ( + icp_sspacc_spi_sclk_polarity_t spiSclkPolaritySelected); + +/** + * @ingroup icp_SspAcc + * Sets the SPI SCLK Phase. + * + * @description + * This API is only used for the SPI frame format and will set the SPI SCLK + * phase according to user input. + * @context + * Calling function thread. + * @assumptions + * None. + * @sideEffects + * None. + * @blocking + * Yes. + * @reentrant + * No. + * @param + * icp_sspacc_spi_sclk_phase_t [in] spiSclkPhaseSelected - Either: + * the SCLK is inactive one cycle at the start of a frame and 1/2 + * cycle at the end of a frame, OR + * the SCLK is inactive 1/2 cycle at the start of a frame and one + * cycle at the end of a frame. + * + * @retval + * ICP_STATUS_SUCCESS SPI SCLK phase set with valid enum value. + * @retval + * ICP_STATUS_INVALID_PARAM Invalid SPI phase value. + * @retval + * ICP_STATUS_RESOURCE SSP not initialized. SSP init needs to be called. + * + * @pre + * SSP needs to be initialized. + * @post + * None. + * @note + * None. + * @see + * None. + */ +icp_status_t +icp_SspAccSpiSclkPhaseSet ( + icp_sspacc_spi_sclk_phase_t spiSclkPhaseSelected); + +/** + * @ingroup icp_SspAcc + * Sets the Microwire control word to 8 or 16 bit format. + * + * @description + * This API is only used for the Microwire frame format and will set the + * control word to 8 or 16 bit format. + * @context + * Calling function thread. + * @assumptions + * None. + * @sideEffects + * None. + * @blocking + * Yes. + * @reentrant + * No. + * @param + * icp_sspacc_microwire_ctl_word_t [in] microwireCtlWordSelected - Microwire + * control word format: can be either 8 or 16 bit format. + * + * + * @retval + * ICP_STATUS_SUCCESS Microwire Control Word set with valid enum value. + * @retval + * ICP_STATUS_INVALID_PARAM Invalid enum value. + * @retval + * ICP_STATUS_RESOURCE Tx FIFO not empty, data size change is not allowed, Or + * SSP not initialized. SSP init needs to be called. + * + * @pre + * SSP needs to be initialized. + * @post + * None. + * @note + * None. + * @see + * None. + */ +icp_status_t +icp_SspAccMicrowireControlWordSet ( + icp_sspacc_microwire_ctl_word_t microwireCtlWordSelected); + +/** + * @ingroup icp_SspAcc + * Sets the Tx FIFO Low Threshold. + * + * @description + * This API will set the Tx FIFO low threshold, when the service request + * interrupt is enabled. + * @context + * Calling function thread. + * @assumptions + * None. + * @sideEffects + * None. + * @blocking + * Yes. + * @reentrant + * No. + * @param + * icp_sspacc_fifo_threshold_t [in] txFIFOThresholdSelected - The Tx FIFO low + * threshold. + * + * @retval + * ICP_STATUS_SUCCESS Tx FIFO Threshold set with valid enum value. + * @retval + * ICP_STATUS_INVALID_PARAM Invalid enum value. + * @retval + * ICP_STATUS_RESOURCE SSP not initialized. SSP init needs to be called. + * + * @pre + * SSP needs to be initialized. + * @post + * None. + * @note + * None. + * @see + * None. + */ +icp_status_t +icp_SspAccTxFifoThresholdSet ( + icp_sspacc_fifo_threshold_t txFIFOThresholdSelected); + +/** + * @ingroup icp_SspAcc + * Sets the Rx FIFO Threshold. + * + * @description + * This API will set the Rx FIFO high threshold, when the service request + * interrupt is enabled. + * @context + * Calling function thread. + * @assumptions + * None. + * @sideEffects + * None. + * @blocking + * Yes. + * @reentrant + * No. + * @param + * icp_sspacc_fifo_threshold_t [in] rxFIFOThresholdSelected - The Rx FIFO high + * threshold. + * + * @retval + * ICP_STATUS_SUCCESS Rx FIFO Threshold set with valid enum value. + * @retval + * ICP_STATUS_INVALID_PARAM Invalid enum value. + * @retval + * ICP_STATUS_RESOURCE SSP not initialized. SSP init needs to be called. + * + * @pre + * SSP needs to be initialized. + * @post + * None. + * @note + * None. + * @see + * None. + */ +icp_status_t +icp_SspAccRxFifoThresholdSet ( + icp_sspacc_fifo_threshold_t rxFIFOThresholdSelected); + + +/** + * Debug functions + */ + +/** + * @ingroup icp_SspAcc + * Returns the SSP Statistics through the pointer passed in. + * + * @description + * This API will return the statistics counters of the SSP transfers. + * @context + * Calling function thread. + * @assumptions + * None. + * @sideEffects + * None. + * @blocking + * Yes. + * @reentrant + * No. + * @param + * icp_sspacc_StatsCounters [in] *sspStats - SSP statistics counter will + * be read and written to the location pointed by this pointer. + * + * @retval + * ICP_STATUS_SUCCESS Stats obtained into the pointer provided successfully. + * @retval + * ICP_STATUS_NULL_PARAM Client provided pointer is NULL + * + * @pre + * None. + * @post + * None. + * @note + * None. + * @see + * None. + */ +icp_status_t +icp_SspAccStatsGet ( + icp_sspacc_stats_counters_t *sspStats); + +/** + * @ingroup icp_SspAcc + * Resets the SSP Statistics. + * + * @description + * This API will reset the SSP statistics counters. + * @context + * Calling function thread. + * @assumptions + * None. + * @sideEffects + * None. + * @blocking + * Yes. + * @reentrant + * No. + * @param + * None. + * @retval + * None. + * @pre + * None. + * @post + * None. + * @note + * None. + * @see + * None. + */ +void +icp_SspAccStatsReset ( + void); + +/** + * @ingroup icp_SspAcc + * Displays SSP status registers and statistics counters. + * + * @description + * This API will display the status registers of the SSP and the statistics + * counters. + * @context + * Calling function thread. + * @assumptions + * None. + * @sideEffects + * None. + * @blocking + * Yes. + * @reentrant + * No. + * @param + * None. + * + * + * @retval + * ICP_STATUS_SUCCESS SSP show called successfully. + * @retval + * ICP_STATUS_RESOURCE SSP not initialized. SSP init needs to be called. + * + * @pre + * SSP needs to be initialized. + * @post + * None. + * @note + * None. + * @see + * None. + */ +icp_status_t +icp_SspAccShow ( + void); + +/** + * @ingroup icp_SspAcc + * Determines the state of the SSP serial port hardware. + * + * @description + * This API will return whether the SSP serial port hardware is idle or busy. + * + * @context + * Calling function thread. + * @assumptions + * None. + * @sideEffects + * None. + * @blocking + * Yes. + * @reentrant + * No. + * @param + * None. + * @retval + * ICP_STATUS_SUCCESS SSP is idle. + * @retval + * ICP_STATUS_FAIL SSP is busy. + * @retval + * ICP_STATUS_RESOURCE SSP not initialized. SSP init needs to be called. + * + * @pre + * SSP needs to be initialized. + * @post + * None. + * @note + * None. + * @see + * None. + */ +icp_status_t +icp_SspAccSspIdleCheck ( + void); + +/** + * @ingroup icp_SspAcc + * Obtains the Tx FIFO's level. + * + * @description + * This API will return the level of the Tx FIFO. + * @context + * Calling function thread. + * @assumptions + * None. + * @sideEffects + * None. + * @blocking + * Yes. + * @reentrant + * No. + * @param + * None. + * + * @retval + * uint8_t 0..16. + * + * @pre + * None. + * @post + * None. + * @note + * A zero return value may be an indication that SSP is not initialized. + * @see + * None. + */ +uint8_t +icp_SspAccTxFifoLevelGet ( + void); + +/** + * @ingroup icp_SspAcc + * Obtains the Rx FIFO's level. + * + * @description + * This API will return the level of the Rx FIFO. + * @context + * Calling function thread. + * @assumptions + * None. + * @sideEffects + * None. + * @blocking + * Yes. + * @reentrant + * No. + * @param + * None. + * + * @retval + * uint8_t 0..16. + * + * @pre + * None. + * @post + * None. + * @note + * A zero return value may be an indication that SSP is not initialized. + * @see + * None. + */ +uint8_t +icp_SspAccRxFifoLevelGet ( + void); + +/** + * @ingroup icp_SspAcc + * Checks if the Rx FIFO has overrun. + * + * @description + * This API will return whether the Rx FIFO has overrun its 16 FIFOs. + * + * @context + * Calling function thread. + * @assumptions + * None. + * @sideEffects + * None. + * @blocking + * Yes. + * @reentrant + * No. + * @param + * None. + * + * @retval + * ICP_STATUS_SUCCESS Rx FIFO did not overrun. + * @retval + * ICP_STATUS_FAIL Rx FIFO overrun occurred. + * @retval + * ICP_STATUS_RESOURCE SSP not initialized. SSP init needs to be called. + * + * @pre + * SSP needs to be initialized. + * @post + * None. + * @note + * None. + * @see + * None. + */ +icp_status_t +icp_SspAccRxFifoOverrunCheck ( + void); + +#endif /* ICPSSPACC_H */ diff --git a/Acceleration/include/hss/icp_tdmsetupdrv.h b/Acceleration/include/hss/icp_tdmsetupdrv.h new file mode 100644 index 0000000..00fafc2 --- /dev/null +++ b/Acceleration/include/hss/icp_tdmsetupdrv.h @@ -0,0 +1,277 @@ +/****************************************************************************** + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + *****************************************************************************/ + +/* + ***************************************************************************** + * Doxygen group definitions + ****************************************************************************/ + +/** + ******************************************************************************* + * @defgroup icp_tdmsetupdrv TDM Setup Driver API + * Public API for the TDM Setup Driver. + * + * @purpose + * The TDM Setup Driver is a Linux Character device + * driver. It presents a Linux user space interface to the client. + * + * This API defines an ioctl interface to the TDM Setup Driver. The + * client can use ioctl in order to either initialize or uninitialize + * the driver via /dev/tdm-setup once the character device file has + * been successfully opened. + * Initialization does the following: + * + * - Performs PCI enumeration and configuration for the TDM I/O Unit + * - Initializes the communication infrastructure between the TDM unit + * and the IA. + * - Downloads the TDM I/O Unit firmware. + * - Initializes the HSS I/O Access Library. + * - Initializes the SSP I/O Access Library. + * - Binds the interrupts for the TDM I/O unit. + * + * The driver implements the following character driver methods that + * can be used in user space by the client to access the driver: + * + * - open() - Opens the device driver. + * + * - release() - De-allocates all resources. + * + * - ioctl() - Used by the client to pass commands to the driver. + * + * Note: The read() and write() device driver methods are not + * implemented for this driver as it has no data path and + * all control path operation are performed using IOCTL calls. + * + * + * The TDM Setup Driver has one command line + * parameter called autoinit which can be set when the driver is being + * loaded. By default this parameter is set to 1. In this scenario + * the TDM System will automatically be initialized when the driver is + * inserted (insmod) and uninitialized when the driver is removed (rmmod). + * In this scenario the client has no need to use the IOCTL calls. + * If autoinit is set to 0 the client has to explicitly initialize the TDM + * System after the driver is inserted (insmod) using the + * ICP_TDMSETUPDRV_INIT ioctl and it has to explicitly uninitialize + * the TDM System before the driver can be removed (rmmod) using + * the ICP_TDMSETUPDRV_UNINIT ioctl. + * + * NOTE:\n + * The Voice Driver, Data Driver and Analog FXO/FXS Device Driver depend + * on this driver being installed and initialized to work properly. + * Consequently the TDM Setup driver should be installed + * first, before any of these drivers. + * + ******************************************************************************/ + +/** + ******************************************************************************* + * @defgroup icp_tdm_io_port_handling TDM Setup Driver Port Reservation APIs + * TDM Setup Driver Kernel space API used by other TDM related drivers. + * + * @purpose + * The TDM Setup Driver provides a set of kernel space APIs that are + * meant for other drivers that handle the peripherals connected to + * the TDM ports. This allows the TDM Setup driver to centralize the + * knowledge of what type of peripheral is connected to which TDM port. + ******************************************************************************/ + +#ifndef ICP_TDMSETUPDRV_H_ +#define ICP_TDMSETUPDRV_H_ + + + +#define ICP_TDMSETUPDRV_IOC_MAGIC 'h' +/**< @ingroup icp_tdmsetupdrv + * Seed for ioctl commands. */ + +/* + * ioctl commands. + * + */ +#define ICP_TDMSETUPDRV_INIT _IO(ICP_TDMSETUPDRV_IOC_MAGIC, 0) +/**< @ingroup icp_tdmsetupdrv + * ioctl command to initialize the TDM System. This + * is called only if autoinit has not been set. + */ + +#define ICP_TDMSETUPDRV_UNINIT _IO(ICP_TDMSETUPDRV_IOC_MAGIC, 1) +/**< @ingroup icp_tdmsetupdrv + * ioctl command to uninitialize the TDM System. This + * is called only if autoinit has not been set. + */ + + /** + * @ingroup icp_tdm_io_port_handling + * Reserve TDM I/O Port Connectivity. + * @description + * Different types of hardware can be connected to the TDM I/O port. + * Each type of hardware is configured by a different Device Driver. + * This function caters for different drivers contending for the + * TDM I/O port connectivity. + * The first Device Driver to reserve the TDM I/O port will get it, + * successive reservation attempts will fail. This function returns the + * physical base address for the TDM I/O port and will prevent anybody + * else from getting the base address for this port until + * @ref tdm_io_port_unreserve is called. Device Drivers responsible for + * Initialization and configuration of the hardware directly connected + * to the TDM I/O Port(s) must call this function to obtain the physical + * base address of the TDM I/O port about to be used. + * @context + * Calling function thread. + * @assumptions + * None. + * @sideEffects + * None. + * @param + * port [IN] - The TDM I/O Port to reserve. + * @blocking + * No. + * @reentrant + * Yes. + * @threadSafe + * Yes. + * @retval + * Returns the base address of the port or else 0 on error. + * @pre + * The setup driver must have been successfully installed. + * @post + * None. + * @note + * None. + * @see + * @ref tdm_io_port_unreserve. + */ + +unsigned int tdm_io_port_reserve(unsigned int port); + + + /** + * @ingroup icp_tdm_io_port_handling + * Unreserve a TDM I/O port. + * @description + * Unreserves the TDM I/O Port connectivity and reset the Local + * Expansion Bus config for the TDM I/O Port. + * @context + * Calling function thread. + * @assumptions + * None. + * @sideEffects + * None. + * @param + * port [IN] - The TDM I/O Port to unreserve. + * @blocking + * No. + * @reentrant + * Yes. + * @threadSafe + * Yes. + * @retval + * Returns 0 on success or 1 on error + * @pre + * The setup driver must have been successfully installed. + * @post + * None. + * @note + * None. + * @see + * @ref tdm_io_port_reserve. + */ +unsigned int tdm_io_port_unreserve(unsigned int port); + + /** + * @ingroup icp_tdm_io_port_handling + * Get the IRQ level for a TDM I/O Port. + * @description + * Return the IRQ level of the interrupt associated with a TDM I/O port. + * @context + * Calling function thread. + * @assumptions + * None. + * @sideEffects + * None. + * @param + * port [IN] - The TDM I/O Port to request the irq level for. + * @blocking + * No. + * @reentrant + * Yes. + * @threadSafe + * Yes. + * @retval + * Returns the IRQ level on success or 0 in the case of failure + * @pre + * The setup driver must have been successfully installed. + * @post + * None. + * @note + * None. + * @see + * None. + */ +unsigned int tdm_io_port_irq_get(unsigned int port); + +typedef void (*tdm_trigger_hardirq_handler)(void); + +void tdm_register_trigger_hardirq_handler(tdm_trigger_hardirq_handler handler); + +#endif /*ICP_TDMSETUPDRV_H_*/ diff --git a/Acceleration/include/icp.h b/Acceleration/include/icp.h new file mode 100644 index 0000000..c3167c7 --- /dev/null +++ b/Acceleration/include/icp.h @@ -0,0 +1,414 @@ +/*************************************************************************** + * + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + ***************************************************************************/ + +/* + ***************************************************************************** + * Doxygen group definitions + ****************************************************************************/ + +/** + ***************************************************************************** + * @file icp.h + * + * @defgroup icp Acceleration API + * + * @description + * This is the top level API definition. It contains structures, data + * types and definitions that are common across the other interfaces. + * + *****************************************************************************/ + +/** + ***************************************************************************** + * @defgroup icp_BaseDataTypes Base Data Types + * + * @ingroup icp + * + * @description + * The base data types for the Intel Acceleration API. + * + *****************************************************************************/ + +#ifndef ICP_H +#define ICP_H + +#include "icp_osal_types.h" + +/** + ***************************************************************************** + * @ingroup icp_BaseDataTypes + * NULL definition + * + * @description + * This define is used to identify a NULL value. + * + *****************************************************************************/ +#ifndef NULL +#define NULL (0) +#endif + +#ifndef TRUE +#define TRUE (1) +/**< @ingroup icp_BaseDataTypes + * True value definition */ +#endif +#ifndef FALSE +#define FALSE (0) +/**< @ingroup icp_BaseDataTypes + * False value definition */ +#endif + +/** + ***************************************************************************** + * @ingroup icp_BaseDataTypes + * Boolean type + * + * @description + * Functions in this API use this type for Boolean variables that take + * true or false values. + * + *****************************************************************************/ +typedef enum +{ + ICP_FALSE = FALSE, /**< False value */ + ICP_TRUE = TRUE, /**< True value */ +} icp_boolean_t; + +/** + ***************************************************************************** + * @ingroup icp_BaseDataTypes + * User provided representation of the context that is returned unmodified. + * + * @description + * This type defines an opaque user context passed in by the user when + * the callback handler is registered. It is returned to the user when + * the callback function is invoked. This value is not modified or used by + * the acceleration components. It may be used to allow the application to + * associate a completion callback call with a specific instance of the + * original function call. + * @see + * + *****************************************************************************/ +typedef void * icp_user_context_t; + +/** + ***************************************************************************** + * @ingroup icp_BaseDataTypes + * User provided correlator value that is returned unmodified. + * + * @description + * This type defines an opaque value provided by the user while making + * an API function call. The value is returned to the user when the + * callback function is invoked. This value is not modified or used + * internally by the components. It may be used by the client to help + * correlate a particular instance of a function call to a particular + * callback. + * + *****************************************************************************/ +typedef void * icp_correlator_t; + +/** + ***************************************************************************** + * @ingroup icp_BaseDataTypes + * Generic handle to items in the Acceleration API + * + * @description + * This type is a handle that uniquely identifies items in the + * acceleration API. + * @note + * To mark a handle as invalid use @ref ICP_INVALID_HANDLE. + * + * + *****************************************************************************/ +typedef uint32_t icp_handle_t; + +/** + ***************************************************************************** + * @ingroup icp_BaseDataTypes + * Invalid handle + * + * @description + * This define is used to identify a handle as invalid. + * @note + * To mark a buffer handle as invalid use the + * @ref ICP_INVALID_BUFFER_HANDLE. + * + *****************************************************************************/ +#define ICP_INVALID_HANDLE ((icp_handle_t)0) + +/** + ***************************************************************************** + * @ingroup icp_BaseDataTypes + * Accelerator handle type + * + * @description + * Handle used to uniquely identify an acceleration device instance + * + * @note + * Where only a single accelerator exists on the Silicon variant, this + * field must be set to @ref ICP_ACCEL_HANDLE_DEFAULT. + * + *****************************************************************************/ +typedef void * icp_accel_handle_t; + +/** + ***************************************************************************** + * @ingroup icp_BaseDataTypes + * Default acceleration handle value + * + * @description + * Used as an acceleration handle value where only one acceleration device + * exists on silicon. + * + *****************************************************************************/ +#define ICP_ACCEL_HANDLE_DEFAULT ((icp_accel_handle_t)0) + +/** + ***************************************************************************** + * @ingroup icp_BaseDataTypes + * Handle to registered callback function + * + * @description + * This type is a handle that uniquely identifies a registered callback + * function. + * + *****************************************************************************/ +typedef icp_handle_t icp_callback_handle_t; + +/** + ***************************************************************************** + * @ingroup icp_BaseDataTypes + * Handle to registered event handler function + * + * @description + * This type is a handle that uniquely identifies a registered event + * handler function + * + *****************************************************************************/ +typedef icp_handle_t icp_event_func_handle_t; + +/** + ***************************************************************************** + * @ingroup icp_BaseDataTypes + * Buffer Handle + * + * @description + * This type uniquely identifies a buffer handle for this API. + * + * @purpose + * The intention is to present an abstraction that hides from the + * clients of the API any of the private, implementation-specific + * aspects of the buffer format used by implementations of this + * API. Functions will be provided to translate between this + * buffer format and those buffer formats used by clients + * (e.g. OS-specific buffer formats such as sk_buffs, mbufs, + * etc.), as well as functions to get key data about the buffer, + * i.e. the length, pointer to the data contained in the buffer, + * etc. The abstraction also supports the concept of buffer + * chaining. + * @note + * The buffer translation module can be used to perform conversions + * between various OS buffer formats and the icp_buffer_handle_t. + * Please refer to the buffer translation module documentation for more + * information on supported data buffer conversions. + * To define an invalid buffer handle use the + * @ref ICP_INVALID_BUFFER_HANDLE define. + * + *****************************************************************************/ +typedef uint64_t icp_buffer_handle_t; + +/** + ***************************************************************************** + * @ingroup icp_BaseDataTypes + * Invalid buffer handle + * + * @description + * This define is used to identify a buffer handle as invalid. + * + *****************************************************************************/ +#define ICP_INVALID_BUFFER_HANDLE ((icp_buffer_handle_t)0) + +/** + ***************************************************************************** + * @ingroup icp_BaseDataTypes + * Flat buffer structure containing a pointer and length member. + * + * @description + * A flat buffer structure. The data pointer, pData, is a virtual address + * however the actual data pointed to is required to be in contiguous + * physical memory. It is expected that this buffer handle will be used + * when simple, unchained buffers are needed. The icp_buffer_handle_t + * defined in icp_buffer.h describe much more fully featured buffers that + * may be used when chaining or mapping from OS specific buffers is + * required. + * + *****************************************************************************/ +typedef struct icp_flat_buffer_s +{ + uint8_t *pData; + /**< The data pointer is a virtual address, however the actual data pointed + * to is required to be in contiguous physical memory. */ + uint32_t dataLenInBytes; + /**< Data length specified in bytes*/ + void * clientBufferHandle; + /**< This is an opaque field that is not read or modified internally. An + * example usage scenario for this structure member is for the client to + * assign this to be the pointer for the start of the buffer in which the + * data resides. Subsequently it may be used to recover the start of the + * data buffer. */ +} icp_flat_buffer_t; + + +/** + ***************************************************************************** + * @ingroup icp_BaseDataTypes + * Acceleration API status value type definition + * @description + * This type definition is used for the return values used in all the + * acceleration API functions. Common values are #defined, for example + * see @ref ICP_STATUS_SUCCESS, @ref ICP_STATUS_FAIL, etc. + *****************************************************************************/ +typedef uint32_t icp_status_t; + +#define ICP_STATUS_SUCCESS (0) +/**< @ingroup icp_BaseDataTypes + * Success status value. */ +#define ICP_STATUS_FAIL (1) +/**< @ingroup icp_BaseDataTypes + * Fail status value. */ +#define ICP_STATUS_RETRY (2) +/**< @ingroup icp_BaseDataTypes + * Retry status value. */ +#define ICP_STATUS_RESOURCE (3) +/**< @ingroup icp_BaseDataTypes + * The resource that has been requested is unavailable status value. Refer + * to relevant sections of the API for specifics on what the suggested + * course of action is. */ +#define ICP_STATUS_INVALID_PARAM (4) +/**< @ingroup icp_BaseDataTypes + * Invalid parameter has been passed in status value. */ +#define ICP_STATUS_FATAL (5) +/**< @ingroup icp_BaseDataTypes + * A serious error has occurred status value. Recommended course of action + * is to shutdown and restart the component. */ +#define ICP_STATUS_UNDERFLOW (6) +/**< @ingroup icp_BaseDataTypes + * Underflow error status value - the client is under submitting data. + * This status value will be deprecated in a subsequent release of this + * interface. */ +#define ICP_STATUS_OVERFLOW (7) +/**< @ingroup icp_BaseDataTypes + * Overflow error status value - the client is over submitting data. This + * status value will be deprecated in a subsequent release of this + * interface. */ +#define ICP_STATUS_NULL_PARAM (8) +/**< @ingroup icp_BaseDataTypes + * One or more parameters is null status value. This status value will be + * deprecated in a subsequent release of this interface. */ +#define ICP_STATUS_MUTEX (9) +/**< @ingroup icp_BaseDataTypes + * Failure with a mutex operation status value. This status value will be + * deprecated in a subsequent release of this interface. */ +#define ICP_STATUS_ALREADY_REGISTERED (10) +/**< @ingroup icp_BaseDataTypes + * An attempt was made to register an item, for example a callback, with + * the same value as an existing registered value. This status value will + * be deprecated in a subsequent release of this interface. */ +#define ICP_STATUS_INVALID_HANDLE (11) +/**< @ingroup icp_BaseDataTypes + * An invalid handle was passed in status value. This status value will + * be deprecated in a subsequent release of this interface. */ +#define ICP_STATUS_NOT_SUPPORTED (12) +/**< @ingroup icp_BaseDataTypes + * Operation not supported in the current implementation status value. + * This status value will be deprecated in a subsequent release of this + * interface. */ + +/** + ***************************************************************************** + * @ingroup icp_BaseDataTypes + * Iterator type + * + * @description + * This type is used in this API, when the same function is repeatedly + * called to get values from a table or other data structure. + * + * In the first call, the iterator is set to ICP_ITERATOR_FIRST. The API + * returns an updated value for the iterator which must be passed into + * the next call until the API returns an iterator value of + * ICP_ITERATOR_LAST + * + *****************************************************************************/ +typedef uint32_t icp_iterator_t; + +#define ICP_ITERATOR_FIRST ((icp_iterator_t)0) +/**< @ingroup icp_BaseDataTypes + * Use this define to access the first element of a table or other data + * structure. */ + +#define ICP_ITERATOR_LAST ((icp_iterator_t) (-1)) +/**< @ingroup icp_BaseDataTypes + * Use this define to indicate the last iteration of a table or other data + * structure */ + +#endif /* ICP_H */ diff --git a/Acceleration/include/icp_osal_types.h b/Acceleration/include/icp_osal_types.h new file mode 100644 index 0000000..4dae7dc --- /dev/null +++ b/Acceleration/include/icp_osal_types.h @@ -0,0 +1,111 @@ +/*************************************************************************** + * + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + ***************************************************************************/ + +/* + ***************************************************************************** + * Doxygen group definitions + ****************************************************************************/ + +/** + ***************************************************************************** + * @file icp_osal_types.h + * + * @defgroup icp_OsalTypes ICP Operating System Abstraction For Type Definition + * + * @ingroup icp + * + * @description + * This is the ICP Operating System Abstraction Layer For Type + * Definitions. + * + *****************************************************************************/ + +#ifndef ICP_OSAL_TYPES_H +#define ICP_OSAL_TYPES_H + +#if defined (__linux__) && defined (__KERNEL__) + +/* Linux kernel mode */ +#include <linux/kernel.h> +#include <linux/types.h> + +#elif defined (__freebsd) && defined (_KERNEL) + +/* FreeBSD kernel mode */ +#include <sys/types.h> +#include <sys/param.h> +#include <sys/kernel.h> + +#elif defined (__linux__) || defined (__freebsd) + +/* Linux or FreeBSD, user mode */ +#include <stdio.h> +#include <stddef.h> +#include <stdint.h> + +#else +#error Unsupported operating system +#endif /* OS and mode */ + +#endif /* ICP_OSAL_TYPES_H */ + diff --git a/Acceleration/library/Kbuild b/Acceleration/library/Kbuild new file mode 100644 index 0000000..e100cd1 --- /dev/null +++ b/Acceleration/library/Kbuild @@ -0,0 +1,179 @@ +obj-m := tdm_infra.o + +ACCELERATION_DIR = $(src)/.. + +cflags_osal_includes = -I$(src)/icp_utils/OSAL/common/include \ + -I$(src)/icp_utils/OSAL/common/include/core \ + -I$(src)/icp_utils/OSAL/common/include/modules/ddk \ + -I$(src)/icp_utils/OSAL/common/include/modules/ioMem \ + -I$(src)/icp_utils/OSAL/common/os/linux/include \ + -I$(src)/icp_utils/OSAL/common/os/linux/include/core \ + -I$(src)/icp_utils/OSAL/common/os/linux/include/modules/ddk \ + -I$(src)/icp_utils/OSAL/common/os/linux/include/modules/ioMem \ + -I$(src)/icp_utils/OSAL/platforms/EP805XX/include \ + -I$(src)/icp_utils/OSAL/platforms/EP805XX/os/linux/include + +cflags_osal = -D__EP805XX__ -D__linux -D__LITTLE_ENDIAN -DIX_HW_COHERENT_MEMORY \ + -DIX_OSAL_MEM_MAP_GLUECODE -DIX_OSAL_THREAD_EXIT_GRACEFULLY \ + -DUSE_NATIVE_OS_TIMER_API -DENABLE_SPINLOCK -DENABLE_IOMEM -DENABLE_DDK \ + $(cflags_osal_includes) \ + -DIX_COMPONENT=1 -DIX_OSAL_TARGET_OS_EXT=_linux \ + -DIX_OSAL_PLATFORM_EXT=_EP805XX -DIX_COMPONENT_NAME=ix_osal + +cflags_tdm_includes = -I$(ACCELERATION_DIR)/include \ + -I$(ACCELERATION_DIR)/include/hss \ + -I$(ACCELERATION_DIR)/include/accel_infra \ + -I$(src)/icp_utils/OSAL/common/include \ + -I$(src)/icp_utils/OSAL/common/include/modules \ + -I$(src)/icp_utils/OSAL/common/include/modules/ddk \ + -I$(src)/icp_utils/OSAL/common/include/modules/bufferMgt \ + -I$(src)/icp_utils/OSAL/common/include/modules/ioMem \ + -I$(src)/icp_utils/OSAL/platforms/EP805XX/include \ + -I$(src)/icp_utils/OSAL/platforms/EP805XX/os/linux/include \ + -I$(src)/icp_utils/OSAL/common/os/linux/include/core \ + -I$(src)/icp_utils/OSAL/common/os/linux/include/modules \ + -I$(src)/icp_utils/OSAL/common/os/linux/include/modules/ddk \ + -I$(src)/icp_utils/OSAL/common/os/linux/include/modules/ioMem \ + -I$(src)/icp_utils/OSAL/common/os/linux/include/modules/bufferMgt + +cflags_tdm_dl_includes = -I$(src)/icp_telephony/tdm_infrastructure_downloader/include \ + $(cflags_tdm_includes) + +cflags_tdm_io_includes = -I$(src)/icp_telephony/tdm_io_access/include \ + $(cflags_tdm_includes) + +cflags_tdm_mh_includes = -I$(src)/icp_telephony/tdm_infrastructure_message_handler/include \ + $(cflags_tdm_includes) + +cflags_tdm_qm_includes = -I$(src)/icp_telephony/tdm_infrastructure_queue_manager/include \ + $(cflags_tdm_includes) + +cflags_tdm_base = -DENABLE_IOMEM -DTOLAPAI -D__tolapai -DIX_HW_COHERENT_MEMORY=1 + +cflags_tdm_common = $(cflags_tdm_base) -DENABLE_BUFFERMGT -DEP805XX -D__ep805xx + +cflags_tdm_dl = $(cflags_tdm_common) -DIX_PIUDL_READ_MICROCODE_FROM_FILE + +tdm_infra-objs := icp_utils/OSAL/common/os/linux/src/modules/ioMem/IxOsalOsIoMemSymbols.o \ + icp_utils/OSAL/common/os/linux/src/modules/ioMem/IxOsalOsIoMem.o \ + icp_utils/OSAL/common/os/linux/src/modules/ddk/IxOsalOsDdkIrq.o \ + icp_utils/OSAL/common/os/linux/src/modules/ddk/IxOsalOsDdkSymbols.o \ + icp_utils/OSAL/common/os/linux/src/modules/ddk/IxOsalOsDdkClk.o \ + icp_utils/OSAL/common/os/linux/src/modules/ddk/IxOsalOsDdkCacheMMU.o \ + icp_utils/OSAL/common/src/modules/ioMem/IxOsalIoMem.o \ + icp_utils/OSAL/common/os/linux/src/core/IxOsalOsTimer.o \ + icp_utils/OSAL/common/os/linux/src/core/IxOsalOsSpinLock.o \ + icp_utils/OSAL/common/os/linux/src/core/IxOsalOsMemBarrier.o \ + icp_utils/OSAL/common/os/linux/src/core/IxOsalOsAtomic.o \ + icp_utils/OSAL/common/os/linux/src/core/IxOsalOsMsgQ.o \ + icp_utils/OSAL/common/os/linux/src/core/IxOsalOsSymbols.o \ + icp_utils/OSAL/common/os/linux/src/core/IxOsalOsSemaphore.o \ + icp_utils/OSAL/common/os/linux/src/core/IxOsalOsServices.o \ + icp_utils/OSAL/common/os/linux/src/core/IxOsalOsThread.o \ + icp_utils/OSAL/common/src/core/IxOsalServices.o \ + icp_utils/OSAL/common/src/core/IxOsalTime.o \ + icp_utils/OSAL/platforms/EP805XX/os/linux/src/IxOsalOsOemSymbols.o \ + icp_utils/OSAL/platforms/EP805XX/os/linux/src/IxOsalOsOem.o \ + \ + icp_telephony/ssp_access/icp_sspacc.o \ + \ + icp_telephony/tdm_infrastructure_downloader/source/IxPiuDl.o \ + icp_telephony/tdm_infrastructure_downloader/source/IxPiuDlFwLoader.o \ + icp_telephony/tdm_infrastructure_downloader/source/IxPiuDlImageMgr.o \ + icp_telephony/tdm_infrastructure_downloader/source/IxPiuDlPiuMgr.o \ + icp_telephony/tdm_infrastructure_downloader/source/IxPiuDlPiuMgrUtils.o \ + \ + icp_telephony/tdm_io_access/icp_hssacc_address_translate.o \ + icp_telephony/tdm_io_access/icp_hssacc_channel_config.o \ + icp_telephony/tdm_io_access/icp_hssacc_channel_list.o \ + icp_telephony/tdm_io_access/icp_hssacc_common.o \ + icp_telephony/tdm_io_access/icp_hssacc_common_timeslot_allocation.o \ + icp_telephony/tdm_io_access/icp_hssacc_param_check.o \ + icp_telephony/tdm_io_access/icp_hssacc_port_config.o \ + icp_telephony/tdm_io_access/icp_hssacc_port_hdma_reg_mgr.o \ + icp_telephony/tdm_io_access/icp_hssacc_queues_config.o \ + icp_telephony/tdm_io_access/icp_hssacc_rx_datapath.o \ + icp_telephony/tdm_io_access/icp_hssacc_service.o \ + icp_telephony/tdm_io_access/icp_hssacc_timeslot_allocation.o \ + icp_telephony/tdm_io_access/icp_hssacc_tx_datapath.o \ + icp_telephony/tdm_io_access/icp_hssacc_voice_bypass.o \ + \ + icp_telephony/tdm_infrastructure_message_handler/IxPiuMh.o \ + icp_telephony/tdm_infrastructure_message_handler/IxPiuMhConfig.o \ + icp_telephony/tdm_infrastructure_message_handler/IxPiuMhDll.o \ + icp_telephony/tdm_infrastructure_message_handler/IxPiuMhReceive.o \ + icp_telephony/tdm_infrastructure_message_handler/IxPiuMhSend.o \ + icp_telephony/tdm_infrastructure_message_handler/IxPiuMhSolicitedCbMgr.o \ + icp_telephony/tdm_infrastructure_message_handler/IxPiuMhUnsolicitedCbMgr.o \ + icp_telephony/tdm_infrastructure_message_handler/linux_kernel_module.o \ + \ + icp_telephony/tdm_infrastructure_queue_manager/IxQMgr.o \ + \ + icp_telephony/ssp_access/icp_sspacc_symbols.o \ + \ + icp_telephony/ssp_access/icp_sspacc_symbols.o \ + icp_telephony/tdm_io_access/icp_hssacc_symbols.o \ + icp_telephony/tdm_infrastructure_queue_manager/IxQMgrSymbols.o \ + icp_telephony/tdm_infrastructure_downloader/source/IxPiuDlSymbols.o \ + icp_telephony/tdm_infrastructure_message_handler/IxPiuMhSymbols.o \ + +CFLAGS_IxOsalOsIoMemSymbols.o := $(cflags_osal) +CFLAGS_IxOsalOsIoMem.o := $(cflags_osal) +CFLAGS_IxOsalOsDdkIrq.o := $(cflags_osal) +CFLAGS_IxOsalOsDdkSymbols.o := $(cflags_osal) +CFLAGS_IxOsalOsDdkClk.o := $(cflags_osal) +CFLAGS_IxOsalOsDdkCacheMMU.o := $(cflags_osal) +CFLAGS_IxOsalIoMem.o := $(cflags_osal) +CFLAGS_IxOsalOsTimer.o := $(cflags_osal) +CFLAGS_IxOsalOsSpinLock.o := $(cflags_osal) +CFLAGS_IxOsalOsMemBarrier.o := $(cflags_osal) +CFLAGS_IxOsalOsAtomic.o := $(cflags_osal) +CFLAGS_IxOsalOsMsgQ.o := $(cflags_osal) +CFLAGS_IxOsalOsSymbols.o := $(cflags_osal) +CFLAGS_IxOsalOsSemaphore.o := $(cflags_osal) +CFLAGS_IxOsalOsServices.o := $(cflags_osal) +CFLAGS_IxOsalOsThread.o := $(cflags_osal) +CFLAGS_IxOsalServices.o := $(cflags_osal) +CFLAGS_IxOsalTime.o := $(cflags_osal) +CFLAGS_IxOsalOsOemSymbols.o := $(cflags_osal) +CFLAGS_IxOsalOsOem.o := $(cflags_osal) + +CFLAGS_icp_sspacc.o := $(cflags_tdm_includes) $(cflags_tdm_base) + +CFLAGS_IxPiuDl.o := $(cflags_tdm_dl_includes) $(cflags_tdm_dl) +CFLAGS_IxPiuDlFwLoader.o := $(cflags_tdm_dl_includes) $(cflags_tdm_dl) +CFLAGS_IxPiuDlImageMgr.o := $(cflags_tdm_dl_includes) $(cflags_tdm_dl) +CFLAGS_IxPiuDlPiuMgr.o := $(cflags_tdm_dl_includes) $(cflags_tdm_dl) +CFLAGS_IxPiuDlPiuMgrUtils.o := $(cflags_tdm_dl_includes) $(cflags_tdm_dl) + +CFLAGS_icp_hssacc_address_translate.o := $(cflags_tdm_io_includes) $(cflags_tdm_common) +CFLAGS_icp_hssacc_channel_config.o := $(cflags_tdm_io_includes) $(cflags_tdm_common) +CFLAGS_icp_hssacc_channel_list.o := $(cflags_tdm_io_includes) $(cflags_tdm_common) +CFLAGS_icp_hssacc_common.o := $(cflags_tdm_io_includes) $(cflags_tdm_common) +CFLAGS_icp_hssacc_common_timeslot_allocation.o := $(cflags_tdm_io_includes) $(cflags_tdm_common) +CFLAGS_icp_hssacc_param_check.o := $(cflags_tdm_io_includes) $(cflags_tdm_common) +CFLAGS_icp_hssacc_port_config.o := $(cflags_tdm_io_includes) $(cflags_tdm_common) +CFLAGS_icp_hssacc_port_hdma_reg_mgr.o := $(cflags_tdm_io_includes) $(cflags_tdm_common) +CFLAGS_icp_hssacc_queues_config.o := $(cflags_tdm_io_includes) $(cflags_tdm_common) +CFLAGS_icp_hssacc_rx_datapath.o := $(cflags_tdm_io_includes) $(cflags_tdm_common) +CFLAGS_icp_hssacc_service.o := $(cflags_tdm_io_includes) $(cflags_tdm_common) +CFLAGS_icp_hssacc_timeslot_allocation.o := $(cflags_tdm_io_includes) $(cflags_tdm_common) +CFLAGS_icp_hssacc_tx_datapath.o := $(cflags_tdm_io_includes) $(cflags_tdm_common) +CFLAGS_icp_hssacc_voice_bypass.o := $(cflags_tdm_io_includes) $(cflags_tdm_common) + +CFLAGS_IxPiuMh.o := $(cflags_tdm_mh_includes) $(cflags_tdm_common) +CFLAGS_IxPiuMhConfig.o := $(cflags_tdm_mh_includes) $(cflags_tdm_common) +CFLAGS_IxPiuMhDll.o := $(cflags_tdm_mh_includes) $(cflags_tdm_common) +CFLAGS_IxPiuMhReceive.o := $(cflags_tdm_mh_includes) $(cflags_tdm_common) +CFLAGS_IxPiuMhSend.o := $(cflags_tdm_mh_includes) $(cflags_tdm_common) +CFLAGS_IxPiuMhSolicitedCbMgr.o := $(cflags_tdm_mh_includes) $(cflags_tdm_common) +CFLAGS_IxPiuMhUnsolicitedCbMgr.o := $(cflags_tdm_mh_includes) $(cflags_tdm_common) +CFLAGS_linux_kernel_module.o := $(cflags_tdm_mh_includes) $(cflags_tdm_common) + +CFLAGS_IxQMgr.o := $(cflags_tdm_qm_includes) $(cflags_tdm_common) + +CFLAGS_icp_sspacc_symbols.o := $(cflags_tdm_io_includes) $(cflags_tdm_common) +CFLAGS_icp_hssacc_symbols.o := $(cflags_tdm_io_includes) $(cflags_tdm_common) +CFLAGS_IxQMgrSymbols.o := $(cflags_tdm_io_includes) $(cflags_tdm_common) +CFLAGS_IxPiuDlSymbols.o := $(cflags_tdm_io_includes) $(cflags_tdm_common) +CFLAGS_IxPiuMhSymbols.o := $(cflags_tdm_io_includes) $(cflags_tdm_common) diff --git a/Acceleration/library/Makefile b/Acceleration/library/Makefile new file mode 100644 index 0000000..d9e3540 --- /dev/null +++ b/Acceleration/library/Makefile @@ -0,0 +1,11 @@ +PWD := $(shell pwd) + +KSRC ?= /bad__ksrc__not_set + +modules: + +modules modules_install clean: + $(MAKE) -C $(KSRC) M=$(PWD) $@ + +distclean: clean + rm -f modules.order diff --git a/Acceleration/library/icp_telephony/Makefile b/Acceleration/library/icp_telephony/Makefile new file mode 100644 index 0000000..1964a7e --- /dev/null +++ b/Acceleration/library/icp_telephony/Makefile @@ -0,0 +1,148 @@ +############################################################################### +# +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# +# +############################################################################### + +# Ensure The ENV_DIR environmental var is defined. +ifndef ICP_ENV_DIR +$(error ICP_ENV_DIR is undefined. Please set the path to your environment makefile \ + "-> setenv ICP_ENV_DIR <path>") +endif + +#Add your project environment Makefile +include $(ICP_ENV_DIR)/environment.mk + +##directories +BUILD_OUTPUT_DIR=build/$(ICP_OS)/$(ICP_OS_LEVEL)/#the folder where the output will be created. +FINAL_OUTPUT_DIR=$(BUILD_OUTPUT_DIR) + + +OUTPUT_NAME?=tdm_infra +LIB_STATIC=$(OUTPUT_NAME).a + + +MODULE_SOURCES= ssp_access/icp_sspacc_symbols.c tdm_io_access/icp_hssacc_symbols.c tdm_infrastructure_queue_manager/IxQMgrSymbols.c tdm_infrastructure_downloader/source/IxPiuDlSymbols.c tdm_infrastructure_message_handler/IxPiuMhSymbols.c + + + +INCLUDES+= -I$(ICP_OSAL_DIR)/platforms/EP805XX/include \ + -I$(ICP_OSAL_DIR)/platforms/EP805XX/os/linux/include \ + -I$(ICP_OSAL_DIR)/common/os/linux/include/core \ + -I$(ICP_OSAL_DIR)/common/os/linux/include/modules \ + -I$(ICP_OSAL_DIR)/common/os/linux/include/modules/ddk \ + -I$(ICP_OSAL_DIR)/common/os/linux/include/modules/ioMem\ + -I$(ICP_OSAL_DIR)/common/os/linux/include/modules/bufferMgt\ + -I$(ICP_OSAL_DIR)/common/include/modules/ioMem\ + -I$(ICP_OSAL_DIR)/common/include/modules/bufferMgt\ + -I$(src)/include \ + -I$(PWD)/include \ + -I$(ICP_API_DIR) \ + -I$(ICP_API_DIR)/hss \ + -I$(ICP_API_DIR)/accel_infra \ + -I$(ICP_OSAL_DIR)/common/include \ + -I$(ICP_TDM_IO_DIR)/include + +EXTRA_CFLAGS += $(INCLUDES) -DTOLAPAI -D__tolapai -DIX_HW_COHERENT_MEMORY=1 -DENABLE_IOMEM -DENABLE_BUFFERMGT +EXTRA_LDFLAGS+=-whole-archive + +# add the path and list of source libraries, +ADDITIONAL_KERNEL_LIBS=ssp_access/$(BUILD_OUTPUT_DIR)/sspAcc.a\ + tdm_infrastructure_downloader/$(BUILD_OUTPUT_DIR)/tdm_Dl.a\ + tdm_io_access/$(BUILD_OUTPUT_DIR)/tdmIOAcc.a\ + tdm_infrastructure_message_handler/$(BUILD_OUTPUT_DIR)/tdm_Mh.a \ + tdm_infrastructure_queue_manager/$(BUILD_OUTPUT_DIR)/tdm_qMgr.a \ + $(OSAL_RELATIVE_PATH)/lib/EP805XX/linux/linuxle/libosal.a + +SUBDIRS=ssp_access/ tdm_infrastructure_downloader/ tdm_io_access/ tdm_infrastructure_message_handler/ tdm_infrastructure_queue_manager/ + +kernel_module: lib_kernel + @echo 'Creating kernel module $(OUTPUT_NAME).ko'; \ + make -C $(KERNEL_SOURCE_ROOT)/ M=$(PWD) + echo "Copying outputs to $(BUILD_OUTPUT_DIR)";\ + test -d $(BUILD_OUTPUT_DIR) || mkdir -p $(BUILD_OUTPUT_DIR);\ + test -f lib.a && mv lib.a $(BUILD_OUTPUT_DIR)/$(LIB_STATIC);\ + test -f $(OUTPUT_NAME).ko && mv -f $(OUTPUT_NAME).ko $(BUILD_OUTPUT_DIR);\ + test -f $(OUTPUT_NAME).o && mv -f *.o $(BUILD_OUTPUT_DIR);\ + $(RM) -rf *.mod.* .*.cmd; + +obj-m := $(OUTPUT_NAME).o +$(OUTPUT_NAME)-objs := $(ADDITIONAL_KERNEL_LIBS)\ + $(patsubst %.c,%.o, $(MODULE_SOURCES)) + +lib_kernel::clean + @for dir in $(SUBDIRS); do \ + (echo ; echo $$dir :; cd $$dir; \ + ($(MAKE) clean && $(MAKE) lib_static) || return 1) \ + done + + +include $(ICP_BUILDSYSTEM_PATH)/build_files/Core/$(ICP_CORE).mk +include $(ICP_BUILDSYSTEM_PATH)/build_files/OS/$(ICP_OS).mk +##################################################################################### + + +.DEFAULT: kernel_module + + +clean: + @echo 'Removing derived objects...'; \ + $(RM) -rf *.o *.a *.mod.* *.ko .*.cmd; \ + $(RM) -rf .tmp_versions; \ + $(RM) -rf $(BUILD_OUTPUT_DIR); diff --git a/Acceleration/library/icp_telephony/environment.mk b/Acceleration/library/icp_telephony/environment.mk new file mode 100644 index 0000000..c3366e7 --- /dev/null +++ b/Acceleration/library/icp_telephony/environment.mk @@ -0,0 +1,108 @@ +##################################################################### +# +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# +# +##################################################################### + +ICP_OSAL_DIR=$(ICP_ROOT)/Acceleration/library/icp_utils/OSAL +OSAL_DIR=$(ICP_ROOT)/Acceleration/library/icp_utils/OSAL +ICP_API_DIR=$(ICP_ROOT)/Acceleration/include +API_DIR=$(ICP_ROOT)/Acceleration/include +ICP_BUILDSYSTEM_PATH=$(ICP_ROOT)/build_system +#access variables +ICP_ACC_DIR=$(ICP_ROOT)/Acceleration/library/icp_telephony +ICP_TDM_IO_DIR=$(ICP_ACC_DIR)/tdm_io_access +ICP_TDM_IO_NAME=tdmIOAcc +ICP_SSPACC_DIR=$(ICP_ACC_DIR)/ssp_access +ICP_TDM_QMGR_DIR=$(ICP_ACC_DIR)/tdm_infrastructure_queue_manager +ICP_TDM_QMGR_NAME=tdm_qMgr +ICP_TDM_MSG_HDLR_DIR=$(ICP_ACC_DIR)/tdm_infrastructure_message_handler +ICP_TDM_MSG_HDLR_NAME=tdm_Mh +ICP_TDM_DL_DIR=$(ICP_ACC_DIR)/tdm_infrastructure_downloader +ICP_TDM_DL_NAME=tdm_Dl + +OSAL_RELATIVE_PATH=../icp_utils/OSAL/ + +#driver variables +ICP_DRIVERS_DIR=$(ICP_ROOT)/Acceleration/drivers/icp_tdm +ICP_VOICE_DRV_DIR=$(ICP_DRIVERS_DIR)/hss_voice_driver +ICP_TDM_SETUP_DRV_DIR=$(ICP_DRIVERS_DIR)/tdm_setup_driver +ICP_COMMON_PLATFORM= +ICP_OS_TYPE= +ICP_SLASH= +ICP_DEVICE= + +#KERNEL_SOURCE_ROOT=/lib/modules/`uname -r`/build +#KERNEL_SOURCE_ROOT?=/localdisk/tolapai/linux-2.6.15.3 + +ICP_OS_LEVEL?=kernel_space +OS_LEVEL?=kernel_space + + +#OSAL VARIABLES +IX_TARGET?=linuxle +IX_OSAL_PLATFORM?=ixpTolapai +IX_HW_COHERENT_MEMORY?=1 + +ICP_INTEL_DEV?=YES + +ICP_CORE=ia +ICP_OS=linux_2.6 +CORE=ia +OS=linux_2.6 diff --git a/Acceleration/library/icp_telephony/ssp_access/Makefile b/Acceleration/library/icp_telephony/ssp_access/Makefile new file mode 100644 index 0000000..a2daba7 --- /dev/null +++ b/Acceleration/library/icp_telephony/ssp_access/Makefile @@ -0,0 +1,135 @@ +######################################################################### +# This Template Makefile will create the libraries, executables and module and place them in the output folder +# Remove the comments around the sections you wish to build for. +# +#Procedure +#1) Copy this template to the location of your source files +#2) "Common variables and defintions" must be filled out +#3) Edit as desired the "Libraries and executable section" and/or the "Linux kernel 2.6 Module section" depending on what you wish to build +#4) Remove the comments around the section and delete the other unnecessary section +#5) Save changes, return to command line and type "make". +# +# +# Targets supported +# all - builds everything and installs +# install - identical to all +# depend - build dependencies +# clean - clears all derived objects +# +# included makefiles +# common.mk - common defintions +# depend.mk - depend and cleandepend rules +# rules.mk - build rules. +# +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# +############################################################################ + +# Ensure The ICP_ENV_DIR environmental var is defined. +ifndef ICP_ENV_DIR +$(error ICP_ENV_DIR is undefined. Please set the path to your environment makefile \ + "-> setenv ICP_ENV_DIR <path>") +endif + +# Ensure The ICP_BUILDSYSTEM_PATH envorionmental var is defined. +ifndef ICP_BUILDSYSTEM_PATH +$(error ICP_BUILDSYSTEM_PATH is undefined. Please set the path to the top of the build structure \ + "-> setenv ICP_BUILDSYSTEM_PATH <path>") +endif + +#Add your project environment Makefile, extra comment +include $(ICP_ENV_DIR)/environment.mk + +#include the makefile with all the default and common Make variable definitions +include $(ICP_BUILDSYSTEM_PATH)/build_files/common.mk + +#Add the name for the executable, Library or Module output definitions +OUTPUT_NAME=sspAcc + +# List of Source Files to be compiled (to be in a single line or on different lines separated by a "\" and tab. +SOURCES = icp_sspacc.c + + +# Setup include directory +INCLUDES += -I $(ICP_API_DIR) \ + -I $(ICP_API_DIR)/hss \ + -I $(ICP_API_DIR)/accel_infra \ + -I $(ICP_OSAL_DIR)/common/include \ + -I $(ICP_OSAL_DIR)/common/ossl_shim/linux_kernel/include + +ifeq ($(ICP_INTEL_DEV),YES) +INCLUDES += -I $(ICP_OSAL_DIR)/common/include/modules \ + -I $(ICP_OSAL_DIR)/common/include/modules/ddk \ + -I $(ICP_OSAL_DIR)/common/include/modules/ioMem +endif + +EXTRA_CFLAGS += -DENABLE_IOMEM + + +#include your $(ICP_OS)_$(ICP_OS_LEVEL).mk file +include $(ICP_SSPACC_DIR)/$(ICP_OS)_$(ICP_OS_LEVEL).mk + +# Install the module to the output dir +install: module + + +###################Include rules and dependency makefiles######################## +include $(ICP_BUILDSYSTEM_PATH)/build_files/rules.mk +###################End of Rules and dependency inclusion######################### + diff --git a/Acceleration/library/icp_telephony/ssp_access/icp_sspacc.c b/Acceleration/library/icp_telephony/ssp_access/icp_sspacc.c new file mode 100644 index 0000000..5e3dbb6 --- /dev/null +++ b/Acceleration/library/icp_telephony/ssp_access/icp_sspacc.c @@ -0,0 +1,1361 @@ +/** + * @file icp_sspacc.c + * + * @description Contents of this file provide the implementation of the Synchronous + * Serial Port (SSP) Access Library + * + * @ingroup icp_SspAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +#include "IxOsal.h" +#include "icp_sspacc.h" + +#define PRIVATE static + + +/** + * Local #defines + */ +#define IX_SSP_CR0_OFFSET 0x0 /* SSP Control Register 0 (SSCR0) + offset from SSP Physical Address */ +#define IX_SSP_CR1_OFFSET 0x4 /* SSP Control Register 1 (SSCR1) + offset from SSP Physical Address */ +#define IX_SSP_SR_OFFSET 0x8 /* SSP Status Register (SSSR) + offset from SSP Physical Address */ +#define IX_SSP_DR_OFFSET 0x10 /* SSP Data Register (SSDR) + offset from SSP Physical Address */ + +#define IX_SSP_FIFO_EMPTY 0x00 /* SSP FIFO empty value is + zero */ +#define IX_SSP_FIFO_FULL 0x10 /* SSP FIFO full value is 16 */ + +#define IX_SSP_FIFO_FULL_OR_EMPTY 0x00/* FIFO level indicates it can + either be empty of full */ +#define IX_SSP_TX_FIFO_EXCEED_THLD 0x0 /* zero indicates a Tx FIFO + exceed threshold for the + Tx FIFO svc request bit of + the SSSR */ +#define IX_SSP_RX_FIFO_BELOW_THLD 0x0 /* zero indicates a Rx FIFO + below threshold for the Rx + FIFO svc request bit of the + SSSR */ +#define IX_SSP_IS_BUSY 0x1 /* One indicates a SSP busy for + the SSP busy bit of the SSSR */ +#define IX_SSP_TX_FIFO_FULL 0x0 /* zero indicates a TX FIFO Full + in the Tx FIFO not full bit + of the SSSR */ +#define IX_SSP_RX_FIFO_EMPTY 0x0 /* zero indicates a RX FIFO Empty + in the Rx FIFO not empty bit + of the SSSR */ +#define IX_SSP_OVERRUN_HAS_OCCURRED 0x1 /* one indicates an overrun has + occurred in the overrun bit + of the SSSR */ +#define IX_SSP_INTERRUPT_ENABLE 0x1 /* one enables the interrupt in + the SSCR1 */ +#define IX_SSP_INTERRUPT_DISABLE 0x0 /* one disables the interrupt in + the SSCR1 */ +#define IX_SSP_INTERRUPTED 0x1 /* one indicates an interrupt has + occured in the SSSR */ + +#define IX_SSP_SET_TO_BE_CLEARED 0x1 /* Use for write 1 to clear in + the registers */ + +/* #defines for mask and location of SSP Control and Status Registers + * contents */ +#define IX_SSP_SERIAL_CLK_RATE_LOC 0x8 +#define IX_SSP_SERIAL_CLK_RATE_MASK (0xFF << IX_SSP_SERIAL_CLK_RATE_LOC) +#define IX_SSP_PORT_STATUS_LOC 0x7 +#define IX_SSP_PORT_STATUS_MASK (0x1 << IX_SSP_PORT_STATUS_LOC) +#define IX_SSP_CLK_SRC_LOC 0x6 +#define IX_SSP_CLK_SRC_MASK (0x1 << IX_SSP_CLK_SRC_LOC) +#define IX_SSP_FRAME_FORMAT_LOC 0x4 +#define IX_SSP_FRAME_FORMAT_MASK (0x3 << IX_SSP_FRAME_FORMAT_LOC) +#define IX_SSP_DATA_SIZE_LOC 0x0 +#define IX_SSP_DATA_SIZE_MASK (0xF << IX_SSP_DATA_SIZE_LOC) +#define IX_SSP_RX_FIFO_THLD_LOC 0xA +#define IX_SSP_RX_FIFO_THLD_MASK (0xF << IX_SSP_RX_FIFO_THLD_LOC) +#define IX_SSP_TX_FIFO_THLD_LOC 0x6 +#define IX_SSP_TX_FIFO_THLD_MASK (0xF << IX_SSP_TX_FIFO_THLD_LOC) +#define IX_SSP_MICROWIRE_CTL_WORD_LOC 0x5 +#define IX_SSP_MICROWIRE_CTL_WORD_MASK (0x1 << IX_SSP_MICROWIRE_CTL_WORD_LOC) +#define IX_SSP_SPI_SCLK_PHASE_LOC 0x4 +#define IX_SSP_SPI_SCLK_PHASE_MASK (0x1 << IX_SSP_SPI_SCLK_PHASE_LOC) +#define IX_SSP_SPI_SCLK_POLARITY_LOC 0x3 +#define IX_SSP_SPI_SCLK_POLARITY_MASK (0x1 << IX_SSP_SPI_SCLK_POLARITY_LOC) +#define IX_SSP_LOOPBACK_ENABLE_LOC 0x2 +#define IX_SSP_LOOPBACK_ENABLE_MASK (0x1 << IX_SSP_LOOPBACK_ENABLE_LOC) +#define IX_SSP_TX_FIFO_INT_ENABLE_LOC 0x1 +#define IX_SSP_TX_FIFO_INT_ENABLE_MASK (0x1 << IX_SSP_TX_FIFO_INT_ENABLE_LOC) +#define IX_SSP_RX_FIFO_INT_ENABLE_LOC 0x0 +#define IX_SSP_RX_FIFO_INT_ENABLE_MASK (0x1 << IX_SSP_RX_FIFO_INT_ENABLE_LOC) +#define IX_SSP_RX_FIFO_LVL_LOC 0xC +#define IX_SSP_RX_FIFO_LVL_MASK (0xF << IX_SSP_RX_FIFO_LVL_LOC) +#define IX_SSP_TX_FIFO_LVL_LOC 0x8 +#define IX_SSP_TX_FIFO_LVL_MASK (0xF << IX_SSP_TX_FIFO_LVL_LOC) +#define IX_SSP_RX_FIFO_OVERRUN_LOC 0x7 +#define IX_SSP_RX_FIFO_OVERRUN_MASK (0x1 << IX_SSP_RX_FIFO_OVERRUN_LOC) +#define IX_SSP_RX_FIFO_SVC_REQ_LOC 0x6 +#define IX_SSP_RX_FIFO_SVC_REQ_MASK (0x1 << IX_SSP_RX_FIFO_SVC_REQ_LOC) +#define IX_SSP_TX_FIFO_SVC_REQ_LOC 0x5 +#define IX_SSP_TX_FIFO_SVC_REQ_MASK (0x1 << IX_SSP_TX_FIFO_SVC_REQ_LOC) +#define IX_SSP_BUSY_LOC 0x4 +#define IX_SSP_BUSY_MASK (0x1 << IX_SSP_BUSY_LOC) +#define IX_SSP_RX_FIFO_NOT_EMPTY_LOC 0x3 +#define IX_SSP_RX_FIFO_NOT_EMPTY_MASK (0x1 << IX_SSP_RX_FIFO_NOT_EMPTY_LOC) +#define IX_SSP_TX_FIFO_NOT_FULL_LOC 0x2 +#define IX_SSP_TX_FIFO_NOT_FULL_MASK (0x1 << IX_SSP_TX_FIFO_NOT_FULL_LOC) + +#define ICP_SSP_MAP_SIZE 0x14 +/** + * macros + */ +#define IX_SSP_INIT_SUCCESS_CHECK(funcName, returnType) \ + if(ICP_FALSE == ixSspAccInitComplete){ \ + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, \ + funcName": SSP Access not initialized\n", \ + 0,0,0,0,0,0); \ + return returnType; \ + } /* end of ICP_FALSE == ixSspAccInitComplete */ + + +#ifdef SW_SWAPPING +#define IX_SSP_READ_REGISTER(wAddr) \ + IX_OSAL_READ_BE_SHARED_LONG((uint32_t *) wAddr) +#define IX_SSP_WRITE_REGISTER(wAddr, wData) \ + IX_OSAL_WRITE_BE_SHARED_LONG((uint32_t *)wAddr, wData) +#else +#define IX_SSP_READ_REGISTER(wAddr) \ + IX_OSAL_READ_LONG_RAW((uint32_t *) wAddr) +#define IX_SSP_WRITE_REGISTER(wAddr, wData) \ + IX_OSAL_WRITE_LONG_RAW((uint32_t *)wAddr, wData) +#endif /*SSP_SWAP*/ + + +#define ICP_SSPACC_MAJOR_VERSION 1 +#define ICP_SSPACC_MINOR_VERSION 0 +#define ICP_SSPACC_PATCH_VERSION 1 +#define ICP_SSPACC_DEBUG_MODULE_NAME "SSP" + + +/** + * typedef + */ + +/* typedef to contain both SSP Control Register 0 and 1 */ +typedef struct +{ + uint32_t sscr0; + uint32_t sscr1; +} IxSspAccConfig; + +/** + * Static variables defined here + */ + +/* Interrupt handler function pointers */ +PRIVATE icp_sspacc_rx_fifo_overrun_handler_t ixRxFIFOOverrunHdlr = NULL; +PRIVATE icp_sspacc_rx_fifo_threshold_handler_t ixRxFIFOThsldHdlr = NULL; +PRIVATE icp_sspacc_tx_fifo_threshold_handler_t ixTxFIFOThsldHdlr = NULL; + +/* The addresses to be used to access the SSP Control Register 0 (CR0), + SSP Control Register 1 (CR1), SSP Status Register (SR), and SSP + Data Register (DR). The address is assigned on init. */ +PRIVATE uint32_t ixSspCR0Addr = 0; +PRIVATE uint32_t ixSspCR1Addr = 0; +PRIVATE uint32_t ixSspSRAddr = 0; +PRIVATE uint32_t ixSspDRAddr = 0; + +/* Storage for the SSP configuration which is used over many functions to +increase efficiency */ +PRIVATE IxSspAccConfig ixSspAccCfgStored; + +/* Storage for the SSP status which is used by many functions to avoid + declaration of the same struct multiple times */ +PRIVATE uint32_t ixSspAccStsStored; + +/* Storage for the SSP statistics counters */ +PRIVATE icp_sspacc_stats_counters_t ixSspAccStatsCounters; + +/* Flag to indicate if the mode is interrupt or poll. */ +PRIVATE icp_boolean_t ixSspAccInterruptMode = ICP_FALSE; + +/* Flag to indicate if the init has been done and thus not performing some + instructions that should not be done more than once (please refer to the + init API. Example: memory mapping). if init is called more than once + (which is allowed) */ +PRIVATE icp_boolean_t ixSspAccInitComplete = ICP_FALSE; + +/* Flag to indicate if the physical address of the SSP unit has been set */ +PRIVATE icp_boolean_t ixSspAccPhysicalAddressSet = ICP_FALSE; + +/* Storage for the SSP phiysical address base register */ +PRIVATE uint32_t ixSspPhysicalRegisterBase = 0x00; +/* Flag to indicate if the interrupt number of the SSP unit has been set */ +PRIVATE icp_boolean_t ixSspAccInterruptNumberSet = ICP_FALSE; + +/* Storage for the SSP interrupt number */ +PRIVATE unsigned int ixSspAccInterruptNumber = 0; + +/** + * static function declaration + */ +PRIVATE void ixSspAccInterruptDetected (void); + +/** + * Function definitions + */ + +icp_status_t +icp_SspAccInterruptSet ( + unsigned int interruptNumber) +{ + + icp_status_t status = ICP_STATUS_FAIL; + + if(ICP_FALSE == ixSspAccInitComplete) + { + ixSspAccInterruptNumber = interruptNumber; + ixSspAccInterruptNumberSet = ICP_TRUE; + status = ICP_STATUS_SUCCESS; + } + return status; +} + +icp_status_t +icp_SspAccPhysicalAddressSet ( + uint32_t address) +{ + + icp_status_t status = ICP_STATUS_FAIL; + + if(ICP_FALSE == ixSspAccInitComplete) + { + ixSspPhysicalRegisterBase = address; + ixSspAccPhysicalAddressSet = ICP_TRUE; + status = ICP_STATUS_SUCCESS; + } + return status; +} + +icp_status_t +icp_SspAccInit ( + icp_sspacc_init_vars_t *initVarsSelected) +{ + icp_status_t temp_return = ICP_STATUS_SUCCESS; + + /* Check if the initVarsSelected is NULL */ + if(NULL == initVarsSelected) + { + return ICP_STATUS_NULL_PARAM; + } + + /* Check if SSP Init has been called before to avoid multiple instances of + memory mapping */ + if(ICP_FALSE == ixSspAccInitComplete) + { + /* Memory map the control, status, and data registers of the SSP */ + if(ICP_TRUE == ixSspAccPhysicalAddressSet) + { + ixSspCR0Addr = (uint32_t)ixOsalIoRemap + (ixSspPhysicalRegisterBase, ICP_SSP_MAP_SIZE); + + + + ixSspCR1Addr = ixSspCR0Addr + IX_SSP_CR1_OFFSET; + ixSspSRAddr = ixSspCR0Addr + IX_SSP_SR_OFFSET; + ixSspDRAddr = ixSspCR0Addr + IX_SSP_DR_OFFSET; + /* Reset the hardware*/ + IX_SSP_WRITE_REGISTER(ixSspCR0Addr, 0x00); + icp_SspAccStatsReset(); /* Clear the SSP statistics counters */ + } + else + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, + "icp_SspAccInit: Base Address not set.\n", + 0,0,0,0,0,0); + return ICP_STATUS_RESOURCE; + } + + ixSspAccInitComplete = ICP_TRUE; /* Set the Init Complete flag so + that a call to init will not + mem map, clear the stats and + register with the debug + component again*/ + } /* end of ICP_FALSE == ixSspAccInitComplete */ + + /* Set the SSP frame format (SPI, SSP, or Microwire) if format is valid */ + if(ICP_STATUS_SUCCESS != icp_SspAccFrameFormatSelect( + initVarsSelected->frameFormatSelected)) + { + return ICP_STATUS_INVALID_PARAM; + } + + /* Set the data size if range is valid and FIFOs empty */ + temp_return = icp_SspAccDataSizeSelect(initVarsSelected->dataSizeSelected); + if(ICP_STATUS_SUCCESS != temp_return) + { + return temp_return; + } + + /* Set the clock source if source is valid */ + if(ICP_STATUS_SUCCESS != icp_SspAccClockSourceSelect( + initVarsSelected->clkSourceSelected)) + { + return ICP_STATUS_INVALID_PARAM; + } + + /* Set the Tx FIFO Threshold if level is valid */ + if(ICP_STATUS_SUCCESS != icp_SspAccTxFifoThresholdSet( + initVarsSelected->txFIFOThresholdSelected)) + { + return ICP_STATUS_INVALID_PARAM; + } + + /* Set the Rx FIFO Threshold if level is valid */ + if(ICP_STATUS_SUCCESS != icp_SspAccRxFifoThresholdSet( + initVarsSelected->rxFIFOThresholdSelected)) + { + return ICP_STATUS_INVALID_PARAM; + } + + /* Unbind the SSP ISR if interrupt mode was enabled previously */ + if(ICP_TRUE == ixSspAccInterruptMode) + { + if(IX_SUCCESS != ixOsalIrqUnbind(ixSspAccInterruptNumber)) + { + return ICP_STATUS_RESOURCE; + } /* end of ixOsalIrqUnbind Fail */ + icp_SspAccRxFifoIntDisable(); + icp_SspAccTxFifoIntDisable(); + ixSspAccInterruptMode = ICP_FALSE; + } /* end of ixSspAccInterruptMode == ICP_TRUE */ + + /* Check if either the Rx FIFO or the Tx FIFO interrupt is selected to be + enabled, then enable interrupt mode */ + if((ICP_TRUE == initVarsSelected->txFIFOIntrEnable) || + (ICP_TRUE == initVarsSelected->rxFIFOIntrEnable)) + { + /* Check if the Rx FIFO Overrun handler is NULL */ + if(NULL == initVarsSelected->rxFIFOOverrunHdlr) + { + return ICP_STATUS_NULL_PARAM; + } + + /* Set the Rx FIFO Overrun handler */ + ixRxFIFOOverrunHdlr = initVarsSelected->rxFIFOOverrunHdlr; + if(ICP_TRUE == ixSspAccInterruptNumberSet) + { + /* Bind the SSP to the SSP ISR */ + if(IX_SUCCESS != ixOsalIrqBind(ixSspAccInterruptNumber, + (IxOsalVoidFnVoidPtr)ixSspAccInterruptDetected, + NULL)) + { + return ICP_STATUS_RESOURCE; + } + ixSspAccInterruptMode = ICP_TRUE; /* Set the Interrupt Mode flag to + ICP_TRUE */ + } + else + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, + "icp_SspAccInit: Interrupt number not set.\n", + 0,0,0,0,0,0); + return ICP_STATUS_RESOURCE; + } + + } /* end of interrupt mode selected */ + else /* start of polling mode selected */ + { + /* Set the Rx FIFO Overrun handler to NULL */ + ixRxFIFOOverrunHdlr = NULL; + + ixSspAccInterruptMode = ICP_FALSE; /* Set the Interrupt Mode flag to + ICP_FALSE */ + } /* end of polling mode selected */ + + /* Check if the Rx FIFO interrupt is selected to be enabled */ + if(ICP_TRUE == initVarsSelected->rxFIFOIntrEnable) + { + /* Enable the Rx FIFO and set the Rx FIFO handler if handler pointer is + not NULL */ + if(ICP_STATUS_SUCCESS != icp_SspAccRxFifoIntEnable( + initVarsSelected->rxFIFOThsldHdlr)) + { + return ICP_STATUS_NULL_PARAM; + } + } /* end of Rx FIFOIntrEnable Selected */ + + /* Check if the Tx FIFO interrupt is selected to be enabled */ + if(ICP_TRUE == initVarsSelected->txFIFOIntrEnable) + { + /* Enable the Tx FIFO and set the Tx FIFO handler if handler pointer is + not NULL */ + if(ICP_STATUS_SUCCESS != icp_SspAccTxFifoIntEnable( + initVarsSelected->txFIFOThsldHdlr)) + { + return ICP_STATUS_NULL_PARAM; + } + } /* end of Tx FIFOIntrEnable Selected */ + + /* Enable/disable the loopback */ + icp_SspAccLoopbackEnable(initVarsSelected->loopbackEnable); + + if(ICP_SSPACC_FRAME_FORMAT_SPI == initVarsSelected->frameFormatSelected) + { + /* Set the SPI SCLK phase if phase selected is valid */ + if(ICP_STATUS_SUCCESS != icp_SspAccSpiSclkPhaseSet( + initVarsSelected->spiSclkPhaseSelected)) + { + return ICP_STATUS_INVALID_PARAM; + } + + /* Set the SPI SCLK polarity if polarity selected is valid */ + if(ICP_STATUS_SUCCESS != icp_SspAccSpiSclkPolaritySet( + initVarsSelected->spiSclkPolaritySelected)) + { + return ICP_STATUS_INVALID_PARAM; + } + } /* end of ICP_SSPACC_FRAME_FORMAT_SPI */ + + if(ICP_SSPACC_FRAME_FORMAT_MICROWIRE == + initVarsSelected->frameFormatSelected) + { + /* Set the Microwire control word size if size is valid and Tx FIFO + * empty */ + temp_return = icp_SspAccMicrowireControlWordSet( + initVarsSelected->microwireCtlWordSelected); + if(ICP_STATUS_SUCCESS != temp_return) + { + if(ICP_STATUS_RESOURCE == temp_return) + { + return ICP_STATUS_RESOURCE; + } + else + { + return ICP_STATUS_INVALID_PARAM; + } + } /* end of temp_return != ICP_STATUS_SUCCESS */ + } /* end of ICP_SSPACC_FRAME_FORMAT_MICROWIRE */ + + /* Set the Serial clock rate to the selected */ + icp_SspAccSerialClockRateConfigure(initVarsSelected->serialClkRateSelected); + + /* Enable the SSP Port to start receiving and transmitting data */ + icp_SspAccSspPortStatusSet(ICP_SSPACC_PORT_ENABLE); + + return ICP_STATUS_SUCCESS; +} /* endo of icp_SspAccInit */ + + +icp_status_t +icp_SspAccUninit ( + void) +{ + if(ICP_TRUE == ixSspAccInitComplete) + { + /* Disable the SSP hardware */ + icp_SspAccSspPortStatusSet(ICP_SSPACC_PORT_DISABLE); + + /* Unbind the SSP ISR if interrupt mode is enabled */ + if(ICP_TRUE == ixSspAccInterruptMode) + { + if(IX_SUCCESS != ixOsalIrqUnbind(ixSspAccInterruptNumber)) + { + return ICP_STATUS_FAIL; + } /* end of ixOsalIrqUnbind Fail */ + icp_SspAccRxFifoIntDisable(); + icp_SspAccTxFifoIntDisable(); + /* Set all Handler pointers to NULL */ + ixRxFIFOOverrunHdlr = NULL; + ixSspAccInterruptMode = ICP_FALSE; + } /* end of ICP_TRUE == ixSspAccInterruptMode */ + + /* Return the memory that was mapped during init which is the SSP + control and status registers and the SSP data register. */ + ixOsalIoUnmap(ixSspCR0Addr, ICP_SSP_MAP_SIZE); + + ixSspAccInitComplete = ICP_FALSE; + } /* end of ICP_TRUE == ixSspAccInitComplete */ + + return ICP_STATUS_SUCCESS; +} /* end of icp_SspAccUninit */ + +icp_status_t +icp_SspAccFifoDataSubmit ( + uint16_t* data, + uint32_t amtOfData) +{ + uint32_t dataLoc = 0; + + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccFifoDataSubmit", ICP_STATUS_RESOURCE); + + /* Check if the data pointer provided is NULL */ + if(NULL == data) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, + "icp_SspAccFifoDataSubmit: data pointer is NULL.\n", + 0,0,0,0,0,0); + return ICP_STATUS_NULL_PARAM; + } /* end of NULL == data */ + + /* Check if the Tx FIFO has sufficient space to store the number of data + specified by amtOfData */ + if((icp_SspAccTxFifoLevelGet() + amtOfData) > IX_SSP_FIFO_FULL) + { + return ICP_STATUS_FAIL; + } + + /* Copy the data from the data buffer pointer into the SSP Data Register */ + while(amtOfData > dataLoc) + { + IX_SSP_WRITE_REGISTER(ixSspDRAddr, (uint32_t)data[dataLoc]); + dataLoc++; + } + + /* Increment the SSP stats counter for data transmitted */ + ixSspAccStatsCounters.xmitCounter+=amtOfData; + + return ICP_STATUS_SUCCESS; +} /* end of icp_SspAccFifoDataSubmit */ + +icp_status_t +icp_SspAccFifoDataReceive ( + uint16_t* data, + uint32_t amtOfData) +{ + uint32_t dataLoc = 0; + + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccFifoDataReceive", ICP_STATUS_RESOURCE); + + /* Check if the data pointer provided is NULL */ + if(NULL == data) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, + "icp_SspAccFifoDataReceive: data pointer is NULL.\n", + 0,0,0,0,0,0); + return ICP_STATUS_NULL_PARAM; + } /* end of NULL == data */ + + /* Check if the Rx FIFO has the number of data specified by amtOfData to be + retrieved */ + if(icp_SspAccRxFifoLevelGet() < amtOfData) + { + return ICP_STATUS_FAIL; + } + + /* Overrun Check is called to increment the overrun counter if it occured + and not used to determine whether an overrun occured therefore no + checking of the return value is necessary */ + icp_SspAccRxFifoOverrunCheck(); + + /* Copy the data from the SSP Data Register into the data buffer pointer */ + while(amtOfData > dataLoc) + { + data[dataLoc] = (uint16_t) IX_SSP_READ_REGISTER(ixSspDRAddr); + dataLoc++; + } + + + /* Increment the SSP stats counter for data received */ + ixSspAccStatsCounters.rcvCounter+=amtOfData; + + return ICP_STATUS_SUCCESS; +} /* end of icp_SspAccFifoDataReceive */ + +icp_status_t +icp_SspAccTxFifoHitLowThresholdCheck ( + void) +{ + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccTxFifoHitLowThresholdCheck", + ICP_STATUS_RESOURCE); + + /* Read the SSP status register, SSSR */ + ixSspAccStsStored = IX_SSP_READ_REGISTER (ixSspSRAddr); + + /* Check the Tx FIFO Service Request bit has been set to determine if the + threshold has been hit or is below */ + if(IX_SSP_TX_FIFO_EXCEED_THLD == + ((ixSspAccStsStored & IX_SSP_TX_FIFO_SVC_REQ_MASK) >> + IX_SSP_TX_FIFO_SVC_REQ_LOC)) + { + return ICP_STATUS_FAIL; + } + else + { + return ICP_STATUS_SUCCESS; + } +} /* end of icp_SspAccTxFifoHitLowThresholdCheck */ + +icp_status_t +icp_SspAccRxFifoHitHighThresholdCheck ( + void) +{ + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccRxFifoHitHighThresholdCheck", + ICP_STATUS_RESOURCE); + + /* Read the SSP status register, SSSR */ + ixSspAccStsStored = IX_SSP_READ_REGISTER (ixSspSRAddr); + + /* Check the Rx FIFO Service Request bit has been set to determine if the + threshold has been hit or is above */ + if(IX_SSP_RX_FIFO_BELOW_THLD == + ((ixSspAccStsStored & IX_SSP_RX_FIFO_SVC_REQ_MASK) >> + IX_SSP_RX_FIFO_SVC_REQ_LOC)) + { + return ICP_STATUS_FAIL; + } + else + { + return ICP_STATUS_SUCCESS; + } +} /* end of icp_SspAccRxFifoHitHighThresholdCheck */ + +/** + * Configuration functions + */ + +icp_status_t +icp_SspAccSspPortStatusSet ( + icp_sspacc_port_status_t portStatusSelected) +{ + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccSspPortStatusSet", + ICP_STATUS_RESOURCE); + + /* Check for validity of parameter */ + if(portStatusSelected >= ICP_SSPACC_PORT_TYPE_DELIMITER) + { + return ICP_STATUS_INVALID_PARAM; + } + + /* Write the parameter into the SSP Port Enable of SSCR0 register if + selected differ from current status */ + if(((ixSspAccCfgStored.sscr0 & IX_SSP_PORT_STATUS_MASK) >> + IX_SSP_PORT_STATUS_LOC) != portStatusSelected) + { + ixSspAccCfgStored.sscr0 = + (ixSspAccCfgStored.sscr0 & (~IX_SSP_PORT_STATUS_MASK)) | + (portStatusSelected << IX_SSP_PORT_STATUS_LOC); + IX_SSP_WRITE_REGISTER (ixSspCR0Addr, ixSspAccCfgStored.sscr0); + } /* end of parameter write when current differs from selected */ + + return ICP_STATUS_SUCCESS; +} /* end of icp_SspAccSspPortStatusSet */ + +icp_status_t +icp_SspAccFrameFormatSelect ( + icp_sspacc_frame_format_t frameFormatSelected) +{ + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccFrameFormatSelect", + ICP_STATUS_RESOURCE); + + /* Check for validity of parameter */ + if(frameFormatSelected >= ICP_SSPACC_FRAME_FORMAT_TYPE_DELIMITER) + { + return ICP_STATUS_INVALID_PARAM; + } + + /* Determine if the SSP port is enabled. */ + if (ICP_SSPACC_PORT_ENABLE == + ((ixSspAccCfgStored.sscr0 & IX_SSP_PORT_STATUS_MASK) >> + IX_SSP_PORT_STATUS_LOC)) + { + /* SSP Port enabled. + Disable the SSP Port (clears FIFOs), then write the parameter + into the Frame Format bit of SSCR0 register and re-enable the SSP + Port. */ + icp_SspAccSspPortStatusSet(ICP_SSPACC_PORT_DISABLE); + ixSspAccCfgStored.sscr0 = + (ixSspAccCfgStored.sscr0 & (~IX_SSP_FRAME_FORMAT_MASK)) | + (frameFormatSelected << IX_SSP_FRAME_FORMAT_LOC); + icp_SspAccSspPortStatusSet(ICP_SSPACC_PORT_ENABLE); /* Both the format + and the status will + be written into the + SSCR0 register + together.*/ + } /* end of ICP_SSPACC_PORT_ENABLE */ + else /* start of ICP_SSPACC_PORT_DISABLE */ + { + /* SSP Port not enabled. + Write the parameter into the Frame Format bit of SSCR0 register */ + ixSspAccCfgStored.sscr0 = + (ixSspAccCfgStored.sscr0 & (~IX_SSP_FRAME_FORMAT_MASK)) | + (frameFormatSelected << IX_SSP_FRAME_FORMAT_LOC); + IX_SSP_WRITE_REGISTER (ixSspCR0Addr, ixSspAccCfgStored.sscr0); + } /* end of ICP_SSPACC_PORT_DISABLE */ + + return ICP_STATUS_SUCCESS; +} /* end of icp_SspAccFrameFormatSelect */ + +icp_status_t +icp_SspAccDataSizeSelect ( + icp_sspacc_data_size_t dataSizeSelected) +{ + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccDataSizeSelect", ICP_STATUS_RESOURCE); + + /* Check for validity of parameter */ + if( (dataSizeSelected <= ICP_SSPACC_DATA_SIZE_TOO_SMALL) || + (dataSizeSelected >= ICP_SSPACC_DATA_SIZE_TYPE_DELIMITER) ) + { + return ICP_STATUS_INVALID_PARAM; + } + + /* Only allow change if Tx FIFO is empty */ + if(IX_SSP_FIFO_EMPTY != icp_SspAccTxFifoLevelGet()) + { + return ICP_STATUS_RESOURCE; + } + + /* Only allow change if Rx FIFO is empty */ + if(IX_SSP_FIFO_EMPTY != icp_SspAccRxFifoLevelGet()) + { + return ICP_STATUS_RESOURCE; + } + + /* Determine if the SSP port is enabled. */ + if (ICP_SSPACC_PORT_ENABLE == + ((ixSspAccCfgStored.sscr0 & IX_SSP_PORT_STATUS_MASK) >> + IX_SSP_PORT_STATUS_LOC)) + { + /* SSP Port enabled. + Disable the SSP Port (clears FIFOs), then write the parameter + into the data size select bit of SSCR0 register and re-enable the + SSP Port. */ + icp_SspAccSspPortStatusSet(ICP_SSPACC_PORT_DISABLE); + ixSspAccCfgStored.sscr0 = + (ixSspAccCfgStored.sscr0 & (~IX_SSP_DATA_SIZE_MASK)) | + (dataSizeSelected << IX_SSP_DATA_SIZE_LOC); + icp_SspAccSspPortStatusSet(ICP_SSPACC_PORT_ENABLE); /* Both the data + size and the status + will be written + into the SSCR0 + register together. + */ + } /* end of ICP_SSPACC_PORT_ENABLE */ + else /* start of ICP_SSPACC_PORT_DISABLE */ + { + /* SSP Port not enabled. + Write the parameter into the data size select bit of SSCR0 + register */ + ixSspAccCfgStored.sscr0 = + (ixSspAccCfgStored.sscr0 & (~IX_SSP_DATA_SIZE_MASK)) | + (dataSizeSelected << IX_SSP_DATA_SIZE_LOC); + IX_SSP_WRITE_REGISTER (ixSspCR0Addr, ixSspAccCfgStored.sscr0); + } /* end of ICP_SSPACC_PORT_DISABLE */ + + return ICP_STATUS_SUCCESS; +} /* end of icp_SspAccDataSizeSelect */ + +icp_status_t +icp_SspAccClockSourceSelect ( + icp_sspacc_clk_source_t clkSourceSelected) +{ + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccClockSourceSelect", + ICP_STATUS_RESOURCE); + + /* Check for validity of parameter */ + if(clkSourceSelected >= ICP_SSPACC_CLK_SOURCE_TYPE_DELIMITER) + { + return ICP_STATUS_INVALID_PARAM; + } + + /* Write the parameter into the Clock Source bit of SSCR0 register */ + ixSspAccCfgStored.sscr0 = (ixSspAccCfgStored.sscr0 & + (~IX_SSP_CLK_SRC_MASK)) + | (clkSourceSelected << IX_SSP_CLK_SRC_LOC); + IX_SSP_WRITE_REGISTER (ixSspCR0Addr, ixSspAccCfgStored.sscr0); + + return ICP_STATUS_SUCCESS; +} /* end of icp_SspAccClockSourceSelect */ + +icp_status_t +icp_SspAccSerialClockRateConfigure ( + uint8_t serialClockRateSelected) +{ + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccSerialClockRateConfigure", + ICP_STATUS_RESOURCE); + + /* Write the parameter into the Clock Rate bits of SSCR0 register */ + ixSspAccCfgStored.sscr0 = + (ixSspAccCfgStored.sscr0 & (~IX_SSP_SERIAL_CLK_RATE_MASK)) | + (serialClockRateSelected << IX_SSP_SERIAL_CLK_RATE_LOC); + IX_SSP_WRITE_REGISTER (ixSspCR0Addr, ixSspAccCfgStored.sscr0); + return ICP_STATUS_SUCCESS; +} /* end of icp_SspAccSerialClockRateConfigure */ + +icp_status_t +icp_SspAccRxFifoIntEnable ( + icp_sspacc_rx_fifo_threshold_handler_t rxFIFOIntrHandler) +{ + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccRxFifoIntEnable", ICP_STATUS_RESOURCE); + + /* Only allow to enable the interrupt if interrupt mode is set at init */ + if(ICP_FALSE == ixSspAccInterruptMode) + { + return ICP_STATUS_FAIL; + } + + /* Check if a handler is provided */ + if(NULL == rxFIFOIntrHandler) + { + return ICP_STATUS_NULL_PARAM; + } + + /* Set the Rx FIFO threshold interrupt handler function pointer to point to + the function pointer parameter and enable the Rx FIFO interrupt by writing + a one to the Rx FIFO Interrupt enable bit ofthe SSCR1 register */ + ixRxFIFOThsldHdlr = rxFIFOIntrHandler; + ixSspAccCfgStored.sscr1 = + (ixSspAccCfgStored.sscr1 & (~IX_SSP_RX_FIFO_INT_ENABLE_MASK)) | + (IX_SSP_INTERRUPT_ENABLE << IX_SSP_RX_FIFO_INT_ENABLE_LOC); + + IX_SSP_WRITE_REGISTER (ixSspCR1Addr, ixSspAccCfgStored.sscr1); + + return ICP_STATUS_SUCCESS; +} /* end of icp_SspAccRxFifoIntEnable */ + +icp_status_t +icp_SspAccRxFifoIntDisable( + void) +{ + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccRxFifoIntDisable", + ICP_STATUS_RESOURCE); + + if(ICP_TRUE == ixSspAccInterruptMode) + { + /* Disable the Rx FIFO interrupt by writing zero to the Rx FIFO + Interrupt enable bit ofthe SSCR1 register and setting the Tx + FIFO threshold interrupt handler function pointer to NULL.*/ + ixSspAccCfgStored.sscr1 = + (ixSspAccCfgStored.sscr1 & (~IX_SSP_RX_FIFO_INT_ENABLE_MASK)) | + (IX_SSP_INTERRUPT_DISABLE << IX_SSP_RX_FIFO_INT_ENABLE_LOC); + IX_SSP_WRITE_REGISTER (ixSspCR1Addr, ixSspAccCfgStored.sscr1); + ixRxFIFOThsldHdlr = NULL; + } /* end of ICP_TRUE == ixSspAccInterruptMode */ + + return ICP_STATUS_SUCCESS; +} /* end of icp_SspAccRxFifoIntDisable */ + +icp_status_t +icp_SspAccTxFifoIntEnable ( + icp_sspacc_tx_fifo_threshold_handler_t txFIFOIntrHandler) +{ + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccTxFifoIntEnable", ICP_STATUS_RESOURCE); + + /* Only allow to enable the interrupt if interrupt mode is set at init */ + if(ICP_FALSE == ixSspAccInterruptMode) + { + return ICP_STATUS_FAIL; + } + + /* Check if a handler is provided */ + if(NULL == txFIFOIntrHandler) + { + return ICP_STATUS_NULL_PARAM; + } + + /* Set the Tx FIFO threshold interrupt handler function pointer to point to + the function pointer parameter and enable the Tx FIFO interrupt by + writing a one to the Rx FIFO Interrupt enable bit ofthe SSCR1 + register */ + ixTxFIFOThsldHdlr = txFIFOIntrHandler; + ixSspAccCfgStored.sscr1 = + (ixSspAccCfgStored.sscr1 & (~IX_SSP_TX_FIFO_INT_ENABLE_MASK)) | + (IX_SSP_INTERRUPT_ENABLE << IX_SSP_TX_FIFO_INT_ENABLE_LOC); + IX_SSP_WRITE_REGISTER (ixSspCR1Addr, ixSspAccCfgStored.sscr1); + + return ICP_STATUS_SUCCESS; +} /* end of icp_SspAccTxFifoIntEnable */ + +icp_status_t +icp_SspAccTxFifoIntDisable ( + void) +{ + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccTxFifoIntDisable", + ICP_STATUS_RESOURCE); + + if(ICP_TRUE == ixSspAccInterruptMode) + { + /* Disable the Tx FIFO interrupt by writing zero to the Rx FIFO + Interrupt enable bit ofthe SSCR1 register and setting the Tx + FIFO threshold interrupt handler function pointer to NULL. */ + ixSspAccCfgStored.sscr1 = + (ixSspAccCfgStored.sscr1 & (~IX_SSP_TX_FIFO_INT_ENABLE_MASK)) | + (IX_SSP_INTERRUPT_DISABLE << IX_SSP_TX_FIFO_INT_ENABLE_LOC); + IX_SSP_WRITE_REGISTER (ixSspCR1Addr, ixSspAccCfgStored.sscr1); + ixTxFIFOThsldHdlr = NULL; + } /* end of ICP_TRUE == ixSspAccInterruptMode */ + + return ICP_STATUS_SUCCESS; +} /* end of icp_SspAccTxFifoIntDisable */ + +icp_status_t +icp_SspAccLoopbackEnable ( + icp_boolean_t loopbackEnable) +{ + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccLoopbackEnable", ICP_STATUS_RESOURCE); + + /* Write the parameter into the loopback enable bit of SSCR1 register */ + ixSspAccCfgStored.sscr1 = + (ixSspAccCfgStored.sscr1 & (~IX_SSP_LOOPBACK_ENABLE_MASK)) | + (loopbackEnable << IX_SSP_LOOPBACK_ENABLE_LOC); + IX_SSP_WRITE_REGISTER (ixSspCR1Addr, ixSspAccCfgStored.sscr1); + + return ICP_STATUS_SUCCESS; +} /* end of icp_SspAccLoopbackEnable */ + +icp_status_t +icp_SspAccSpiSclkPolaritySet ( + icp_sspacc_spi_sclk_polarity_t spiSclkPolaritySelected) +{ + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccSpiSclkPolaritySet", + ICP_STATUS_RESOURCE); + + /* Check for validity of parameter */ + if(spiSclkPolaritySelected >= ICP_SSPACC_SPI_SCLK_POLARITY_TYPE_DELIMITER) + { + return ICP_STATUS_INVALID_PARAM; + } + + /* Write the parameter into the SPI SCLK Polarity bit of SSCR1 register */ + ixSspAccCfgStored.sscr1 = + (ixSspAccCfgStored.sscr1 & (~IX_SSP_SPI_SCLK_POLARITY_MASK)) | + (spiSclkPolaritySelected << IX_SSP_SPI_SCLK_POLARITY_LOC); + IX_SSP_WRITE_REGISTER (ixSspCR1Addr, ixSspAccCfgStored.sscr1); + + return ICP_STATUS_SUCCESS; +} /* end of icp_SspAccSpiSclkPolaritySet */ + +icp_status_t +icp_SspAccSpiSclkPhaseSet ( + icp_sspacc_spi_sclk_phase_t spiSclkPhaseSelected) +{ + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccSpiSclkPhaseSet", ICP_STATUS_RESOURCE); + + /* Check for validity of parameter */ + if(spiSclkPhaseSelected >= ICP_SSPACC_SPI_SCLK_PHASE_TYPE_DELIMITER) + { + return ICP_STATUS_INVALID_PARAM; + } + + /* Write the parameter into the SPI SCLK Phase bit of SSCR1 register */ + ixSspAccCfgStored.sscr1 = + (ixSspAccCfgStored.sscr1 & (~IX_SSP_SPI_SCLK_PHASE_MASK)) | + (spiSclkPhaseSelected << IX_SSP_SPI_SCLK_PHASE_LOC); + IX_SSP_WRITE_REGISTER (ixSspCR1Addr, ixSspAccCfgStored.sscr1); + + return ICP_STATUS_SUCCESS; +} /* end of icp_SspAccSpiSclkPhaseSet */ + +icp_status_t +icp_SspAccMicrowireControlWordSet ( + icp_sspacc_microwire_ctl_word_t microwireCtlWordSelected) +{ + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccMicrowireControlWordSet", + ICP_STATUS_RESOURCE); + + /* Check for validity of parameter */ + if(microwireCtlWordSelected >= + ICP_SSPACC_MICROWIRE_CTL_WORD_TYPE_DELIMITER) + { + return ICP_STATUS_INVALID_PARAM; + } + + /* Only allow change if Tx FIFO is empty */ + if(IX_SSP_FIFO_EMPTY != icp_SspAccTxFifoLevelGet()) + { + return ICP_STATUS_RESOURCE; + } + + /* Write the parameter into the Microwire Data Size bit of SSCR1 register*/ + ixSspAccCfgStored.sscr1 = + (ixSspAccCfgStored.sscr1 & (~IX_SSP_MICROWIRE_CTL_WORD_MASK)) | + (microwireCtlWordSelected << IX_SSP_MICROWIRE_CTL_WORD_LOC); + IX_SSP_WRITE_REGISTER (ixSspCR1Addr, ixSspAccCfgStored.sscr1); + + return ICP_STATUS_SUCCESS; +} /* end of icp_SspAccMicrowireControlWordSet */ + +icp_status_t +icp_SspAccTxFifoThresholdSet ( + icp_sspacc_fifo_threshold_t txFIFOThresholdSelected) +{ + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccTxFifoThresholdSet", + ICP_STATUS_RESOURCE); + + /* Check for validity of parameter */ + if(txFIFOThresholdSelected >= ICP_SSPACC_FIFO_TSHLD_TYPE_DELIMITER) + { + return ICP_STATUS_INVALID_PARAM; + } + + /* Write the parameter into the Tx FIFO threshold bits of SSCR1 register */ + ixSspAccCfgStored.sscr1 = + (ixSspAccCfgStored.sscr1 & (~IX_SSP_TX_FIFO_THLD_MASK)) | + (txFIFOThresholdSelected << IX_SSP_TX_FIFO_THLD_LOC); + IX_SSP_WRITE_REGISTER (ixSspCR1Addr, ixSspAccCfgStored.sscr1); + + return ICP_STATUS_SUCCESS; +} /* end of icp_SspAccTxFifoThresholdSet */ + +icp_status_t +icp_SspAccRxFifoThresholdSet ( + icp_sspacc_fifo_threshold_t rxFIFOThresholdSelected) +{ + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccRxFifoThresholdSet", + ICP_STATUS_RESOURCE); + + /* Check for validity of parameter */ + if(rxFIFOThresholdSelected >= ICP_SSPACC_FIFO_TSHLD_TYPE_DELIMITER) + { + return ICP_STATUS_INVALID_PARAM; + } + + /* Write the parameter into the Rx FIFO threshold bits of SSCR1 register */ + ixSspAccCfgStored.sscr1 = + (ixSspAccCfgStored.sscr1 & (~IX_SSP_RX_FIFO_THLD_MASK)) | + (rxFIFOThresholdSelected << IX_SSP_RX_FIFO_THLD_LOC); + IX_SSP_WRITE_REGISTER (ixSspCR1Addr, ixSspAccCfgStored.sscr1); + + return ICP_STATUS_SUCCESS; +} /* end of icp_SspAccRxFifoThresholdSet */ + +/** + * Debug functions + */ + +icp_status_t +icp_SspAccStatsGet ( + icp_sspacc_stats_counters_t *sspStats) +{ + if(NULL == sspStats) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, + "icp_SspAccStatsGet: stats pointer is NULL.\n", + 0,0,0,0,0,0); + return ICP_STATUS_NULL_PARAM; + } /* end of NULL == sspStats */ + /* Copy the SSP stats counters to the struct pointer passed in */ + sspStats->rcvCounter = ixSspAccStatsCounters.rcvCounter; + sspStats->xmitCounter = ixSspAccStatsCounters.xmitCounter; + sspStats->overflowCounter = ixSspAccStatsCounters.overflowCounter; + + return ICP_STATUS_SUCCESS; +} /* end of icp_SspAccStatsGet */ + +void +icp_SspAccStatsReset ( + void) +{ + /* Clear the SSP stats counters to zero */ + ixSspAccStatsCounters.rcvCounter = 0; + ixSspAccStatsCounters.xmitCounter = 0; + ixSspAccStatsCounters.overflowCounter = 0; + + return; +} /* end of icp_SspAccStatsReset */ + +icp_status_t +icp_SspAccShow ( + void) +{ + icp_sspacc_stats_counters_t sspStats; + uint8_t TxFIFOLevel; + uint8_t RxFIFOLevel; + + /* Disallow this function from running further if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccShow", ICP_STATUS_RESOURCE); + + /* Read and display the SSP status */ + ixSspAccStsStored = IX_SSP_READ_REGISTER (ixSspSRAddr); + + RxFIFOLevel = icp_SspAccRxFifoLevelGet(); + TxFIFOLevel = icp_SspAccTxFifoLevelGet(); + ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, + "Rx FIFO Level : %d\n", RxFIFOLevel,0,0,0,0,0); + ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, + "Tx FIFO Level : %d\n", TxFIFOLevel,0,0,0,0,0); + ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, + "1 = YES, 0 = NO\n",0,0,0,0,0,0); + ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, + "Rx FIFO Overrun: %d\n", ((ixSspAccStsStored & + IX_SSP_RX_FIFO_OVERRUN_MASK) >> IX_SSP_RX_FIFO_OVERRUN_LOC),0,0,0,0,0); + ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, + "SSP Busy: %d\n", ((ixSspAccStsStored & IX_SSP_BUSY_MASK) >> + IX_SSP_BUSY_LOC),0,0,0,0,0); + ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, + "Rx FIFO Threshold Hit or Above: %d\n", + ((ixSspAccStsStored & IX_SSP_RX_FIFO_SVC_REQ_MASK) >> + IX_SSP_RX_FIFO_SVC_REQ_LOC),0,0,0,0,0); + ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, + "Tx FIFO Threshold Hit or Below: %d\n", + ((ixSspAccStsStored & IX_SSP_TX_FIFO_SVC_REQ_MASK) >> + IX_SSP_TX_FIFO_SVC_REQ_LOC),0,0,0,0,0); + + /* Read and display the SSP stats counters */ + icp_SspAccStatsGet(&sspStats); + ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, + "SSP frames received : %d\n", sspStats.rcvCounter,0,0,0,0,0); + ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, + "SSP frames transmitted: %d\n", sspStats.xmitCounter,0,0,0,0,0); + ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, + "SSP overflow occurence: %d\n", sspStats.overflowCounter,0,0,0,0,0); + + return ICP_STATUS_SUCCESS; +} /* end of icp_SspAccShow */ + +icp_status_t +icp_SspAccSspIdleCheck ( + void) +{ + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccSspIdleCheck", ICP_STATUS_RESOURCE); + + /* Read the SSSR to determine the state of the SSP */ + ixSspAccStsStored = IX_SSP_READ_REGISTER (ixSspSRAddr); + /* Return the status of the SSP Port (busy or idle) */ + if(IX_SSP_IS_BUSY == + ((ixSspAccStsStored & IX_SSP_BUSY_MASK) >> IX_SSP_BUSY_LOC)) + { + return ICP_STATUS_FAIL; + } + else + { + return ICP_STATUS_SUCCESS; + } +} /* end of icp_SspAccSspIdleCheck */ + +uint8_t +icp_SspAccTxFifoLevelGet ( + void) +{ + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccTxFifoLevelGet", ICP_STATUS_RESOURCE); + + ixSspAccStsStored = IX_SSP_READ_REGISTER (ixSspSRAddr); + /* If the Tx FIFO level is non-zero, the value is the actual level */ + if(IX_SSP_FIFO_FULL_OR_EMPTY != + ((ixSspAccStsStored & IX_SSP_TX_FIFO_LVL_MASK) >> + IX_SSP_TX_FIFO_LVL_LOC)) + { + return ((ixSspAccStsStored & IX_SSP_TX_FIFO_LVL_MASK) >> + IX_SSP_TX_FIFO_LVL_LOC); + } + + /* If the Tx FIFO level is zero, the value can be 0 (empty) or 16 (full) + depending on the Tx FIFO Not Full bit */ + if(IX_SSP_TX_FIFO_FULL == + ((ixSspAccStsStored & IX_SSP_TX_FIFO_NOT_FULL_MASK) >> + IX_SSP_TX_FIFO_NOT_FULL_LOC)) + { + return IX_SSP_FIFO_FULL; + } + else + { + return IX_SSP_FIFO_EMPTY; + } +} /* end of icp_SspAccTxFifoLevelGet */ + +uint8_t +icp_SspAccRxFifoLevelGet ( + void) +{ + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccRxFifoLevelGet", ICP_STATUS_RESOURCE); + + ixSspAccStsStored = IX_SSP_READ_REGISTER (ixSspSRAddr); + /* If the Rx FIFO level is non-zero, the value is the actual level */ + if(IX_SSP_FIFO_FULL_OR_EMPTY != + ((((ixSspAccStsStored & IX_SSP_RX_FIFO_LVL_MASK) >> + IX_SSP_RX_FIFO_LVL_LOC) + 1) & 0xF)) + { + return (((ixSspAccStsStored & IX_SSP_RX_FIFO_LVL_MASK) >> + IX_SSP_RX_FIFO_LVL_LOC) + 1); + } + + /* If the Rx FIFO level is zero, the value can be 0 (empty) or 16 (full) + depending on the Rx FIFO Not Empty bit */ + if(IX_SSP_RX_FIFO_EMPTY == + ((ixSspAccStsStored & IX_SSP_RX_FIFO_NOT_EMPTY_MASK) >> + IX_SSP_RX_FIFO_NOT_EMPTY_LOC)) + { + return IX_SSP_FIFO_EMPTY; + } + else + { + return IX_SSP_FIFO_FULL; + } +} /* end of icp_SspAccRxFifoLevelGet */ + +icp_status_t +icp_SspAccRxFifoOverrunCheck( + void) +{ + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccRxFifoOverrunCheck", + ICP_STATUS_RESOURCE); + + ixSspAccStsStored = IX_SSP_READ_REGISTER (ixSspSRAddr); + /* Check if an overrun has occurred*/ + if(IX_SSP_OVERRUN_HAS_OCCURRED != + ((ixSspAccStsStored & IX_SSP_RX_FIFO_OVERRUN_MASK) >> + IX_SSP_RX_FIFO_OVERRUN_LOC)) + { + return ICP_STATUS_SUCCESS; + } + + /* Update the overrun stats counter */ + ixSspAccStatsCounters.overflowCounter++; + + /* Write 1 to clear the overrun bit */ + ixSspAccStsStored = IX_SSP_SET_TO_BE_CLEARED << IX_SSP_RX_FIFO_OVERRUN_LOC; + IX_SSP_WRITE_REGISTER (ixSspSRAddr, ixSspAccStsStored); + + return ICP_STATUS_FAIL; +} /* end of icp_SspAccRxFifoOverrunCheck */ + +/** + * @ingroup IxSspAcc + * + * @fn ixSspAccInterruptDetected ( + void); + * + * @brief The top level Interrupt Service Routine that is called when an SSP + * interrupt occurs + * + * @param - None + * + * This function is the interrupt service routine that is called when a SSP + * interrupt occurs. It will determine the source of the interrupt by checking + * the SSSR and call the appropriate handler - ixRxFIFOOverrunHdlr, + * ixRxFIFOThsldHdlr, or ixTxFIFOThsldHdlr + * + * @return + * - void + * + * @li Reentrant : no + * @li ISR Callable : yes + * + */ +PRIVATE void ixSspAccInterruptDetected ( + void) +{ + ixSspAccStsStored = IX_SSP_READ_REGISTER (ixSspSRAddr); + if(IX_SSP_INTERRUPTED == ((ixSspAccStsStored & + IX_SSP_RX_FIFO_OVERRUN_MASK) >> IX_SSP_RX_FIFO_OVERRUN_LOC)) + { + /* Increment the overrun counter */ + ixSspAccStatsCounters.overflowCounter++; + + /* Call the Rx FIFO Overrun handler registered in the IxSspInitVars */ + (*ixRxFIFOOverrunHdlr)(); + + /* Clear the overrun interrupt */ + ixSspAccStsStored = IX_SSP_SET_TO_BE_CLEARED << + IX_SSP_RX_FIFO_OVERRUN_LOC; + IX_SSP_WRITE_REGISTER (ixSspSRAddr, ixSspAccStsStored); + return; + } /* end of rxFIFOOverrun interrupt detected */ + + if((IX_SSP_INTERRUPTED == + ((ixSspAccStsStored & IX_SSP_RX_FIFO_SVC_REQ_MASK) >> + IX_SSP_RX_FIFO_SVC_REQ_LOC)) && (NULL != ixRxFIFOThsldHdlr)) + { + /* Call the Rx FIFO threshold handler registered through the function + ixSspAccInit or ixSspAccRxFIFOIntEnable */ + (*ixRxFIFOThsldHdlr)(); + return; + } /* end of rxFIFO interrupt detected */ + + if((IX_SSP_INTERRUPTED == + ((ixSspAccStsStored & IX_SSP_TX_FIFO_SVC_REQ_MASK) >> + IX_SSP_TX_FIFO_SVC_REQ_LOC)) && (NULL != ixTxFIFOThsldHdlr)) + { + /* Call the Tx FIFO threshold handler registered through the function + ixSspAccInit or ixSspAccTxFIFOIntEnable */ + (*ixTxFIFOThsldHdlr)(); + return; + } /* end of TxFIFO interrupt detected */ + + return; +} /* end of ixSspAccInterruptDetected */ + diff --git a/Acceleration/library/icp_telephony/ssp_access/icp_sspacc_symbols.c b/Acceleration/library/icp_telephony/ssp_access/icp_sspacc_symbols.c new file mode 100644 index 0000000..e3dd726 --- /dev/null +++ b/Acceleration/library/icp_telephony/ssp_access/icp_sspacc_symbols.c @@ -0,0 +1,103 @@ +/** + * @file icp_sspacc_symbols.c + * + * @description Contents of this file provide the Linux kernel symbols for + * Synchronous Serial Port (SSP) Access Library + * + * @ingroup icp_SspAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ +#include <linux/module.h> +#include "icp_sspacc.h" + +EXPORT_SYMBOL(icp_SspAccInterruptSet); +EXPORT_SYMBOL(icp_SspAccPhysicalAddressSet); +EXPORT_SYMBOL(icp_SspAccInit); +EXPORT_SYMBOL(icp_SspAccUninit); +EXPORT_SYMBOL(icp_SspAccFifoDataSubmit); +EXPORT_SYMBOL(icp_SspAccFifoDataReceive); +EXPORT_SYMBOL(icp_SspAccTxFifoHitLowThresholdCheck); +EXPORT_SYMBOL(icp_SspAccRxFifoHitHighThresholdCheck); +EXPORT_SYMBOL(icp_SspAccSspPortStatusSet); +EXPORT_SYMBOL(icp_SspAccFrameFormatSelect); +EXPORT_SYMBOL(icp_SspAccDataSizeSelect); +EXPORT_SYMBOL(icp_SspAccClockSourceSelect); +EXPORT_SYMBOL(icp_SspAccSerialClockRateConfigure); +EXPORT_SYMBOL(icp_SspAccRxFifoIntEnable); +EXPORT_SYMBOL(icp_SspAccRxFifoIntDisable); +EXPORT_SYMBOL(icp_SspAccTxFifoIntEnable); +EXPORT_SYMBOL(icp_SspAccTxFifoIntDisable); +EXPORT_SYMBOL(icp_SspAccLoopbackEnable); +EXPORT_SYMBOL(icp_SspAccSpiSclkPolaritySet); +EXPORT_SYMBOL(icp_SspAccSpiSclkPhaseSet); +EXPORT_SYMBOL(icp_SspAccMicrowireControlWordSet); +EXPORT_SYMBOL(icp_SspAccTxFifoThresholdSet); +EXPORT_SYMBOL(icp_SspAccRxFifoThresholdSet); +EXPORT_SYMBOL(icp_SspAccStatsGet); +EXPORT_SYMBOL(icp_SspAccStatsReset); +EXPORT_SYMBOL(icp_SspAccShow); +EXPORT_SYMBOL(icp_SspAccSspIdleCheck); +EXPORT_SYMBOL(icp_SspAccTxFifoLevelGet); +EXPORT_SYMBOL(icp_SspAccRxFifoLevelGet); +EXPORT_SYMBOL(icp_SspAccRxFifoOverrunCheck); + diff --git a/Acceleration/library/icp_telephony/ssp_access/linux_2.6_kernel_space.mk b/Acceleration/library/icp_telephony/ssp_access/linux_2.6_kernel_space.mk new file mode 100644 index 0000000..91ac681 --- /dev/null +++ b/Acceleration/library/icp_telephony/ssp_access/linux_2.6_kernel_space.mk @@ -0,0 +1,74 @@ +################### +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# +################### + +#specific include directories in kernel space +INCLUDES+= -I $(ICP_OSAL_DIR)/platforms/EP805XX/include \ + -I $(ICP_OSAL_DIR)/platforms/EP805XX/os/linux/include \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/core \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules/ddk \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules/ioMem + +#Extra Flags Specific in kernel space e.g. include path or debug flags etc. e.g to add an include path EXTRA_CFLAGS += -I$(src)/../include +EXTRA_CFLAGS += $(INCLUDES) -DTOLAPAI -D__tolapai -DIX_HW_COHERENT_MEMORY=1 +EXTRA_LDFLAGS+=-whole-archive + + diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/Makefile b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/Makefile new file mode 100644 index 0000000..c0321a7 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/Makefile @@ -0,0 +1,148 @@ +######################################################################### +# This Template Makefile will create the libraries, executables and module and place them in the output folder +# Remove the comments around the sections you wish to build for. +# +#Procedure +#1) Copy this template to the location of your source files +#2) "Common variables and defintions" must be filled out +#3) Edit as desired the "Libraries and executable section" and/or the "Linux kernel 2.6 Module section" depending on what you wish to build +#4) Remove the comments around the section and delete the other unnecessary section +#5) Save changes, return to command line and type "make". +# +# +# Targets supported +# all - builds everything and installs +# install - identical to all +# depend - build dependencies +# clean - clears all derived objects +# +# included makefiles +# common.mk - common defintions +# depend.mk - depend and cleandepend rules +# rules.mk - build rules. +# +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# Contact Information: +# Intel Corporation +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# +############################################################################ + +# Ensure The ICP_ENV_DIR environmental var is defined. +ifndef ICP_ENV_DIR +$(error ICP_ENV_DIR is undefined. Please set the path to your environment makefile \ + "-> setenv ICP_ENV_DIR <path>") +endif + +# Ensure The ICP_BUILDSYSTEM_PATH envorionmental var is defined. +ifndef ICP_BUILDSYSTEM_PATH +$(error ICP_BUILDSYSTEM_PATH is undefined. Please set the path to the top of the build structure \ + "-> setenv ICP_BUILDSYSTEM_PATH <path>") +endif + +#Add your project environment Makefile, extra comment +include $(ICP_ENV_DIR)/environment.mk + +#include the makefile with all the default and common Make variable definitions +include $(ICP_BUILDSYSTEM_PATH)/build_files/common.mk + +#Add the name for the executable, Library or Module output definitions +OUTPUT_NAME=$(ICP_TDM_DL_NAME) + +# List of Source Files to be compiled (to be in a single line or on different lines separated by a "\" and tab. +SOURCES = source/IxPiuDl.c \ + source/IxPiuDlImageMgr.c \ + source/IxPiuDlPiuMgr.c \ + source/IxPiuDlPiuMgrUtils.c \ + + +# Setup include directory +INCLUDES += -I $(src)/include \ + -I $(PWD)/include \ + -I $(ICP_API_DIR) \ + -I $(ICP_API_DIR)/accel_infra \ + -I $(ICP_NPEDL_DIR)/../include \ + -I $(ICP_NPEFW_DIR)/src \ + -I $(ICP_OSAL_DIR)/common/include \ + -I $(ICP_OSAL_DIR)/common/ossl_shim/linux_kernel/include \ + +ifeq ($(ICP_INTEL_DEV),YES) +INCLUDES += -I $(ICP_OSAL_DIR)/common/include/modules \ + -I $(ICP_OSAL_DIR)/common/include/modules/ddk \ + -I $(ICP_OSAL_DIR)/common/include/modules/bufferMgt \ + -I $(ICP_OSAL_DIR)/common/include/modules/ioMem +endif + +EXTRA_CFLAGS += -DENABLE_IOMEM -DENABLE_BUFFERMGT + +ifndef IX_INCLUDE_MICROCODE +SOURCES += source/IxPiuDlFwLoader.c +EXTRA_CFLAGS += -DIX_PIUDL_READ_MICROCODE_FROM_FILE +endif + + +#include your $(ICP_OS)_$(ICP_OS_LEVEL).mk file +include $(ICP_TDM_DL_DIR)/$(ICP_OS)_$(ICP_OS_LEVEL).mk + +# Install the module to the output dir +install: module + + +###################Include rules and dependency makefiles######################## +include $(ICP_BUILDSYSTEM_PATH)/build_files/rules.mk +###################End of Rules and dependency inclusion######################### + diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlFwLoader_p.h b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlFwLoader_p.h new file mode 100644 index 0000000..5ca9e9e --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlFwLoader_p.h @@ -0,0 +1,131 @@ +/** + * @file IxPiuDlFwLoader_p.h + * + * @date 25 June 2007 + + * @brief This file contains the API for reading PIU firmware from file using + * the 'request_firmware' loading mechanism available in Linux kernel v2.6 + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +/** + * @defgroup IxPiuDlFwLoader_p IxPiuDlFwLoader_p + * + * @brief header file for loading firmware from file + * + * @{ + */ + +#ifndef IXPIUDLFWLOADER_P_H +#define IXPIUDLFWLOADER_P_H + +/* + * Put the user defined include files required + */ +#include "IxPiuDl.h" + +/* + * Prototypes for interface functions + */ + +/** + * @fn ix_error ixPiuDlFwLoaderGetFw (ix_uint32** firmwareArray) + * + * @brief This function loads an PIU firmware image from a file + * + * @param ix_uint32[out] firmwareArray - pointer to pointer to hold loaded + * firmware image + + * This function uses the firmware loading mechanism available in Linux kernel + * v2.6 to read a firmware file into kernel space memory + * + * @return + * - IX_SUCCESS if the file was loaded successfully + * - IX_FAIL if the firmware load failed + */ +ix_error +ixPiuDlFwLoaderGetFw(ix_uint32** firmwareArray); + +/** + * @fn ix_error ixPiuDlFwLoaderCleanup (void) + * + * @brief This function performs cleanup following loading an PIU firmware + * image from a file + * + * This function performs cleanup after loading PIU firmware which has used the + * loading mechanism available in Linux kernel v2.6 to read a firmware file + * into kernel space memory + * + * @return + * - nothing + */ +void +ixPiuDlFwLoaderCleanup(void); + +#endif /* IXPIUDLFWLOADER_P_H */ + +/** + * @} defgroup IxPiuDlFwLoader_p + */ + + diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlImageMgr_p.h b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlImageMgr_p.h new file mode 100644 index 0000000..361b893 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlImageMgr_p.h @@ -0,0 +1,339 @@ +/** + * @file IxPiuDlImageMgr_p.h + * + * @author Intel Corporation + * @date 13 August 2003 + + * @brief This file contains the private API for the ImageMgr module + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + +/** + * @defgroup IxPiuDlImageMgr_p IxPiuDlImageMgr_p + * + * @brief The private API for the IxPiuDl ImageMgr module + * + * @{ + */ + +#ifndef IXPIUDLIMAGEMGR_P_H +#define IXPIUDLIMAGEMGR_P_H + + +/* + * Put the user defined include files required. + */ +#include "IxPiuDl.h" + + +/* + * #defines and macros + */ + +/** + * @def IX_PIUDL_IMAGEMGR_SIGNATURE + * + * @brief Signature found as 1st word in a microcode image library + */ +#define IX_PIUDL_IMAGEMGR_SIGNATURE 0xFEEDF00D + +/** + * @def IX_PIUDL_IMAGEMGR_END_OF_HEADER + * + * @brief Marks end of header in a microcode image library + */ +#define IX_PIUDL_IMAGEMGR_END_OF_HEADER 0xFFFFFFFF + +/** + * @def IX_PIUDL_IMAGEID_PIUID_OFFSET + * + * @brief Offset from LSB of PIU ID field in Image ID + */ +#define IX_PIUDL_IMAGEID_PIUID_OFFSET 25 + +/** + * @def IX_PIUDL_IMAGEID_PIUCODE_OFFSET + * + * @brief Offset from LSB of PIU CODE (PIU ID+ Chip architecture) field in Image ID + */ +#define IX_PIUDL_IMAGEID_PIUCODE_OFFSET 24 + +/** + * @def IX_PIUDL_IMAGEID_FUNCTIONID_OFFSET + * + * @brief Offset from LSB of Functionality ID field in Image ID + */ +#define IX_PIUDL_IMAGEID_FUNCTIONID_OFFSET 16 + +/** + * @def IX_PIUDL_IMAGEID_MAJOR_OFFSET + * + * @brief Offset from LSB of Major revision field in Image ID + */ +#define IX_PIUDL_IMAGEID_MAJOR_OFFSET 8 + +/** + * @def IX_PIUDL_IMAGEID_MINOR_OFFSET + * + * @brief Offset from LSB of Minor revision field in Image ID + */ +#define IX_PIUDL_IMAGEID_MINOR_OFFSET 0 + + +/** + * @def IX_PIUDL_PIUIMAGE_FIELD_MASK + * + * @brief Mask for PIU Image ID's Field + * + */ +#define IX_PIUDL_PIUIMAGE_FIELD_MASK 0xff + +/** + * @def IX_PIUDL_PIUIMAGE_PIUID_MASK + * + * @brief Mask for PIU Image ID's PIU ID Field + * + */ +#define IX_PIUDL_PIUIMAGE_PIUID_MASK 0x07 + +/** + * @def IX_PIUDL_PIUID_FROM_IMAGEID_GET + * + * @brief Macro to extract PIU ID field from Image ID + */ +#define IX_PIUDL_PIUID_FROM_IMAGEID_GET(imageId) \ + (((imageId) >> IX_PIUDL_IMAGEID_PIUID_OFFSET) & \ + IX_PIUDL_PIUIMAGE_PIUID_MASK) + +/** + * @def IX_PIUDL_FUNCTIONID_FROM_IMAGEID_GET + * + * @brief Macro to extract Functionality ID field from Image ID + */ +#define IX_PIUDL_FUNCTIONID_FROM_IMAGEID_GET(imageId) \ + (((imageId) >> IX_PIUDL_IMAGEID_FUNCTIONID_OFFSET) & \ + IX_PIUDL_PIUIMAGE_FIELD_MASK) + +/** + * @def IX_PIUDL_MAJOR_FROM_IMAGEID_GET + * + * @brief Macro to extract Major revision field from Image ID + */ +#define IX_PIUDL_MAJOR_FROM_IMAGEID_GET(imageId) \ + (((imageId) >> IX_PIUDL_IMAGEID_MAJOR_OFFSET) & \ + IX_PIUDL_PIUIMAGE_FIELD_MASK) + +/** + * @def IX_PIUDL_MINOR_FROM_IMAGEID_GET + * + * @brief Macro to extract Minor revision field from Image ID + */ +#define IX_PIUDL_MINOR_FROM_IMAGEID_GET(imageId) \ + (((imageId) >> IX_PIUDL_IMAGEID_MINOR_OFFSET) & \ + IX_PIUDL_PIUIMAGE_FIELD_MASK) + +/** + * @def IX_PIUDL_IMAGEID_FROM_STRUCT_GET + * + * @brief Macro to combine Image Id fields into a uint32 + */ +#define IX_PIUDL_IMAGEID_FROM_STRUCT_GET(imageId) \ + (((imageId).piuId << IX_PIUDL_IMAGEID_PIUID_OFFSET) | \ + ((imageId).functionalityId << IX_PIUDL_IMAGEID_FUNCTIONID_OFFSET) | \ + ((imageId).major << IX_PIUDL_IMAGEID_MAJOR_OFFSET) | \ + ((imageId).minor << IX_PIUDL_IMAGEID_MINOR_OFFSET)) + + +/* + * Prototypes for interface functions + */ + + + + +/** + * @fn void ixPiuDlImageMgrStatsShow (void) + * + * @brief This function will display the statistics of the IxPiuDl ImageMgr + * module + * + * @return none + */ +void +ixPiuDlImageMgrStatsShow (void); + + +/** + * @fn void ixPiuDlImageMgrStatsReset (void) + * + * @brief This function will reset the statistics of the IxPiuDl ImageMgr + * module + * + * @return none + */ +void +ixPiuDlImageMgrStatsReset (void); + + +/** + * @fn ix_error ixPiuDlImageMgrImageFind (ix_uint32 *imageLibrary, + ix_uint32 imageId, + ix_uint32 **imagePtr, + ix_uint32 *imageSize) + * + * @brief Finds a image block in the PIU microcode image library. + * + * @param ix_uint32* [in] imageLibrary - the image library to use + * @param ix_uint32 [in] imageId - the id of the image to locate + * @param ix_uint32** [out] imagePtr - pointer to the image in memory + * @param ix_uint32* [out] imageSize - size (in 32-bit words) of image + * + * This function examines the header of the specified microcode image library + * for the location and size of the specified image. It returns a pointer to + * the image in the <i>imagePtr</i> parameter. + * If no image library is specified (imageLibrary == NULL), then the default + * built-in image library will be used. + * + * @pre + * + * @post + * + * @return + * - IX_SUCCESS if the operation was successful + * - IX_FAIL otherwise + */ +ix_error +ixPiuDlImageMgrImageFind (ix_uint32 *imageLibrary, + ix_uint32 imageId, + ix_uint32 **imagePtr, + ix_uint32 *imageSize); + + + +/** + * @fn ix_error ixPiuDlImageMgrImageListExtract (IxPiuDlImageId *imageListPtr, + ix_uint32 *numImages) + * + * @brief Extracts a list of images available in the PIU microcode image library. + * + * @param IxPiuDlImageId* [out] imageListPtr - pointer to array to contain + * a list of images. If NULL, + * only the number of images + * is returned (in + * <i>numImages</i>) + * @param ix_uint32* [inout] numImages - As input, it points to a variable + * containing the number of images which + * can be stored in the + * <i>imageListPtr</i> array. Its value + * is ignored as input if + * <i>imageListPtr</i> is NULL. As an + * output, it will contain number of + * images in the image library. + * + * This function reads the header of the microcode image library and extracts a list of the + * images available in the image library. It can also be used to find the number of + * images in the image library. + * + * + * @pre + * - if <i>imageListPtr</i> != NULL, <i>numImages</i> should reflect the + * number of image Id elements the <i>imageListPtr</i> can contain. + * + * @post + * - <i>numImages</i> will reflect the number of image Id's found in the + * microcode image library. + * + * @return + * - IX_SUCCESS if the operation was successful + * - IX_FAIL otherwise + */ +ix_error +ixPiuDlImageMgrImageListExtract (IxPiuDlImageId *imageListPtr, + ix_uint32 *numImages); + + + +/** + * @fn void ixPiuDlImageMgrImageIdFormat (ix_uint32 rawImageId, + IxPiuDlImageId *imageId) + * + * @brief Converts a raw image Id (uint32) to the PIU Dl structure. + * + * @param ix_uint32 [in] rawImageId - the raw image Id to be converted + * @param IxPiuDlImageId [out] *imageId - placeholder for the converted Id. + * + * + * @return + * - IX_SUCCESS if the operation was successful + * - IX_FAIL otherwise + */ + +void +ixPiuDlImageMgrImageIdFormat ( + ix_uint32 rawImageId, + IxPiuDlImageId *imageId); +#endif /* IXPIUDLIMAGEMGR_P_H */ + +/** + * @} defgroup IxPiuDlImageMgr_p + */ diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlMacros_p.h b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlMacros_p.h new file mode 100644 index 0000000..252ba7c --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlMacros_p.h @@ -0,0 +1,287 @@ +/** + * @file IxPiuDlMacros_p.h + * + * @author Intel Corporation + * @date 13 August 2003 + * + * @brief This file contains the macros for the IxPiuDl component. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + +/** + * @defgroup IxPiuDlMacros_p IxPiuDlMacros_p + * + * @brief Macros for the IxPiuDl component. + * + * @{ + */ + +#ifndef IXPIUDLMACROS_P_H +#define IXPIUDLMACROS_P_H + + +/* + * Put the user defined include files required. + */ + + +#include "IxOsal.h" +#ifdef __KERNEL__ +#define printf printk +#endif + + + +/* + * Typedefs + */ + +/** + * @typedef IxPiuDlTraceTypes + * @brief Enumeration defining IxPiuDl trace levels + */ +typedef enum +{ + IX_PIUDL_TRACE_OFF, /**< no trace */ + IX_PIUDL_DEBUG, /**< debug */ + IX_PIUDL_FN_ENTRY_EXIT /**< function entry/exit */ +} IxPiuDlTraceTypes; + + +/* + * #defines and macros. + */ + +/* Implementation of the following macros for use with IxPiuDl unit test code */ + +/* Implementation of the following macros when integrated with IxOsal */ + +/** + * @def IX_PIUDL_TRACE_LEVEL + * + * @brief IxPiuDl debug trace level + */ +#define IX_PIUDL_TRACE_LEVEL IX_PIUDL_TRACE_OFF + +/** + * @def IX_PIUDL_ERROR_REPORT + * + * @brief Mechanism for reporting IxPiuDl software errors + * + * @param char* [in] STR - Error string to report + * + * This macro is used to report IxPiuDl software errors. + * + * @return none + */ +#define IX_PIUDL_ERROR_REPORT(STR) \ + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, STR, \ + 0, 0, 0, 0, 0, 0); + +/** + * @def IX_PIUDL_WARNING_REPORT + * + * @brief Mechanism for reporting IxPiuDl software warnings + * + * @param char* [in] STR - Warning string to report + * + * This macro is used to report IxPiuDl software warnings. + * + * @return none + */ +#define IX_PIUDL_WARNING_REPORT(STR) \ + ixOsalLog (IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDOUT, STR, \ + 0, 0, 0, 0, 0, 0); + + +/** + * @def IX_PIUDL_TRACE0 + * + * @brief Mechanism for tracing debug for the IxPiuDl component, for no arguments + * + * @param unsigned [in] LEVEL - one of IxPiuDlTraceTypes enumerated values + * @param char* [in] STR - Trace string + * + * This macro simply prints the trace string passed, if the level is supported. + * + * @return none + */ +#define IX_PIUDL_TRACE0(LEVEL, STR) \ +do { \ + if (LEVEL <= IX_PIUDL_TRACE_LEVEL) \ + { \ + if (LEVEL == IX_PIUDL_FN_ENTRY_EXIT) \ + { \ + ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3, IX_OSAL_LOG_DEV_STDOUT, STR, \ + 0, 0, 0, 0, 0, 0); \ + } \ + else if (LEVEL == IX_PIUDL_DEBUG) \ + { \ + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, STR, \ + 0, 0, 0, 0, 0, 0); \ + } \ + } \ +} while(0) + +/** + * @def IX_PIUDL_TRACE1 + * + * @brief Mechanism for tracing debug for the IxPiuDl component, with 1 argument + * + * @param unsigned [in] LEVEL - one of IxPiuDlTraceTypes enumerated values + * @param char* [in] STR - Trace string + * @param argType [in] ARG1 - Argument to trace + * + * This macro simply prints the trace string passed, if the level is supported. + * + * @return none + */ +#define IX_PIUDL_TRACE1(LEVEL, STR, ARG1) \ +do { \ + if (LEVEL <= IX_PIUDL_TRACE_LEVEL) \ + { \ + if (LEVEL == IX_PIUDL_FN_ENTRY_EXIT) \ + { \ + ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3, IX_OSAL_LOG_DEV_STDOUT, STR, \ + ARG1, 0, 0, 0, 0, 0); \ + } \ + else if (LEVEL == IX_PIUDL_DEBUG) \ + { \ + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, STR, \ + ARG1, 0, 0, 0, 0, 0); \ + } \ + } \ +} while(0) + +/** + * @def IX_PIUDL_TRACE2 + * + * @brief Mechanism for tracing debug for the IxPiuDl component, with 2 arguments + * + * @param unsigned [in] LEVEL - one of IxPiuDlTraceTypes enumerated values + * @param char* [in] STR - Trace string + * @param argType [in] ARG1 - Argument to trace + * @param argType [in] ARG2 - Argument to trace + * + * This macro simply prints the trace string passed, if the level is supported. + * + * @return none + */ +#define IX_PIUDL_TRACE2(LEVEL, STR, ARG1, ARG2) \ +do { \ + if (LEVEL <= IX_PIUDL_TRACE_LEVEL) \ + { \ + if (LEVEL == IX_PIUDL_FN_ENTRY_EXIT) \ + { \ + ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3, IX_OSAL_LOG_DEV_STDOUT, STR, \ + ARG1, ARG2, 0, 0, 0, 0); \ + } \ + else if (LEVEL == IX_PIUDL_DEBUG) \ + { \ + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, STR, \ + ARG1, ARG2, 0, 0, 0, 0); \ + } \ + } \ +} while(0) + +/** + * @def IX_PIUDL_REG_WRITE + * + * @brief Mechanism for writing to a memory-mapped register + * + * @param ix_uint32 [in] base - Base memory address for this PIU's registers + * @param ix_uint32 [in] offset - Offset from base memory address + * @param ix_uint32 [in] value - Value to write to register + * + * This macro forms the address of the register from base address + offset, and + * dereferences that address to write the contents of the register. + * + * @return none + */ +#define IX_PIUDL_REG_WRITE(base, offset, value) \ + (*((volatile ix_uint32*)((base) + (offset))) = value) + + +/** + * @def IX_PIUDL_REG_READ + * + * @brief Mechanism for reading from a memory-mapped register + * + * @param ix_uint32 [in] base - Base memory address for this PIU's registers + * @param ix_uint32 [in] offset - Offset from base memory address + * @param ix_uint32 *[out] value - Value read from register + * + * This macro forms the address of the register from base address + offset, and + * dereferences that address to read the register contents. + * + * @return none + */ +#define IX_PIUDL_REG_READ(base, offset, valuePtr) \ + (*(valuePtr) = *((volatile ix_uint32*)((base) + (offset)))) + + +#endif /* IXPIUDLMACROS_P_H */ + +/** + * @} defgroup IxPiuDlMacros_p + */ diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlPiuMgrEcRegisters_p.h b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlPiuMgrEcRegisters_p.h new file mode 100644 index 0000000..3a8351b --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlPiuMgrEcRegisters_p.h @@ -0,0 +1,982 @@ +/** + * @file IxPiuDlPiuMgrEcRegisters_p.h + * + * @author Intel Corporation + * @date 13 August 2003 + + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + + +#ifndef IXPIUDLPIUMGRECREGISTERS_P_H +#define IXPIUDLPIUMGRECREGISTERS_P_H + +/* + * Put the system defined include files required. + */ + +#if defined(__linux) +#if !defined(__ep805xx) +#include <asm/hardware.h> +#endif +#endif + +/* + * Put the user defined include files required. + */ + + +/* + * Instruction Memory Size (in words) for each PIU + */ + +#define IX_PIUDL_PIUBASEADDRESS_PIU0_MAP(phys)\ +IX_OSAL_MEM_MAP((phys),0) + +#define IX_PIUDL_PIUBASEADDRESS_PIU1_MAP(phys)\ +IX_OSAL_MEM_MAP((phys),0) + +#define IX_PIUDL_PIUBASEADDRESS_UNMAP(virt)\ +IX_OSAL_MEM_UNMAP((virt)) + + + + + +/** + * @def IX_PIUDL_INS_MEMSIZE_WORDS_PIU0 + * @brief Size (in words) of PIU-0 Instruction Memory + */ +#if defined(__ep805xx) +#define IX_PIUDL_INS_MEMSIZE_WORDS_PIU0 (8192) +#else +#define IX_PIUDL_INS_MEMSIZE_WORDS_PIU0 (4096) +#endif + +/** + * @def IX_PIUDL_INS_MEMSIZE_WORDS_PIU1 + * @brief Size (in words) of PIU-1 Instruction Memory + */ +#define IX_PIUDL_INS_MEMSIZE_WORDS_PIU1 (4096) + + +/* + * Data Memory Size (in words) for each PIU + */ + +/** + * @def IX_PIUDL_DATA_MEMSIZE_WORDS_PIU0 + * @brief Size (in words) of PIU-0 Data Memory + */ +#define IX_PIUDL_DATA_MEMSIZE_WORDS_PIU0 (8192) + +/** + * @def IX_PIUDL_DATA_MEMSIZE_WORDS_PIU1 + * @brief Size (in words) of PIU-1 Data Memory + */ +#define IX_PIUDL_DATA_MEMSIZE_WORDS_PIU1 (4096) + + +/* + * Configuration Bus Register offsets (in bytes) from PIU Base Address + */ + +/** + * @def IX_PIUDL_REG_OFFSET_EXAD + * @brief Offset (in bytes) of EXAD (Execution Address) register from PIU Base + * Address + */ +#define IX_PIUDL_REG_OFFSET_EXAD (0x00000000) + +/** + * @def IX_PIUDL_REG_OFFSET_EXDATA + * @brief Offset (in bytes) of EXDATA (Execution Data) register from PIU Base + * Address + */ +#define IX_PIUDL_REG_OFFSET_EXDATA (0x00000004) + +/** + * @def IX_PIUDL_REG_OFFSET_EXCTL + * @brief Offset (in bytes) of EXCTL (Execution Control) register from PIU Base + * Address + */ +#define IX_PIUDL_REG_OFFSET_EXCTL (0x00000008) + +/** + * @def IX_PIUDL_REG_OFFSET_EXCT + * @brief Offset (in bytes) of EXCT (Execution Count) register from PIU Base + * Address + */ +#define IX_PIUDL_REG_OFFSET_EXCT (0x0000000C) + +/** + * @def IX_PIUDL_REG_OFFSET_AP0 + * @brief Offset (in bytes) of AP0 (Action Point 0) register from PIU Base + * Address + */ +#define IX_PIUDL_REG_OFFSET_AP0 (0x00000010) + +/** + * @def IX_PIUDL_REG_OFFSET_AP1 + * @brief Offset (in bytes) of AP1 (Action Point 1) register from PIU Base + * Address + */ +#define IX_PIUDL_REG_OFFSET_AP1 (0x00000014) + +/** + * @def IX_PIUDL_REG_OFFSET_AP2 + * @brief Offset (in bytes) of AP2 (Action Point 2) register from PIU Base + * Address + */ +#define IX_PIUDL_REG_OFFSET_AP2 (0x00000018) + +/** + * @def IX_PIUDL_REG_OFFSET_AP3 + * @brief Offset (in bytes) of AP3 (Action Point 3) register from PIU Base + * Address + */ +#define IX_PIUDL_REG_OFFSET_AP3 (0x0000001C) + +/** + * @def IX_PIUDL_REG_OFFSET_WFIFO + * @brief Offset (in bytes) of WFIFO (Watchpoint FIFO) register from PIU Base + * Address + */ +#define IX_PIUDL_REG_OFFSET_WFIFO (0x00000020) + +/** + * @def IX_PIUDL_REG_OFFSET_WC + * @brief Offset (in bytes) of WC (Watch Count) register from PIU Base + * Address + */ +#define IX_PIUDL_REG_OFFSET_WC (0x00000024) + +/** + * @def IX_PIUDL_REG_OFFSET_PROFCT + * @brief Offset (in bytes) of PROFCT (Profile Count) register from PIU Base + * Address + */ +#define IX_PIUDL_REG_OFFSET_PROFCT (0x00000028) + +/** + * @def IX_PIUDL_REG_OFFSET_STAT + * @brief Offset (in bytes) of STAT (Messaging Status) register from PIU Base + * Address + */ +#define IX_PIUDL_REG_OFFSET_STAT (0x0000002C) + +/** + * @def IX_PIUDL_REG_OFFSET_CTL + * @brief Offset (in bytes) of CTL (Messaging Control) register from PIU Base + * Address + */ +#define IX_PIUDL_REG_OFFSET_CTL (0x00000030) + +/** + * @def IX_PIUDL_REG_OFFSET_MBST + * @brief Offset (in bytes) of MBST (Mailbox Status) register from PIU Base + * Address + */ +#define IX_PIUDL_REG_OFFSET_MBST (0x00000034) + +/** + * @def IX_PIUDL_REG_OFFSET_FIFO + * @brief Offset (in bytes) of FIFO (messaging in/out FIFO) register from PIU + * Base Address + */ +#define IX_PIUDL_REG_OFFSET_FIFO (0x00000038) + + +/* + * Non-zero reset values for the Configuration Bus registers + */ + +/** + * @def IX_PIUDL_REG_RESET_FIFO + * @brief Reset value for Mailbox (MBST) register + * NOTE that if used, it should be complemented with an PIU intruction + * to clear the Mailbox at the PIU side as well + */ +#define IX_PIUDL_REG_RESET_MBST (0x0000F0F0) + + +/* + * Bit-masks used to read/write particular bits in Configuration Bus registers + */ + +/** + * @def IX_PIUDL_MASK_WFIFO_VALID + * @brief Masks the VALID bit in the WFIFO register + */ +#define IX_PIUDL_MASK_WFIFO_VALID (0x80000000) + +/** + * @def IX_PIUDL_MASK_STAT_OFNE + * @brief Masks the OFNE bit in the STAT register + */ +#define IX_PIUDL_MASK_STAT_OFNE (0x00010000) + +/** + * @def IX_PIUDL_MASK_STAT_IFNE + * @brief Masks the IFNE bit in the STAT register + */ +#define IX_PIUDL_MASK_STAT_IFNE (0x00080000) + + +/* + * EXCTL (Execution Control) Register commands +*/ + +/** + * @def IX_PIUDL_EXCTL_CMD_PIU_STEP + * @brief EXCTL Command to Step execution of an PIU Instruction + */ + +#define IX_PIUDL_EXCTL_CMD_PIU_STEP (0x01) + +/** + * @def IX_PIUDL_EXCTL_CMD_PIU_START + * @brief EXCTL Command to Start PIU execution + */ +#define IX_PIUDL_EXCTL_CMD_PIU_START (0x02) + +/** + * @def IX_PIUDL_EXCTL_CMD_PIU_STOP + * @brief EXCTL Command to Stop PIU execution + */ +#define IX_PIUDL_EXCTL_CMD_PIU_STOP (0x03) + +/** + * @def IX_PIUDL_EXCTL_CMD_CLR_TRIGGER + * @brief EXCTL Command to clear TRIGGER interrupt event source + */ +#define IX_PIUDL_EXCTL_CMD_CLR_TRIGGER (0x0d) + +/** + * @def IX_PIUDL_EXCTL_CMD_PIU_CLR_PIPE + * @brief EXCTL Command to Clear PIU instruction pipeline + */ +#define IX_PIUDL_EXCTL_CMD_PIU_CLR_PIPE (0x04) + +/** + * @def IX_PIUDL_EXCTL_CMD_RD_INS_MEM + * @brief EXCTL Command to read PIU instruction memory at address in EXAD + * register and return value in EXDATA register + */ +#define IX_PIUDL_EXCTL_CMD_RD_INS_MEM (0x10) + +/** + * @def IX_PIUDL_EXCTL_CMD_WR_INS_MEM + * @brief EXCTL Command to write PIU instruction memory at address in EXAD + * register with data in EXDATA register + */ +#define IX_PIUDL_EXCTL_CMD_WR_INS_MEM (0x11) + +/** + * @def IX_PIUDL_EXCTL_CMD_RD_DATA_MEM + * @brief EXCTL Command to read PIU data memory at address in EXAD + * register and return value in EXDATA register + */ +#define IX_PIUDL_EXCTL_CMD_RD_DATA_MEM (0x12) + +/** + * @def IX_PIUDL_EXCTL_CMD_WR_DATA_MEM + * @brief EXCTL Command to write PIU data memory at address in EXAD + * register with data in EXDATA register + */ +#define IX_PIUDL_EXCTL_CMD_WR_DATA_MEM (0x13) + +/** + * @def IX_PIUDL_EXCTL_CMD_RD_ECS_REG + * @brief EXCTL Command to read Execution Access register at address in EXAD + * register and return value in EXDATA register + */ +#define IX_PIUDL_EXCTL_CMD_RD_ECS_REG (0x14) + +/** + * @def IX_PIUDL_EXCTL_CMD_WR_ECS_REG + * @brief EXCTL Command to write Execution Access register at address in EXAD + * register with data in EXDATA register + */ +#define IX_PIUDL_EXCTL_CMD_WR_ECS_REG (0x15) + +/** + * @def IX_PIUDL_EXCTL_CMD_CLR_PROFILE_CNT + * @brief EXCTL Command to clear Profile Count register + */ +#define IX_PIUDL_EXCTL_CMD_CLR_PROFILE_CNT (0x0C) + + +/* + * EXCTL (Execution Control) Register status bit masks + */ + +/** + * @def IX_PIUDL_EXCTL_STATUS_RUN + * @brief Masks the RUN status bit in the EXCTL register + */ +#define IX_PIUDL_EXCTL_STATUS_RUN (0x80000000) + +/** + * @def IX_PIUDL_EXCTL_STATUS_STOP + * @brief Masks the STOP status bit in the EXCTL register + */ +#define IX_PIUDL_EXCTL_STATUS_STOP (0x40000000) + +/** + * @def IX_PIUDL_EXCTL_STATUS_CLEAR + * @brief Masks the CLEAR status bit in the EXCTL register + */ +#define IX_PIUDL_EXCTL_STATUS_CLEAR (0x20000000) + +/** + * @def IX_PIUDL_EXCTL_STATUS_ECS_K + * @brief Masks the K (pipeline Klean) status bit in the EXCTL register + */ +#define IX_PIUDL_EXCTL_STATUS_ECS_K (0x00800000) + + +/* + * Executing Context Stack (ECS) level registers + */ + +/** + * @def IX_PIUDL_ECS_BG_CTXT_REG_0 + * @brief Execution Access register address for register 0 at Backgound + * Executing Context Stack level + */ +#define IX_PIUDL_ECS_BG_CTXT_REG_0 (0x00) + +/** + * @def IX_PIUDL_ECS_BG_CTXT_REG_1 + * @brief Execution Access register address for register 1 at Backgound + * Executing Context Stack level + */ +#define IX_PIUDL_ECS_BG_CTXT_REG_1 (0x01) + +/** + * @def IX_PIUDL_ECS_BG_CTXT_REG_2 + * @brief Execution Access register address for register 2 at Backgound + * Executing Context Stack level + */ +#define IX_PIUDL_ECS_BG_CTXT_REG_2 (0x02) + +/** + * @def IX_PIUDL_ECS_PRI_1_CTXT_REG_0 + * @brief Execution Access register address for register 0 at Priority 1 + * Executing Context Stack level + */ +#define IX_PIUDL_ECS_PRI_1_CTXT_REG_0 (0x04) + +/** + * @def IX_PIUDL_ECS_PRI_1_CTXT_REG_1 + * @brief Execution Access register address for register 1 at Priority 1 + * Executing Context Stack level + */ +#define IX_PIUDL_ECS_PRI_1_CTXT_REG_1 (0x05) + +/** + * @def IX_PIUDL_ECS_PRI_1_CTXT_REG_2 + * @brief Execution Access register address for register 2 at Priority 1 + * Executing Context Stack level + */ +#define IX_PIUDL_ECS_PRI_1_CTXT_REG_2 (0x06) + +/** + * @def IX_PIUDL_ECS_PRI_2_CTXT_REG_0 + * @brief Execution Access register address for register 0 at Priority 2 + * Executing Context Stack level + */ +#define IX_PIUDL_ECS_PRI_2_CTXT_REG_0 (0x08) + +/** + * @def IX_PIUDL_ECS_PRI_2_CTXT_REG_1 + * @brief Execution Access register address for register 1 at Priority 2 + * Executing Context Stack level + */ +#define IX_PIUDL_ECS_PRI_2_CTXT_REG_1 (0x09) + +/** + * @def IX_PIUDL_ECS_PRI_2_CTXT_REG_2 + * @brief Execution Access register address for register 2 at Priority 2 + * Executing Context Stack level + */ +#define IX_PIUDL_ECS_PRI_2_CTXT_REG_2 (0x0A) + +/** + * @def IX_PIUDL_ECS_DBG_CTXT_REG_0 + * @brief Execution Access register address for register 0 at Debug + * Executing Context Stack level + */ +#define IX_PIUDL_ECS_DBG_CTXT_REG_0 (0x0C) + +/** + * @def IX_PIUDL_ECS_DBG_CTXT_REG_1 + * @brief Execution Access register address for register 1 at Debug + * Executing Context Stack level + */ +#define IX_PIUDL_ECS_DBG_CTXT_REG_1 (0x0D) + +/** + * @def IX_PIUDL_ECS_DBG_CTXT_REG_2 + * @brief Execution Access register address for register 2 at Debug + * Executing Context Stack level + */ +#define IX_PIUDL_ECS_DBG_CTXT_REG_2 (0x0E) + +/** + * @def IX_PIUDL_ECS_INSTRUCT_REG + * @brief Execution Access register address for PIU Instruction Register + */ +#define IX_PIUDL_ECS_INSTRUCT_REG (0x11) + + +/* + * Execution Access register reset values + */ + +/** + * @def IX_PIUDL_ECS_BG_CTXT_REG_0_RESET + * @brief Reset value for Execution Access Background ECS level register 0 + */ +#define IX_PIUDL_ECS_BG_CTXT_REG_0_RESET (0xA0000000) + +/** + * @def IX_PIUDL_ECS_BG_CTXT_REG_1_RESET + * @brief Reset value for Execution Access Background ECS level register 1 + */ +#define IX_PIUDL_ECS_BG_CTXT_REG_1_RESET (0x01000000) + +/** + * @def IX_PIUDL_ECS_BG_CTXT_REG_2_RESET + * @brief Reset value for Execution Access Background ECS level register 2 + */ +#define IX_PIUDL_ECS_BG_CTXT_REG_2_RESET (0x00008000) + +/** + * @def IX_PIUDL_ECS_PRI_1_CTXT_REG_0_RESET + * @brief Reset value for Execution Access Priority 1 ECS level register 0 + */ +#define IX_PIUDL_ECS_PRI_1_CTXT_REG_0_RESET (0x20000080) + +/** + * @def IX_PIUDL_ECS_PRI_1_CTXT_REG_1_RESET + * @brief Reset value for Execution Access Priority 1 ECS level register 1 + */ +#define IX_PIUDL_ECS_PRI_1_CTXT_REG_1_RESET (0x01000000) + +/** + * @def IX_PIUDL_ECS_PRI_1_CTXT_REG_2_RESET + * @brief Reset value for Execution Access Priority 1 ECS level register 2 + */ +#define IX_PIUDL_ECS_PRI_1_CTXT_REG_2_RESET (0x00008000) + +/** + * @def IX_PIUDL_ECS_PRI_2_CTXT_REG_0_RESET + * @brief Reset value for Execution Access Priority 2 ECS level register 0 + */ +#define IX_PIUDL_ECS_PRI_2_CTXT_REG_0_RESET (0x20000080) + +/** + * @def IX_PIUDL_ECS_PRI_2_CTXT_REG_1_RESET + * @brief Reset value for Execution Access Priority 2 ECS level register 1 + */ +#define IX_PIUDL_ECS_PRI_2_CTXT_REG_1_RESET (0x01000000) + +/** + * @def IX_PIUDL_ECS_PRI_2_CTXT_REG_2_RESET + * @brief Reset value for Execution Access Priority 2 ECS level register 2 + */ +#define IX_PIUDL_ECS_PRI_2_CTXT_REG_2_RESET (0x00008000) + +/** + * @def IX_PIUDL_ECS_DBG_CTXT_REG_0_RESET + * @brief Reset value for Execution Access Debug ECS level register 0 + */ +#define IX_PIUDL_ECS_DBG_CTXT_REG_0_RESET (0x20000000) + +/** + * @def IX_PIUDL_ECS_DBG_CTXT_REG_1_RESET + * @brief Reset value for Execution Access Debug ECS level register 1 + */ +#define IX_PIUDL_ECS_DBG_CTXT_REG_1_RESET (0x00000000) + +/** + * @def IX_PIUDL_ECS_DBG_CTXT_REG_2_RESET + * @brief Reset value for Execution Access Debug ECS level register 2 + */ +#define IX_PIUDL_ECS_DBG_CTXT_REG_2_RESET (0x001E0000) + +/** + * @def IX_PIUDL_ECS_INSTRUCT_REG_RESET + * @brief Reset value for Execution Access PIU Instruction Register + */ +#define IX_PIUDL_ECS_INSTRUCT_REG_RESET (0x1003C00F) + + +/* + * masks used to read/write particular bits in Execution Access registers + */ + +/** + * @def IX_PIUDL_MASK_ECS_REG_0_ACTIVE + * @brief Mask the A (Active) bit in Execution Access Register 0 of all ECS + * levels + */ +#define IX_PIUDL_MASK_ECS_REG_0_ACTIVE (0x80000000) + +/** + * @def IX_PIUDL_MASK_ECS_REG_0_NEXTPC + * @brief Mask the NextPC bits in Execution Access Register 0 of all ECS + * levels (except Debug ECS level) + */ +#define IX_PIUDL_MASK_ECS_REG_0_NEXTPC (0x1FFF0000) + +/** + * @def IX_PIUDL_MASK_ECS_REG_0_LDUR + * @brief Mask the LDUR bits in Execution Access Register 0 of all ECS levels + */ +#define IX_PIUDL_MASK_ECS_REG_0_LDUR (0x00000700) + +/** + * @def IX_PIUDL_MASK_ECS_REG_1_CCTXT + * @brief Mask the NextPC bits in Execution Access Register 1 of all ECS levels + */ +#define IX_PIUDL_MASK_ECS_REG_1_CCTXT (0x000F0000) + +/** + * @def IX_PIUDL_MASK_ECS_REG_1_SELCTXT + * @brief Mask the NextPC bits in Execution Access Register 1 of all ECS levels + */ +#define IX_PIUDL_MASK_ECS_REG_1_SELCTXT (0x0000000F) + +/** + * @def IX_PIUDL_MASK_ECS_DBG_REG_2_IF + * @brief Mask the IF bit in Execution Access Register 2 of Debug ECS level + */ +#define IX_PIUDL_MASK_ECS_DBG_REG_2_IF (0x00100000) + +/** + * @def IX_PIUDL_MASK_ECS_DBG_REG_2_IE + * @brief Mask the IE bit in Execution Access Register 2 of Debug ECS level + */ +#define IX_PIUDL_MASK_ECS_DBG_REG_2_IE (0x00080000) + + +/* + * Bit-Offsets from LSB of particular bit-fields in Execution Access registers + */ + +/** + * @def IX_PIUDL_OFFSET_ECS_REG_0_NEXTPC + * @brief LSB-offset of NextPC field in Execution Access Register 0 of all ECS + * levels (except Debug ECS level) + */ +#define IX_PIUDL_OFFSET_ECS_REG_0_NEXTPC (16) + +/** + * @def IX_PIUDL_OFFSET_ECS_REG_0_LDUR + * @brief LSB-offset of LDUR field in Execution Access Register 0 of all ECS + * levels + */ +#define IX_PIUDL_OFFSET_ECS_REG_0_LDUR (8) + +/** + * @def IX_PIUDL_OFFSET_ECS_REG_1_CCTXT + * @brief LSB-offset of CCTXT field in Execution Access Register 1 of all ECS + * levels + */ +#define IX_PIUDL_OFFSET_ECS_REG_1_CCTXT (16) + +/** + * @def IX_PIUDL_OFFSET_ECS_REG_1_SELCTXT + * @brief LSB-offset of SELCTXT field in Execution Access Register 1 of all ECS + * levels + */ +#define IX_PIUDL_OFFSET_ECS_REG_1_SELCTXT (0) + + +/* + * PIU core & co-processor instruction templates to load into PIU Instruction + * Register, for read/write of PIU register file registers + */ + +/** + * @def IX_PIUDL_INSTR_RD_REG_BYTE + * @brief PIU Instruction, used to read an 8-bit PIU internal logical register + * and return the value in the EXDATA register (aligned to MSB). + * PIU Assembler instruction: "mov8 d0, d0 &&& DBG_WrExec" + */ +#define IX_PIUDL_INSTR_RD_REG_BYTE (0x0FC00000) + +/** + * @def IX_PIUDL_INSTR_RD_REG_SHORT + * @brief PIU Instruction, used to read a 16-bit PIU internal logical register + * and return the value in the EXDATA register (aligned to MSB). + * PIU Assembler instruction: "mov16 d0, d0 &&& DBG_WrExec" + */ +#define IX_PIUDL_INSTR_RD_REG_SHORT (0x0FC08010) + +/** + * @def IX_PIUDL_INSTR_RD_REG_WORD + * @brief PIU Instruction, used to read a 16-bit PIU internal logical register + * and return the value in the EXDATA register. + * PIU Assembler instruction: "mov32 d0, d0 &&& DBG_WrExec" + */ +#define IX_PIUDL_INSTR_RD_REG_WORD (0x0FC08210) + +/** + * @def IX_PIUDL_INSTR_WR_REG_BYTE + * @brief PIU Immediate-Mode Instruction, used to write an 8-bit PIU internal + * logical register. + * PIU Assembler instruction: "mov8 d0, #0" + */ +#define IX_PIUDL_INSTR_WR_REG_BYTE (0x00004000) + +/** + * @def IX_PIUDL_INSTR_WR_REG_SHORT + * @brief PIU Immediate-Mode Instruction, used to write a 16-bit PIU internal + * logical register. + * PIU Assembler instruction: "mov16 d0, #0" + */ +#define IX_PIUDL_INSTR_WR_REG_SHORT (0x0000C000) + +/** + * @def IX_PIUDL_INSTR_RD_FIFO + * @brief PIU Immediate-Mode Instruction, used to write a 16-bit PIU internal + * logical register. + * PIU Assembler instruction: "cprd32 d0 &&& DBG_RdInFIFO" + */ +#define IX_PIUDL_INSTR_RD_FIFO (0x0F888220) + +/** + * @def IX_PIUDL_INSTR_RESET_MBOX + * @brief PIU Instruction, used to reset Mailbox (MBST) register + * PIU Assembler instruction: "mov32 d0, d0 &&& DBG_ClearM" + */ +#define IX_PIUDL_INSTR_RESET_MBOX (0x0FAC8210) + + +/** + * @def IX_PIUDL_INSTR_RESET_COPROCS + * @brief PIU Instruction, used to reset co-processors. Register d0 must + * contain the value (0xFFFF to reset all co-processors. + * PIU Assembler instruction: "mov16 d0, d0 &&&DBG_WrRst" + */ +#define IX_PIUDL_INSTR_RESET_COPROCS (0xAFB88010) + + +/* + * Bit-offsets from LSB, of particular bit-fields in an PIU instruction + */ + +/** + * @def IX_PIUDL_OFFSET_INSTR_SRC + * @brief LSB-offset to SRC (source operand) field of an PIU Instruction + */ +#define IX_PIUDL_OFFSET_INSTR_SRC (4) + +/** + * @def IX_PIUDL_OFFSET_INSTR_DEST + * @brief LSB-offset to DEST (destination operand) field of an PIU Instruction + */ +#define IX_PIUDL_OFFSET_INSTR_DEST (9) + +/** + * @def IX_PIUDL_OFFSET_INSTR_COPROC + * @brief LSB-offset to COPROC (coprocessor instruction) field of an PIU + * Instruction + */ +#define IX_PIUDL_OFFSET_INSTR_COPROC (18) + + +/* + * masks used to read/write particular bits of an PIU Instruction + */ + +/** + * @def IX_PIUDL_MASK_IMMED_INSTR_SRC_DATA + * @brief Mask the bits of 16-bit data value (least-sig 5 bits) to be used in + * SRC field of immediate-mode PIU instruction + */ +#define IX_PIUDL_MASK_IMMED_INSTR_SRC_DATA (0x1F) + +/** + * @def IX_PIUDL_MASK_IMMED_INSTR_COPROC_DATA + * @brief Mask the bits of 16-bit data value (most-sig 11 bits) to be used in + * COPROC field of immediate-mode PIU instruction + */ +#define IX_PIUDL_MASK_IMMED_INSTR_COPROC_DATA (0xFFE0) + +/** + * @def IX_PIUDL_OFFSET_IMMED_INSTR_COPROC_DATA + * @brief LSB offset of the bit-field of 16-bit data value (most-sig 11 bits) + * to be used in COPROC field of immediate-mode PIU instruction + */ +#define IX_PIUDL_OFFSET_IMMED_INSTR_COPROC_DATA (5) + +/** + * @def IX_PIUDL_DISPLACE_IMMED_INSTR_COPROC_DATA + * @brief Number of left-shifts required to align most-sig 11 bits of 16-bit + * data value into COPROC field of immediate-mode PIU instruction + */ +#define IX_PIUDL_DISPLACE_IMMED_INSTR_COPROC_DATA \ + (IX_PIUDL_OFFSET_INSTR_COPROC - IX_PIUDL_OFFSET_IMMED_INSTR_COPROC_DATA) + +/** + * @def IX_PIUDL_WR_INSTR_LDUR + * @brief LDUR value used with immediate-mode PIU Instructions by the PiuDl + * for writing to PIU internal logical registers + */ +#define IX_PIUDL_WR_INSTR_LDUR (1) + +/** + * @def IX_PIUDL_RD_INSTR_LDUR + * @brief LDUR value used with NON-immediate-mode PIU Instructions by the PiuDl + * for reading from PIU internal logical registers + */ +#define IX_PIUDL_RD_INSTR_LDUR (0) + + +/** + * @enum IxPiuDlCtxtRegNum + * @brief Numeric values to identify the PIU internal Context Store registers + */ +typedef enum +{ + IX_PIUDL_CTXT_REG_STEVT = 0, /**< identifies STEVT */ + IX_PIUDL_CTXT_REG_STARTPC, /**< identifies STARTPC */ + IX_PIUDL_CTXT_REG_REGMAP, /**< identifies REGMAP */ + IX_PIUDL_CTXT_REG_CINDEX, /**< identifies CINDEX */ + IX_PIUDL_CTXT_REG_MAX /**< Total number of Context Store registers */ +} IxPiuDlCtxtRegNum; + + +/* + * PIU Context Store register logical addresses + */ + +/** + * @def IX_PIUDL_CTXT_REG_ADDR_STEVT + * @brief Logical address of STEVT PIU internal Context Store register + */ +#define IX_PIUDL_CTXT_REG_ADDR_STEVT (0x0000001B) + +/** + * @def IX_PIUDL_CTXT_REG_ADDR_STARTPC + * @brief Logical address of STARTPC PIU internal Context Store register + */ +#define IX_PIUDL_CTXT_REG_ADDR_STARTPC (0x0000001C) + +/** + * @def IX_PIUDL_CTXT_REG_ADDR_REGMAP + * @brief Logical address of REGMAP PIU internal Context Store register + */ +#define IX_PIUDL_CTXT_REG_ADDR_REGMAP (0x0000001E) + +/** + * @def IX_PIUDL_CTXT_REG_ADDR_CINDEX + * @brief Logical address of CINDEX PIU internal Context Store register + */ +#define IX_PIUDL_CTXT_REG_ADDR_CINDEX (0x0000001F) + + +/* + * PIU Context Store register reset values + */ + +/** + * @def IX_PIUDL_CTXT_REG_RESET_STEVT + * @brief Reset value of STEVT PIU internal Context Store register + * (STEVT = off, 0x80) + */ +#define IX_PIUDL_CTXT_REG_RESET_STEVT (0x80) + +/** + * @def IX_PIUDL_CTXT_REG_RESET_STARTPC + * @brief Reset value of STARTPC PIU internal Context Store register + * (STARTPC = 0x0000) + */ +#define IX_PIUDL_CTXT_REG_RESET_STARTPC (0x0000) + +/** + * @def IX_PIUDL_CTXT_REG_RESET_REGMAP + * @brief Reset value of REGMAP PIU internal Context Store register + * (REGMAP = d0->p0, d8->p2, d16->p4) + */ +#define IX_PIUDL_CTXT_REG_RESET_REGMAP (0x0820) + +/** + * @def IX_PIUDL_CTXT_REG_RESET_CINDEX + * @brief Reset value of CINDEX PIU internal Context Store register + * (CINDEX = 0) + */ +#define IX_PIUDL_CTXT_REG_RESET_CINDEX (0x00) + + +/* + * numeric range of context levels available on an PIU + */ + +/** + * @def IX_PIUDL_CTXT_NUM_MIN + * @brief Lowest PIU Context number in range + */ +#define IX_PIUDL_CTXT_NUM_MIN (0) + +/** + * @def IX_PIUDL_CTXT_NUM_MAX + * @brief Highest PIU Context number in range + */ +#define IX_PIUDL_CTXT_NUM_MAX (15) + + +/* + * Physical PIU internal registers + */ + +/** + * @def IX_PIUDL_TOTAL_NUM_PHYS_REG + * @brief Number of Physical registers currently supported + * Initial PIU implementations will have a 32-word register file. + * Later implementations may have a 64-word register file. + */ +#define IX_PIUDL_TOTAL_NUM_PHYS_REG (32) + +/** + * @def IX_PIUDL_OFFSET_PHYS_REG_ADDR_REGMAP + * @brief LSB-offset of Regmap number in Physical PIU register address, used + * for Physical To Logical register address mapping in the PIU + */ +#define IX_PIUDL_OFFSET_PHYS_REG_ADDR_REGMAP (1) + +/** + * @def IX_PIUDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR + * @brief Mask to extract a logical PIU register address from a physical + * register address, used for Physical To Logical address mapping + */ +#define IX_PIUDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR (0x1) + +#if defined(__ep805xx) +/* + * application specific dual related defines + */ + +/** + * @def IX_PIUDL_APPDUAL_ID_MAX + * @brief The maximum number for an application specific dual coprocessor + * instruction Id + */ +#define IX_PIUDL_APPDUAL_ID_MAX (0xF) + +/** + * @def IX_PIUDL_APPDUAL_COPR_ID_MAX + * @brief The maximum number for an application specific dual coprocessor + * instruction coprocessor Id + */ +#define IX_PIUDL_APPDUAL_COPR_ID_MAX (0xF) + +/** + * @def IX_PIUDL_APPDUAL_INST_ID_MAX + * @brief The maximum number for an application specific dual coprocessor + * instruction instruction Id + */ +#define IX_PIUDL_APPDUAL_INST_ID_MAX (0x3F) + +/** + * @def IX_PIUDL_APPDUAL_REG_OFFSET + * @brief The register offset from the base address for application specific + * dual coprocessor instruction configuration registers + */ +#define IX_PIUDL_APPDUAL_REG_OFFSET (0x20) + +/** + * @def IX_PIUDL_APPDUAL_REG_COPR0_BIT_OFFSET + * @brief The offset within the application specific dual coprocessor register + * for the coprocessor 0 decode field + */ +#define IX_PIUDL_APPDUAL_REG_COPR0_BIT_OFFSET (16) + +/** + * @def IX_PIUDL_APPDUAL_REG_INST0_BIT_OFFSET + * @brief The offset within the application specific dual coprocessor register + * for the coprocessor 0 instruction decode field + */ +#define IX_PIUDL_APPDUAL_REG_INST0_BIT_OFFSET (0) + +/** + * @def IX_PIUDL_APPDUAL_REG_COPR1_BIT_OFFSET + * @brief The offset within the application specific dual coprocessor register + * for the coprocessor 1 decode field + */ +#define IX_PIUDL_APPDUAL_REG_COPR1_BIT_OFFSET (24) + +/** + * @def IX_PIUDL_APPDUAL_REG_INST1_OFFSET + * @brief The offset within the application specific dual coprocessor register + * for the coprocessor 1 instruction decode field + */ +#define IX_PIUDL_APPDUAL_REG_INST1_BIT_OFFSET (8) + +#endif // #if defined(__ep805xx) + +#endif /* IXPIUDLPIUMGRECREGISTERS_P_H */ diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlPiuMgrUtils_p.h b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlPiuMgrUtils_p.h new file mode 100644 index 0000000..93b00e8 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlPiuMgrUtils_p.h @@ -0,0 +1,499 @@ +/** + * @file IxPiuDlPiuMgrUtils_p.h + * + * @author Intel Corporation + * @date 13 August 2003 + * @brief This file contains the private API for the PiuMgr module. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + + +/** + * @defgroup IxPiuDlPiuMgrUtils_p IxPiuDlPiuMgrUtils_p + * + * @brief The private API for the IxPiuDl PiuMgr Utils module + * + * @{ + */ + +#ifndef IXpiuDLpiuMGRUTILS_P_H +#define IXpiuDLpiuMGRUTILS_P_H + + +/* + * Put the user defined include files required. + */ +#include "IxPiuDl.h" +#include "IxPiuDlPiuMgrEcRegisters_p.h" + + +/* + * Function Prototypes + */ + +/** + * @fn ix_error ixPiuDlPiuMgrInsMemWrite (ix_uint32 piuBaseAddress, + ix_uint32 insMemAddress, + ix_uint32 insMemData, + BOOL verify) + * + * @brief Writes a word to piu Instruction memory + * + * @param ix_uint32 [in] piuBaseAddress - Base Address of piu + * @param ix_uint32 [in] insMemAddress - piu instruction memory address to write + * @param ix_uint32 [in] insMemData - data to write to instruction memory + * @param BOOL [in] verify - if TRUE, verify the memory location is + * written successfully. + * + * This function is used to write a single word of data to a location in piu + * instruction memory. If the <i>verify</i> option is ON, PiuDl will read back + * from the memory location to verify that it was written successfully + * + * @pre + * + * @post + * + * @return + * - IX_FAIL if verify is TRUE and the memory location was not written + * successfully + * - IX_SUCCESS otherwise + */ +ix_error +ixPiuDlPiuMgrInsMemWrite (ix_uint32 piuBaseAddress, ix_uint32 insMemAddress, + ix_uint32 insMemData, BOOL verify); + + +/** + * @fn ix_error ixPiuDlPiuMgrDataMemWrite (ix_uint32 piuBaseAddress, + ix_uint32 dataMemAddress, + ix_uint32 dataMemData, + BOOL verify) + * + * @brief Writes a word to piu Data memory + * + * @param ix_uint32 [in] piuBaseAddress - Base Address of piu + * @param ix_uint32 [in] dataMemAddress - piu data memory address to write + * @param ix_uint32 [in] dataMemData - data to write to piu data memory + * @param BOOL [in] verify - if TRUE, verify the memory location is + * written successfully. + * + * This function is used to write a single word of data to a location in piu + * data memory. If the <i>verify</i> option is ON, PiuDl will read back from + * the memory location to verify that it was written successfully + * + * @pre + * + * @post + * + * @return + * - IX_FAIL if verify is TRUE and the memory location was not written + * successfully + * - IX_SUCCESS otherwise + */ +ix_error +ixPiuDlPiuMgrDataMemWrite (ix_uint32 piuBaseAddress, ix_uint32 dataMemAddress, + ix_uint32 dataMemData, BOOL verify); + + +/** + * @fn void ixPiuDlPiuMgrExecAccRegWrite (ix_uint32 piuBaseAddress, + ix_uint32 regAddress, + ix_uint32 regData) + * + * @brief Writes a word to an piu Execution Access register + * + * @param ix_uint32 [in] piuBaseAddress - Base Address of piu + * @param ix_uint32 [in] regAddress - piu Execution Access register address + * @param ix_uint32 [in] regData - data to write to register + * + * This function is used to write a single word of data to an piu Execution + * Access register. + * + * @pre + * + * @post + * + * @return none + */ +void +ixPiuDlPiuMgrExecAccRegWrite (ix_uint32 piuBaseAddress, ix_uint32 regAddress, + ix_uint32 regData); + +#if defined(__ep805xx) +/** + * @fn ix_error ixPiuDlPiuMgrAppDualRegWrite (ix_uint32 piuBaseAddress, + * ix_uint32 appDualRegAddress, + * ix_uint32 appDualRegData, + * BOOL verify) + * + * @brief Configures an application specific dual coprocessor register + * + * @param ix_uint32 [in] piuBaseAddress - Base Address of piu + * @param ix_uint32 [in] appDualRegAddress - address of appDual reg to write + * @param ix_uint32 [in] appDualRegData - data to write to appDual reg + * @param BOOL [in] verify - if TRUE, verify the register is + * written successfully. + * + * This function is used to configure an application specific dual coprocessor + * register. If the <i>verify</i> option is ON, the register will be read back + * to verify that it was written successfully + * + * @pre + * - it is assumed that a valid value is passed in for the register i.e. all + * reserved bits have been set to zero + * @post + * + * @return + * - IX_FAIL if verify is TRUE and the register was not written + * successfully + * + * - IX_SUCCESS otherwise + */ +ix_uint32 +ixPiuDlPiuMgrAppDualRegWrite ( + ix_uint32 piuBaseAddress, + ix_uint32 appDualRegAddress, + ix_uint32 appDualRegData, + BOOL verify); +#endif // #if defined(__ep805xx) + +/** + * @fn ix_uint32 ixPiuDlPiuMgrExecAccRegRead (ix_uint32 piuBaseAddress, + ix_uint32 regAddress) + * + * @brief Reads the contents of an piu Execution Access register + * + * @param ix_uint32 [in] piuBaseAddress - Base Address of piu + * @param ix_uint32 [in] regAddress - piu Execution Access register address + * + * This function is used to read the contents of an piu Execution + * Access register. + * + * @pre + * + * @post + * + * @return The value read from the Execution Access register + */ +ix_uint32 +ixPiuDlPiuMgrExecAccRegRead (ix_uint32 piuBaseAddress, ix_uint32 regAddress); + + +/** + * @fn void ixPiuDlPiuMgrCommandIssue (ix_uint32 piuBaseAddress, + ix_uint32 command) + * + * @brief Issues an piu Execution Control command + * + * @param ix_uint32 [in] piuBaseAddress - Base Address of piu + * @param ix_uint32 [in] command - Command to issue + * + * This function is used to issue a stand-alone piu Execution Control command + * (e.g. command to Stop piu execution) + * + * @pre + * + * @post + * + * @return none + */ +void +ixPiuDlPiuMgrCommandIssue (ix_uint32 piuBaseAddress, ix_uint32 command); + + +/** + * @fn void ixPiuDlPiuMgrDebugInstructionPreExec (ix_uint32 piuBaseAddress) + * + * @brief Prepare to executes one or more piu instructions in the Debug + * Execution Stack level. + * + * @param ix_uint32 [in] piuBaseAddress - Base Address of piu + * + * This function should be called once before a sequence of calls to + * ixPiuDlPiuMgrDebugInstructionExec(). + * + * @pre + * + * @post + * - ixPiuDlPiuMgrDebugInstructionPostExec() should be called to restore + * registers values altered by this function + * + * @return none + */ +void +ixPiuDlPiuMgrDebugInstructionPreExec (ix_uint32 piuBaseAddress); + + +/** + * @fn void ixPiuDlPiuMgrDebugInstructionExec (ix_uint32 piuBaseAddress, + ix_uint32 piuInstruction, + ix_uint32 ctxtNum, + ix_uint32 ldur) + * + * @brief Executes a single instruction on the piu at the Debug Execution Stack + * level + * + * @param ix_uint32 [in] piuBaseAddress - Base Address of piu + * @param ix_uint32 [in] piuInstruction - Value to write to INSTR (Instruction) + * register + * @param ix_uint32 [in] ctxtNum - context the instruction will be executed + * in and which context store it may access + * @param ix_uint32 [in] ldur - Long Immediate Duration, set to non-zero + * to use long-immediate mode instruction + * + * This function is used to execute a single instruction in the piu pipeline at + * the debug Execution Context Stack level. It won't disturb the state of other + * executing contexts. Its useful for performing piu operations, such as + * writing to piu Context Store registers and physical registers, that cannot + * be carried out directly using the Configuration Bus registers. + * + * @pre + * - The piu should be stopped and in a clean state + * - ixPiuDlPiuMgrDebugInstructionPreExec() should be called once before + * a sequential of 1 or more calls to this function + * + * @post + * - ixPiuDlPiuMgrDebugInstructionPostExec() should be called after + * a sequence of calls to this function + * + * @return none + */ +void +ixPiuDlPiuMgrDebugInstructionExec (ix_uint32 piuBaseAddress, + ix_uint32 piuInstruction, + ix_uint32 ctxtNum, ix_uint32 ldur); + + +/** + * @fn void ixPiuDlPiuMgrDebugInstructionPostExec (ix_uint32 piuBaseAddress) + * + * @brief Clean up after executing one or more piu instructions in the + * Debug Stack Level + * + * @param ix_uint32 [in] piuBaseAddress - Base Address of piu + * + * This function should be called once following a sequence of calls to + * ixPiuDlPiuMgrDebugInstructionExec(). + * + * @pre + * - ixPiuDlPiuMgrDebugInstructionPreExec() was called earlier + * + * @post + * - The Instruction Pipeline will cleared + * + * @return none + */ +void +ixPiuDlPiuMgrDebugInstructionPostExec (ix_uint32 piuBaseAddress); + + +/** + * @fn ix_error ixPiuDlPiuMgrLogicalRegWrite (ix_uint32 piuBaseAddress, + ix_uint32 regAddr, + ix_uint32 regValue, + ix_uint32 regSize, + ix_uint32 ctxtNum, + BOOL verify) + * + * @brief Write a logical registers in the piu data + * register file + * + * @param ix_uint32 [in] piuBaseAddress - Base Address of piu + * @param ix_uint32 [in] regAddr - number of the physical register (0-31)* + * @param ix_uint32 [in] regValue - value to write to the register + * @param ix_uint32 [in] regSize - the size in bits of the value to be written + * @param ix_uint32 [in] ctxtNum - the context number + * @param BOOL [in] verify - if TRUE, verify the register is written + * successfully. + * + * This function writes a logical register in the piu data register file. + * If the <i>verify</i> option is ON, PiuDl will read back the register to + * verify that it was written successfully + * + * @pre + * - The piu should be stopped and in a clean state + * - ixPiuDlPiuMgrDebugInstructionPreExec() should be called once before + * a sequential of 1 or more calls to this function + * + * @post + * - Contents of REGMAP Context Store register for Context 0 will be altered + * - ixPiuDlPiuMgrDebugInstructionPostExec() should be called after + * a sequence of calls to this function + * + * @return + * - IX_FAIL if verify is TRUE and the Context Register was not written + * successfully + * - IX_SUCCESS otherwise + */ +ix_error +ixPiuDlPiuMgrLogicalRegWrite (ix_uint32 piuBaseAddress, ix_uint32 regAddr, + ix_uint32 regVal, ix_uint32 regSize, + ix_uint32 ctxtNum, BOOL verify); + +/** + * @fn ix_error ixPiuDlPiuMgrPhysicalRegWrite (ix_uint32 piuBaseAddress, + ix_uint32 regAddr, + ix_uint32 regValue, + BOOL verify) + * + * @brief Write one of the 32* 32-bit physical registers in the piu data + * register file + * + * @param ix_uint32 [in] piuBaseAddress - Base Address of piu + * @param ix_uint32 [in] regAddr - number of the physical register (0-31)* + * @param ix_uint32 [in] regValue - value to write to the physical register + * @param BOOL [in] verify - if TRUE, verify the register is written + * successfully. + * + * This function writes a physical register in the piu data register file. + * If the <i>verify</i> option is ON, PiuDl will read back the register to + * verify that it was written successfully + * *Note that release 1.0 of this software supports 32 physical + * registers, but 64 may be supported in future versions. + * + * @pre + * - The piu should be stopped and in a clean state + * - ixPiuDlPiuMgrDebugInstructionPreExec() should be called once before + * a sequential of 1 or more calls to this function + * + * @post + * - Contents of REGMAP Context Store register for Context 0 will be altered + * - ixPiuDlPiuMgrDebugInstructionPostExec() should be called after + * a sequence of calls to this function + * + * @return + * - IX_FAIL if verify is TRUE and the Context Register was not written + * successfully + * - IX_SUCCESS otherwise + */ +ix_error +ixPiuDlPiuMgrPhysicalRegWrite (ix_uint32 piuBaseAddress, ix_uint32 regAddr, + ix_uint32 regValue, BOOL verify); + + +/** + * @fn ix_error ixPiuDlPiuMgrCtxtRegWrite (ix_uint32 piuBaseAddress, + ix_uint32 ctxtNum, + IxPiuDlCtxtRegNum ctxtReg, + ix_uint32 ctxtRegVal, + BOOL verify) + * + * @brief Writes a value to a Context Store register on an piu + * + * @param ix_uint32 [in] piuBaseAddress - Base Address of piu + * @param ix_uint32 [in] ctxtNum - context store to access + * @param IxPiuDlCtxtRegNum [in] ctxtReg - which Context Store reg to write + * @param ix_uint32 [in] ctxtRegVal - value to write to the Context Store + * register + * @param BOOL [in] verify - if TRUE, verify the register is + * written successfully. + * + * This function writes the contents of a Context Store register in the piu + * register file. If the <i>verify</i> option is ON, PiuDl will read back the + * register to verify that it was written successfully + * + * @pre + * - The piu should be stopped and in a clean state + * - ixPiuDlPiuMgrDebugInstructionPreExec() should be called once before + * a sequential of 1 or more calls to this function + * + * @post + * - ixPiuDlPiuMgrDebugInstructionPostExec() should be called after + * a sequence of calls to this function + * + * @return + * - IX_FAIL if verify is TRUE and the Context Register was not written + * successfully + * - IX_SUCCESS otherwise + */ +ix_error +ixPiuDlPiuMgrCtxtRegWrite (ix_uint32 piuBaseAddress, ix_uint32 ctxtNum, + IxPiuDlCtxtRegNum ctxtReg, ix_uint32 ctxtRegVal, + BOOL verify); + + +/** + * @fn void ixPiuDlPiuMgrUtilsStatsShow (void) + * + * @brief This function will display the statistics of the IxPiuDl PiuMgrUtils + * module + * + * @return none + */ +void +ixPiuDlPiuMgrUtilsStatsShow (void); + + +/** + * @fn void ixPiuDlPiuMgrUtilsStatsReset (void) + * + * @brief This function will reset the statistics of the IxPiuDl PiuMgrUtils + * module + * + * @return none + */ +void +ixPiuDlPiuMgrUtilsStatsReset (void); + + +#endif /* IXpiuDLpiuMGRUTILS_P_H */ diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlPiuMgr_p.h b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlPiuMgr_p.h new file mode 100644 index 0000000..3a6286b --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlPiuMgr_p.h @@ -0,0 +1,370 @@ +/** + * @file IxPiuDlPiuMgr_p.h + * + * @author Intel Corporation + * @date 13 August 2003 + * @brief This file contains the private API for the PiuMgr module. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + + +/** + * @defgroup IxPiuDlPiuMgr_p IxPiuDlPiuMgr_p + * + * @brief The private API for the IxPiuDl PiuMgr module + * + * @{ + */ + +#ifndef IXPIUDLPIUMGR_P_H +#define IXPIUDLPIUMGR_P_H + + +/* + * Put the user defined include files required. + */ +#include "IxPiuDl.h" + + +/* + * Function Prototypes + */ +#if defined(__ep805xx) +/** + * @fn ix_error ixPiuDlPiuMgrPhysicalAddressSet ( + * IxPiuDlPiuId piuId, + * ix_uint32 address) + * + * @brief This function sets the physical base address for the given PIU. + * + * @param piuId @ref IxPiuDlPiuId [in] - The ID of the PIU whose physical base + * address will be set - note that it assumed that this has been validated + * by the caller + * @param address ix_uint32 [in] - The address to set the physical address to + * + * This function sets the physical base address for the given PIU. It must be + * called when the piuDl component is not initialized i.e. prior to calling the + * @ref ixPiuDlPiuMgrInit function (maps the physical address to a virtual + * address) or after calling the @ref ixPiuDlPiuMgrUninit function. + * + * @return + * - IX_SUCCESS if the address was set successfully + * - IX_FAIL if the function is called after memory has been initialised + */ +ix_error +ixPiuDlPiuMgrPhysicalAddressSet ( + IxPiuDlPiuId piuId, + ix_uint32 address); + +/** + * @fn ix_error ixPiuDlPiuMgrAppDualSet ( + * IxPiuDlPiuId piuId, + * ix_uint32 appDualId, + * IxPiuDlAppDualInstruction *appDualInstruction + * ) + * + * @brief This function configures an PIU application specific dual coprocessor + * instruction register + * + * @param piuId IxPiuDlPiuId [in] - Id of the target PIU. + * @param appDualId ix_uint32 [in] - The application specific dual coprocessor + * instruction Id + * @param IxPiuDlAppDualInstruction appDualInstruction [in] - pointer to an + * application specific dual coprocessor instruction structure + * + * This function configures an PIU application specific dual coprocessor + * instruction register which allows 2 arbitrary coprocessor instructions to + * execute at the same time. + * + * @return + * - IX_SUCCESS if the dual instruction was set successfully + * - IX_PIUDL_PARAM_ERR if a parameter error occurred + * - IX_FAIL if the verification of the register write fails + */ + +ix_error +ixPiuDlPiuMgrAppDualSet ( + IxPiuDlPiuId piuId, + ix_uint32 appDualId, + IxPiuDlAppDualInstruction *appDualInstruction +); + +/** + * @fn ix_error ixPiuDlPiuMgrAppDualGet ( + * IxPiuDlPiuId piuId, + * ix_uint32 appDualId, + * IxPiuDlAppDualInstruction *appDualInstruction + * ) + * + * @brief This function retrieves the fields of an PIU application specific + * dual coprocessor instruction register + * + * @param piuId IxPiuDlPiuId [in] - Id of the target PIU. + * @param appDualId ix_uint32 [in] - The application specific dual coprocessor + * instruction Id + * @param IxPiuDlAppDualInstruction appDualInstruction [out] - pointer to an + * application specific dual coprocessor instruction structure which will be + * filled by this function + * + * This function retrieves the fields of an PIU application specific dual + * coprocessor instruction. + * + * @return + * - IX_SUCCESS if the dual instruction was set successfully + * - IX_PIUDL_PARAM_ERR if a parameter error occurred + */ + +ix_error +ixPiuDlPiuMgrAppDualGet ( + IxPiuDlPiuId piuId, + ix_uint32 appDualId, + IxPiuDlAppDualInstruction *appDualInstruction +); + +#endif // #if defined(__ep805xx) + +/** + * @fn void ixPiuDlPiuMgrInit (void) + * + * @brief Initialises the PiuMgr module + * + * @param none + * + * This function initialises the PiuMgr module. + * It should be called before any other function in this module is called. + * It only needs to be called once, but can be called multiple times safely. + * The code will ASSERT on failure. + * + * @pre + * - It must be called before any other function in this module + * + * @post + * - PIU Configuration Register memory space will be mapped using + * IxOsal. This memory will not be unmapped by this module. + * + * @return none + */ +void +ixPiuDlPiuMgrInit (void); + + +/** + * @fn ix_error ixPiuDlPiuMgrUninit (void) + * + * @brief This function will uninitialise the IxPiuDlPiuMgr sub-component. + * + * This function will uninitialise the IxPiuDlPiuMgr sub-component. + * It should only be called once, and only if the IxPiuDlPiuMgr sub-component + * has already been initialised by calling @ref ixPiuDlPiuMgrInit(). + * No other IxPiuDlPiuMgr sub-component API functions should be called + * until @ref ixPiuDlPiuMgrInit() is called again. + * If possible, this function should be called before a soft reboot or unloading + * a kernel module to perform any clean up operations required for IxPiuDl. + * + * @return + * - IX_SUCCESS if the operation was successful + * - IX_FAIL otherwise + */ + +ix_error ixPiuDlPiuMgrUninit (void); + + +/** + * @fn ix_error ixPiuDlPiuMgrImageLoad (IxPiuDlPiuId piuId, + ix_uint32 *imageCodePtr, + BOOL verify) + * + * @brief Loads a image of microcode onto an PIU + * + * @param IxPiuDlPiuId [in] piuId - Id of target PIU + * @param ix_uint32* [in] imageCodePtr - pointer to image code in image to be + * downloaded + * @param BOOL [in] verify - if TRUE, verify each word written to + * PIU memory. + * + * This function loads a image containing blocks of microcode onto a + * particular PIU. If the <i>verify</i> option is ON, PiuDl will read back each + * word written and verify that it was written successfully + * + * @pre + * - The PIU should be stopped beforehand + * + * @post + * - The PIU Instruction Pipeline may be flushed clean + * + * @return + * - IX_SUCCESS if the download was successful + * - IX_FAIL otherwise + */ +ix_error +ixPiuDlPiuMgrImageLoad (IxPiuDlPiuId piuId, ix_uint32 *imageCodePtr, + BOOL verify); + + +/** + * @fn ix_error ixPiuDlPiuMgrPiuReset (IxPiuDlPiuId piuId) + * + * @brief sets a PIU to RESET state + * + * @param IxPiuDlPiuId [in] piuId - id of target PIU + * + * This function performs a soft PIU reset by writing reset values to the + * Configuration Bus Execution Control registers, the Execution Context Stack + * registers, the Physical Register file, and the Context Store registers for + * each context number. It also clears inFIFO, outFIFO and Watchpoint FIFO. + * It does not reset PIU Co-processors. + * + * @pre + * - The PIU should be stopped beforehand + * + * @post + * - PIU NextProgram Counter (NextPC) will be set to a fixed initial value, + * such as 0. This should be explicitly set by downloading State + * Information before starting PIU Execution. + * - The PIU Instruction Pipeline will be in a clean state. + * + * @return + * - IX_SUCCESS if the operation was successful + * - IX_FAIL otherwise + */ +ix_error +ixPiuDlPiuMgrPiuReset (IxPiuDlPiuId piuId); + + +/** + * @fn ix_error ixPiuDlPiuMgrPiuStart (IxPiuDlPiuId piuId) + * + * @brief Starts PIU Execution + * + * @param IxPiuDlPiuId [in] piuId - Id of target PIU + * + * Ensures only background Execution Stack Level is Active, clears instruction + * pipeline, and starts Execution on a PIU by sending a Start PIU command to + * the PIU. Checks the execution status of the PIU to verify that it is + * running. + * + * @pre + * - The PIU should be stopped beforehand. + * - Note that this function does not set the PIU Next Program Counter + * (NextPC), so it should be set beforehand if required by downloading + * appropriate State Information. + * + * @post + * + * @return + * - IX_SUCCESS if the operation was successful + * - IX_FAIL otherwise + */ +ix_error +ixPiuDlPiuMgrPiuStart (IxPiuDlPiuId piuId); + + +/** + * @fn ix_error ixPiuDlPiuMgrPiuStop (IxPiuDlPiuId piuId) + * + * @brief Halts PIU Execution + * + * @param IxPiuDlPiuId [in] piuId - id of target PIU + * + * Stops execution on an PIU by sending a Stop PIU command to the PIU. + * Checks the execution status of the PIU to verify that it has stopped. + * + * @pre + * + * @post + * + * @return + * - IX_SUCCESS if the operation was successful + * - IX_FAIL otherwise + */ +ix_error +ixPiuDlPiuMgrPiuStop (IxPiuDlPiuId piuId); + + +/** + * @fn void ixPiuDlPiuMgrStatsShow (void) + * + * @brief This function will display statistics of the IxPiuDl PiuMgr module + * + * @return none + */ +void +ixPiuDlPiuMgrStatsShow (void); + + +/** + * @fn void ixPiuDlPiuMgrStatsReset (void) + * + * @brief This function will reset the statistics of the IxPiuDl PiuMgr module + * + * @return none + */ +void +ixPiuDlPiuMgrStatsReset (void); + + +#endif /* IXPIUDLIMAGEMGR_P_H */ + +/** + * @} defgroup IxPiuDlPiuMgr_p + */ diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlTestReg.h b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlTestReg.h new file mode 100644 index 0000000..c333ceb --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlTestReg.h @@ -0,0 +1,110 @@ +/** + * @file IxPiuDlTestReg.h + * + * @author Intel Corporation + * @date 13 August 2003 + * @brief This file contains some test function prototypes. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + +/** + * @defgroup IxPiuDlTestReg IxPiuDlTestReg + * + * @brief Test PIU register read/write function prototypes. + * + * @{ + */ + +#ifndef IXPIUDLTESTREG_P_H +#define IXPIUDLTESTREG_P_H + + +/* + * Put the user defined include files required. + */ + +#include "IxPiuTypes.h" + +extern ix_uint32 ixp23xx_reset1_reg; +#define IXP23XX_RESET1_REG ixp23xx_reset1_reg + +/* + * Prototypes for interface functions. + */ + +void ixPiuDlTestRegRead ( + ix_uint32 baseAddr, + ix_uint32 offset, + ix_uint32 *value); + +void ixPiuDlTestRegWrite ( + ix_uint32 baseAddr, + ix_uint32 offset, + ix_uint32 value); + + +#endif /* IXPIUDLTESTREG_P_H */ + +/** + * @} defgroup IxPiuDlTest_p + */ diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDl_p.h b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDl_p.h new file mode 100644 index 0000000..713c542 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDl_p.h @@ -0,0 +1,167 @@ +/** + * @file IxPiuDl_p.h + * + * @author Intel Corporation + * @date 13 August 2003 + + * @brief This file contains the private API for the ImageMgr module + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +/** + * @defgroup IxPiuDl_p IxPiuDl_p + * + * @brief The private API for the IxPiuDl module + * + * @{ + */ + +#ifndef IXPIUDL_P_H +#define IXPIUDL_P_H + + +/* + * Put the user defined include files required. + */ +#include "IxPiuDl.h" + + +/* + * #defines and macros + */ + + +/* + * Prototypes for interface functions +*/ + +/** + * @ingroup IxPiuDl_p + * + * @fn ix_error ixPiuDlPiuExecutionStart (IxPiuDlPiuId piuId) + * + * @brief Starts code execution on a PIU + * + * @param IxPiuDlPiuId [in] piuId - Id of the target PIU + * + * Starts execution of code on a particular PIU. A client would typically use + * this after a download to PIU is performed, to start/restart code execution + * on the PIU. + * + * @note It is no longer necessary to call this function after downloading + * a new image to the PIU. It is left on the API only to allow greater control + * of PIU execution if required. Where appropriate, use @ref ixPiuDlPiuInitAndStart + * or @ref ixPiuDlCustomImagePiuInitAndStart instead. + * + * @pre + * - The Client is responsible for ensuring mutual access to the PIU. + * - Note that this function does not set the PIU Next Program Counter + * (NextPC), so it should be set beforehand if required by downloading + * appropriate State Information (using ixPiuDlVersionDownload()). + * + * @post + * + * @return + * - IX_SUCCESS if the operation was successful + * - IX_PIUDL_PARAM_ERR if a parameter error occured + * - IX_FAIL otherwise + */ +ix_error +ixPiuDlPiuExecutionStart (IxPiuDlPiuId piuId); + +/** + * @ingroup IxPiuDl_p + * + * @fn ix_error ixPiuDlPiuExecutionStop (IxPiuDlPiuId piuId) + * + * @brief Stops code execution on a PIU + * + * @param IxPiuDlPiuId [in] piuId - Id of the target PIU + * + * Stops execution of code on a particular PIU. This would typically be used + * by a client before a download to PIU is performed, to stop code execution on + * an PIU, unless ixPiuDlPiuStopAndReset() is used instead. Unlike + * ixPiuDlPiuStopAndReset(), this function only halts the PIU and leaves + * all registers and settings intact. This is useful, for example, between + * stages of a multi-stage download, to stop the PIU prior to downloading the + * next image while leaving the current state of the PIU intact.. + * + * @pre + * - The Client is responsible for ensuring mutual access to the PIU. + * + * @post + * + * @return + * - IX_SUCCESS if the operation was successful + * - IX_PIUDL_PARAM_ERR if a parameter error occured + * - IX_FAIL otherwise + */ +ix_error +ixPiuDlPiuExecutionStop (IxPiuDlPiuId piuId); + +#endif /* IXPIUDL_P_H */ + +/** + * @} defgroup IxPiuDl_p + */ + diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuMicrocode.h b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuMicrocode.h new file mode 100644 index 0000000..cf34b49 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuMicrocode.h @@ -0,0 +1,123 @@ +/** + * @date February 25, 2009 + * + * @brief IXP400 PIU Microcode Image file + * + * This file was generated by the IxPiuDlImageGen tool. + * It contains a PIU microcode image suitable for use + * with the PIU Downloader (IxPiuDl) component in the + * IXP400 Access Driver software library. + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + +/** + * @defgroup IxPiuMicrocode Intel (R) IXP400 PIU Microcode Image Library + * + * @brief Library containing a set of PIU firmware images, for use + * with PIU Downloader s/w component + * + * @{ + */ + +/** + * @def IX_PIU_IMAGE_INCLUDE + * + * @brief Wrap the following Image identifiers with "#if IX_PIU_IMAGE_INCLUDE ... #endif" to include the image in the library + */ +#define IX_PIU_IMAGE_INCLUDE 1 + +/** + * @def IX_PIU_IMAGE_OMIT + * + * @brief Wrap the following Image identifiers with "#if IX_PIU_IMAGE_OMIT ... #endif" to OMIT the image from the library + */ +#define IX_PIU_IMAGE_OMIT 0 + + +#if IX_PIU_IMAGE_INCLUDE +/** + * @def IX_PIUDL_PIUIMAGE_PIU_HSS_TOLAPAI + * + * @brief Common HSS Build for Tolapai platform + */ +#define IX_PIUDL_PIUIMAGE_PIU_HSS_TOLAPAI 0x30010000 +#endif + +/* Number of PIU firmware images in this library */ +#define IX_PIU_MICROCODE_AVAILABLE_VERSIONS_COUNT 1 + +/* Location of Microcode Images */ +#ifdef IX_PIU_MICROCODE_FIRMWARE_INCLUDED +#ifdef IX_PIUDL_READ_MICROCODE_FROM_FILE + +extern UINT32* ixPiuMicrocode_binaryArray; + +#else + +extern unsigned IxPiuMicrocode_array[]; + +#endif +#endif + +/** + * @} defgroup IxPiuMicrocode + */ diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/linux_2.6_kernel_space.mk b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/linux_2.6_kernel_space.mk new file mode 100644 index 0000000..6feb7cc --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/linux_2.6_kernel_space.mk @@ -0,0 +1,76 @@ +################### +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# Contact Information: +# Intel Corporation +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# +################### + +#specific include directories in kernel space +INCLUDES+= -I $(ICP_OSAL_DIR)/platforms/EP805XX/include \ + -I $(ICP_OSAL_DIR)/platforms/EP805XX/os/linux/include \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/core \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules/ddk \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules/ioMem \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules/bufferMgt + +#Extra Flags Specific in kernel space e.g. include path or debug flags etc. e.g to add an include path EXTRA_CFLAGS += -I$(src)/../include +EXTRA_CFLAGS += $(INCLUDES) -DTOLAPAI -D__tolapai -DEP805XX -D__ep805xx -DIX_HW_COHERENT_MEMORY=1 +EXTRA_LDFLAGS+=-whole-archive + + diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/source/IxPiuDl.c b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/source/IxPiuDl.c new file mode 100644 index 0000000..6f36c1e --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/source/IxPiuDl.c @@ -0,0 +1,599 @@ +/** + * @file IxPiuDl.c + * + * @author Intel Corporation + * @date 13 August 2003 + * + * @description Contents are the implementation of the public API for the + * PIU Downloader component + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +/* + * Put the system defined include files required + */ + +/* + * Put the user defined include files required + */ +#include "IxPiuDl.h" +#include "IxPiuDlImageMgr_p.h" +#include "IxPiuDlPiuMgr_p.h" +#include "IxPiuDlMacros_p.h" +#include "IxPiuDl_p.h" + +/* + * #defines used in this file + */ +#define IMAGEID_MAJOR_NUMBER_DEFAULT 0 +#define IMAGEID_MINOR_NUMBER_DEFAULT 0 + +/* + * Typedefs whose scope is limited to this file. + */ +typedef struct +{ + BOOL validImage; + IxPiuDlImageId imageId; +} IxPiuDlPiuState; + +/* module statistics counters */ +typedef struct +{ + ix_uint32 attemptedDownloads; + ix_uint32 successfulDownloads; + ix_uint32 criticalFailDownloads; /*This means the PIU is in a bad state*/ +} IxPiuDlStats; + +/* + * Variable declarations global to this file only. Externs are followed + * by static variables. + */ +static IxPiuDlPiuState ixPiuDlPiuState[IX_PIUDL_PIUID_MAX] = +{ + { + FALSE, /*TRUE if valid image downloaded*/ + {0,0,0,0} /* ID of the image*/ + } + +#if !defined(__ep805xx) + , + { + FALSE, /*TRUE if valid image downloaded*/ + {0,0,0,0} /* ID of the image*/ + } +#endif +}; + +static IxPiuDlStats ixPiuDlStats; + +/* + * Software guard to prevent PIU from being started multiple times. + */ +#if defined(__ep805xx) +static BOOL ixPiuDlPiuStarted[IX_PIUDL_PIUID_MAX] ={FALSE } ; +#else +static BOOL ixPiuDlPiuStarted[IX_PIUDL_PIUID_MAX] ={FALSE, FALSE } ; +#endif + +/* + * static function prototypes. + */ +PIU_PRIVATE ix_error +ixPiuDlPiuInitAndStartInternal (ix_uint32 *imageLibrary, ix_uint32 imageId); + + +/* + * Function definition: ixPiuDlPiuStopAndReset + */ +ix_error +ixPiuDlPiuStopAndReset (IxPiuDlPiuId piuId) +{ + ix_error status = IX_SUCCESS; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPiuStopAndReset\n"); + + /* Check input parameters */ + if ((piuId >= IX_PIUDL_PIUID_MAX) || (piuId < 0)) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuStopAndReset - invalid parameter\n"); + status = IX_PIUDL_PARAM_ERR; + } + + if (status == IX_SUCCESS) + { + /* Ensure initialisation has been completed */ + ixPiuDlPiuMgrInit(); + + /* call PiuMgr function to stop the PIU */ + status = ixPiuDlPiuMgrPiuStop (piuId); + } + + if (status == IX_SUCCESS) + { + /* call PiuMgr function to reset the PIU */ + status = ixPiuDlPiuMgrPiuReset (piuId); + } + + if (IX_SUCCESS == status) + { + /* Indicate PIU has been stopped */ + ixPiuDlPiuStarted[piuId] = FALSE ; + } + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPiuStopAndReset : status = %u\n", status); + + return status; +} + +/* + * Function definition: ixPiuDlPiuExecutionStart + */ +ix_error +ixPiuDlPiuExecutionStart (IxPiuDlPiuId piuId) +{ + ix_error status = IX_SUCCESS; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPiuExecutionStart\n"); + + if (TRUE == ixPiuDlPiuStarted[piuId]) + { + /* PIU has been started. */ + return IX_SUCCESS ; + } + + /* Ensure initialisation has been completed */ + ixPiuDlPiuMgrInit(); + + /* call PiuMgr function to start the PIU */ + status = ixPiuDlPiuMgrPiuStart (piuId); + + if (IX_SUCCESS == status) + { + /* Indicate PIU has started */ + ixPiuDlPiuStarted[piuId] = TRUE ; + } + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPiuExecutionStart : status = %u\n", + status); + + return status; +} + +/* + * Function definition: ixPiuDlPiuExecutionStop + */ +ix_error +ixPiuDlPiuExecutionStop (IxPiuDlPiuId piuId) +{ + ix_error status = IX_SUCCESS; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPiuExecutionStop\n"); + + /* Ensure initialisation has been completed */ + ixPiuDlPiuMgrInit(); + + /* call PiuMgr function to stop the PIU */ + status = ixPiuDlPiuMgrPiuStop (piuId); + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPiuExecutionStop : status = %u\n", + status); + + if (IX_SUCCESS == status) + { + /* Indicate PIU has been stopped */ + ixPiuDlPiuStarted[piuId] = FALSE ; + } + + return status; +} + +/* + * Function definition: ixPiuDlUnload + */ +ix_error +ixPiuDlUnload (void) +{ + ix_error status; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlUnload\n"); + + status = ixPiuDlPiuMgrUninit(); + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlUnload : status = %u\n", + status); + return status; +} + +/* + * Function definition: ixPiuDlStatsShow + */ +void +ixPiuDlStatsShow (void) +{ + printf("\nixPiuDlStatsShow:\n"); + + printf("\tDownloads Attempted by user: %u\n", + ixPiuDlStats.attemptedDownloads); + printf("\tSuccessful Downloads: %u\n", + ixPiuDlStats.successfulDownloads); + printf("\tFailed Downloads (due to Critical Error, PIU in bad state): %u\n", + ixPiuDlStats.criticalFailDownloads); + + printf("\n"); + + ixPiuDlImageMgrStatsShow (); + ixPiuDlPiuMgrStatsShow (); +} + +/* + * Function definition: ixPiuDlStatsReset + */ +void +ixPiuDlStatsReset (void) +{ + ixPiuDlStats.attemptedDownloads = 0; + ixPiuDlStats.successfulDownloads = 0; + ixPiuDlStats.criticalFailDownloads = 0; + + ixPiuDlImageMgrStatsReset (); + ixPiuDlPiuMgrStatsReset (); +} + +/* + * Function definition: ixPiuDlPiuInitAndStartInternal + */ +PIU_PRIVATE ix_error +ixPiuDlPiuInitAndStartInternal (ix_uint32 *imageLibrary, + ix_uint32 imageId) +{ + ix_uint32 imageSize; + ix_uint32 *imageCodePtr = NULL; + ix_error status; + IxPiuDlPiuId piuId = IX_PIUDL_PIUID_FROM_IMAGEID_GET(imageId); + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPiuInitAndStartInternal\n"); + IX_PIUDL_TRACE1 (IX_PIUDL_DEBUG, + "Download and Start Image 0x%08X\n", + imageId); + + ixPiuDlStats.attemptedDownloads++; + + /* Check input parameters */ + if ((piuId >= IX_PIUDL_PIUID_MAX) || (piuId < 0)) + { + status = IX_PIUDL_PARAM_ERR; + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuInitAndStartInternal - " + "invalid parameter\n"); + } + else + { + /* Ensure initialisation has been completed */ + ixPiuDlPiuMgrInit(); + + /* stop and reset the PIU */ + if (IX_SUCCESS != ixPiuDlPiuStopAndReset (piuId)) + { + IX_PIUDL_ERROR_REPORT ("Failed to stop and reset PIU\n"); + return IX_FAIL; + } + + /* Locate image */ + status = ixPiuDlImageMgrImageFind (imageLibrary, imageId, + &imageCodePtr, &imageSize); + + if (IX_SUCCESS == status) + { + /* + * If download was successful, store image Id in list of + * currently loaded images. If a critical error occured + * during download, record that the PIU has an invalid image + */ + status = ixPiuDlPiuMgrImageLoad (piuId, imageCodePtr, TRUE); + + if (IX_SUCCESS == status) + { + ixPiuDlPiuState[piuId].validImage = TRUE; + ixPiuDlStats.successfulDownloads++; + + status = ixPiuDlPiuExecutionStart (piuId); + } + else if ((status == IX_PIUDL_CRITICAL_PIU_ERR) || + (status == IX_PIUDL_CRITICAL_MICROCODE_ERR)) + { + ixPiuDlPiuState[piuId].validImage = FALSE; + ixPiuDlStats.criticalFailDownloads++; + } + + ixPiuDlImageMgrImageIdFormat(imageId, + &(ixPiuDlPiuState[piuId].imageId)); + + } /* end of if(IX_SUCCESS) */ + /* condition: image located successfully in microcode image */ + } /* end of if-else(piuId) *//* condition: parameter checks ok */ + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPiuInitAndStartInternal : " + "status = %u\n", status); + return status; +} + +/* + * Function definition: ixPiuDlCustomImagePiuInitAndStart + */ +ix_error +ixPiuDlCustomImagePiuInitAndStart (ix_uint32 *imageLibrary, + ix_uint32 imageId) +{ + ix_error status; + if (imageLibrary == NULL) + { + status = IX_PIUDL_PARAM_ERR; + IX_PIUDL_ERROR_REPORT ("ixPiuDlCustomImagePiuInitAndStart " + "- invalid parameter\n"); + } + else + { + status = ixPiuDlPiuInitAndStartInternal (imageLibrary,imageId ); + } /* end of if-else(imageLibrary) */ + + return status; +} + +/* + * Function definition: ixPiuDlPiuInitAndStart + */ +ix_error +ixPiuDlPiuInitAndStart (ix_uint32 imageId) +{ + return ixPiuDlPiuInitAndStartInternal (NULL, imageId); +} + +/* + * Function definition: ixPiuDlLoadedImageGet + */ +ix_error +ixPiuDlLoadedImageGet (IxPiuDlPiuId piuId, + IxPiuDlImageId *imageIdPtr) +{ + ix_error status = IX_SUCCESS; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlLoadedImageGet\n"); + + /* Check input parameters */ + if ((piuId >= IX_PIUDL_PIUID_MAX) || (piuId < 0) || (imageIdPtr == NULL)) + { + status = IX_PIUDL_PARAM_ERR; + IX_PIUDL_ERROR_REPORT ("ixPiuDlLoadedImageGet - invalid parameter\n"); + } + else + { + + if (ixPiuDlPiuState[piuId].validImage) + { + /* use piuId to get imageId from list of currently loaded + images */ + *imageIdPtr = ixPiuDlPiuState[piuId].imageId; + } + else + { + status = IX_FAIL; + IX_PIUDL_ERROR_REPORT ("ixPiuDlLoadedImageGet - " + "PIU does not have a valid image\n"); + } /* end of if-else(ixPiuDlPiuState) */ + } /* end of if-else(piuId) */ + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlLoadedImageGet : status = %d\n", + status); + return status; +} + + +/* + * Function definition: ixPiuDlAvailableImagesListGet + */ +ix_error +ixPiuDlAvailableImagesListGet (IxPiuDlImageId *imageIdListPtr, + ix_uint32 *listSizePtr) +{ + ix_error status; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlAvailableImagesListGet\n"); + + /* Check input parameters */ + if ((imageIdListPtr == NULL) || (listSizePtr == NULL)) + { + status = IX_PIUDL_PARAM_ERR; + IX_PIUDL_ERROR_REPORT ("ixPiuDlAvailableImagesListGet - " + "invalid parameter\n"); + } + else + { + /* Call ImageMgr to get list of images listed in Image Library Header */ + status = ixPiuDlImageMgrImageListExtract (imageIdListPtr, + listSizePtr); + } /* end of if-else(imageIdListPtr) */ + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlAvailableImagesListGet : status = %d\n", + status); + return status; +} +#if defined(__ep805xx) + +/* + * Function definition: ixPiuDlPhysicalAddressSet + */ +ix_error +ixPiuDlPhysicalAddressSet ( + IxPiuDlPiuId piuId, + ix_uint32 address) +{ + ix_error status = IX_SUCCESS; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPhysicalAddressSet\n"); + + /* Check input parameters */ + if ((piuId >= IX_PIUDL_PIUID_MAX) || (piuId < 0)) + { + status = IX_PIUDL_PARAM_ERR; + IX_PIUDL_ERROR_REPORT("ixPiuDlPhysicalAddressSet - invalid " + "parameter\n"); + } + else + { + /* store the address */ + status = ixPiuDlPiuMgrPhysicalAddressSet(piuId, address); + } + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPhysicalAddressSet : status = %d\n", + status); + return status; +} + +/* + * Function definition: ixPiuDlAppDualSet + */ +ix_error +ixPiuDlAppDualSet ( + IxPiuDlPiuId piuId, + ix_uint32 appDualId, + IxPiuDlAppDualInstruction *appDualInstruction ) +{ + ix_error status = IX_SUCCESS; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlAppDualSet\n"); + + /* Check input parameters */ + if ((piuId >= IX_PIUDL_PIUID_MAX) || (piuId < 0)) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlAppDualSet - invalid parameter\n"); + return IX_PIUDL_PARAM_ERR; + } + if (appDualInstruction == NULL) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlAppDualSet - invalid parameter\n"); + return IX_PIUDL_PARAM_ERR; + } + + /* set the appDual register */ + status = ixPiuDlPiuMgrAppDualSet(piuId, appDualId, appDualInstruction); + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlAppDualSet : status = %d\n", + status); + return status; +} + +/* + * Function definition: ixPiuDlAppDualGet + */ +ix_error +ixPiuDlAppDualGet ( + IxPiuDlPiuId piuId, + ix_uint32 appDualId, + IxPiuDlAppDualInstruction *appDualInstruction ) +{ + ix_error status = IX_SUCCESS; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlAppDualGet\n"); + + /* Check input parameters */ + if ((piuId >= IX_PIUDL_PIUID_MAX) || (piuId < 0)) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlAppDualGet - invalid parameter\n"); + return IX_PIUDL_PARAM_ERR; + } + if (appDualInstruction == NULL) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlAppDualSet - invalid parameter\n"); + return IX_PIUDL_PARAM_ERR; + } + + /* get the appDual register */ + status = ixPiuDlPiuMgrAppDualGet(piuId, appDualId,appDualInstruction); + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlAppDualGet : status = %d\n", + status); + return status; +} + +#endif /* #if defined(__ep805xx) */ + diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/source/IxPiuDlFwLoader.c b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/source/IxPiuDlFwLoader.c new file mode 100644 index 0000000..79ccf51 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/source/IxPiuDlFwLoader.c @@ -0,0 +1,210 @@ +/** + * @file IxPiuDlFwLoader.c + * + * @author Intel Corporation + * @date 25 June 2007 + * + * @brief Contents are the implementation of a method for reading PIU firmware + * from file using the 'request_firmware' loading mechanism available in Linux + * kernel v2.6 + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +/* + * Put the system defined include files required + */ + +#include "linux/device.h" +#include "linux/firmware.h" + +/* + * Put the user defined include files required + */ +#include "IxPiuDlFwLoader_p.h" +#include "IxPiuDlMacros_p.h" + +/* + * Variable declarations global to this file only. Externs are followed + * by static variables. + */ + +/* + * release function for piu firmware temporary device below + */ +static void piuDeviceRelease(struct device *dev) +{ + printk("piuDevice released after loading firmware\n"); +} + +/* + * The following is a temporary device which is used for loading the firmware + * image - the 'request_firmware()' function needs a device to be passed to it - + * it doesn't matter what the device is - once the device is within the system, + * the udev looks for the requested file from the /lib/firmware location - the + * approach here is to create a temporary device so as not to have any + * dependencies on any particular devices + */ + +static struct device piuFirmwareDevice = { +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30) + .init_name = "piuDevice", +#else + .bus_id = "piuDevice", +#endif + .release = piuDeviceRelease +}; + +/* + * the following is used to record when firmware has been loaded such that + * loading a new image without freeing a previous one and freeing an image + * before loading can be prevented + */ +static BOOL piuFwLoaded = FALSE; + +/* + * the following is used to store the firmware (populated by the + * request_firmware function) + */ +const struct firmware *piuFwEntry; + +/* + * the name of the file to load + */ +#define PIU_FIRMWARE_FILENAME "IxPiuMicrocode.dat" + +/* + * Function definition: ixPiuDlFwLoaderGetFw + */ +ix_error +ixPiuDlFwLoaderGetFw(ix_uint32** firmwareArray) +{ + int r; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlFwLoaderGetFw\n"); + + /* + * first check if the fw is already loaded - if it is then release the + * piuFwEntry structure + */ + if (piuFwLoaded) + { + release_firmware(piuFwEntry); + piuFwLoaded = FALSE; + } + + /* register the temporary device used for requesting firmware */ + if (device_register(&piuFirmwareDevice) != 0) + { + /* BUGBUG? should we also put_device? */ + IX_PIUDL_ERROR_REPORT ("ixPiuDlFwLoaderGetFw: could not register device\n"); + return IX_FAIL; + } + + /* load the firmware */ + if ((r = request_firmware(&piuFwEntry, PIU_FIRMWARE_FILENAME, + &piuFirmwareDevice)) != 0) + { + ixOsalLog(IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, + "Error loading " PIU_FIRMWARE_FILENAME " from file: %d\n", + r, 0, 0, 0, 0, 0); + + /* unregister the temporary device from the system */ + device_unregister(&piuFirmwareDevice); + + return IX_FAIL; + } + + /* record successful load */ + piuFwLoaded = TRUE; + + /* cast the firmware pointer to the required type */ + *firmwareArray = (ix_uint32*) piuFwEntry->data; + + /* unregister the temporary device from the system */ + device_unregister(&piuFirmwareDevice); + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlFwLoaderGetFw\n"); + + return IX_SUCCESS; +} + +/* + * Function definition: ixPiuDlFwLoaderCleanup + */ +void +ixPiuDlFwLoaderCleanup(void) +{ + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlFwLoaderCleanup\n"); + + if (piuFwLoaded) + { + /* release the structure used to hold the firmware */ + release_firmware(piuFwEntry); + piuFwLoaded = FALSE; + } + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlFwLoaderCleanup\n"); +} diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/source/IxPiuDlImageMgr.c b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/source/IxPiuDlImageMgr.c new file mode 100644 index 0000000..76685b6 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/source/IxPiuDlImageMgr.c @@ -0,0 +1,416 @@ +/** + * @file IxPiuDlImageMgr.c + * + * @author Intel Corporation + * @date 13 August 2003 + * + * @description Contents are the implementation of the private API for the + * PIU Downloader ImageMgr module + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + + +/* + * Put the system defined include files required. + */ + + +/* + * Put the user defined include files required. + */ +#include "IxPiuDlImageMgr_p.h" +#include "IxPiuDlMacros_p.h" + +#if defined(IX_PIUDL_READ_MICROCODE_FROM_FILE) && defined (__ep805xx) +#include "IxPiuDlFwLoader_p.h" +#else +/* + * define the flag which toggles the firmare inclusion + */ +#define IX_PIU_MICROCODE_FIRMWARE_INCLUDED +#include "IxPiuMicrocode.h" +#endif + + +/* + * Typedefs whose scope is limited to this file. + */ + +typedef struct +{ + ix_uint32 size; + ix_uint32 offset; + ix_uint32 id; +} IxPiuDlImageMgrImageEntry; + +typedef union +{ + IxPiuDlImageMgrImageEntry image; + ix_uint32 eohMarker; +} IxPiuDlImageMgrHeaderEntry; + +typedef struct +{ + ix_uint32 signature; + /* 1st entry in the header (there may be more than one) */ + IxPiuDlImageMgrHeaderEntry entry[1]; +} IxPiuDlImageMgrImageLibraryHeader; + + +/* + * PIU Image Header definition, used in new PIU Image Library format + */ +typedef struct +{ + ix_uint32 marker; + ix_uint32 id; + ix_uint32 size; +} IxPiuDlImageMgrImageHeader; + + +/* module statistics counters */ +typedef struct +{ + ix_uint32 invalidSignature; + ix_uint32 imageIdListOverflow; + ix_uint32 imageIdNotFound; +} IxPiuDlImageMgrStats; + + +/* + * Variable declarations global to this file only. Externs are followed by + * static variables. + */ +static IxPiuDlImageMgrStats ixPiuDlImageMgrStats; + +/* default image */ +#ifdef IX_PIUDL_READ_MICROCODE_FROM_FILE + +#if !defined(__ep805xx) +extern ix_uint32 *ixPiuMicrocode_binaryArray; +#endif + +static ix_uint32 *IxPiuMicroCodeImageLibrary = NULL; + +#else +static ix_uint32 *IxPiuMicroCodeImageLibrary = (ix_uint32*)IxPiuMicrocode_array; +#endif + +/* + * static function prototypes. + */ +PIU_PRIVATE BOOL +ixPiuDlImageMgrSignatureCheck (ix_uint32 *microCodeImageLibrary); + + +/* + * Function definition: ixPiuDlImageMgrSignatureCheck + */ +PIU_PRIVATE BOOL +ixPiuDlImageMgrSignatureCheck (ix_uint32 *microCodeImageLibrary) +{ + IxPiuDlImageMgrImageLibraryHeader *header = + (IxPiuDlImageMgrImageLibraryHeader *) microCodeImageLibrary; + BOOL result = TRUE; + + if (header->signature != IX_PIUDL_IMAGEMGR_SIGNATURE) + { + result = FALSE; + ixPiuDlImageMgrStats.invalidSignature++; + } + + return result; +} + + + +/* + * Function definition: ixPiuDlImageMgrStatsShow + */ +void +ixPiuDlImageMgrStatsShow (void) +{ + printf ("\nixPiuDlImageMgrStatsShow:\n"); + + printf ("\tInvalid Image Signatures: %u\n", + ixPiuDlImageMgrStats.invalidSignature); + printf ("\tImage Id List capacity too small: %u\n", + ixPiuDlImageMgrStats.imageIdListOverflow); + printf ("\tImage Id not found: %u\n", + ixPiuDlImageMgrStats.imageIdNotFound); + + printf ("\n"); +} + + +/* + * Function definition: ixPiuDlImageMgrStatsReset + */ +void +ixPiuDlImageMgrStatsReset (void) +{ + ixPiuDlImageMgrStats.invalidSignature = 0; + ixPiuDlImageMgrStats.imageIdListOverflow = 0; + ixPiuDlImageMgrStats.imageIdNotFound = 0; +} + +/* + * Function definition: ixPiuDlImageMgrImageFind + */ +ix_error +ixPiuDlImageMgrImageFind ( + ix_uint32 *imageLibrary, + ix_uint32 imageId, + ix_uint32 **imagePtr, + ix_uint32 *imageSize) +{ + ix_uint32 offset = 0; + IxPiuDlImageMgrImageHeader *image; + ix_error status = IX_FAIL; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlImageMgrImageFind\n"); + IX_PIUDL_TRACE1 (IX_PIUDL_DEBUG, + "Looking for Image 0x%08X\n",imageId); + + + /* If user didn't specify a library to use, use the default + * one from IxPiuMicrocode.h + */ + if (imageLibrary == NULL) + { +#ifdef IX_PIUDL_READ_MICROCODE_FROM_FILE + +#if defined(__ep805xx) + /* + * For EP805xx use the linux 2.6 firmware download mechanism available + * in the kernel to read the firmware + */ + + if (ixPiuDlFwLoaderGetFw(&imageLibrary) != IX_SUCCESS) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlImageMgrImageFind: Failed " + "to load Microcode Image from file\n"); + return IX_FAIL; + } +#else + /* + * For ixp23xx use the pre linux 2.6 download mechanism which uses an + * PIU character device driver to read the firmware + */ + if (ixPiuMicrocode_binaryArray == NULL) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlImageMgrImageFind: " + "No Microcode Loaded in memory\n"); + return IX_FAIL; + } + else + { + imageLibrary = ixPiuMicrocode_binaryArray; + } +#endif /* #if defined(__ep805xx) */ + +#else + /* + * image is already in memory + */ + IX_PIUDL_TRACE1 (IX_PIUDL_DEBUG, + "Looking in library at 0x%08X\n", + (ix_uint32)IxPiuMicroCodeImageLibrary); + imageLibrary = IxPiuMicroCodeImageLibrary; +#endif + } + + if (ixPiuDlImageMgrSignatureCheck (imageLibrary)) + { + while (*(imageLibrary+offset) == IX_PIUDL_IMAGEMGR_SIGNATURE) + { + image = (IxPiuDlImageMgrImageHeader *)(imageLibrary+offset); + offset += sizeof(IxPiuDlImageMgrImageHeader)/sizeof(ix_uint32); + + if (image->id == imageId) + { + *imagePtr = imageLibrary + offset; + *imageSize = image->size; + return IX_SUCCESS; + } + /* 2 consecutive IX_PIUDL_IMAGEMGR_SIGNATURE's indicates end of + * library */ + else if (image->id == IX_PIUDL_IMAGEMGR_SIGNATURE) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlImageMgrImageFind: " + "imageId not found in image library header\n"); + ixPiuDlImageMgrStats.imageIdNotFound++; + /* reached end of library, image not found */ + return IX_FAIL; + } + offset += image->size; + } + /* If we get here, our image library may be corrupted */ + IX_PIUDL_ERROR_REPORT ("ixPiuDlImageMgrImageFind: " + "image library format may be invalid or corrupted\n"); + } + else + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlImageMgrImageFind: " + "invalid signature in image library\n"); + } + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlImageMgrImageFind: status = %u\n", status); + return status; +} + + +/* + * Function definition: ixPiuDlImageMgrImageIdFormat + */ +void +ixPiuDlImageMgrImageIdFormat ( + ix_uint32 rawImageId, + IxPiuDlImageId *imageId) +{ + imageId->piuId = (rawImageId >> + IX_PIUDL_IMAGEID_PIUCODE_OFFSET) & + IX_PIUDL_PIUIMAGE_FIELD_MASK; + imageId->functionalityId = (rawImageId >> + IX_PIUDL_IMAGEID_FUNCTIONID_OFFSET) & + IX_PIUDL_PIUIMAGE_FIELD_MASK; + imageId->major = (rawImageId >> + IX_PIUDL_IMAGEID_MAJOR_OFFSET) & + IX_PIUDL_PIUIMAGE_FIELD_MASK; + imageId->minor = (rawImageId >> + IX_PIUDL_IMAGEID_MINOR_OFFSET) & + IX_PIUDL_PIUIMAGE_FIELD_MASK; + +} + +/* + * Function definition: ixPiuDlImageMgrImageListExtract + */ +ix_error +ixPiuDlImageMgrImageListExtract ( + IxPiuDlImageId *imageListPtr, + ix_uint32 *numImages) +{ + IxPiuDlImageId formattedImageId; + ix_error status = IX_SUCCESS; + ix_uint32 imageCount = 0; + IxPiuDlImageMgrImageLibraryHeader *header; + ix_uint32 *microcode; + ix_uint32 index = 0; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlImageMgrImageListExtract\n"); + + microcode = (ix_uint32*) IxPiuMicroCodeImageLibrary; + header = (IxPiuDlImageMgrImageLibraryHeader *) IxPiuMicroCodeImageLibrary; + + if (ixPiuDlImageMgrSignatureCheck ((ix_uint32*)header)) + { + IX_PIUDL_TRACE0 (IX_PIUDL_DEBUG, + "ixPiuDlImageMgrImageListExtract: About to search\n"); + while (!((microcode[index] == IX_PIUDL_IMAGEMGR_SIGNATURE) && + (microcode[index+1] == IX_PIUDL_IMAGEMGR_SIGNATURE))) + { + if (microcode[index] == IX_PIUDL_IMAGEMGR_SIGNATURE) + { + IX_PIUDL_TRACE0 (IX_PIUDL_DEBUG, + "ixPiuDlImageMgrImageListExtract: found an image\n"); + ixPiuDlImageMgrImageIdFormat (microcode[index+1], + &formattedImageId); + imageListPtr[imageCount] = formattedImageId; + imageCount++; + } + index++; + } + + /* + * if image list container from calling function was too small to + * contain all image ids in the header, set return status to FAIL + */ + if ((imageListPtr != NULL) && (imageCount > *numImages)) + { + status = IX_FAIL; + IX_PIUDL_ERROR_REPORT ("ixPiuDlImageMgrImageListExtract: " + "number of Ids found exceeds list capacity\n"); + ixPiuDlImageMgrStats.imageIdListOverflow++; + } + /* return number of image ids found in image library header */ + *numImages = imageCount; + } + else + { + status = IX_FAIL; + IX_PIUDL_ERROR_REPORT ("ixPiuDlImageMgrImageListExtract: " + "invalid signature in image\n"); + } + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlImageMgrImageListExtract: status = %d\n", + status); + return status; +} + + + diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/source/IxPiuDlPiuMgr.c b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/source/IxPiuDlPiuMgr.c new file mode 100644 index 0000000..4fe9a41 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/source/IxPiuDlPiuMgr.c @@ -0,0 +1,1547 @@ +/** + * @file IxPiuDlPiuMgr.c + * + * @author Intel Corporation + * @date 13 August 2003 + * + * @description Contents are the implementation of the private API for the + * PIU Downloader PiuMgr module + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + + +/* + * Put the user defined include files required. + */ + + +/* + * Put the user defined include files required. + */ +#include "IxPiuDl.h" +#include "IxPiuDlPiuMgr_p.h" +#include "IxPiuDlPiuMgrUtils_p.h" +#include "IxPiuDlPiuMgrEcRegisters_p.h" +#include "IxPiuDlMacros_p.h" + +#if defined(IX_PIUDL_READ_MICROCODE_FROM_FILE) && defined (__ep805xx) +#include "IxPiuDlFwLoader_p.h" +#endif + +/* + * #defines and macros used in this file. + */ +#define IX_PIUDL_BYTES_PER_WORD 4 + +/* used to read download map from version in microcode image */ +#define IX_PIUDL_BLOCK_TYPE_INSTRUCTION 0x00000000 +#define IX_PIUDL_BLOCK_TYPE_DATA 0x00000001 +#define IX_PIUDL_BLOCK_TYPE_STATE 0x00000002 +#define IX_PIUDL_END_OF_DOWNLOAD_MAP 0x0000000F + + + +#define IX_PIUDL_PIU0_RESET_BIT_OFFSET 4 +#define IX_PIUDL_PIU1_RESET_BIT_OFFSET 5 + + +/* + * masks used to extract address info from State information context + * register addresses as read from microcode image + */ +#define IX_PIUDL_MASK_STATE_ADDR_CTXT_REG 0x0000000F +#define IX_PIUDL_MASK_STATE_ADDR_CTXT_NUM 0x000000F0 + +/* LSB offset of Context Number field in State-Info Context Address */ +#define IX_PIUDL_OFFSET_STATE_ADDR_CTXT_NUM 4 + +/* size (in words) of single State Information entry (ctxt reg address|data) */ +#define IX_PIUDL_STATE_INFO_ENTRY_SIZE 2 + +/* size of Co-Processor reset instruction */ +#define IX_PIUDL_CP_RESET_SIZE 16 + +/* value for Co-Processor. There is one bit for each of 16 possible + co-processors. If a co-processor does not exist, setting it's bit + to one has no effect. */ +#define IX_PIUDL_CP_RESET_VALUE 0xFFFF + + + +/* + * Typedefs whose scope is limited to this file. + */ + +typedef struct +{ + ix_uint32 type; + ix_uint32 offset; +} IxPiuDlPiuMgrDownloadMapBlockEntry; + +typedef union +{ + IxPiuDlPiuMgrDownloadMapBlockEntry block; + ix_uint32 eodmMarker; +} IxPiuDlPiuMgrDownloadMapEntry; + +typedef struct +{ + /* 1st entry in the download map (there may be more than one) */ + IxPiuDlPiuMgrDownloadMapEntry entry[1]; +} IxPiuDlPiuMgrDownloadMap; + + +/* used to access an instruction or data block in a microcode image */ +typedef struct +{ + ix_uint32 piuMemAddress; + ix_uint32 size; + ix_uint32 data[1]; +} IxPiuDlPiuMgrCodeBlock; + +/* used to access each Context Reg entry state-information block */ +typedef struct +{ + ix_uint32 addressInfo; + ix_uint32 value; +} IxPiuDlPiuMgrStateInfoCtxtRegEntry; + +/* used to access a state-information block in a microcode image */ +typedef struct +{ + ix_uint32 size; + IxPiuDlPiuMgrStateInfoCtxtRegEntry ctxtRegEntry[1]; +} IxPiuDlPiuMgrStateInfoBlock; + +/* used to store some useful PIU information for easy access */ +typedef struct +{ +#if defined(__ep805xx) + ix_uint32 physicalBaseAddress; +#endif + ix_uint32 baseAddress; + ix_uint32 insMemSize; + ix_uint32 dataMemSize; +} IxPiuDlPiuInfo; + +/* used to distinguish instruction and data memory operations */ +typedef enum +{ + IX_PIUDL_MEM_TYPE_INSTRUCTION = 0, + IX_PIUDL_MEM_TYPE_DATA +} IxPiuDlPiuMemType; + +/* used to hold a reset value for a particular ECS register */ +typedef struct +{ + ix_uint32 regAddr; + ix_uint32 regResetVal; +} IxPiuDlEcsRegResetValue; + +/* prototype of function to write either Instruction or Data memory */ +typedef ix_error (*IxPiuDlPiuMgrMemWrite) (ix_uint32 piuBaseAddress, + ix_uint32 piuMemAddress, + ix_uint32 piuMemData, + BOOL verify); + +/* module statistics counters */ +typedef struct +{ + ix_uint32 instructionBlocksLoaded; + ix_uint32 dataBlocksLoaded; + ix_uint32 instructionMemInit; + ix_uint32 dataMemInit; + ix_uint32 stateInfoBlocksLoaded; + ix_uint32 criticalPiuErrors; + ix_uint32 criticalMicrocodeErrors; + ix_uint32 piuStarts; + ix_uint32 piuStops; + ix_uint32 piuResets; +} IxPiuDlPiuMgrStats; + + +/* + * Variable declarations global to this file only. Externs are followed by + * static variables. + */ +static IxPiuDlPiuInfo ixPiuDlPiuInfo[IX_PIUDL_PIUID_MAX] = +{ + { +#if defined(__ep805xx) + 0, +#endif + 0, + IX_PIUDL_INS_MEMSIZE_WORDS_PIU0, + IX_PIUDL_DATA_MEMSIZE_WORDS_PIU0 + } +#if !defined(__ep805xx) + , + { + 0, + IX_PIUDL_INS_MEMSIZE_WORDS_PIU1, + IX_PIUDL_DATA_MEMSIZE_WORDS_PIU1 + } +#endif +}; + +/* contains Reset values for Context Store Registers */ +static ix_uint32 ixPiuDlCtxtRegResetValues[] = +{ + IX_PIUDL_CTXT_REG_RESET_STEVT, + IX_PIUDL_CTXT_REG_RESET_STARTPC, + IX_PIUDL_CTXT_REG_RESET_REGMAP, + IX_PIUDL_CTXT_REG_RESET_CINDEX, +}; + +/* contains Reset values for Context Store Registers */ +static IxPiuDlEcsRegResetValue ixPiuDlEcsRegResetValues[] = +{ + {IX_PIUDL_ECS_BG_CTXT_REG_0, IX_PIUDL_ECS_BG_CTXT_REG_0_RESET}, + {IX_PIUDL_ECS_BG_CTXT_REG_1, IX_PIUDL_ECS_BG_CTXT_REG_1_RESET}, + {IX_PIUDL_ECS_BG_CTXT_REG_2, IX_PIUDL_ECS_BG_CTXT_REG_2_RESET}, + {IX_PIUDL_ECS_PRI_1_CTXT_REG_0, IX_PIUDL_ECS_PRI_1_CTXT_REG_0_RESET}, + {IX_PIUDL_ECS_PRI_1_CTXT_REG_1, IX_PIUDL_ECS_PRI_1_CTXT_REG_1_RESET}, + {IX_PIUDL_ECS_PRI_1_CTXT_REG_2, IX_PIUDL_ECS_PRI_1_CTXT_REG_2_RESET}, + {IX_PIUDL_ECS_PRI_2_CTXT_REG_0, IX_PIUDL_ECS_PRI_2_CTXT_REG_0_RESET}, + {IX_PIUDL_ECS_PRI_2_CTXT_REG_1, IX_PIUDL_ECS_PRI_2_CTXT_REG_1_RESET}, + {IX_PIUDL_ECS_PRI_2_CTXT_REG_2, IX_PIUDL_ECS_PRI_2_CTXT_REG_2_RESET}, + {IX_PIUDL_ECS_DBG_CTXT_REG_0, IX_PIUDL_ECS_DBG_CTXT_REG_0_RESET}, + {IX_PIUDL_ECS_DBG_CTXT_REG_1, IX_PIUDL_ECS_DBG_CTXT_REG_1_RESET}, + {IX_PIUDL_ECS_DBG_CTXT_REG_2, IX_PIUDL_ECS_DBG_CTXT_REG_2_RESET}, + {IX_PIUDL_ECS_INSTRUCT_REG, IX_PIUDL_ECS_INSTRUCT_REG_RESET} +}; + +static IxPiuDlPiuMgrStats ixPiuDlPiuMgrStats; + +/* Set when PIU register memory has been mapped */ +static BOOL ixPiuDlMemInitialised = FALSE; + + +/* + * static function prototypes. + */ +PIU_PRIVATE ix_error +ixPiuDlPiuMgrMemLoad (IxPiuDlPiuId piuId, ix_uint32 piuBaseAddress, + IxPiuDlPiuMgrCodeBlock *codeBlockPtr, + BOOL verify, IxPiuDlPiuMemType piuMemType); + +PIU_PRIVATE ix_error +ixPiuDlPiuMgrMemInit (IxPiuDlPiuId piuId, ix_uint32 piuBaseAddress, + BOOL verify, IxPiuDlPiuMemType piuMemType); +PIU_PRIVATE ix_error +ixPiuDlPiuMgrStateInfoLoad (ix_uint32 piuBaseAddress, + IxPiuDlPiuMgrStateInfoBlock *codeBlockPtr, + BOOL verify); +PIU_PRIVATE BOOL +ixPiuDlPiuMgrBitsSetCheck (ix_uint32 piuBaseAddress, ix_uint32 regOffset, + ix_uint32 expectedBitsSet); + +PIU_PRIVATE ix_error +ixPiuDlPiuMgrBaseAddressGet (IxPiuDlPiuId piuId, ix_uint32* piuBaseAddressPtr); + +PIU_PRIVATE ix_error +ixPiuDlPiuMgrResetContextStores(ix_uint32 piuBaseAddress); + +PIU_PRIVATE ix_error +ixPiuDlPiuMgrAllMemInit (IxPiuDlPiuId piuId, + ix_uint32 piuBaseAddress); + +PIU_PRIVATE void +ixPiuDlPiuMgrClearFifos (ix_uint32 piuBaseAddress); + +PIU_PRIVATE ix_error +ixPiuDlPiuMgrPhyRegsReset (ix_uint32 piuBaseAddress); + +PIU_PRIVATE void +ixPiuDlPiuMgrRegistersClear (ix_uint32 piuBaseAddress); + + +/* + * Function definition: ixPiuDlPiuMgrBaseAddressGet + */ +PIU_PRIVATE ix_error +ixPiuDlPiuMgrBaseAddressGet (IxPiuDlPiuId piuId, ix_uint32* piuBaseAddressPtr) +{ + ix_error status = IX_SUCCESS; + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPiuMgrBaseAddressGet\n"); + if (!ixPiuDlMemInitialised) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrBaseAddressGet: " + "Memory not initialised\n"); + status = IX_FAIL; + } + else + { + *piuBaseAddressPtr = ixPiuDlPiuInfo[piuId].baseAddress; + } + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPiuMgrBaseAddressGet\n"); + return status; +} + +#if defined(__ep805xx) +/* + * Function definition: ixPiuDlPiuMgrPhysicalAddressSet + */ +ix_error +ixPiuDlPiuMgrPhysicalAddressSet ( + IxPiuDlPiuId piuId, + ix_uint32 address) +{ + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPiuMgrPhysicalAddressSet\n"); + + if (ixPiuDlMemInitialised) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrPhysicalAddressSet: " + "Cannot set physical address after memory has been initialised\n"); + return IX_FAIL; + } + else + { + ixPiuDlPiuInfo[piuId].physicalBaseAddress = address; + IX_PIUDL_TRACE1 (IX_PIUDL_DEBUG, + "ixPiuDlPiuMgrPhysicalAddressSet : address = 0x%08X\n", + ixPiuDlPiuInfo[piuId].physicalBaseAddress); + } + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPiuMgrPhysicalAddressSet\n"); + + return IX_SUCCESS; +} + +/* + * Function definition: ixPiuDlPiuMgrAppDualSet + */ +ix_error +ixPiuDlPiuMgrAppDualSet ( + IxPiuDlPiuId piuId, + ix_uint32 appDualId, + IxPiuDlAppDualInstruction *appDualInstruction ) +{ + ix_error status = IX_SUCCESS; + ix_uint32 appDualRegAddress = IX_PIUDL_APPDUAL_REG_OFFSET; + ix_uint32 appDualRegValue = 0; + ix_uint32 piuBaseAddress = 0; + ix_uint32 copr0 = appDualInstruction->copr0; + ix_uint32 inst0 = appDualInstruction->inst0; + ix_uint32 copr1 = appDualInstruction->copr1; + ix_uint32 inst1 = appDualInstruction->inst1; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPiuMgrAppDualSet\n"); + + if (!ixPiuDlMemInitialised) + { + ixPiuDlPiuMgrInit(); + } + + /* Check input parameters */ + if ((appDualId > IX_PIUDL_APPDUAL_ID_MAX) || (appDualId < 0)) + { + status = IX_PIUDL_PARAM_ERR; + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrAppDualSet - invalid appDualId " + "parameter\n"); + } + if ((copr0 > IX_PIUDL_APPDUAL_COPR_ID_MAX) || (copr0 < 0)) + { + status = IX_PIUDL_PARAM_ERR; + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrAppDualSet - invalid copr0 " + "parameter\n"); + } + if ((inst0 > IX_PIUDL_APPDUAL_INST_ID_MAX) || (inst0 < 0)) + { + status = IX_PIUDL_PARAM_ERR; + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrAppDualSet - invalid inst0 " + "parameter\n"); + } + if ((copr1 > IX_PIUDL_APPDUAL_COPR_ID_MAX) || (copr1 < 0)) + { + status = IX_PIUDL_PARAM_ERR; + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrAppDualSet - invalid copr1 " + "parameter\n"); + } + if ((inst1 > IX_PIUDL_APPDUAL_INST_ID_MAX) || (inst1 < 0)) + { + status = IX_PIUDL_PARAM_ERR; + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrAppDualSet - invalid inst1 " + "parameter\n"); + } + + if (IX_SUCCESS == status) + { + /* get base memory address of PIU from piuId */ + status = ixPiuDlPiuMgrBaseAddressGet (piuId, &piuBaseAddress); + if (status != IX_SUCCESS) + { + return status; + } + + /* map the appDualId to the correct register address */ + appDualRegAddress += appDualId; + + /* construct the value to be written to the appDual register - + note that because the input parameters have been range checked, this + guarantees that all reserved bits in the register value are 0 */ + appDualRegValue |= copr0 << IX_PIUDL_APPDUAL_REG_COPR0_BIT_OFFSET; + appDualRegValue |= inst0 << IX_PIUDL_APPDUAL_REG_INST0_BIT_OFFSET; + appDualRegValue |= copr1 << IX_PIUDL_APPDUAL_REG_COPR1_BIT_OFFSET; + appDualRegValue |= inst1 << IX_PIUDL_APPDUAL_REG_INST1_BIT_OFFSET; + + + /* to configure appDuals the PIU must be stopped */ + if (ixPiuDlPiuMgrPiuStop(piuId) != IX_SUCCESS) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrAppDualSet - failed to " + "stop PIU\n"); + return IX_FAIL; + } + + /* write the register and verify */ + if (ixPiuDlPiuMgrAppDualRegWrite(piuBaseAddress, appDualRegAddress, + appDualRegValue, TRUE) != IX_SUCCESS) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrAppDualSet - failed to " + "write appDual register\n"); + return IX_FAIL; + } + + /* restart the PIU */ + if (ixPiuDlPiuMgrPiuStart(piuId) != IX_SUCCESS) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrAppDualSet - failed to " + "restart PIU\n"); + return IX_FAIL; + } + + } + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPiuMgrAppDualSet : status = %d\n", + status); + return status; +} + +/* + * Function definition: ixPiuDlPiuMgrAppDualGet + */ +ix_error +ixPiuDlPiuMgrAppDualGet ( + IxPiuDlPiuId piuId, + ix_uint32 appDualId, + IxPiuDlAppDualInstruction *appDualInstruction ) +{ + ix_error status = IX_SUCCESS; + ix_uint32 appDualRegAddress = IX_PIUDL_APPDUAL_REG_OFFSET; + ix_uint32 appDualRegValue = 0; + ix_uint32 piuBaseAddress = 0; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPiuMgrAppDualGet\n"); + + if (!ixPiuDlMemInitialised) + { + ixPiuDlPiuMgrInit(); + } + /* Check input parameters */ + if ((appDualId > IX_PIUDL_APPDUAL_ID_MAX) || (appDualId < 0)) + { + status = IX_PIUDL_PARAM_ERR; + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrAppDualGet - invalid appDualId " + "parameter\n"); + } + + if (IX_SUCCESS == status) + { + /* get base memory address of PIU from piuId */ + status = ixPiuDlPiuMgrBaseAddressGet (piuId, &piuBaseAddress); + if (status != IX_SUCCESS) + { + return status; + } + + /* map the appDualId to the correct register address */ + appDualRegAddress += appDualId; + + /* read the app dual register value */ + appDualRegValue = ixPiuDlPiuMgrExecAccRegRead (piuBaseAddress, + appDualRegAddress); + + /* extract instruction fields from the register value */ + appDualInstruction->copr0 = (appDualRegValue >> + IX_PIUDL_APPDUAL_REG_COPR0_BIT_OFFSET) & + IX_PIUDL_APPDUAL_COPR_ID_MAX; + appDualInstruction->inst0 = (appDualRegValue >> + IX_PIUDL_APPDUAL_REG_INST0_BIT_OFFSET) & + IX_PIUDL_APPDUAL_INST_ID_MAX; + appDualInstruction->copr1 = (appDualRegValue >> + IX_PIUDL_APPDUAL_REG_COPR1_BIT_OFFSET) & + IX_PIUDL_APPDUAL_COPR_ID_MAX; + appDualInstruction->inst1 = (appDualRegValue >> + IX_PIUDL_APPDUAL_REG_INST1_BIT_OFFSET) & + IX_PIUDL_APPDUAL_INST_ID_MAX; + } + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPiuMgrAppDualGet : status = %d\n", + status); + return status; +} + +#endif /* #if defined(__ep805xx) */ + +/* + * Function definition: ixPiuDlPiuMgrInit + */ +void +ixPiuDlPiuMgrInit (void) +{ + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPiuMgrInit\n"); + /* Only map the memory once */ + if (!ixPiuDlMemInitialised) + { + /* + * The base address is defined here because for Linux the base may be + * obtained dynamically + */ +#if defined(__ep805xx) + + /* PIU-0 register address space */ + ix_uint32 physAddr = + ixPiuDlPiuInfo[IX_PIUDL_PIUID_PIU0].physicalBaseAddress; + ixPiuDlPiuInfo[IX_PIUDL_PIUID_PIU0].baseAddress = + (ix_uint32) ioremap (physAddr, 0x1000); + /* TODO remove printk */ + printk("PIU Virtual Address is 0x%x - Physical Address is 0x%x\n", + ixPiuDlPiuInfo[IX_PIUDL_PIUID_PIU0].baseAddress, physAddr); + +#else + ixPiuDlPiuInfo[IX_PIUDL_PIUID_PIU0].baseAddress = + (ix_uint32) IX_PIUDL_PIUBASEADDRESS_PIU0_MAP(IX_PIU_PIU0_PHYS); + ixPiuDlPiuInfo[IX_PIUDL_PIUID_PIU1].baseAddress = + (ix_uint32) IX_PIUDL_PIUBASEADDRESS_PIU1_MAP(IX_PIU_PIU1_PHYS); +#endif /* #if defined(__ep805xx) */ + + ixPiuDlMemInitialised = TRUE; + } + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPiuMgrInit\n"); +} + + +/* + * Function definition: ixPiuDlPiuMgrUninit + */ +ix_error +ixPiuDlPiuMgrUninit (void) +{ + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPiuMgrUninit\n"); + if (!ixPiuDlMemInitialised) + { + return IX_FAIL; + } + + iounmap((void *)ixPiuDlPiuInfo[IX_PIUDL_PIUID_PIU0].baseAddress); + ixPiuDlPiuInfo[IX_PIUDL_PIUID_PIU0].baseAddress = 0; +#if !defined(__ep805xx) + IX_PIUDL_PIUBASEADDRESS_UNMAP( + ixPiuDlPiuInfo[IX_PIUDL_PIUID_PIU1].baseAddress); + ixPiuDlPiuInfo[IX_PIUDL_PIUID_PIU1].baseAddress = 0; +#endif + +#if defined(__ep805xx) && defined(IX_PIUDL_READ_MICROCODE_FROM_FILE) + ixPiuDlFwLoaderCleanup(); +#endif + + ixPiuDlMemInitialised = FALSE; + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPiuMgrUninit\n"); + return IX_SUCCESS; +} + +/* + * Function definition: ixPiuDlPiuMgrImageLoad + */ +ix_error +ixPiuDlPiuMgrImageLoad ( + IxPiuDlPiuId piuId, + ix_uint32 *imageCodePtr, + BOOL verify) +{ + ix_uint32 piuBaseAddress; + IxPiuDlPiuMgrDownloadMap *downloadMap; + ix_uint32 *blockPtr; + ix_uint32 mapIndex = 0; + ix_error status = IX_SUCCESS; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPiuMgrImageLoad\n"); + + /* get base memory address of PIU from piuId */ + status = ixPiuDlPiuMgrBaseAddressGet (piuId, &piuBaseAddress); + if (status != IX_SUCCESS) + { + return status; + } + + /* check execution status of PIU to verify PIU Stop was successful */ + if (!ixPiuDlPiuMgrBitsSetCheck (piuBaseAddress, IX_PIUDL_REG_OFFSET_EXCTL, + IX_PIUDL_EXCTL_STATUS_STOP)) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrImageDownload - " + "PIU was not stopped before download\n"); + status = IX_FAIL; + } + else + { + + /* + * Read Download Map, checking each block type and calling + * appropriate function to perform download + */ + downloadMap = (IxPiuDlPiuMgrDownloadMap *) imageCodePtr; + + while ((downloadMap->entry[mapIndex].eodmMarker != + IX_PIUDL_END_OF_DOWNLOAD_MAP) + && (status == IX_SUCCESS)) + { + /* calculate pointer to block to be downloaded */ + blockPtr = imageCodePtr + + downloadMap->entry[mapIndex].block.offset; + + switch (downloadMap->entry[mapIndex].block.type) + { + case IX_PIUDL_BLOCK_TYPE_INSTRUCTION: + status = ixPiuDlPiuMgrMemLoad (piuId, piuBaseAddress, + (IxPiuDlPiuMgrCodeBlock *)blockPtr, + verify, + IX_PIUDL_MEM_TYPE_INSTRUCTION); + break; + case IX_PIUDL_BLOCK_TYPE_DATA: + status = ixPiuDlPiuMgrMemLoad (piuId, piuBaseAddress, + (IxPiuDlPiuMgrCodeBlock *)blockPtr, + verify, IX_PIUDL_MEM_TYPE_DATA); + break; + case IX_PIUDL_BLOCK_TYPE_STATE: + status = ixPiuDlPiuMgrStateInfoLoad (piuBaseAddress, + (IxPiuDlPiuMgrStateInfoBlock *) blockPtr, + verify); + break; + default: + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrImageLoad: " + "unknown block type in download map\n"); + status = IX_PIUDL_CRITICAL_MICROCODE_ERR; + ixPiuDlPiuMgrStats.criticalMicrocodeErrors++; + break; + } + mapIndex++; + }/* loop: for each entry in download map, while status == SUCCESS */ + }/* condition: PIU stopped before attempting download */ + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPiuMgrImageLoad : status = %u\n", + status); + return status; +} + + +/* + * Function definition: ixPiuDlPiuMgrMemLoad + */ +PIU_PRIVATE ix_error +ixPiuDlPiuMgrMemLoad ( + IxPiuDlPiuId piuId, + ix_uint32 piuBaseAddress, + IxPiuDlPiuMgrCodeBlock *blockPtr, + BOOL verify, + IxPiuDlPiuMemType piuMemType) +{ + ix_uint32 piuMemAddress; + ix_uint32 blockSize; + ix_uint32 memSize = 0; + IxPiuDlPiuMgrMemWrite memWriteFunc = NULL; + ix_uint32 localIndex = 0; + ix_error status = IX_SUCCESS; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPiuMgrMemLoad\n"); + + /* + * select PIU EXCTL reg read/write commands depending on memory + * type (instruction/data) to be accessed + */ + if (piuMemType == IX_PIUDL_MEM_TYPE_INSTRUCTION) + { + memSize = ixPiuDlPiuInfo[piuId].insMemSize; + memWriteFunc = (IxPiuDlPiuMgrMemWrite) ixPiuDlPiuMgrInsMemWrite; + } + else if (piuMemType == IX_PIUDL_MEM_TYPE_DATA) + { + memSize = ixPiuDlPiuInfo[piuId].dataMemSize; + memWriteFunc = (IxPiuDlPiuMgrMemWrite) ixPiuDlPiuMgrDataMemWrite; + } + + /* + * PIU memory is loaded contiguously from each block, so only address + * of 1st word in block is needed + */ + piuMemAddress = blockPtr->piuMemAddress; + /* number of words of instruction/data microcode in block to download */ + blockSize = blockPtr->size; + + if ((piuMemAddress + blockSize) > memSize) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrMemLoad: " + "Block size too big for PIU memory\n"); + status = IX_PIUDL_CRITICAL_MICROCODE_ERR; + ixPiuDlPiuMgrStats.criticalMicrocodeErrors++; + } + else + { + for (localIndex = 0; localIndex < blockSize; localIndex++) + { + status = memWriteFunc (piuBaseAddress, piuMemAddress, + blockPtr->data[localIndex], verify); + + if (status != IX_SUCCESS) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrMemLoad: " + "write to PIU memory failed\n"); + status = IX_PIUDL_CRITICAL_PIU_ERR; + ixPiuDlPiuMgrStats.criticalPiuErrors++; + break; /* abort download */ + } + /* increment target (word)address in PIU memory */ + piuMemAddress++; + } + }/* condition: block size will fit in PIU memory */ + + if (status == IX_SUCCESS) + { + if (piuMemType == IX_PIUDL_MEM_TYPE_INSTRUCTION) + { + ixPiuDlPiuMgrStats.instructionBlocksLoaded++; + } + else if (piuMemType == IX_PIUDL_MEM_TYPE_DATA) + { + ixPiuDlPiuMgrStats.dataBlocksLoaded++; + } + } + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPiuMgrMemLoad : status = %u\n", status); + return status; +} + + +/* + * Function definition: ixPiuDlPiuMgrStateInfoLoad + */ +PIU_PRIVATE ix_error +ixPiuDlPiuMgrStateInfoLoad ( + ix_uint32 piuBaseAddress, + IxPiuDlPiuMgrStateInfoBlock *blockPtr, + BOOL verify) +{ + ix_uint32 blockSize; + ix_uint32 ctxtRegAddrInfo; + ix_uint32 ctxtRegVal; + IxPiuDlCtxtRegNum ctxtReg; /* identifies Context Store reg (0-3) */ + ix_uint32 ctxtNum; /* identifies Context number (0-16) */ + ix_uint32 i; + ix_error status = IX_SUCCESS; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPiuMgrStateInfoLoad\n"); + + /* block size contains number of words of state-info in block */ + blockSize = blockPtr->size; + + ixPiuDlPiuMgrDebugInstructionPreExec (piuBaseAddress); + + /* for each state-info context register entry in block */ + for (i = 0; i < (blockSize/IX_PIUDL_STATE_INFO_ENTRY_SIZE); i++) + { + /* each state-info entry is 2 words (address, value) in length */ + ctxtRegAddrInfo = (blockPtr->ctxtRegEntry[i]).addressInfo; + ctxtRegVal = (blockPtr->ctxtRegEntry[i]).value; + + ctxtReg = (ctxtRegAddrInfo & IX_PIUDL_MASK_STATE_ADDR_CTXT_REG); + ctxtNum = (ctxtRegAddrInfo & IX_PIUDL_MASK_STATE_ADDR_CTXT_NUM) >> + IX_PIUDL_OFFSET_STATE_ADDR_CTXT_NUM; + + /* error-check Context Register No. and Context Number values */ + /* NOTE that there is no STEVT register for Context 0 */ + if ((ctxtReg < 0) || + (ctxtReg >= IX_PIUDL_CTXT_REG_MAX) || + (ctxtNum > IX_PIUDL_CTXT_NUM_MAX) || + ((ctxtNum == 0) && (ctxtReg == IX_PIUDL_CTXT_REG_STEVT))) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrStateInfoLoad: " + "invalid Context Register Address\n"); + status = IX_PIUDL_CRITICAL_MICROCODE_ERR; + ixPiuDlPiuMgrStats.criticalMicrocodeErrors++; + break; /* abort download */ + } + + status = ixPiuDlPiuMgrCtxtRegWrite (piuBaseAddress, ctxtNum, ctxtReg, + ctxtRegVal, verify); + if (status != IX_SUCCESS) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrStateInfoLoad: " + "write of state-info to PIU failed\n"); + status = IX_PIUDL_CRITICAL_PIU_ERR; + ixPiuDlPiuMgrStats.criticalPiuErrors++; + break; /* abort download */ + } + }/* loop: for each context reg entry in State Info block */ + + ixPiuDlPiuMgrDebugInstructionPostExec (piuBaseAddress); + + if (status == IX_SUCCESS) + { + ixPiuDlPiuMgrStats.stateInfoBlocksLoaded++; + } + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPiuMgrStateInfoLoad : status = %u\n", + status); + return status; +} + + +/* + * Function definition: ixPiuDlPiuMgrPiuReset + */ +ix_error +ixPiuDlPiuMgrPiuReset ( + IxPiuDlPiuId piuId) +{ + ix_uint32 piuBaseAddress; + ix_error status = IX_SUCCESS; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPiuMgrPiuReset\n"); + + /* get base memory address of PIU from piuId */ + status = ixPiuDlPiuMgrBaseAddressGet (piuId, &piuBaseAddress); + if (status != IX_SUCCESS) + { + return status; + } + + status = ixPiuDlPiuMgrAllMemInit (piuId,piuBaseAddress); + if ( status != IX_SUCCESS) + { + return status; + } + + IX_PIUDL_TRACE0 (IX_PIUDL_DEBUG,"Interrupts unlocked\n"); + + ixPiuDlPiuMgrDebugInstructionPreExec (piuBaseAddress); + + + ixPiuDlPiuMgrClearFifos (piuBaseAddress); + + + IX_PIUDL_TRACE0 (IX_PIUDL_DEBUG, + "ixPiuDlPiuMgrPiuReset: read inFIFO step exec\n"); + + /* + * Reset the mailbox reg + */ + /* ...from XScale side */ + IX_PIUDL_REG_WRITE (piuBaseAddress, IX_PIUDL_REG_OFFSET_MBST, + IX_PIUDL_REG_RESET_MBST); + /* ...from PIU side */ + ixPiuDlPiuMgrDebugInstructionExec (piuBaseAddress, + IX_PIUDL_INSTR_RESET_MBOX, 0, 0); + + IX_PIUDL_TRACE0 (IX_PIUDL_DEBUG,"ixPiuDlPiuMgrPiuReset: Mail Box Reset\n"); + + /* + * Reset the PIU Co-Processors + */ + status = ixPiuDlPiuMgrLogicalRegWrite (piuBaseAddress, + 0, /*reg d0*/ + IX_PIUDL_CP_RESET_VALUE, + IX_PIUDL_CP_RESET_SIZE, + 0, /*context 0*/ + TRUE); + if (status == IX_SUCCESS) + { + ixPiuDlPiuMgrDebugInstructionExec (piuBaseAddress, + IX_PIUDL_INSTR_RESET_COPROCS, + 0, /*context 0*/ + 0); /*LDUR*/ + } + else + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrPiuReset: error writing d0 with " + "IX_PIUDL_CP_RESET_VALUE for Co-Processor " + "reset\n"); + return status; /* abort reset */ + } + + IX_PIUDL_TRACE0 (IX_PIUDL_DEBUG, + "ixPiuDlPiuMgrPiuReset: Co-processors reset\n"); + + /* + * Take Co-Processors out of Reset + */ + if (status == IX_SUCCESS) + { + status = ixPiuDlPiuMgrLogicalRegWrite (piuBaseAddress, + 0, /*reg d0*/ + 0, /*take coprocs out of reset*/ + IX_PIUDL_CP_RESET_SIZE, + 0, /*context 0*/ + TRUE); + if (status == IX_SUCCESS) + { + ixPiuDlPiuMgrDebugInstructionExec (piuBaseAddress, + IX_PIUDL_INSTR_RESET_COPROCS, + 0, /*context 0*/ + 0); /*LDUR*/ + } + else + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrPiuReset: error writing d0 " + "with 0 for Co-Processor out of reset\n"); + return status; /* abort reset */ + } + } + + IX_PIUDL_TRACE0 (IX_PIUDL_DEBUG,"ixPiuDlPiuMgrPiuReset: Co-processors " + "taken out of reset\n"); + + + status = ixPiuDlPiuMgrPhyRegsReset (piuBaseAddress); + if (status != IX_SUCCESS) + { + return status; + } + + IX_PIUDL_TRACE0 (IX_PIUDL_DEBUG, + "ixPiuDlPiuMgrPiuReset: phy registers reset\n"); + + + status = ixPiuDlPiuMgrResetContextStores(piuBaseAddress); + if (status != IX_SUCCESS) + { + return status; + } + + + ixPiuDlPiuMgrRegistersClear (piuBaseAddress); + + ixPiuDlPiuMgrStats.piuResets++; + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPiuMgrPiuReset : status = %u\n", status); + return status; +} + + +/* + * Function definition: ixPiuDlPiuMgrPiuStart + */ +ix_error +ixPiuDlPiuMgrPiuStart ( + IxPiuDlPiuId piuId) +{ + ix_uint32 piuBaseAddress; + ix_uint32 ecsRegVal; + BOOL piuRunning; + ix_error status = IX_SUCCESS; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPiuMgrPiuStart\n"); + + /* get base memory address of PIU from piuId */ + status = ixPiuDlPiuMgrBaseAddressGet (piuId, &piuBaseAddress); + if (status != IX_SUCCESS) + { + return status; + } + + /* + * ensure only Background Context Stack Level is Active by turning off + * the Active bit in each of the other Executing Context Stack levels + */ + ecsRegVal = ixPiuDlPiuMgrExecAccRegRead (piuBaseAddress, + IX_PIUDL_ECS_PRI_1_CTXT_REG_0); + ecsRegVal &= ~IX_PIUDL_MASK_ECS_REG_0_ACTIVE; + ixPiuDlPiuMgrExecAccRegWrite (piuBaseAddress, IX_PIUDL_ECS_PRI_1_CTXT_REG_0, + ecsRegVal); + + ecsRegVal = ixPiuDlPiuMgrExecAccRegRead (piuBaseAddress, + IX_PIUDL_ECS_PRI_2_CTXT_REG_0); + ecsRegVal &= ~IX_PIUDL_MASK_ECS_REG_0_ACTIVE; + ixPiuDlPiuMgrExecAccRegWrite (piuBaseAddress, IX_PIUDL_ECS_PRI_2_CTXT_REG_0, + ecsRegVal); + + ecsRegVal = ixPiuDlPiuMgrExecAccRegRead (piuBaseAddress, + IX_PIUDL_ECS_DBG_CTXT_REG_0); + ecsRegVal &= ~IX_PIUDL_MASK_ECS_REG_0_ACTIVE; + ixPiuDlPiuMgrExecAccRegWrite (piuBaseAddress, IX_PIUDL_ECS_DBG_CTXT_REG_0, + ecsRegVal); + + /* clear the pipeline */ + ixPiuDlPiuMgrCommandIssue (piuBaseAddress, IX_PIUDL_EXCTL_CMD_PIU_CLR_PIPE); + + IX_PIUDL_TRACE1 (IX_PIUDL_DEBUG, + "ixPiuDlPiuMgrPiuStart : about to start piu%u\n", + (unsigned)piuId); + + /* start PIU execution by issuing command through EXCTL register on PIU */ + ixPiuDlPiuMgrCommandIssue (piuBaseAddress, IX_PIUDL_EXCTL_CMD_PIU_START); + + IX_PIUDL_TRACE1 (IX_PIUDL_DEBUG, + "ixPiuDlPiuMgrPiuStart : started piu %u\n", + (unsigned)piuId); + /* + * check execution status of PIU to verify PIU Start operation was + * successful + */ + piuRunning = ixPiuDlPiuMgrBitsSetCheck (piuBaseAddress, + IX_PIUDL_REG_OFFSET_EXCTL, + IX_PIUDL_EXCTL_STATUS_RUN); + if (piuRunning) + { + ixPiuDlPiuMgrStats.piuStarts++; + } + else + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrPiuStart: " + "failed to start PIU execution\n"); + status = IX_FAIL; + } + + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPiuMgrPiuStart : status = %u\n", status); + return status; +} + + +/* + * Function definition: ixPiuDlPiuMgrPiuStop + */ +ix_error +ixPiuDlPiuMgrPiuStop ( + IxPiuDlPiuId piuId) +{ + ix_uint32 piuBaseAddress; + ix_error status = IX_SUCCESS; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPiuMgrPiuStop\n"); + + /* First verify that the PIU is out of reset */ + status = ixPiuDlPiuMgrPiuResetDeassert (piuId); + + if (status != IX_SUCCESS) + { + return status; + } + + /* get base memory address of PIU from piuId */ + status = ixPiuDlPiuMgrBaseAddressGet (piuId, &piuBaseAddress); + + if (status != IX_SUCCESS) + { + return status; + } + + /* stop PIU execution by issuing command through EXCTL register on PIU */ + ixPiuDlPiuMgrCommandIssue (piuBaseAddress, IX_PIUDL_EXCTL_CMD_PIU_STOP); + + /* verify that PIU Stop was successful */ + if (!ixPiuDlPiuMgrBitsSetCheck (piuBaseAddress, IX_PIUDL_REG_OFFSET_EXCTL, + IX_PIUDL_EXCTL_STATUS_STOP)) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrPiuStop: " + "failed to stop PIU execution\n"); + status = IX_FAIL; + } + + ixPiuDlPiuMgrStats.piuStops++; + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPiuMgrPiuStop : status = %u\n", status); + return status; +} + + +/* + * Function definition: ixPiuDlPiuMgrBitsSetCheck + */ +PIU_PRIVATE BOOL +ixPiuDlPiuMgrBitsSetCheck ( + ix_uint32 piuBaseAddress, + ix_uint32 regOffset, + ix_uint32 expectedBitsSet) +{ + ix_uint32 regVal; + IX_PIUDL_REG_READ (piuBaseAddress, regOffset, ®Val); + + return expectedBitsSet == (expectedBitsSet & regVal); +} + + +/* + * Function definition: ixPiuDlPiuMgrStatsShow + */ +void +ixPiuDlPiuMgrStatsShow (void) +{ + printf ("\nixPiuDlPiuMgrStatsShow:\n"); + + printf ("\tInstruction Blocks loaded: %u\n", + ixPiuDlPiuMgrStats.instructionBlocksLoaded); + printf ("\tData Blocks loaded: %u\n", + ixPiuDlPiuMgrStats.dataBlocksLoaded); + printf ("\tInstruction Mem Initialisations: %u\n", + ixPiuDlPiuMgrStats.instructionMemInit); + printf ("\tData Mem Initialisations: %u\n", + ixPiuDlPiuMgrStats.dataMemInit); + printf ("\tState Information Blocks loaded: %u\n", + ixPiuDlPiuMgrStats.stateInfoBlocksLoaded); + printf ("\tCritical PIU errors: %u\n", + ixPiuDlPiuMgrStats.criticalPiuErrors); + printf ("\tCritical Microcode errors: %u\n", + ixPiuDlPiuMgrStats.criticalMicrocodeErrors); + printf ("\tSuccessful PIU Starts: %u\n", + ixPiuDlPiuMgrStats.piuStarts); + printf ("\tSuccessful PIU Stops: %u\n", + ixPiuDlPiuMgrStats.piuStops); + printf ("\tSuccessful PIU Resets: %u\n", + ixPiuDlPiuMgrStats.piuResets); + + printf ("\n"); + + ixPiuDlPiuMgrUtilsStatsShow (); +} + + +/* + * Function definition: ixPiuDlPiuMgrStatsReset + */ +void +ixPiuDlPiuMgrStatsReset (void) +{ + ixPiuDlPiuMgrStats.instructionBlocksLoaded = 0; + ixPiuDlPiuMgrStats.dataBlocksLoaded = 0; + ixPiuDlPiuMgrStats.instructionMemInit = 0; + ixPiuDlPiuMgrStats.dataMemInit = 0; + ixPiuDlPiuMgrStats.stateInfoBlocksLoaded = 0; + ixPiuDlPiuMgrStats.criticalPiuErrors = 0; + ixPiuDlPiuMgrStats.criticalMicrocodeErrors = 0; + ixPiuDlPiuMgrStats.piuStarts = 0; + ixPiuDlPiuMgrStats.piuStops = 0; + ixPiuDlPiuMgrStats.piuResets = 0; + + ixPiuDlPiuMgrUtilsStatsReset (); +} + + + +/* + * Function definition: ixPiuDlPiuMgrMemInit + */ +PIU_PRIVATE ix_error +ixPiuDlPiuMgrMemInit ( + IxPiuDlPiuId piuId, + ix_uint32 piuBaseAddress, + BOOL verify, + IxPiuDlPiuMemType piuMemType) +{ + ix_uint32 piuMemAddress; + ix_uint32 memSize = 0; + IxPiuDlPiuMgrMemWrite memWriteFunc = NULL; + ix_uint32 localIndex = 0; + ix_error status = IX_SUCCESS; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPiuMgrMemInit\n"); + + /* + * select PIU EXCTL reg read/write commands depending on memory + * type (instruction/data) to be accessed + */ + if (piuMemType == IX_PIUDL_MEM_TYPE_INSTRUCTION) + { + memSize = ixPiuDlPiuInfo[piuId].insMemSize; + memWriteFunc = (IxPiuDlPiuMgrMemWrite) ixPiuDlPiuMgrInsMemWrite; + } + else if (piuMemType == IX_PIUDL_MEM_TYPE_DATA) + { + memSize = ixPiuDlPiuInfo[piuId].dataMemSize; + memWriteFunc = (IxPiuDlPiuMgrMemWrite) ixPiuDlPiuMgrDataMemWrite; + } + + + /* Start at address 0 */ + piuMemAddress = 0; + + for (localIndex = 0; localIndex < memSize; localIndex++) + { + status = memWriteFunc (piuBaseAddress, piuMemAddress, + 0, verify); + + if (status != IX_SUCCESS) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrMemLoad: " + "write to PIU memory failed\n"); + status = IX_PIUDL_CRITICAL_PIU_ERR; + ixPiuDlPiuMgrStats.criticalPiuErrors++; + break; /* abort download */ + } + /* increment target (word)address in PIU memory */ + piuMemAddress++; + + } + + /* SCR #1936 - In case of parity error, need to do one more write + * to clear it + */ + memWriteFunc (piuBaseAddress, 0, 0, verify); + + if (status == IX_SUCCESS) + { + if (piuMemType == IX_PIUDL_MEM_TYPE_INSTRUCTION) + { + ixPiuDlPiuMgrStats.instructionMemInit++; + } + else if (piuMemType == IX_PIUDL_MEM_TYPE_DATA) + { + ixPiuDlPiuMgrStats.dataMemInit++; + } + } + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPiuMgrMemInit : status = %u\n", status); + return status; +} + + +/* + * Function definition: ixPiuDlPiuMgrPiuResetAssert + */ +ix_error +ixPiuDlPiuMgrPiuResetAssert ( + IxPiuDlPiuId piuId) +{ + ix_uint32 resetReg = 0; + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPiuMgrPiuResetAssert\n"); + +#if !defined(__ep805xx) + IX_PIUDL_REG_READ (IXP23XX_RESET1_REG, 0, &resetReg); +#endif + if (piuId == IX_PIUDL_PIUID_PIU0) + { + resetReg &= ~(1 << IX_PIUDL_PIU0_RESET_BIT_OFFSET); + } +#if !defined(__ep805xx) + else if (piuId == IX_PIUDL_PIUID_PIU1) + { + resetReg &= ~(1 << IX_PIUDL_PIU1_RESET_BIT_OFFSET); + } +#endif + else + { + return IX_FAIL; + } +#if !defined(__ep805xx) + IX_PIUDL_REG_WRITE (IXP23XX_RESET1_REG, 0, resetReg); +#endif + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPiuMgrPiuResetAssert\n"); + return IX_SUCCESS; +} + + + + +/* + * Function definition: ixPiuDlPiuMgrPiuResetDeassert + */ +ix_error +ixPiuDlPiuMgrPiuResetDeassert (IxPiuDlPiuId piuId) +{ + ix_uint32 resetReg = 0; + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPiuMgrPiuResetDeassert\n"); + +#if !defined(__ep805xx) + IX_PIUDL_REG_READ (IXP23XX_RESET1_REG, 0, &resetReg); +#endif + if (piuId == IX_PIUDL_PIUID_PIU0) + { + resetReg |= 1 << IX_PIUDL_PIU0_RESET_BIT_OFFSET; + } +#if !defined(__ep805xx) + else if (piuId == IX_PIUDL_PIUID_PIU1) + { + resetReg |= 1 << IX_PIUDL_PIU1_RESET_BIT_OFFSET; + } +#endif + else + { + return IX_FAIL; + } +#if !defined(__ep805xx) + IX_PIUDL_REG_WRITE (IXP23XX_RESET1_REG, 0, resetReg); +#endif + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPiuMgrPiuResetDeassert\n"); + return IX_SUCCESS; +} + +/* + * Function definition: ixPiuDlPiuMgrTriggerInterruptReset + */ +void +ixPiuDlPiuMgrTriggerInterruptReset (void) +{ +#if defined(__ep805xx) + ixPiuDlPiuMgrCommandIssue (ixPiuDlPiuInfo[IX_PIUDL_PIUID_PIU0].baseAddress, + IX_PIUDL_EXCTL_CMD_CLR_TRIGGER); +#else + ixPiuDlPiuMgrCommandIssue (ixPiuDlPiuInfo[IX_PIUDL_PIUID_PIU1].baseAddress, + IX_PIUDL_EXCTL_CMD_CLR_TRIGGER); +#endif + +} + + +ix_error +ixPiuDlPiuMgrResetContextStores(ix_uint32 piuBaseAddress) +{ + IxPiuDlCtxtRegNum ctxtReg; /* identifies Context Store reg (0-3) */ + ix_uint32 ctxtNum; /* identifies Context number (0-16) */ + ix_uint32 regVal; + ix_error status = IX_SUCCESS; + /* + * Reset the context store: + */ + for (ctxtNum = IX_PIUDL_CTXT_NUM_MIN; + ctxtNum <= IX_PIUDL_CTXT_NUM_MAX; ctxtNum++) + { + /* set each context's Context Store registers to reset values: */ + for (ctxtReg = 0; ctxtReg < IX_PIUDL_CTXT_REG_MAX; ctxtReg++) + { + /* NOTE that there is no STEVT register for Context 0 */ + if (!((ctxtNum == 0) && (ctxtReg == IX_PIUDL_CTXT_REG_STEVT))) + { + regVal = ixPiuDlCtxtRegResetValues[ctxtReg]; + status = ixPiuDlPiuMgrCtxtRegWrite (piuBaseAddress, ctxtNum, + ctxtReg, regVal, TRUE); + if (status != IX_SUCCESS) + { + return status; /* abort reset */ + } + } + } + } + return status; + +} + +ix_error +ixPiuDlPiuMgrAllMemInit (IxPiuDlPiuId piuId, + ix_uint32 piuBaseAddress) +{ + ix_error status = IX_SUCCESS; + ix_uint32 key; + + /* + * We must disable interrupts for this to succeed as there will be an + * interrupt triggered by the PIU when trying to do this + */ + IX_PIUDL_TRACE0 (IX_PIUDL_DEBUG,"Lock Interrupts\n"); + key = ixOsalIrqLock(); + + if (IX_SUCCESS != ixPiuDlPiuMgrMemInit(piuId, piuBaseAddress,FALSE, + IX_PIUDL_MEM_TYPE_INSTRUCTION)) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrPiuReset - " + "PIU Memory could not be initialised\n"); + status = IX_FAIL; + } + if (IX_SUCCESS != ixPiuDlPiuMgrMemInit(piuId, piuBaseAddress,FALSE, + IX_PIUDL_MEM_TYPE_DATA)) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrPiuReset - " + "PIU Memory could not be initialised\n"); + status = IX_FAIL; + } + + ixOsalIrqUnlock(key); + return status; +} + + +void +ixPiuDlPiuMgrClearFifos (ix_uint32 piuBaseAddress) +{ + ix_uint32 regVal; + /* + * clear the FIFOs + */ + while (ixPiuDlPiuMgrBitsSetCheck (piuBaseAddress, + IX_PIUDL_REG_OFFSET_WFIFO, + IX_PIUDL_MASK_WFIFO_VALID)) + { + IX_PIUDL_TRACE1 (IX_PIUDL_DEBUG, + "Watch-point FIFO 0x%x\n", + *(ix_uint32*)(piuBaseAddress+IX_PIUDL_REG_OFFSET_WFIFO)); + /* read from the Watch-point FIFO until empty */ + IX_PIUDL_REG_READ (piuBaseAddress, IX_PIUDL_REG_OFFSET_WFIFO, + ®Val); + } + + IX_PIUDL_TRACE0 (IX_PIUDL_DEBUG, + "ixPiuDlPiuMgrPiuReset: Watch-point FIFO Empty\n"); + + while (ixPiuDlPiuMgrBitsSetCheck (piuBaseAddress, + IX_PIUDL_REG_OFFSET_STAT, + IX_PIUDL_MASK_STAT_IFNE)) + { + /* + * step execution of the PIU intruction to read inFIFO using + * the Debug Executing Context stack + */ + ixPiuDlPiuMgrDebugInstructionExec (piuBaseAddress, + IX_PIUDL_INSTR_RD_FIFO, 0, 0); + } +} + + +ix_error +ixPiuDlPiuMgrPhyRegsReset (ix_uint32 piuBaseAddress) +{ + ix_error status = IX_SUCCESS; + ix_uint32 regAddr; + /* + * Reset the physical registers in the PIU register file: + * Note: no need to save/restore REGMAP for Context 0 here + * since all Context Store regs are reset in subsequent code + */ + for (regAddr = 0; + (regAddr < IX_PIUDL_TOTAL_NUM_PHYS_REG) && (status != IX_FAIL); + regAddr++) + { + /* for each physical register in the PIU reg file, write 0 : */ + status = ixPiuDlPiuMgrPhysicalRegWrite (piuBaseAddress, regAddr, + 0, TRUE); + if (status != IX_SUCCESS) + { + return status; /* abort reset */ + } + } + return status; +} + + + +void +ixPiuDlPiuMgrRegistersClear (ix_uint32 piuBaseAddress) +{ + ix_uint32 regAddr; + ix_uint32 regVal; + ix_uint32 localIndex; + ix_uint32 indexMax; + + ixPiuDlPiuMgrDebugInstructionPostExec (piuBaseAddress); + + /* write Reset values to Execution Context Stack registers */ + indexMax = sizeof (ixPiuDlEcsRegResetValues) / + sizeof (IxPiuDlEcsRegResetValue); + for (localIndex = 0; localIndex < indexMax; localIndex++) + { + regAddr = ixPiuDlEcsRegResetValues[localIndex].regAddr; + regVal = ixPiuDlEcsRegResetValues[localIndex].regResetVal; + ixPiuDlPiuMgrExecAccRegWrite (piuBaseAddress, regAddr, regVal); + } + + /* clear the profile counter */ + ixPiuDlPiuMgrCommandIssue (piuBaseAddress, + IX_PIUDL_EXCTL_CMD_CLR_PROFILE_CNT); + + /* clear registers EXCT, AP0, AP1, AP2 and AP3 */ + for (regAddr = IX_PIUDL_REG_OFFSET_EXCT; + regAddr <= IX_PIUDL_REG_OFFSET_AP3; + regAddr += IX_PIUDL_BYTES_PER_WORD) + { + IX_PIUDL_REG_WRITE (piuBaseAddress, regAddr, 0); + } + + /* Reset the Watch-count register */ + IX_PIUDL_REG_WRITE (piuBaseAddress, IX_PIUDL_REG_OFFSET_WC, 0); +} diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/source/IxPiuDlPiuMgrUtils.c b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/source/IxPiuDlPiuMgrUtils.c new file mode 100644 index 0000000..398c315 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/source/IxPiuDlPiuMgrUtils.c @@ -0,0 +1,809 @@ +/** + * @file IxPiuDlPiuMgrUtils.c + * + * @author Intel Corporation + * @date 13 August 2003 + * + * @description Contents are the implementation of the private API for the + * PIU Downloader PiuMgr Utils module + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + + +/* + * Put the system defined include files required. + */ + +#include "IxPiuTypes.h" +/* + * Put the user defined include files required. + */ +#include "IxPiuDl.h" +#include "IxPiuDlPiuMgrUtils_p.h" +#include "IxPiuDlPiuMgrEcRegisters_p.h" +#include "IxPiuDlMacros_p.h" + + +/* + * #defines and macros used in this file. + */ + +/* used to bit-mask a number of bytes */ +#define IX_PIUDL_MASK_LOWER_BYTE_OF_WORD 0x000000FF +#define IX_PIUDL_MASK_LOWER_SHORT_OF_WORD 0x0000FFFF +#define IX_PIUDL_MASK_FULL_WORD 0xFFFFFFFF + +#define IX_PIUDL_BYTES_PER_WORD 4 +#define IX_PIUDL_BYTES_PER_SHORT 2 + +#define IX_PIUDL_REG_SIZE_BYTE 8 +#define IX_PIUDL_REG_SIZE_SHORT 16 +#define IX_PIUDL_REG_SIZE_WORD 32 + +/* + * Introduce extra read cycles after issuing read command to PIU + * so that we read the register after the PIU has updated it + * This is to overcome race condition between XScale and PIU + */ +#define IX_PIUDL_DELAY_READ_CYCLES 2 + +/* + * The following needed to mask off the top 3 bits in an PIU instruction word + * since the PIU instruction word is 29 bits + */ +#define IX_PIUDL_INSTRUCTION_WORD_MASK 0x1FFFFFFF + +/* + * typedefs + */ +typedef struct +{ + ix_uint32 regAddress; + ix_uint32 regSize; +} IxPiuDlCtxtRegAccessInfo; + +/* module statistics counters */ +typedef struct +{ + ix_uint32 insMemWrites; + ix_uint32 insMemWriteFails; + ix_uint32 dataMemWrites; + ix_uint32 dataMemWriteFails; + ix_uint32 ecsRegWrites; + ix_uint32 ecsRegReads; + ix_uint32 dbgInstructionExecs; + ix_uint32 contextRegWrites; + ix_uint32 physicalRegWrites; + ix_uint32 nextPcWrites; +#if defined(__ep805xx) + ix_uint32 appDualWrites; + ix_uint32 appDualWriteFails; +#endif +} IxPiuDlPiuMgrUtilsStats; + + +/* + * Variable declarations global to this file only. Externs are followed by + * static variables. + */ + +/* + * contains useful address and function pointers to read/write Context Regs, + * eliminating some switch or if-else statements in places + */ +static IxPiuDlCtxtRegAccessInfo ixPiuDlCtxtRegAccInfo[IX_PIUDL_CTXT_REG_MAX] = +{ + { + IX_PIUDL_CTXT_REG_ADDR_STEVT, + IX_PIUDL_REG_SIZE_BYTE + }, + { + IX_PIUDL_CTXT_REG_ADDR_STARTPC, + IX_PIUDL_REG_SIZE_SHORT + }, + { + IX_PIUDL_CTXT_REG_ADDR_REGMAP, + IX_PIUDL_REG_SIZE_SHORT + }, + { + IX_PIUDL_CTXT_REG_ADDR_CINDEX, + IX_PIUDL_REG_SIZE_BYTE + } +}; + +static ix_uint32 ixPiuDlSavedExecCount = 0; +static ix_uint32 ixPiuDlSavedEcsDbgCtxtReg2 = 0; + +static IxPiuDlPiuMgrUtilsStats ixPiuDlPiuMgrUtilsStats; + + +/* + * static function prototypes. + */ +PIU_PRIVATE __inline__ void +ixPiuDlPiuMgrWriteCommandIssue (ix_uint32 piuBaseAddress, ix_uint32 cmd, + ix_uint32 addr, ix_uint32 data); + +PIU_PRIVATE __inline__ ix_uint32 +ixPiuDlPiuMgrReadCommandIssue (ix_uint32 piuBaseAddress, ix_uint32 cmd, + ix_uint32 addr); + +PIU_PRIVATE ix_uint32 +ixPiuDlPiuMgrLogicalRegRead (ix_uint32 piuBaseAddress, ix_uint32 regAddr, + ix_uint32 regSize, ix_uint32 ctxtNum); + +/* + * Function definition: ixPiuDlPiuMgrWriteCommandIssue + */ +PIU_PRIVATE __inline__ void +ixPiuDlPiuMgrWriteCommandIssue ( + ix_uint32 piuBaseAddress, + ix_uint32 cmd, + ix_uint32 addr, + ix_uint32 data) +{ + IX_PIUDL_REG_WRITE (piuBaseAddress, IX_PIUDL_REG_OFFSET_EXDATA, data); + IX_PIUDL_REG_WRITE (piuBaseAddress, IX_PIUDL_REG_OFFSET_EXAD, addr); + IX_PIUDL_REG_WRITE (piuBaseAddress, IX_PIUDL_REG_OFFSET_EXCTL, cmd); +} + + +/* + * Function definition: ixPiuDlPiuMgrReadCommandIssue + */ +PIU_PRIVATE __inline__ ix_uint32 +ixPiuDlPiuMgrReadCommandIssue ( + ix_uint32 piuBaseAddress, + ix_uint32 cmd, + ix_uint32 addr) +{ + ix_uint32 data = 0; + int i; + + IX_PIUDL_REG_WRITE (piuBaseAddress, IX_PIUDL_REG_OFFSET_EXAD, addr); + IX_PIUDL_REG_WRITE (piuBaseAddress, IX_PIUDL_REG_OFFSET_EXCTL, cmd); + for (i = 0; i <= IX_PIUDL_DELAY_READ_CYCLES; i++) + { + IX_PIUDL_REG_READ (piuBaseAddress, IX_PIUDL_REG_OFFSET_EXDATA, &data); + } + + return data; +} + +/* + * Function definition: ixPiuDlPiuMgrInsMemWrite + */ +ix_error +ixPiuDlPiuMgrInsMemWrite ( + ix_uint32 piuBaseAddress, + ix_uint32 insMemAddress, + ix_uint32 insMemData, + BOOL verify) +{ + ix_uint32 readData = 0; + + ixPiuDlPiuMgrWriteCommandIssue (piuBaseAddress, + IX_PIUDL_EXCTL_CMD_WR_INS_MEM, + insMemAddress, insMemData); + if (verify) + { + /* write invalid data to this reg, so we can see if we're reading + the EXDATA register too early */ + IX_PIUDL_REG_WRITE (piuBaseAddress, IX_PIUDL_REG_OFFSET_EXDATA, + ~insMemData); + + readData = ixPiuDlPiuMgrReadCommandIssue (piuBaseAddress, + IX_PIUDL_EXCTL_CMD_RD_INS_MEM, + insMemAddress); + +#if defined(__ep805xx) + /* when data is read back, it has the top 3 bits set to 0 */ + insMemData &= IX_PIUDL_INSTRUCTION_WORD_MASK; + readData &= IX_PIUDL_INSTRUCTION_WORD_MASK; +#endif + + if (insMemData != readData) + { + ixPiuDlPiuMgrUtilsStats.insMemWriteFails++; + return IX_FAIL; + } + } + + ixPiuDlPiuMgrUtilsStats.insMemWrites++; + return IX_SUCCESS; +} + + +/* + * Function definition: ixPiuDlPiuMgrDataMemWrite + */ +ix_error +ixPiuDlPiuMgrDataMemWrite ( + ix_uint32 piuBaseAddress, + ix_uint32 dataMemAddress, + ix_uint32 dataMemData, + BOOL verify) +{ + ixPiuDlPiuMgrWriteCommandIssue (piuBaseAddress, + IX_PIUDL_EXCTL_CMD_WR_DATA_MEM, + dataMemAddress, dataMemData); + if (verify) + { + /* write invalid data to this reg, so we can see if we're reading + the EXDATA register too early */ + IX_PIUDL_REG_WRITE (piuBaseAddress, + IX_PIUDL_REG_OFFSET_EXDATA, + ~dataMemData); + + if (dataMemData != + ixPiuDlPiuMgrReadCommandIssue (piuBaseAddress, + IX_PIUDL_EXCTL_CMD_RD_DATA_MEM, + dataMemAddress)) + { + ixPiuDlPiuMgrUtilsStats.dataMemWriteFails++; + return IX_FAIL; + } + } + + ixPiuDlPiuMgrUtilsStats.dataMemWrites++; + return IX_SUCCESS; +} + + +/* + * Function definition: ixPiuDlPiuMgrExecAccRegWrite + */ +void +ixPiuDlPiuMgrExecAccRegWrite ( + ix_uint32 piuBaseAddress, + ix_uint32 regAddress, + ix_uint32 regData) +{ + ixPiuDlPiuMgrWriteCommandIssue (piuBaseAddress, + IX_PIUDL_EXCTL_CMD_WR_ECS_REG, + regAddress, regData); + ixPiuDlPiuMgrUtilsStats.ecsRegWrites++; +} + +#if defined(__ep805xx) +/* + * Function definition: ixPiuDlPiuMgrAppDualRegWrite + */ +ix_uint32 +ixPiuDlPiuMgrAppDualRegWrite ( + ix_uint32 piuBaseAddress, + ix_uint32 appDualRegAddress, + ix_uint32 appDualRegData, + BOOL verify) +{ + ixPiuDlPiuMgrWriteCommandIssue (piuBaseAddress, + IX_PIUDL_EXCTL_CMD_WR_ECS_REG, + appDualRegAddress, + appDualRegData); + if (verify) + { + if (appDualRegData != + ixPiuDlPiuMgrReadCommandIssue (piuBaseAddress, + IX_PIUDL_EXCTL_CMD_RD_ECS_REG, + appDualRegAddress)) + { + ixPiuDlPiuMgrUtilsStats.appDualWriteFails++; + return IX_FAIL; + } + } + + ixPiuDlPiuMgrUtilsStats.appDualWrites++; + return IX_SUCCESS; +} +#endif /* #if defined(__ep805xx) */ + +/* + * Function definition: ixPiuDlPiuMgrExecAccRegRead + */ +ix_uint32 +ixPiuDlPiuMgrExecAccRegRead ( + ix_uint32 piuBaseAddress, + ix_uint32 regAddress) +{ + ixPiuDlPiuMgrUtilsStats.ecsRegReads++; + return ixPiuDlPiuMgrReadCommandIssue (piuBaseAddress, + IX_PIUDL_EXCTL_CMD_RD_ECS_REG, + regAddress); +} + + +/* + * Function definition: ixPiuDlPiuMgrCommandIssue + */ +void +ixPiuDlPiuMgrCommandIssue ( + ix_uint32 piuBaseAddress, + ix_uint32 command) +{ + + IX_PIUDL_REG_WRITE (piuBaseAddress, IX_PIUDL_REG_OFFSET_EXCTL, command); + +} + + +/* + * Function definition: ixPiuDlPiuMgrDebugInstructionPreExec + */ +void +ixPiuDlPiuMgrDebugInstructionPreExec( + ix_uint32 piuBaseAddress) +{ + /* turn off the halt bit by clearing Execution Count register. */ + /* save reg contents 1st and restore later */ + IX_PIUDL_REG_READ (piuBaseAddress, IX_PIUDL_REG_OFFSET_EXCT, + &ixPiuDlSavedExecCount); + IX_PIUDL_REG_WRITE (piuBaseAddress, IX_PIUDL_REG_OFFSET_EXCT, 0); + + /* ensure that IF and IE are on (temporarily), so that we don't end up + * stepping forever */ + ixPiuDlSavedEcsDbgCtxtReg2 = ixPiuDlPiuMgrExecAccRegRead (piuBaseAddress, + IX_PIUDL_ECS_DBG_CTXT_REG_2); + + ixPiuDlPiuMgrExecAccRegWrite (piuBaseAddress, IX_PIUDL_ECS_DBG_CTXT_REG_2, + (ixPiuDlSavedEcsDbgCtxtReg2 | + IX_PIUDL_MASK_ECS_DBG_REG_2_IF | + IX_PIUDL_MASK_ECS_DBG_REG_2_IE)); +} + + +/* + * Function definition: ixPiuDlPiuMgrDebugInstructionExec + */ +void +ixPiuDlPiuMgrDebugInstructionExec( + ix_uint32 piuBaseAddress, + ix_uint32 piuInstruction, + ix_uint32 ctxtNum, + ix_uint32 ldur) +{ + ix_uint32 ecsDbgRegVal; + ix_uint32 oldWatchcount, newWatchcount; + + /* set the Active bit, and the LDUR, in the debug level */ + ecsDbgRegVal = IX_PIUDL_MASK_ECS_REG_0_ACTIVE | + (ldur << IX_PIUDL_OFFSET_ECS_REG_0_LDUR); + + ixPiuDlPiuMgrExecAccRegWrite (piuBaseAddress, IX_PIUDL_ECS_DBG_CTXT_REG_0, + ecsDbgRegVal); + + /* + * set CCTXT at ECS DEBUG L3 to specify in which context to execute the + * instruction, and set SELCTXT at ECS DEBUG Level to specify which context + * store to access. + * Debug ECS Level Reg 1 has form 0x000n000n, where n = context number + */ + ecsDbgRegVal = (ctxtNum << IX_PIUDL_OFFSET_ECS_REG_1_CCTXT) | + (ctxtNum << IX_PIUDL_OFFSET_ECS_REG_1_SELCTXT); + + ixPiuDlPiuMgrExecAccRegWrite (piuBaseAddress, IX_PIUDL_ECS_DBG_CTXT_REG_1, + ecsDbgRegVal); + + /* clear the pipeline */ + ixPiuDlPiuMgrCommandIssue (piuBaseAddress, IX_PIUDL_EXCTL_CMD_PIU_CLR_PIPE); + + /* load PIU instruction into the instruction register */ + ixPiuDlPiuMgrExecAccRegWrite (piuBaseAddress, IX_PIUDL_ECS_INSTRUCT_REG, + piuInstruction); + + /* we need this value later to wait for completion of PIU execution step */ + IX_PIUDL_REG_READ (piuBaseAddress, IX_PIUDL_REG_OFFSET_WC, &oldWatchcount); + + /* issue a Step One command via the Execution Control register */ + ixPiuDlPiuMgrCommandIssue (piuBaseAddress, IX_PIUDL_EXCTL_CMD_PIU_STEP); + + /* + * force the XScale to wait until the PIU has finished execution step + * NOTE that this delay will be very small, just long enough to allow a + * single PIU instruction to complete execution + */ + do + { + /* Watch Count register increments when PIU completes an instruction */ + IX_PIUDL_REG_READ (piuBaseAddress, IX_PIUDL_REG_OFFSET_WC, + &newWatchcount); + } + while (newWatchcount == oldWatchcount); + + ixPiuDlPiuMgrUtilsStats.dbgInstructionExecs++; + +} + + +/* + * Function definition: ixPiuDlPiuMgrDebugInstructionPostExec + */ +void +ixPiuDlPiuMgrDebugInstructionPostExec( + ix_uint32 piuBaseAddress) +{ + /* clear active bit in debug level */ + ixPiuDlPiuMgrExecAccRegWrite (piuBaseAddress, IX_PIUDL_ECS_DBG_CTXT_REG_0, + 0); + + /* clear the pipeline */ + ixPiuDlPiuMgrCommandIssue (piuBaseAddress, IX_PIUDL_EXCTL_CMD_PIU_CLR_PIPE); + + /* restore Execution Count register contents. */ + IX_PIUDL_REG_WRITE (piuBaseAddress, IX_PIUDL_REG_OFFSET_EXCT, + ixPiuDlSavedExecCount); + + /* restore IF and IE bits to original values */ + ixPiuDlPiuMgrExecAccRegWrite (piuBaseAddress, IX_PIUDL_ECS_DBG_CTXT_REG_2, + ixPiuDlSavedEcsDbgCtxtReg2); +} + + +/* + * Function definition: ixPiuDlPiuMgrLogicalRegRead + */ +PIU_PRIVATE ix_uint32 +ixPiuDlPiuMgrLogicalRegRead ( + ix_uint32 piuBaseAddress, + ix_uint32 regAddr, + ix_uint32 regSize, + ix_uint32 ctxtNum) +{ + ix_uint32 regVal; + ix_uint32 piuInstruction = 0; + ix_uint32 mask = 0; + + switch (regSize) + { + case IX_PIUDL_REG_SIZE_BYTE: + piuInstruction = IX_PIUDL_INSTR_RD_REG_BYTE; + mask = IX_PIUDL_MASK_LOWER_BYTE_OF_WORD; + break; + case IX_PIUDL_REG_SIZE_SHORT: + piuInstruction = IX_PIUDL_INSTR_RD_REG_SHORT; + mask = IX_PIUDL_MASK_LOWER_SHORT_OF_WORD; + break; + case IX_PIUDL_REG_SIZE_WORD: + piuInstruction = IX_PIUDL_INSTR_RD_REG_WORD; + mask = IX_PIUDL_MASK_FULL_WORD; + break; + default: + break; + } + + /* make regAddr be the SRC and DEST operands (e.g. movX d0, d0) */ + piuInstruction |= (regAddr << IX_PIUDL_OFFSET_INSTR_SRC) | + (regAddr << IX_PIUDL_OFFSET_INSTR_DEST); + + /* step execution of PIU intruction using Debug Executing Context stack */ + ixPiuDlPiuMgrDebugInstructionExec (piuBaseAddress, piuInstruction, + ctxtNum, IX_PIUDL_RD_INSTR_LDUR); + + /* read value of register from Execution Data register */ + IX_PIUDL_REG_READ (piuBaseAddress, IX_PIUDL_REG_OFFSET_EXDATA, ®Val); + + /* align value from left to right */ + regVal = (regVal >> (IX_PIUDL_REG_SIZE_WORD - regSize)) & mask; + + return regVal; +} + + +/* + * Function definition: ixPiuDlPiuMgrLogicalRegWrite + */ +ix_error +ixPiuDlPiuMgrLogicalRegWrite ( + ix_uint32 piuBaseAddress, + ix_uint32 regAddr, + ix_uint32 regVal, + ix_uint32 regSize, + ix_uint32 ctxtNum, + BOOL verify) +{ + ix_uint32 piuInstruction = 0; + ix_uint32 mask = 0; + ix_error status = IX_SUCCESS; + + if (regSize == IX_PIUDL_REG_SIZE_WORD) + { + /* PIU register addressing is left-to-right: e.g. |d0|d1|d2|d3| */ + /* Write upper half-word (short) to |d0|d1| */ + ixPiuDlPiuMgrLogicalRegWrite (piuBaseAddress, regAddr, + regVal >> IX_PIUDL_REG_SIZE_SHORT, + IX_PIUDL_REG_SIZE_SHORT, + ctxtNum, verify); + /* Write lower half-word (short) to |d2|d3| */ + ixPiuDlPiuMgrLogicalRegWrite (piuBaseAddress, + regAddr + IX_PIUDL_BYTES_PER_SHORT, + regVal & IX_PIUDL_MASK_LOWER_SHORT_OF_WORD, + IX_PIUDL_REG_SIZE_SHORT, + ctxtNum, verify); + /* NOTE that we did not need the return status here from these calls. + The seperate "verify" step below allows for this */ + + } + else + { + switch (regSize) + { + case IX_PIUDL_REG_SIZE_BYTE: + piuInstruction = IX_PIUDL_INSTR_WR_REG_BYTE; + mask = IX_PIUDL_MASK_LOWER_BYTE_OF_WORD; + break; + case IX_PIUDL_REG_SIZE_SHORT: + piuInstruction = IX_PIUDL_INSTR_WR_REG_SHORT; + mask = IX_PIUDL_MASK_LOWER_SHORT_OF_WORD; + break; + default: + break; + } + /* mask out any redundant bits, so verify will work later */ + regVal &= mask; + + /* fill dest operand field of instruction with destination reg addr */ + piuInstruction |= (regAddr << IX_PIUDL_OFFSET_INSTR_DEST); + + /* fill src operand field of instruction with least-sig 5 bits of val*/ + piuInstruction |= ((regVal & IX_PIUDL_MASK_IMMED_INSTR_SRC_DATA) << + IX_PIUDL_OFFSET_INSTR_SRC); + + /* fill coprocessor field of instruction with most-sig 11 bits of val*/ + piuInstruction |= ((regVal & IX_PIUDL_MASK_IMMED_INSTR_COPROC_DATA) << + IX_PIUDL_DISPLACE_IMMED_INSTR_COPROC_DATA); + + /* step execution of PIU intruction using Debug ECS */ + ixPiuDlPiuMgrDebugInstructionExec(piuBaseAddress, piuInstruction, + ctxtNum, IX_PIUDL_WR_INSTR_LDUR); + }/* condition: if reg to be written is 8-bit or 16-bit (not 32-bit) */ + + if (verify) + { + if (regVal != ixPiuDlPiuMgrLogicalRegRead (piuBaseAddress, regAddr, + regSize, ctxtNum)) + { + status = IX_FAIL; + } + } + + return status; +} + + +/* + * Function definition: ixPiuDlPiuMgrPhysicalRegWrite + */ +ix_error +ixPiuDlPiuMgrPhysicalRegWrite ( + ix_uint32 piuBaseAddress, + ix_uint32 regAddr, + ix_uint32 regValue, + BOOL verify) +{ + ix_error status; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPiuMgrPhysicalRegWrite\n"); + +/* + * There are 32 physical registers used in an PIU. These are + * treated as 16 pairs of 32-bit registers. To write one of the pair, + * write the pair number (0-16) to the REGMAP for Context 0. Then write + * the value to register 0 or 4 in the regfile, depending on which + * register of the pair is to be written + */ + + /* + * set REGMAP for context 0 to (regAddr >> 1) to choose which pair (0-16) + * of physical registers to write + */ + status = ixPiuDlPiuMgrLogicalRegWrite (piuBaseAddress, + IX_PIUDL_CTXT_REG_ADDR_REGMAP, + (regAddr >> + IX_PIUDL_OFFSET_PHYS_REG_ADDR_REGMAP), + IX_PIUDL_REG_SIZE_SHORT, 0, verify); + if (status == IX_SUCCESS) + { + /* regAddr = 0 or 4 */ + regAddr = (regAddr & IX_PIUDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR) * + IX_PIUDL_BYTES_PER_WORD; + + status = ixPiuDlPiuMgrLogicalRegWrite (piuBaseAddress, regAddr, regValue, + IX_PIUDL_REG_SIZE_WORD, 0, verify); + } + + if (status != IX_SUCCESS) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrPhysicalRegWrite: " + "error writing to physical register\n"); + } + + ixPiuDlPiuMgrUtilsStats.physicalRegWrites++; + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPiuMgrPhysicalRegWrite : status = %u\n", + status); + return status; +} + + +/* + * Function definition: ixPiuDlPiuMgrCtxtRegWrite + */ +ix_error +ixPiuDlPiuMgrCtxtRegWrite ( + ix_uint32 piuBaseAddress, + ix_uint32 ctxtNum, + IxPiuDlCtxtRegNum ctxtReg, + ix_uint32 ctxtRegVal, + BOOL verify) +{ + ix_uint32 tempRegVal; + ix_uint32 ctxtRegAddr; + ix_uint32 ctxtRegSize; + ix_error status = IX_SUCCESS; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPiuMgrCtxtRegWrite\n"); + + /* + * Context 0 has no STARTPC. Instead, this value is used to set + * NextPC for Background ECS, to set where PIU starts executing code + */ + if ((ctxtNum == 0) && (ctxtReg == IX_PIUDL_CTXT_REG_STARTPC)) + { + /* read BG_CTXT_REG_0, update NEXTPC bits, and write back to reg */ + tempRegVal = ixPiuDlPiuMgrExecAccRegRead (piuBaseAddress, + IX_PIUDL_ECS_BG_CTXT_REG_0); + tempRegVal &= ~IX_PIUDL_MASK_ECS_REG_0_NEXTPC; + tempRegVal |= (ctxtRegVal << IX_PIUDL_OFFSET_ECS_REG_0_NEXTPC) & + IX_PIUDL_MASK_ECS_REG_0_NEXTPC; + + ixPiuDlPiuMgrExecAccRegWrite (piuBaseAddress, + IX_PIUDL_ECS_BG_CTXT_REG_0, tempRegVal); + + ixPiuDlPiuMgrUtilsStats.nextPcWrites++; + } + else + { + ctxtRegAddr = ixPiuDlCtxtRegAccInfo[ctxtReg].regAddress; + ctxtRegSize = ixPiuDlCtxtRegAccInfo[ctxtReg].regSize; + status = ixPiuDlPiuMgrLogicalRegWrite (piuBaseAddress, ctxtRegAddr, + ctxtRegVal, ctxtRegSize, + ctxtNum, verify); + if (status != IX_SUCCESS) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrCtxtRegWrite: " + "error writing to context store register\n"); + } + + ixPiuDlPiuMgrUtilsStats.contextRegWrites++; + } + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPiuMgrCtxtRegWrite : status = %u\n", + status); + + return status; +} + + +/* + * Function definition: ixPiuDlPiuMgrUtilsStatsShow + */ +void +ixPiuDlPiuMgrUtilsStatsShow (void) +{ + printf ("\nixPiuDlPiuMgrUtilsStatsShow:\n"); + + printf ("\tInstruction Memory writes: %u\n", + ixPiuDlPiuMgrUtilsStats.insMemWrites); + printf ("\tInstruction Memory writes failed: %u\n", + ixPiuDlPiuMgrUtilsStats.insMemWriteFails); + printf ("\tData Memory writes: %u\n", + ixPiuDlPiuMgrUtilsStats.dataMemWrites); + printf ("\tData Memory writes failed: %u\n", + ixPiuDlPiuMgrUtilsStats.dataMemWriteFails); + printf ("\tExecuting Context Stack Register writes: %u\n", + ixPiuDlPiuMgrUtilsStats.ecsRegWrites); + printf ("\tExecuting Context Stack Register reads: %u\n", + ixPiuDlPiuMgrUtilsStats.ecsRegReads); + printf ("\tPhysical Register writes: %u\n", + ixPiuDlPiuMgrUtilsStats.physicalRegWrites); + printf ("\tContext Store Register writes: %u\n", + ixPiuDlPiuMgrUtilsStats.contextRegWrites); + printf ("\tExecution Backgound Context NextPC writes: %u\n", + ixPiuDlPiuMgrUtilsStats.nextPcWrites); + printf ("\tDebug Instructions Executed: %u\n", + ixPiuDlPiuMgrUtilsStats.dbgInstructionExecs); +#if defined(__ep805xx) + printf ("\tApplication Specific Dual Instruction Writes: %u\n", + ixPiuDlPiuMgrUtilsStats.appDualWrites); + printf ("\tApplication Specific Dual Instruction Write Fails: %u\n", + ixPiuDlPiuMgrUtilsStats.appDualWriteFails); +#endif + + printf ("\n"); +} + + +/* + * Function definition: ixPiuDlPiuMgrUtilsStatsReset + */ +void +ixPiuDlPiuMgrUtilsStatsReset (void) +{ + ixPiuDlPiuMgrUtilsStats.insMemWrites = 0; + ixPiuDlPiuMgrUtilsStats.insMemWriteFails = 0; + ixPiuDlPiuMgrUtilsStats.dataMemWrites = 0; + ixPiuDlPiuMgrUtilsStats.dataMemWriteFails = 0; + ixPiuDlPiuMgrUtilsStats.ecsRegWrites = 0; + ixPiuDlPiuMgrUtilsStats.ecsRegReads = 0; + ixPiuDlPiuMgrUtilsStats.physicalRegWrites = 0; + ixPiuDlPiuMgrUtilsStats.contextRegWrites = 0; + ixPiuDlPiuMgrUtilsStats.nextPcWrites = 0; + ixPiuDlPiuMgrUtilsStats.dbgInstructionExecs = 0; +#if defined(__ep805xx) + ixPiuDlPiuMgrUtilsStats.appDualWrites = 0; + ixPiuDlPiuMgrUtilsStats.appDualWriteFails = 0; +#endif +} diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/source/IxPiuDlSymbols.c b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/source/IxPiuDlSymbols.c new file mode 100644 index 0000000..f5b122c --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/source/IxPiuDlSymbols.c @@ -0,0 +1,96 @@ +/** + * @file IxPiuDlSymbols.c + * + * @description Contents are declarations of exported symbols for linux kernel + * module builds. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + + +#ifdef __linux + + +#include <linux/module.h> +#include <IxPiuDl.h> + +MODULE_LICENSE("GPL"); + +EXPORT_SYMBOL(ixPiuDlPhysicalAddressSet); +EXPORT_SYMBOL(ixPiuDlPiuInitAndStart); +EXPORT_SYMBOL(ixPiuDlCustomImagePiuInitAndStart); +EXPORT_SYMBOL(ixPiuDlPiuStopAndReset); +EXPORT_SYMBOL(ixPiuDlUnload); +EXPORT_SYMBOL(ixPiuDlStatsShow); +EXPORT_SYMBOL(ixPiuDlStatsReset); +EXPORT_SYMBOL(ixPiuDlLoadedImageGet); +EXPORT_SYMBOL(ixPiuDlAvailableImagesListGet); +EXPORT_SYMBOL(ixPiuDlPiuMgrPiuResetAssert); +EXPORT_SYMBOL(ixPiuDlPiuMgrPiuResetDeassert); +EXPORT_SYMBOL(ixPiuDlPiuMgrTriggerInterruptReset); + +#if defined(__ep805xx) +EXPORT_SYMBOL(ixPiuDlAppDualSet); +EXPORT_SYMBOL(ixPiuDlAppDualGet); +#endif + +#endif diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/source/IxPiuMicrocode.c b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/source/IxPiuMicrocode.c new file mode 100644 index 0000000..d45e72e --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/source/IxPiuMicrocode.c @@ -0,0 +1,2212 @@ +/** + * @date February 25, 2009 + * + * @brief IXP400 PIU Microcode Image file + * + * This file was generated by the IxPiuDlImageGen tool. + * It contains a PIU microcode image suitable for use + * with the PIU Downloader (IxPiuDl) component in the + * IXP400 Access Driver software library. + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + +/* Need to include the following header file for the + * image #defines used in the code below + */ +#define IX_PIUFW_VERSION_ID "2_4_0" +#include "IxPiuMicrocode.h" + + +#ifndef IX_PIUDL_READ_MICROCODE_FROM_FILE +/* NOTE - Only the IxPiuDl component should reference this array */ + +const unsigned IxPiuMicrocode_array[]={ + + +/* --- PIU FIRMWARE IMAGE --- */ +#if defined(IX_PIUDL_PIUIMAGE_PIU_HSS_TOLAPAI) +/* Image Description: Common HSS Build for Tolapai platform */ +0xfeedf00d, /* Image Marker */ +0x30010000, /* Image Identifier */ +0x00002066, /* Image Size */ + +/* DOWNLOAD MAP (for Image ID: 0x30010000) */ +0x00000000, /* block type (instruction) */ +0x0000000d, /* offset to block */ +0x00000001, /* block type (data) */ +0x00000a59, /* offset to block */ +0x00000001, /* block type (data) */ +0x000014a6, /* offset to block */ +0x00000001, /* block type (data) */ +0x000014b3, /* offset to block */ +0x00000001, /* block type (data) */ +0x00001eb8, /* offset to block */ +0x00000001, /* block type (data) */ +0x00001f3c, /* offset to block */ +0x0000000f, /* end of Download Map */ + +/* instruction block */ +0x00000000, /* location in PIU memory */ +0x00000a4a, /* number of words in the block */ +0xb002be03, 0xf0007020, 0xf0007020, 0xb000000b, +0xb000000b, 0x7044000b, 0x67b8fce0, 0xb000000b, +0xb000000b, 0xb000000b, 0x804ce800, 0x900074f0, +0xb000000b, 0xb000000b, 0x7048000b, 0x6000f9a0, +0xa01c7770, 0x308c000b, 0xc014ac00, 0xb000000b, +0xa048a820, 0xb000000b, 0xd0006986, 0x9002f9fd, +0x90007400, 0xd002ffe8, 0x7044000b, 0x67b8fce0, +0xb000000b, 0xb000000b, 0xb000000b, 0x7044000b, +0x801c77f0, 0xafd0000b, 0x3080000b, 0x7048000b, +0xa07cc1f0, 0xa048c500, 0x05048210, 0x7044000b, +0x20044020, 0x45380000, 0x7044000b, 0x40004000, +0x85400000, 0xd0004000, 0xc5440000, 0xd0004000, +0xf0004200, 0x056c0000, 0x45680210, 0x7084000b, +0x7048000b, 0xa07cc1f0, 0xe040c500, 0x05048210, +0x7044000b, 0x20044020, 0x45380000, 0x7044000b, +0x40004000, 0x85400000, 0xd0004000, 0xc5440000, +0xd0004000, 0xf0004200, 0x056c0000, 0x45680210, +0xb09c000b, 0x7048000b, 0xa01cc1f0, 0xc040c400, +0x05048210, 0x7044000b, 0x20044130, 0x45380000, +0xd0004000, 0x85400000, 0xd0004000, 0xc5440000, +0xd0004000, 0xf0004200, 0x056c0000, 0x45680210, +0x3080000b, 0xb0007410, 0xb000000b, 0xb000000b, +0xb000000b, 0x704c7e00, 0x27bcfce0, 0x2128f840, +0xa01076a0, 0xb0007420, 0xb000000b, 0xb000000b, +0xb000000b, 0x504c7e70, 0x47b8fca0, 0x0124f9b0, +0x000077f0, 0x90007430, 0xb000000b, 0xb000000b, +0xb000000b, 0x504c7e70, 0x47b8fca0, 0xc0dcf9d0, +0x20007710, 0xb0007440, 0xb000000b, 0xb000000b, +0xb000000b, 0x704c7e00, 0x67b8fce0, 0x4000f800, +0x801c77f0, 0x90007450, 0xb000000b, 0xb000000b, +0xb000000b, 0x504c7e70, 0x67b8fcd0, 0x80b8f920, +0xc0147700, 0x90007460, 0xb000000b, 0xb000000b, +0xb000000b, 0x504c7e10, 0x67b8fcb0, 0x40acf9b0, +0x00007790, 0xb0007470, 0xb000000b, 0xb000000b, +0xb000000b, 0x704c7e00, 0x47b8fcc0, 0xe0b0f810, +0x20007780, 0xb0007480, 0xb000000b, 0xb000000b, +0xb000000b, 0x704c7e00, 0x039cfc60, 0xc13cf910, +0xa01c7780, 0x90007490, 0xb000000b, 0xb000000b, +0xb000000b, 0x704c7e00, 0x67b8fce0, 0x4000f800, +0x801c77f0, 0x900074a0, 0xb000000b, 0xb000000b, +0xb000000b, 0x504c7e20, 0xa4a0fc20, 0x2068f8d0, +0x801c7730, 0xb00074b0, 0xb000000b, 0xb000000b, +0xb000000b, 0x504c7e20, 0xa4a0fc10, 0x2064f9f0, +0xa01c7720, 0x900074c0, 0xb000000b, 0xb000000b, +0xb000000b, 0x504c7e20, 0x84a0fc00, 0x0068f9b0, +0xe0147600, 0xb00074d0, 0xb000000b, 0xb000000b, +0xb000000b, 0x704c7e30, 0x4398fc50, 0xe02cf930, +0xa01c7710, 0xb00074e0, 0xb000000b, 0xb000000b, +0xb000000b, 0x504c7e20, 0x6398fc40, 0xc02cf860, +0x801c7700, 0x900074f0, 0xb000000b, 0xb000000b, +0xb000000b, 0x4fa04030, 0xf0007e00, 0xa9444010, +0xe92c4020, 0x093c4830, 0x7044000b, 0x000441e0, +0xc9280000, 0xd0007e10, 0xa9444010, 0xe92c4020, +0xa9284040, 0x293c4820, 0xd0007e20, 0xa9444010, +0xe92c4020, 0x293c4820, 0x7044000b, 0x60004160, +0xc9280000, 0xf0007e30, 0xa9444010, 0xe92c4020, +0x293c4820, 0x7044000b, 0x20044080, 0xc9280000, +0xd0007e40, 0xa9444010, 0xe92c4020, 0x293c4820, +0x89284000, 0xf0007e50, 0xa9444010, 0xe92c4020, +0x293c4820, 0x7044000b, 0x40004120, 0xc9280000, +0xf0007e60, 0xa9444010, 0xe92c4020, 0x293c4820, +0x7044000b, 0x20044040, 0xc9280000, 0xd0007e70, +0xa9444010, 0xe92c4020, 0x093c4830, 0x7044000b, +0x20044160, 0xc9280000, 0x7044000b, 0x200441f0, +0x89400000, 0x90005c00, 0x68701ce0, 0xb000000b, +0xb000000b, 0xb0005e00, 0x28181ef0, 0xe80c1ef0, +0xd000d000, 0x081c9090, 0x08109090, 0x9000d980, +0xe83c98d0, 0xa83898d0, 0x9000d800, 0x7044000b, +0x600c71f0, 0xe83c98d0, 0x7044000b, 0x600c71f0, +0xa83898d0, 0xd000d180, 0x081c9090, 0x08109090, +0x9000d800, 0xd0007180, 0xe83c98d0, 0xd0007180, +0xa83898d0, 0xb0005e11, 0xb0005e27, 0xb002f9e7, +0x7044000b, 0xc020d000, 0x9000d800, 0xd0005580, +0x081c9090, 0x08109090, 0xd000d011, 0xe83c98d0, +0xa83898d0, 0xd0005412, 0xb002f9fa, 0x90005c11, +0x90005c47, 0x9002f9d5, 0x308c000b, 0x403c8000, +0x10487e20, 0x4398fc30, 0x80107700, 0xb0033e4d, +0x6848ac20, 0x7048000b, 0x6004d880, 0x0af0c180, +0xb0003160, 0xd00080d1, 0x90018c1b, 0x90006e13, +0x90003170, 0xd0004c21, 0x90019a1c, 0xd0012414, +0x70449010, 0x6a6cc500, 0xf0018420, 0x9001951c, +0xf0006650, 0xf0006612, 0xd002b61f, 0xd000c800, +0xf0000ac0, 0x9000da4a, 0x9000da4a, 0xb0019511, +0xb001ab91, 0xf000641a, 0xb002fbf7, 0xf000c81a, +0xb0008831, 0xf0018840, 0xd000e000, 0xf0002340, +0x9000a0b1, 0xd00129d0, 0xd000e000, 0xd0002350, +0x9000a0b1, 0xf0012bd0, 0xd000e000, 0xd0002360, +0x9000a0b1, 0x90012dd0, 0xd000e000, 0xf0002370, +0x9000a0b1, 0x70452fd0, 0x90008871, 0xd001ea40, +0xd002ffe1, 0x9002be1c, 0x6848ac20, 0x7048000b, +0x6004e900, 0xca14c180, 0xb0003160, 0xd0008151, +0xf0018415, 0x90006e13, 0x90003170, 0x90004421, +0x90018017, 0x90007620, 0x9002be2f, 0x6848ac20, +0x7048000b, 0x6004e900, 0xca14c180, 0xb0003160, +0xd0008151, 0xf0018415, 0x90006e13, 0x90003170, +0x90004421, 0x90018018, 0xb0007630, 0xb002be22, +0xd002ffb4, 0x6848ac20, 0x7048000b, 0x6004e900, +0xca14c180, 0xb0003160, 0xd0008151, 0xf0018415, +0x90006e13, 0x90003170, 0x90004421, 0xb001201f, +0xf0006600, 0xb0006007, 0xd002b60e, 0x5045661f, +0x6a6cd100, 0x9001aa80, 0xb000000b, 0xb001ec80, +0xd001e881, 0x7044d810, 0xaa2cd480, 0xd001d8a0, +0x68702d60, 0xe804000b, 0xf0007e00, 0xa010000b, +0xb0018016, 0x50887610, 0xe028000b, 0x60a8000b, +0x7084000b, 0xb000c007, 0xf002b6b7, 0x70452e00, +0x6a6cc900, 0xf0018840, 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0xd0001eb0, 0xd0005433, 0xf0005407, +0xf002b605, 0x9000da4a, 0x9000da2a, 0xd0005412, +0x9002f9fd, 0x7044000b, 0xe520c480, 0xd0018a20, +0xb000000b, 0xb0008ad4, 0x9001ca20, 0xd00007f0, +0xf0007e00, 0x80108400, 0xb0003e30, 0xa86c000b, +0xf0037fad, 0xb000000b, 0xb000000b, 0xf002fffe, +0xb000000b, 0xb000000b, + +/* data block */ +0x00000000, /* location in PIU memory */ +0x00000a4b, /* number of words in the block */ +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 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0x4050409c, 0x40e84134, +0x418041cc, 0x42184264, 0x42b042fc, 0x43484394, +0x43e0442c, 0x447844c4, 0x4510455c, 0x45a845f4, +0x4640468c, 0x46d84724, 0x477047bc, 0x48084854, +0x48a048ec, 0x49384984, 0x49d04a1c, 0x4a684ab4, +0x4b004b4c, 0x4b984be4, 0x4c304c7c, 0x4cc84d14, +0x4d604dac, 0x4df84e44, 0x4e904edc, 0x4f284f74, +0x04000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x0c000800, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x14001000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x1c001800, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, + +/* data block */ +0x0000145c, /* location in PIU memory */ +0x00000082, /* number of words in the block */ +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x51705270, 0x51705270, + +/* data block */ +0x000014e0, /* location in PIU memory */ +0x00000128, /* number of words in the block */ +0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, +0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f, +0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, +0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f, +0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, +0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f, +0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, +0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f, +0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, +0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f, +0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, +0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf, +0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, +0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf, +0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, +0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff, +0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, +0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f, +0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, +0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f, +0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, +0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f, +0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, +0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f, +0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, +0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f, +0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, +0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf, +0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, +0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf, +0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, +0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff, +0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, +0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f, +0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, +0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f, +0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, +0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f, +0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, +0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f, +0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, +0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f, +0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, +0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf, +0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, +0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf, +0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, +0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff, +0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, +0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f, +0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, +0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f, +0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, +0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f, +0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, +0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f, +0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, +0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f, +0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, +0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf, +0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, +0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf, +0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, +0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff, +0x04000400, 0x00000000, 0x00000000, 0x00000000, +0x53805480, 0x55805680, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x0c000c00, 0x00000000, +0x00000000, 0x00000800, 0x53805480, 0x55805680, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x14001400, 0x00000000, 0x00000000, 0x00001000, +0x53805480, 0x55805680, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x1c001c00, 0x00000000, +0x00000000, 0x00001800, 0x53805480, 0x55805680, +0x00000000, 0x00000000, 0x00000000, 0x00000000, + +#endif /* IX_PIUDL_PIUIMAGE_PIU_HSS_TOLAPAI */ +/* END OF PIU FIRMWARE IMAGE */ + + +/* END OF IMAGE LIBRARY MARKER */ + +0xfeedf00d, 0xfeedf00d + + +}; /* END OF MICROCODE IMAGE */ + + +#endif /* IX_PIUDL_READ_MICROCODE_FROM_FILE */ diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMh.c b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMh.c new file mode 100644 index 0000000..b0e9bff --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMh.c @@ -0,0 +1,692 @@ +/** + * @file IxPiuMh.c + * + * @author Intel Corporation + * @date 18 Jan 2002 + * + * @description Contents are the implementation of the public API for the + * PIU Message Handler component. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + +/* + * Put the system defined include files required. + */ + +/* + * Put the user defined include files required. + */ + +#include "IxOsal.h" +#include "IxPiuMhMacros_p.h" + +#include "IxPiuMh.h" + +#include "IxPiuMhConfig_p.h" +#include "IxPiuMhReceive_p.h" +#include "IxPiuMhSend_p.h" +#include "IxPiuMhSolicitedCbMgr_p.h" +#include "IxPiuMhUnsolicitedCbMgr_p.h" + +/* + * #defines and macros used in this file. + */ + +/* + * Typedefs whose scope is limited to this file. + */ + +/* + * Variable declarations global to this file only. Externs are followed by + * static variables. + */ + +PRIVATE BOOL ixPiuMhInitialized = FALSE; + +/* + * Extern function prototypes. + */ + +/* + * Static function prototypes. + */ + +#if defined(__ep805xx) +/* + * Function definition: ixPiuMhPhysicalAddressSet + */ + +PUBLIC IX_STATUS ixPiuMhPhysicalAddressSet ( + IxPiuMhPiuId piuId, + UINT32 address) +{ + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhPhysicalAddressSet\n"); + + + /* check the piuId parameter */ + if (!ixPiuMhConfigPiuIdIsValid (piuId)) + { + IX_PIUMH_ERROR_REPORT ("PIU ID invalid\n"); + return IX_FAIL; + } + + /* ensure that the compoonent is not initialized */ + if (ixPiuMhInitialized) + { + return IX_FAIL; + } + + /* set the address */ + ixPiuMhConfigPhysicalAddressSet(piuId, address); + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhPhysicalAddressSet\n"); + + return IX_SUCCESS; +} +/* + * Function definition: ixPiuMhInterruptIdSet + */ + +PUBLIC IX_STATUS ixPiuMhInterruptIdSet ( + IxPiuMhPiuId piuId, + UINT32 interruptId) +{ + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhInterruptIdSet\n"); + + + /* check the piuId parameter */ + if (!ixPiuMhConfigPiuIdIsValid (piuId)) + { + IX_PIUMH_ERROR_REPORT ("PIU ID invalid\n"); + return IX_FAIL; + } + + /* ensure that the compoonent is not initialized */ + if (ixPiuMhInitialized) + { + return IX_FAIL; + } + + /* set the address */ + ixPiuMhConfigInterruptIdSet(piuId, interruptId); + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhInterruptIdSet\n"); + + return IX_SUCCESS; +} +#endif /* #if defined(__ep805xx) */ + +/* + * Function definition: ixPiuMhInitialize + */ + +PUBLIC IX_STATUS ixPiuMhInitialize ( + IxPiuMhPiuInterrupts piuInterrupts) +{ + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhInitialize\n"); + + /* check the piuInterrupts parameter */ + if ((piuInterrupts != IX_PIUMH_PIUINTERRUPTS_NO) && + (piuInterrupts != IX_PIUMH_PIUINTERRUPTS_YES)) + { + IX_PIUMH_ERROR_REPORT ("Illegal piuInterrupts parameter value\n"); + return IX_FAIL; + } + + /* parameters are ok ... */ + + /* initialize the Receive module */ + ixPiuMhReceiveInitialize (); + + + /* initialize the Solicited Callback Manager module */ + ixPiuMhSolicitedCbMgrInitialize (); + + /* initialize the Unsolicited Callback Manager module */ + ixPiuMhUnsolicitedCbMgrInitialize (); + + /* initialize the Configuration module + * + * NOTE: This module was originally configured before the + * others, but the sequence was changed so that interrupts + * would only be enabled after the handler functions were + * set up. The above modules need to be initialised to + * handle the PIU interrupts. See SCR #2231. + */ + ixPiuMhConfigInitialize (piuInterrupts); + + ixPiuMhInitialized = TRUE; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhInitialize\n"); + + return IX_SUCCESS; +} + +/* + * Function definition: ixPiuMhUnload + */ + +PUBLIC IX_STATUS ixPiuMhUnload (void) +{ + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhUnload\n"); + + if (!ixPiuMhInitialized) + { + return IX_FAIL; + } + + /* Uninitialize the Configuration module */ + ixPiuMhConfigUninit (); + /* Reset the PiuMhShow */ +#if defined(__ixp23xx) + ixPiuMhShowReset (IX_PIUMH_PIUID_PIU0); + ixPiuMhShowReset (IX_PIUMH_PIUID_PIU1); +#endif +#if defined(__ep805xx) + ixPiuMhShowReset (IX_PIUMH_PIUID_PIU0); +#endif +#if defined(__ixp42X) || defined(__ixp46X) || defined(__ixp5XX) + ixPiuMhShowReset (IX_PIUMH_PIUID_PIUA); + ixPiuMhShowReset (IX_PIUMH_PIUID_PIUB); +#endif +#if defined(__ixp42X) || defined(__ixp46X) && !defined(__ixp5XX) + ixPiuMhShowReset (IX_PIUMH_PIUID_PIUC); +#endif + + ixPiuMhUnsolicitedCbMgrUninitialize (); + ixPiuMhSolicitedCbMgrUninitialize (); + ixPiuMhReceiveUninitialize (); + ixPiuMhInitialized = FALSE; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhUnload\n"); + + return IX_SUCCESS; +} + + +/* + * Function definition: ixPiuMhUnsolicitedCallbackRegister + */ + +PUBLIC IX_STATUS ixPiuMhUnsolicitedCallbackRegister ( + IxPiuMhPiuId piuId, + IxPiuMhMessageId messageId, + IxPiuMhCallback unsolicitedCallback) +{ + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhUnsolicitedCallbackRegister\n"); + + /* check that we are initialized */ + if (!ixPiuMhInitialized) + { + IX_PIUMH_ERROR_REPORT ("IxPiuMh component is not initialized\n"); + return IX_FAIL; + } + + /* check the piuId parameter */ + if (!ixPiuMhConfigPiuIdIsValid (piuId)) + { + IX_PIUMH_ERROR_REPORT ("PIU ID invalid\n"); + return IX_FAIL; + } + + /* check the messageId parameter */ + if ((messageId < IX_PIUMH_MIN_MESSAGE_ID) + || (messageId > IX_PIUMH_MAX_MESSAGE_ID)) + { + IX_PIUMH_ERROR_REPORT ("Message ID is out of range\n"); + return IX_FAIL; + } + + /* the unsolicitedCallback parameter is allowed to be NULL */ + + /* parameters are ok ... */ + + /* get the lock to prevent other clients from entering */ + ixPiuMhConfigLockGet (piuId); + + /* save the unsolicited callback for the message ID */ + ixPiuMhUnsolicitedCbMgrCallbackSave ( + piuId, messageId, unsolicitedCallback); + + /* release the lock to allow other clients back in */ + ixPiuMhConfigLockRelease (piuId); + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhUnsolicitedCallbackRegister\n"); + + return IX_SUCCESS; +} + +/* + * Function definition: ixPiuMhUnsolicitedCallbackForRangeRegister + */ + +PUBLIC IX_STATUS ixPiuMhUnsolicitedCallbackForRangeRegister ( + IxPiuMhPiuId piuId, + IxPiuMhMessageId minMessageId, + IxPiuMhMessageId maxMessageId, + IxPiuMhCallback unsolicitedCallback) +{ + IxPiuMhMessageId messageId; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhUnsolicitedCallbackForRangeRegister\n"); + + /* check that we are initialized */ + if (!ixPiuMhInitialized) + { + IX_PIUMH_ERROR_REPORT ("IxPiuMh component is not initialized\n"); + return IX_FAIL; + } + + /* check the piuId parameter */ + if (!ixPiuMhConfigPiuIdIsValid (piuId)) + { + IX_PIUMH_ERROR_REPORT ("PIU ID invalid\n"); + return IX_FAIL; + } + + /* check the minMessageId parameter */ + if ((minMessageId < IX_PIUMH_MIN_MESSAGE_ID) + || (minMessageId > IX_PIUMH_MAX_MESSAGE_ID)) + { + IX_PIUMH_ERROR_REPORT ("Min message ID is out of range\n"); + return IX_FAIL; + } + + /* check the maxMessageId parameter */ + if ((maxMessageId < IX_PIUMH_MIN_MESSAGE_ID) + || (maxMessageId > IX_PIUMH_MAX_MESSAGE_ID)) + { + IX_PIUMH_ERROR_REPORT ("Max message ID is out of range\n"); + return IX_FAIL; + } + + /* check the semantics of the message range parameters */ + if (minMessageId > maxMessageId) + { + IX_PIUMH_ERROR_REPORT ("Min message ID greater than max message " + "ID\n"); + return IX_FAIL; + } + + /* the unsolicitedCallback parameter is allowed to be NULL */ + + /* parameters are ok ... */ + + /* get the lock to prevent other clients from entering */ + ixPiuMhConfigLockGet (piuId); + + /* for each message ID in the range ... */ + for (messageId = minMessageId; messageId <= maxMessageId; messageId++) + { + /* save the unsolicited callback for the message ID */ + ixPiuMhUnsolicitedCbMgrCallbackSave ( + piuId, messageId, unsolicitedCallback); + } + + /* release the lock to allow other clients back in */ + ixPiuMhConfigLockRelease (piuId); + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhUnsolicitedCallbackForRangeRegister\n"); + + return IX_SUCCESS; +} + +/* + * Function definition: ixPiuMhMessageSend + */ + +PUBLIC IX_STATUS ixPiuMhMessageSend ( + IxPiuMhPiuId piuId, + IxPiuMhMessage message, + UINT32 maxSendRetries) +{ + IX_STATUS status = IX_SUCCESS; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhMessageSend\n"); + + /* check that we are initialized */ + if (!ixPiuMhInitialized) + { + IX_PIUMH_ERROR_REPORT ("IxPiuMh component is not initialized\n"); + return IX_FAIL; + } + + /* check the piuId parameter */ + if (!ixPiuMhConfigPiuIdIsValid (piuId)) + { + IX_PIUMH_ERROR_REPORT ("PIU ID invalid\n"); + return IX_FAIL; + } + + /* parameters are ok ... */ + + /* get the lock to prevent other clients from entering */ + ixPiuMhConfigLockGet (piuId); + + /* send the message */ + status = ixPiuMhSendMessageSend (piuId, message, maxSendRetries); + if (status != IX_SUCCESS) + { + IX_PIUMH_ERROR_REPORT ("Failed to send message\n"); + } + + /* release the lock to allow other clients back in */ + ixPiuMhConfigLockRelease (piuId); + + IX_PIUMH_TRACE1 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhMessageSend" + " : status = %d\n", status); + + return status; +} + +/* + * Function definition: ixPiuMhMessageWithResponseSend + */ + +PUBLIC IX_STATUS ixPiuMhMessageWithResponseSend ( + IxPiuMhPiuId piuId, + IxPiuMhMessage message, + IxPiuMhMessageId solicitedMessageId, + IxPiuMhCallback solicitedCallback, + UINT32 maxSendRetries) +{ + IX_STATUS status = IX_SUCCESS; + IxPiuMhCallback unsolicitedCallback = NULL; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhMessageWithResponseSend\n"); + + /* check that we are initialized */ + if (!ixPiuMhInitialized) + { + IX_PIUMH_ERROR_REPORT ("IxPiuMh component is not initialized\n"); + return IX_FAIL; + } + + /* the solicitecCallback parameter is allowed to be NULL. this */ + /* signifies the client is not interested in the response message */ + + /* check the piuId parameter */ + if (!ixPiuMhConfigPiuIdIsValid (piuId)) + { + IX_PIUMH_ERROR_REPORT ("PIU ID invalid\n"); + return IX_FAIL; + } + + /* check the solicitedMessageId parameter */ + if ((solicitedMessageId < IX_PIUMH_MIN_MESSAGE_ID) + || (solicitedMessageId > IX_PIUMH_MAX_MESSAGE_ID)) + { + IX_PIUMH_ERROR_REPORT ("Solicited message ID is out of range\n"); + return IX_FAIL; + } + + /* check the solicitedMessageId parameter. if an unsolicited */ + /* callback has been registered for the specified message ID then */ + /* report an error and return failure */ + ixPiuMhUnsolicitedCbMgrCallbackRetrieve ( + piuId, solicitedMessageId, &unsolicitedCallback); + if (unsolicitedCallback != NULL) + { + IX_PIUMH_ERROR_REPORT ("Solicited message ID conflicts with " + "unsolicited message ID\n"); + return IX_FAIL; + } + + /* parameters are ok ... */ + + /* get the lock to prevent other clients from entering */ + ixPiuMhConfigLockGet (piuId); + + /* send the message */ + status = ixPiuMhSendMessageWithResponseSend ( + piuId, message, solicitedMessageId, solicitedCallback, + maxSendRetries); + if (status != IX_SUCCESS) + { + IX_PIUMH_ERROR_REPORT ("Failed to send message\n"); + } + + /* release the lock to allow other clients back in */ + ixPiuMhConfigLockRelease (piuId); + + IX_PIUMH_TRACE1 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhMessageWithResponseSend" + " : status = %d\n", status); + + return status; +} + +/* + * Function definition: ixPiuMhMessagesReceive + */ + +PUBLIC IX_STATUS ixPiuMhMessagesReceive ( + IxPiuMhPiuId piuId) +{ + IX_STATUS status = IX_SUCCESS; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhMessagesReceive\n"); + + /* check that we are initialized */ + if (!ixPiuMhInitialized) + { + IX_PIUMH_ERROR_REPORT ("IxPiuMh component is not initialized\n"); + return IX_FAIL; + } + + /* check the piuId parameter */ + if (!ixPiuMhConfigPiuIdIsValid (piuId)) + { + IX_PIUMH_ERROR_REPORT ("PIU ID invalid\n"); + return IX_FAIL; + } + + /* parameters are ok ... */ + + /* get the lock to prevent other clients from entering */ + ixPiuMhConfigLockGet (piuId); + + /* receive messages from the PIU */ + status = ixPiuMhReceiveMessagesReceive (piuId); + + if (status != IX_SUCCESS) + { + IX_PIUMH_ERROR_REPORT ("Failed to receive message\n"); + } + + /* release the lock to allow other clients back in */ + ixPiuMhConfigLockRelease (piuId); + + IX_PIUMH_TRACE1 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhMessagesReceive" + " : status = %d\n", status); + + return status; +} + +/* + * Function definition: ixPiuMhShow + */ + +PUBLIC IX_STATUS ixPiuMhShow ( + IxPiuMhPiuId piuId) +{ + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhShow\n"); + + /* check that we are initialized */ + if (!ixPiuMhInitialized) + { + IX_PIUMH_ERROR_REPORT ("IxPiuMh component is not initialized\n"); + return IX_FAIL; + } + + /* check the piuId parameter */ + if (!ixPiuMhConfigPiuIdIsValid (piuId)) + { + IX_PIUMH_ERROR_REPORT ("PIU ID invalid\n"); + return IX_FAIL; + } + + /* parameters are ok ... */ + + /* note we don't get the lock here as printing the statistics */ + /* to a console may take some time and we don't want to impact */ + /* system performance. this means that the statistics displayed */ + /* may be in a state of flux and make not represent a consistent */ + /* snapshot. */ + + /* display a header */ + ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, + "Current state of PIU ID %d:\n\n", piuId, 0, 0, 0, 0, 0); + + /* show the current state of each module */ + + /* show the current state of the Configuration module */ + ixPiuMhConfigShow (piuId); + + /* show the current state of the Receive module */ + ixPiuMhReceiveShow (piuId); + + /* show the current state of the Send module */ + ixPiuMhSendShow (piuId); + + /* show the current state of the Solicited Callback Manager module */ + ixPiuMhSolicitedCbMgrShow (piuId); + + /* show the current state of the Unsolicited Callback Manager module */ + ixPiuMhUnsolicitedCbMgrShow (piuId); + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhShow\n"); + + return IX_SUCCESS; +} + +/* + * Function definition: ixPiuMhShowReset + */ + +PUBLIC IX_STATUS ixPiuMhShowReset ( + IxPiuMhPiuId piuId) +{ + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhShowReset\n"); + + /* check that we are initialized */ + if (!ixPiuMhInitialized) + { + IX_PIUMH_ERROR_REPORT ("IxPiuMh component is not initialized\n"); + return IX_FAIL; + } + + /* check the piuId parameter */ + if (!ixPiuMhConfigPiuIdIsValid (piuId)) + { + IX_PIUMH_ERROR_REPORT ("PIU ID invalid\n"); + return IX_FAIL; + } + + /* parameters are ok ... */ + + /* note we don't get the lock here as resetting the statistics */ + /* shouldn't impact system performance. */ + + /* reset the current state of each module */ + + /* reset the current state of the Configuration module */ + ixPiuMhConfigShowReset (piuId); + + /* reset the current state of the Receive module */ + ixPiuMhReceiveShowReset (piuId); + + /* reset the current state of the Send module */ + ixPiuMhSendShowReset (piuId); + + /* reset the current state of the Solicited Callback Manager module */ + ixPiuMhSolicitedCbMgrShowReset (piuId); + + /* reset the current state of the Unsolicited Callback Manager module */ + ixPiuMhUnsolicitedCbMgrShowReset (piuId); + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhShowReset\n"); + + return IX_SUCCESS; +} diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMhConfig.c b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMhConfig.c new file mode 100644 index 0000000..0c9061a --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMhConfig.c @@ -0,0 +1,776 @@ +/** + * @file IxPiuMhConfig.c + * + * @author Intel Corporation + * @date 18 Jan 2002 + * + * @description Contents are the implementation of the private API for the + * Configuration module. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + +/* + * Put the system defined include files required. + */ + + +/* + * Put the user defined include files required. + */ + +#include "IxOsal.h" + +#include "IxPiuMhMacros_p.h" + +#include "IxPiuMhConfig_p.h" + + +#if defined(__ixp23xx) +#define IX_PIUMH_PIU0_INT (IX_PIU_IRQ_DBG0) +#define IX_PIUMH_PIU1_INT (IX_PIU_IRQ_DBG1) +#endif +#if defined(__ep805xx) +#define IX_PIUMH_PIU0_INT (IX_PIU_IRQ_DBG0) +#endif + + +PRIVATE IxPiuMhPiuInterrupts ixPiuMhConfigInterrupts; + +/* + * #defines and macros used in this file. + */ +#define IX_PIU_MH_MAX_NUM_OF_RETRIES 1000000 /**< Maximum number of + * retries before + * timeout + */ + +/* + * Typedefs whose scope is limited to this file. + */ + +/** + * @struct IxPiuMhConfigStats + * + * @brief This structure is used to maintain statistics for the + * Configuration module. + */ + +typedef struct +{ + UINT32 outFifoReads; /**< outFifo reads */ + UINT32 inFifoWrites; /**< inFifo writes */ + UINT32 maxInFifoFullRetries; /**< max retries if inFIFO full */ + UINT32 maxOutFifoEmptyRetries; /**< max retries if outFIFO empty */ +} IxPiuMhConfigStats; + +/* + * Variable declarations global to this file only. Externs are followed by + * static variables. + */ + +IxPiuMhConfigPiuInfo ixPiuMhConfigPiuInfo[IX_PIUMH_NUM_PIUS] = +{ +#if defined(__ixp23xx) + { + 0, /*mutex*/ + IX_PIUMH_PIU0_INT, /*interrupt ID*/ + 0, /*register virtual base address*/ + 0, /*status register virtual address*/ + 0, /*control register virtual address*/ + 0, /*inFIFO register virutal address*/ + 0, /*outFIFO register virtual address*/ + NULL, /*isr routine for handling interrupt*/ + FALSE /*old interrupt state (TRUE => enabled)*/ + }, + { + 0, /*mutex*/ + IX_PIUMH_PIU1_INT, /*interrupt ID*/ + 0, /*register virtual base address*/ + 0, /*status register virtual address*/ + 0, /*control register virtual address*/ + 0, /*inFIFO register virutal address*/ + 0, /*outFIFO register virtual address*/ + NULL, /*isr routine for handling interrupt*/ + FALSE /*old interrupt state (TRUE => enabled)*/ + } +#endif +#if defined(__ep805xx) + { + 0, /*mutex*/ + IX_PIUMH_PIU0_INT, /*interrupt ID*/ + IX_PIU_PIU0_PHYS, /*register physical base address*/ + 0, /*register virtual base address*/ + 0, /*status register virtual address*/ + 0, /*control register virtual address*/ + 0, /*inFIFO register virutal address*/ + 0, /*outFIFO register virtual address*/ + NULL, /*isr routine for handling interrupt*/ + FALSE /*old interrupt state (TRUE => enabled)*/ + } +#endif +#if defined(__ixp42X) || defined(__ixp46X) || defined(__ixp5XX) + { + 0, + IX_PIUMH_PIUA_INT, + 0, + 0, + 0, + 0, + 0, + NULL, + FALSE + }, + { + 0, + IX_PIUMH_PIUB_INT, + 0, + 0, + 0, + 0, + 0, + NULL, + FALSE + } +#endif +#if defined(__ixp42X) || defined(__ixp46X) && !defined(__ixp5XX) + , + { + 0, + IX_PIUMH_PIUC_INT, + 0, + 0, + 0, + 0, + 0, + NULL, + FALSE + } +#endif +}; + +PRIVATE IxPiuMhConfigStats ixPiuMhConfigStats[IX_PIUMH_NUM_PIUS]; + +/* + * Extern function prototypes. + */ + +/* + * Static function prototypes. + */ + +/* + * Function definition: ixPiuMhIsr + */ +void ixPiuMhIsr (void *parameter) +{ + IxPiuMhPiuId piuId = (IxPiuMhPiuId)parameter; + UINT32 ofint; + volatile UINT32 *statusReg = + (UINT32 *)ixPiuMhConfigPiuInfo[piuId].statusRegister; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhIsr\n"); + + /* get the OFINT (OutFifo interrupt) bit of the status register */ + IX_PIUMH_REGISTER_READ_BITS (statusReg, &ofint, IX_PIUMH_PIU_STAT_OFINT); + + /* if the OFINT status bit is set */ + if (ofint) + { + /* if there is an ISR registered for this PIU */ + if (ixPiuMhConfigPiuInfo[piuId].isr != NULL) + { + /* invoke the ISR routine */ + ixPiuMhConfigPiuInfo[piuId].isr (piuId); + } + else + { + /* if we don't service the interrupt the PIU will */ + /* continue to trigger the interrupt indefinitely */ + IX_PIUMH_ERROR_REPORT ("No ISR registered to service " + "interrupt\n"); + } + } + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhIsr\n"); +} + + +#if defined(__ep805xx) +/* + * Function definition: ixPiuMhConfigPhysicalAddressSet + */ + +void ixPiuMhConfigPhysicalAddressSet( + IxPiuMhPiuId piuId, + UINT32 address) +{ + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhConfigPhysicalAddressSet\n"); + + /* set the address for the given PIU in the config structure */ + ixPiuMhConfigPiuInfo[piuId].physicalRegisterBase = address; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhConfigPhysicalAddressSet\n"); +} + +/* + * Function definition: ixPiuMhConfigInterruptIdSet + */ + +void ixPiuMhConfigInterruptIdSet( + IxPiuMhPiuId piuId, + UINT32 interruptId) +{ + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhConfigInterruptIdSet\n"); + + /* set the interruptID for the given PIU in the config structure */ + ixPiuMhConfigPiuInfo[piuId].interruptId = interruptId; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhConfigInterruptIdSet\n"); +} +#endif /* #if defined(__ep805xx) */ + + +/* + * Function definition: ixPiuMhConfigInitialize + */ + +void ixPiuMhConfigInitialize ( + IxPiuMhPiuInterrupts piuInterrupts) +{ + IxPiuMhPiuId piuId; + UINT32 virtualAddr[IX_PIUMH_NUM_PIUS]; +#if defined(__ep805xx) + UINT32 physAddr = 0; +#endif + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhConfigInitialize\n"); + + +#if defined(__ixp23xx) + /* PIU-0 register address space */ + virtualAddr[IX_PIUMH_PIUID_PIU0] = + (UINT32) IX_OSAL_MEM_MAP(IX_PIU_PIU0_PHYS,0); + + /* PIU-1 register address space */ + virtualAddr[IX_PIUMH_PIUID_PIU1] = + (UINT32) IX_OSAL_MEM_MAP(IX_PIU_PIU1_PHYS,0); +#endif + +#if defined(__ep805xx) + /* PIU-0 register address space */ + physAddr = ixPiuMhConfigPiuInfo[IX_PIUMH_PIUID_PIU0].physicalRegisterBase; + + /* no OS agnostic OSAL function available for memory mapping which works + * for linux - using linux ioremap call */ + virtualAddr[IX_PIUMH_PIUID_PIU0] = + (UINT32) ixOsalIoRemap (physAddr, IX_PIU_MAPPED_MEMORY_SIZE); + +#endif + +#if defined(__ixp42X) || defined(__ixp46X) || defined(__ixp5XX) + + /* Request a mapping for the PIU-A config register address space */ + virtualAddr[IX_PIUMH_PIUID_PIUA] = + (UINT32) IX_OSAL_MEM_MAP (IX_PIUMH_PIUA_BASE, + IX_OSAL_IXP400_PIUA_MAP_SIZE); + IX_OSAL_ASSERT (virtualAddr[IX_PIUMH_PIUID_PIUA]); + + /* Request a mapping for the PIU-B config register address space */ + virtualAddr[IX_PIUMH_PIUID_PIUB] = + (UINT32) IX_OSAL_MEM_MAP (IX_PIUMH_PIUB_BASE, + IX_OSAL_IXP400_PIUB_MAP_SIZE); + IX_OSAL_ASSERT (virtualAddr[IX_PIUMH_PIUID_PIUB]); +#endif +#if defined(__ixp42X) || defined(__ixp46X) && !defined(__ixp5XX) + /* Request a mapping for the PIU-C config register address space */ + virtualAddr[IX_PIUMH_PIUID_PIUC] = + (UINT32) IX_OSAL_MEM_MAP (IX_PIUMH_PIUC_BASE, + IX_OSAL_IXP400_PIUC_MAP_SIZE); + IX_OSAL_ASSERT (virtualAddr[IX_PIUMH_PIUID_PIUC]); +#endif + + /* for each PIU ... */ + for (piuId = 0; piuId < IX_PIUMH_NUM_PIUS; piuId++) + { + /* declare a convenience pointer */ + IxPiuMhConfigPiuInfo *piuInfo = &ixPiuMhConfigPiuInfo[piuId]; + + /* store the virtual addresses of the PIU registers for later use */ + piuInfo->virtualRegisterBase = virtualAddr[piuId]; + piuInfo->statusRegister = virtualAddr[piuId] + IX_PIUMH_PIUSTAT_OFFSET; + piuInfo->controlRegister = virtualAddr[piuId] + IX_PIUMH_PIUCTL_OFFSET; + piuInfo->inFifoRegister = virtualAddr[piuId] + IX_PIUMH_PIUFIFO_OFFSET; + piuInfo->outFifoRegister = virtualAddr[piuId] + IX_PIUMH_PIUFIFO_OFFSET; + + /* for test purposes - to verify the register addresses */ + IX_PIUMH_TRACE2 (IX_PIUMH_DEBUG, "PIU %d status register = " + "0x%08X\n", piuId, piuInfo->statusRegister); + IX_PIUMH_TRACE2 (IX_PIUMH_DEBUG, "PIU %d control register = " + "0x%08X\n", piuId, piuInfo->controlRegister); + IX_PIUMH_TRACE2 (IX_PIUMH_DEBUG, "PIU %d inFifo register = " + "0x%08X\n", piuId, piuInfo->inFifoRegister); + IX_PIUMH_TRACE2 (IX_PIUMH_DEBUG, "PIU %d outFifo register = " + "0x%08X\n", piuId, piuInfo->outFifoRegister); + + /* initialise a mutex for this PIU */ + (void) ixOsalMutexInit (&piuInfo->mutex); + + /* if we should service the PIU's "outFIFO not empty" interrupt */ + if (piuInterrupts == IX_PIUMH_PIUINTERRUPTS_YES) + { + /* enable the PIU's "outFIFO not empty" interrupt */ + ixPiuMhConfigPiuInterruptEnable (piuId); + } + else + { + /* disable the PIU's "outFIFO not empty" interrupt */ + ixPiuMhConfigPiuInterruptDisable (piuId); + } + } + + /* This will be used in ixPiuMhConfigUninit() */ + ixPiuMhConfigInterrupts = piuInterrupts; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhConfigInitialize\n"); +} + +/* + * Function definition: ixPiuMhConfigUninit + */ + +void ixPiuMhConfigUninit (void) +{ + IxPiuMhPiuId piuId; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhConfigUninit\n"); + + /* for each PIU ... */ + for (piuId = 0; piuId < IX_PIUMH_NUM_PIUS; piuId++) + { + /* declare a convenience pointer */ + IxPiuMhConfigPiuInfo *piuInfo = &ixPiuMhConfigPiuInfo[piuId]; + + /* Disconnect our ISR to the PIU interrupt */ + if (IX_PIUMH_PIUINTERRUPTS_YES == ixPiuMhConfigInterrupts) + { + ixPiuMhConfigPiuInterruptDisable (piuId); + } + + ixOsalMutexDestroy(&piuInfo->mutex); + +#if defined(__ep805xx) && !defined(UNIT_TEST) + /* no OS agnostic OSAL function available for memory mapping which works + * for linux - using linux iounmap call */ + ixOsalIoUnmap(piuInfo->virtualRegisterBase, IX_PIU_MAPPED_MEMORY_SIZE); +#endif + +#if !defined(__ep805xx) || defined(UNIT_TEST) + IX_OSAL_MEM_UNMAP (piuInfo->virtualRegisterBase); + IX_OSAL_MEM_UNMAP (piuInfo->statusRegister); + IX_OSAL_MEM_UNMAP (piuInfo->controlRegister); + IX_OSAL_MEM_UNMAP (piuInfo->inFifoRegister); + IX_OSAL_MEM_UNMAP (piuInfo->outFifoRegister); +#endif + } + + /* Reset this parameter here which was set during Init */ + if (IX_PIUMH_PIUINTERRUPTS_YES == ixPiuMhConfigInterrupts) + { + ixPiuMhConfigInterrupts = IX_PIUMH_PIUINTERRUPTS_NO; + } + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhConfigUninit\n"); +} + +/* + * Function definition: ixPiuMhConfigIsrRegister + */ + +void ixPiuMhConfigIsrRegister ( + IxPiuMhPiuId piuId, + IxPiuMhConfigIsr isr) +{ + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhConfigIsrRegister\n"); + + /* check if there is already an ISR registered for this PIU */ + if (ixPiuMhConfigPiuInfo[piuId].isr != NULL) + { + IX_PIUMH_TRACE0 (IX_PIUMH_DEBUG, "Over-writing registered PIU ISR\n"); + } + + /* save the ISR routine with the PIU info */ + ixPiuMhConfigPiuInfo[piuId].isr = isr; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhConfigIsrRegister\n"); +} + +void ixPiuMhConfigIsrUnregister (IxPiuMhPiuId piuId) +{ + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhConfigIsrUnregister\n"); + + ixPiuMhConfigPiuInfo[piuId].isr = NULL; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhConfigIsrUnregister\n"); +} + +/* + * Function definition: ixPiuMhConfigPiuInterruptEnable + */ + +BOOL ixPiuMhConfigPiuInterruptEnable ( + IxPiuMhPiuId piuId) +{ + UINT32 ofe; + volatile UINT32 *controlReg = + (UINT32 *)ixPiuMhConfigPiuInfo[piuId].controlRegister; + + /* get the OFE (OutFifoEnable) bit of the control register */ + IX_PIUMH_REGISTER_READ_BITS (controlReg, &ofe, IX_PIUMH_PIU_CTL_OFE); + + /* if the interrupt is disabled then we must enable it */ + if (!ofe) + { + /* set the OFE (OutFifoEnable) bit of the control register */ + /* we must set the OFEWE (OutFifoEnableWriteEnable) at the same */ + /* time for the write to have effect */ + IX_PIUMH_REGISTER_WRITE_BITS (controlReg, + (IX_PIUMH_PIU_CTL_OFE | + IX_PIUMH_PIU_CTL_OFEWE), + (IX_PIUMH_PIU_CTL_OFE | + IX_PIUMH_PIU_CTL_OFEWE)); + } + + /* return the previous state of the interrupt */ + return (ofe != 0); +} + +/* + * Function definition: ixPiuMhConfigPiuInterruptDisable + */ + +BOOL ixPiuMhConfigPiuInterruptDisable ( + IxPiuMhPiuId piuId) +{ + UINT32 ofe; + volatile UINT32 *controlReg = + (UINT32 *)ixPiuMhConfigPiuInfo[piuId].controlRegister; + + /* get the OFE (OutFifoEnable) bit of the control register */ + IX_PIUMH_REGISTER_READ_BITS (controlReg, &ofe, IX_PIUMH_PIU_CTL_OFE); + + /* if the interrupt is enabled then we must disable it */ + if (ofe) + { + /* unset the OFE (OutFifoEnable) bit of the control register */ + /* we must set the OFEWE (OutFifoEnableWriteEnable) at the same */ + /* time for the write to have effect */ + IX_PIUMH_REGISTER_WRITE_BITS (controlReg, + (0 | + IX_PIUMH_PIU_CTL_OFEWE), + (IX_PIUMH_PIU_CTL_OFE | + IX_PIUMH_PIU_CTL_OFEWE)); + } + + /* return the previous state of the interrupt */ + return (ofe != 0); +} + +/* + * Function definition: ixPiuMhConfigMessageIdGet + */ + +IxPiuMhMessageId ixPiuMhConfigMessageIdGet ( + IxPiuMhMessage message) +{ + /* return the most-significant byte of the first word of the */ + /* message */ + return ((IxPiuMhMessageId) ((message.data[0] >> + IX_PIUMH_MESSAGE_ID_OFFSET) & 0xFF)); +} + +/* + * Function definition: ixPiuMhConfigPiuIdIsValid + */ + +BOOL ixPiuMhConfigPiuIdIsValid ( + IxPiuMhPiuId piuId) +{ + /* check that the piuId parameter is within the range of valid IDs */ + return (piuId >= 0 && piuId < IX_PIUMH_NUM_PIUS); +} + +/* + * Function definition: ixPiuMhConfigLockGet + */ + +void ixPiuMhConfigLockGet ( + IxPiuMhPiuId piuId) +{ + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhConfigLockGet\n"); + + /* lock the mutex for this PIU */ + (void) ixOsalMutexLock (&ixPiuMhConfigPiuInfo[piuId].mutex, + IX_OSAL_WAIT_FOREVER); + + /* disable the PIU's "outFIFO not empty" interrupt */ + ixPiuMhConfigPiuInfo[piuId].oldInterruptState = + ixPiuMhConfigPiuInterruptDisable (piuId); + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhConfigLockGet\n"); +} + +/* + * Function definition: ixPiuMhConfigLockRelease + */ + +void ixPiuMhConfigLockRelease ( + IxPiuMhPiuId piuId) +{ + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhConfigLockRelease\n"); + + /* if the interrupt was previously enabled */ + if (ixPiuMhConfigPiuInfo[piuId].oldInterruptState) + { + /* enable the PIU's "outFIFO not empty" interrupt */ + ixPiuMhConfigPiuInfo[piuId].oldInterruptState = + ixPiuMhConfigPiuInterruptEnable (piuId); + } + + /* unlock the mutex for this PIU */ + (void) ixOsalMutexUnlock (&ixPiuMhConfigPiuInfo[piuId].mutex); + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhConfigLockRelease\n"); +} + +/* + * Function definition: ixPiuMhConfigInFifoWrite + */ + +IX_STATUS ixPiuMhConfigInFifoWrite ( + IxPiuMhPiuId piuId, + IxPiuMhMessage message) +{ + volatile UINT32 *piuInFifo = + (UINT32 *)ixPiuMhConfigPiuInfo[piuId].inFifoRegister; + UINT32 retriesCount = 0; + + /* write the first word of the message to the PIU's inFIFO */ + IX_PIUMH_REGISTER_WRITE (piuInFifo, message.data[0]); + + /* need to wait for room to write second word - see SCR #493, + poll for maximum number of retries, if exceed maximum + retries, exit from while loop */ + while ((IX_PIU_MH_MAX_NUM_OF_RETRIES > retriesCount) + && ixPiuMhConfigInFifoIsFull (piuId)) + { + retriesCount++; + } + + /* Return TIMEOUT status to caller, indicate that PIU Hang / Halt */ + if (IX_PIU_MH_MAX_NUM_OF_RETRIES == retriesCount) + { + return IX_PIUMH_CRITICAL_PIU_ERR; + } + + /* write the second word of the message to the PIU's inFIFO */ + IX_PIUMH_REGISTER_WRITE (piuInFifo, message.data[1]); + + /* record in the stats the maximum number of retries needed */ + if (ixPiuMhConfigStats[piuId].maxInFifoFullRetries < retriesCount) + { + ixPiuMhConfigStats[piuId].maxInFifoFullRetries = retriesCount; + } + + /* update statistical info */ + ixPiuMhConfigStats[piuId].inFifoWrites++; + + return IX_SUCCESS; +} + +/* + * Function definition: ixPiuMhConfigOutFifoRead + */ + +IX_STATUS ixPiuMhConfigOutFifoRead ( + IxPiuMhPiuId piuId, + IxPiuMhMessage *message) +{ + volatile UINT32 *piuOutFifo = + (UINT32 *)ixPiuMhConfigPiuInfo[piuId].outFifoRegister; + + /* read the first word of the message from the PIU's outFIFO */ + IX_PIUMH_REGISTER_READ (piuOutFifo, &message->data[0]); + +#if !defined(__ep805xx) + UINT32 retriesCount = 0; + /* need to wait for PIU to write second word - see SCR #493 + poll for maximum number of retries, if exceed maximum + retries, exit from while loop */ + while ((IX_PIU_MH_MAX_NUM_OF_RETRIES > retriesCount) + && ixPiuMhConfigOutFifoIsEmpty (piuId)) + { + retriesCount++; + } + + /* Return TIMEOUT status to caller, indicate that PIU Hang / Halt */ + if (IX_PIU_MH_MAX_NUM_OF_RETRIES == retriesCount) + { + return IX_PIUMH_CRITICAL_PIU_ERR; + } + + /* record in the stats the maximum number of retries needed */ + if (ixPiuMhConfigStats[piuId].maxOutFifoEmptyRetries < retriesCount) + { + ixPiuMhConfigStats[piuId].maxOutFifoEmptyRetries = retriesCount; + } +#endif /* #if !defined(__ep805xx) */ + + /* read the second word of the message from the PIU's outFIFO */ + IX_PIUMH_REGISTER_READ (piuOutFifo, &message->data[1]); + + /* update statistical info */ + ixPiuMhConfigStats[piuId].outFifoReads++; + + return IX_SUCCESS; +} + +/* + * Function definition: ixPiuMhConfigShow + */ + +void ixPiuMhConfigShow ( + IxPiuMhPiuId piuId) +{ + /* show the message fifo read counter */ + IX_PIUMH_SHOW ("Message FIFO reads", + ixPiuMhConfigStats[piuId].outFifoReads); + + /* show the message fifo write counter */ + IX_PIUMH_SHOW ("Message FIFO writes", + ixPiuMhConfigStats[piuId].inFifoWrites); + + /* show the max retries performed when inFIFO full */ + IX_PIUMH_SHOW ("Max inFIFO Full retries", + ixPiuMhConfigStats[piuId].maxInFifoFullRetries); + + /* show the max retries performed when outFIFO empty */ + IX_PIUMH_SHOW ("Max outFIFO Empty retries", + ixPiuMhConfigStats[piuId].maxOutFifoEmptyRetries); + + /* show the current status of the inFifo */ + ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, + "InFifo is %s and %s\n", + (ixPiuMhConfigInFifoIsEmpty (piuId) ? + (int) "EMPTY" : (int) "NOT EMPTY"), + (ixPiuMhConfigInFifoIsFull (piuId) ? + (int) "FULL" : (int) "NOT FULL"), + 0, 0, 0, 0); + + /* show the current status of the outFifo */ + ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, + "OutFifo is %s and %s\n", + (ixPiuMhConfigOutFifoIsEmpty (piuId) ? + (int) "EMPTY" : (int) "NOT EMPTY"), + (ixPiuMhConfigOutFifoIsFull (piuId) ? + (int) "FULL" : (int) "NOT FULL"), + 0, 0, 0, 0); +} + +/* + * Function definition: ixPiuMhConfigShowReset + */ + +void ixPiuMhConfigShowReset ( + IxPiuMhPiuId piuId) +{ + /* reset the message fifo read counter */ + ixPiuMhConfigStats[piuId].outFifoReads = 0; + + /* reset the message fifo write counter */ + ixPiuMhConfigStats[piuId].inFifoWrites = 0; + + /* reset the max inFIFO Full retries counter */ + ixPiuMhConfigStats[piuId].maxInFifoFullRetries = 0; + + /* reset the max outFIFO empty retries counter */ + ixPiuMhConfigStats[piuId].maxOutFifoEmptyRetries = 0; +} + + diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMhDll.c b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMhDll.c new file mode 100644 index 0000000..d01b0bb --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMhDll.c @@ -0,0 +1,135 @@ +/* + * Copyright (c) Microsoft Corporation. All rights reserved. + * + * + * Use of this source code is subject to the terms of the Microsoft end-user + * license agreement (EULA) under which you licensed this SOFTWARE PRODUCT. + * If you did not accept the terms of the EULA, you are not authorized to use + * this source code. For a copy of the EULA, please see the LICENSE.RTF on your + * install media. +*/ +/** + * @file IxPiuMhDll.c + * + * @date June 23, 2003 + * + * @description Contents are the implementation for the piuMh layer + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +#ifdef __wince + +/* + * System Defined Include Files + */ + +/* + * User Defined Header Files + */ +#include "IxOsalTypes.h" + +/* + * Macro Definitions + */ + +/* + * Type Definitions + */ + +/* + * Variable Declarations + */ + +/* + * Extern Function Prototypes + */ + +/* + * Static Function Prototypes + */ + +/* + * Function Definition + */ + +BOOL APIENTRY +IxPiuMhDllMain( + HANDLE hModule, + DWORD ul_reason_for_call, + LPVOID lpReserved) +{ + switch (ul_reason_for_call) + { + case DLL_PROCESS_ATTACH: + break; + case DLL_THREAD_ATTACH: + break; + case DLL_THREAD_DETACH: + break; + case DLL_PROCESS_DETACH: + break; + } + + return TRUE; +} + +#endif /* def __wince */ diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMhReceive.c b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMhReceive.c new file mode 100644 index 0000000..ee8737f --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMhReceive.c @@ -0,0 +1,364 @@ +/** + * @file IxPiuMhReceive.c + * + * @author Intel Corporation + * @date 18 Jan 2002 + * + * @description Contents are the implementation of the private API for + * the Receive module. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + +/* + * Put the system defined include files required. + */ + + +/* + * Put the user defined include files required. + */ +#include "IxOsal.h" +#include "IxPiuMhMacros_p.h" +#include "IxPiuMhConfig_p.h" +#include "IxPiuMhReceive_p.h" +#include "IxPiuMhSolicitedCbMgr_p.h" +#include "IxPiuMhUnsolicitedCbMgr_p.h" + +/* + * #defines and macros used in this file. + */ + +/* + * Typedefs whose scope is limited to this file. + */ + +/** + * @struct IxPiuMhReceiveStats + * + * @brief This structure is used to maintain statistics for the Receive + * module. + */ + +typedef struct +{ + UINT32 isrs; /**< receive ISR invocations */ + UINT32 receives; /**< receive messages invocations */ + UINT32 messages; /**< messages received */ + UINT32 solicited; /**< solicited messages received */ + UINT32 unsolicited; /**< unsolicited messages received */ + UINT32 callbacks; /**< callbacks invoked */ +} IxPiuMhReceiveStats; + +/* + * Variable declarations global to this file only. Externs are followed by + * static variables. + */ + +PRIVATE IxPiuMhReceiveStats ixPiuMhReceiveStats[IX_PIUMH_NUM_PIUS]; + +/* + * Extern function prototypes. + */ + +/* + * Static function prototypes. + */ +PRIVATE +void ixPiuMhReceiveIsr (int piuId); + +PRIVATE +void ixPiuMhReceiveIsr (int piuId) +{ + int lockKey; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhReceiveIsr\n"); + + lockKey = ixOsalIrqLock (); + + /* invoke the message receive routine to get messages from the PIU */ + ixPiuMhReceiveMessagesReceive (piuId); + + /* update statistical info */ + ixPiuMhReceiveStats[piuId].isrs++; + + ixOsalIrqUnlock (lockKey); + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhReceiveIsr\n"); +} + +/* + * Function definition: ixPiuMhReceiveInitialize + */ + +void ixPiuMhReceiveInitialize (void) +{ + IxPiuMhPiuId piuId = 0; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhReceiveInitialize\n"); + + /* for each PIU ... */ + for (piuId = 0; piuId < IX_PIUMH_NUM_PIUS; piuId++) + { + /* register our internal ISR for the PIU to handle "outFIFO not */ + /* empty" interrupts */ + ixPiuMhConfigIsrRegister (piuId, ixPiuMhReceiveIsr); + } + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhReceiveInitialize\n"); +} + +/* + * Function definition: ixPiuMhReceiveUninitialize + */ +void ixPiuMhReceiveUninitialize (void) +{ + IxPiuMhPiuId piuId; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhReceiveUninitialize\n"); + + /* for each PIU ... */ + for (piuId = 0; piuId < IX_PIUMH_NUM_PIUS; piuId++) + { + /* unregister and set ISR to NULL */ + ixPiuMhConfigIsrUnregister (piuId); + } + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhReceiveUninitialize\n"); + +} + +/* + * Function definition: ixPiuMhReceiveMessagesReceive + */ + +IX_STATUS ixPiuMhReceiveMessagesReceive ( + IxPiuMhPiuId piuId) +{ + IxPiuMhMessage message = { { 0, 0 } }; + IxPiuMhMessageId messageId = 0; + IxPiuMhCallback callback = NULL; + IX_STATUS status; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhReceiveMessagesReceive\n"); + + /* update statistical info */ + ixPiuMhReceiveStats[piuId].receives++; + + /* while the PIU has messages in its outFIFO */ + while (!ixPiuMhConfigOutFifoIsEmpty (piuId)) + { + /* read a message from the PIU's outFIFO */ + status = ixPiuMhConfigOutFifoRead (piuId, &message); + + if (IX_SUCCESS != status) + { + return status; + } + + /* get the ID of the message */ + messageId = ixPiuMhConfigMessageIdGet (message); + + IX_PIUMH_TRACE2 (IX_PIUMH_DEBUG, + "Received message from PIU %d with ID 0x%02X\n", + piuId, messageId); + + /* update statistical info */ + ixPiuMhReceiveStats[piuId].messages++; + + /* try to find a matching unsolicited callback for this message. */ + + /* we assume the message is unsolicited. only if there is no */ + /* unsolicited callback for this message type do we assume the */ + /* message is solicited. it is much faster to check for an */ + /* unsolicited callback, so doing this check first should result */ + /* in better performance. */ + + ixPiuMhUnsolicitedCbMgrCallbackRetrieve ( + piuId, messageId, &callback); + + if (callback != NULL) + { + IX_PIUMH_TRACE0 (IX_PIUMH_DEBUG, + "Found matching unsolicited callback\n"); + + /* update statistical info */ + ixPiuMhReceiveStats[piuId].unsolicited++; + } + + /* if no unsolicited callback was found try to find a matching */ + /* solicited callback for this message */ + if (callback == NULL) + { + ixPiuMhSolicitedCbMgrCallbackRetrieve ( + piuId, messageId, &callback); + + if (callback != NULL) + { + IX_PIUMH_TRACE0 (IX_PIUMH_DEBUG, + "Found matching solicited callback\n"); + + /* update statistical info */ + ixPiuMhReceiveStats[piuId].solicited++; + } + } + + /* if a callback (either unsolicited or solicited) was found */ + if (callback != NULL) + { + /* invoke the callback to pass the message back to the client */ + callback (piuId, message); + + /* update statistical info */ + ixPiuMhReceiveStats[piuId].callbacks++; + } + else /* no callback (neither unsolicited nor solicited) was found */ + { + IX_PIUMH_TRACE2 (IX_PIUMH_WARNING, + "No matching callback for PIU %d" + " and ID 0x%02X, discarding message\n", + piuId, messageId); + + /* the message will be discarded. this is normal behaviour */ + /* if the client passes a NULL solicited callback when */ + /* sending a message. this indicates that the client is not */ + /* interested in receiving the response. alternatively a */ + /* NULL callback here may signify an unsolicited message */ + /* with no appropriate registered callback. */ + } + } + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhReceiveMessagesReceive\n"); + + return IX_SUCCESS; +} + +/* + * Function definition: ixPiuMhReceiveShow + */ + +void ixPiuMhReceiveShow ( + IxPiuMhPiuId piuId) +{ + /* show the ISR invocation counter */ + IX_PIUMH_SHOW ("Receive ISR invocations", + ixPiuMhReceiveStats[piuId].isrs); + + /* show the receive message invocation counter */ + IX_PIUMH_SHOW ("Receive messages invocations", + ixPiuMhReceiveStats[piuId].receives); + + /* show the message received counter */ + IX_PIUMH_SHOW ("Messages received", + ixPiuMhReceiveStats[piuId].messages); + + /* show the solicited message counter */ + IX_PIUMH_SHOW ("Solicited messages received", + ixPiuMhReceiveStats[piuId].solicited); + + /* show the unsolicited message counter */ + IX_PIUMH_SHOW ("Unsolicited messages received", + ixPiuMhReceiveStats[piuId].unsolicited); + + /* show the callback invoked counter */ + IX_PIUMH_SHOW ("Callbacks invoked", + ixPiuMhReceiveStats[piuId].callbacks); + + /* show the message discarded counter */ + IX_PIUMH_SHOW ("Received messages discarded", + (ixPiuMhReceiveStats[piuId].messages - + ixPiuMhReceiveStats[piuId].callbacks)); +} + +/* + * Function definition: ixPiuMhReceiveShowReset + */ + +void ixPiuMhReceiveShowReset ( + IxPiuMhPiuId piuId) +{ + /* reset the ISR invocation counter */ + ixPiuMhReceiveStats[piuId].isrs = 0; + + /* reset the receive message invocation counter */ + ixPiuMhReceiveStats[piuId].receives = 0; + + /* reset the message received counter */ + ixPiuMhReceiveStats[piuId].messages = 0; + + /* reset the solicited message counter */ + ixPiuMhReceiveStats[piuId].solicited = 0; + + /* reset the unsolicited message counter */ + ixPiuMhReceiveStats[piuId].unsolicited = 0; + + /* reset the callback invoked counter */ + ixPiuMhReceiveStats[piuId].callbacks = 0; +} diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMhSend.c b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMhSend.c new file mode 100644 index 0000000..5950352 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMhSend.c @@ -0,0 +1,327 @@ +/** + * @file IxPiuMhSend.c + * + * @author Intel Corporation + * @date 18 Jan 2002 + * + * @description Contents are the implementation of the private API for + * the Send module. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + +/* + * Put the system defined include files required. + */ + + +/* + * Put the user defined include files required. + */ + +#include "IxPiuMhMacros_p.h" + +#include "IxPiuMhConfig_p.h" +#include "IxPiuMhSend_p.h" +#include "IxPiuMhSolicitedCbMgr_p.h" + +/* + * #defines and macros used in this file. + */ + +/** + * @def IX_PIUMH_INFIFO_RETRY_DELAY_US + * + * @brief Amount of time (uSecs) to delay between retries + * while inFIFO is Full when attempting to send a message + */ +#define IX_PIUMH_INFIFO_RETRY_DELAY_US (1) + + +/* + * Typedefs whose scope is limited to this file. + */ + +/** + * @struct IxPiuMhSendStats + * + * @brief This structure is used to maintain statistics for the Send + * module. + */ + +typedef struct +{ + UINT32 sends; /**< send invocations */ + UINT32 sendWithResponses; /**< send with response invocations */ + UINT32 queueFulls; /**< fifo queue full occurrences */ + UINT32 queueFullRetries; /**< fifo queue full retry occurrences */ + UINT32 maxQueueFullRetries; /**< max fifo queue full retries */ + UINT32 callbackFulls; /**< callback list full occurrences */ +} IxPiuMhSendStats; + +/* + * Variable declarations global to this file only. Externs are followed by + * static variables. + */ + +PRIVATE IxPiuMhSendStats ixPiuMhSendStats[IX_PIUMH_NUM_PIUS]; + +/* + * Extern function prototypes. + */ + +/* + * Static function prototypes. + */ +PRIVATE +BOOL ixPiuMhSendInFifoIsFull( + IxPiuMhPiuId piuId, + UINT32 maxSendRetries); + +/* + * Function definition: ixPiuMhSendInFifoIsFull + */ + +PRIVATE +BOOL ixPiuMhSendInFifoIsFull( + IxPiuMhPiuId piuId, + UINT32 maxSendRetries) +{ + BOOL isFull = FALSE; + UINT32 numRetries = 0; + + /* check the PIU's inFIFO */ + isFull = ixPiuMhConfigInFifoIsFull (piuId); + + /* we retry a few times, just to give the PIU a chance to read from */ + /* the FIFO if the FIFO is currently full */ + while (isFull && (numRetries < maxSendRetries)) + { + numRetries++; + if (numRetries >= IX_PIUMH_SEND_RETRIES_DEFAULT) + { + /* Delay here for as short a time as possible (1 us). */ + /* Adding a delay here should ensure we are not hogging */ + /* the AHB bus while we are retrying */ + ixOsalBusySleep (IX_PIUMH_INFIFO_RETRY_DELAY_US); + } + + /* re-check the PIU's inFIFO */ + isFull = ixPiuMhConfigInFifoIsFull (piuId); + + /* update statistical info */ + ixPiuMhSendStats[piuId].queueFullRetries++; + } + + /* record the highest number of retries that occurred */ + if (ixPiuMhSendStats[piuId].maxQueueFullRetries < numRetries) + { + ixPiuMhSendStats[piuId].maxQueueFullRetries = numRetries; + } + + if (isFull) + { + /* update statistical info */ + ixPiuMhSendStats[piuId].queueFulls++; + } + + return isFull; +} + +/* + * Function definition: ixPiuMhSendMessageSend + */ + +IX_STATUS ixPiuMhSendMessageSend ( + IxPiuMhPiuId piuId, + IxPiuMhMessage message, + UINT32 maxSendRetries) +{ + IX_STATUS status; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhSendMessageSend\n"); + + /* update statistical info */ + ixPiuMhSendStats[piuId].sends++; + + /* check if the PIU's inFIFO is full - if so return an error */ + if (ixPiuMhSendInFifoIsFull (piuId, maxSendRetries)) + { + IX_PIUMH_TRACE0 (IX_PIUMH_WARNING, "PIU's inFIFO is full\n"); + return IX_FAIL; + } + + /* write the message to the PIU's inFIFO */ + status = ixPiuMhConfigInFifoWrite (piuId, message); + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhSendMessageSend\n"); + + return status; +} + +/* + * Function definition: ixPiuMhSendMessageWithResponseSend + */ + +IX_STATUS ixPiuMhSendMessageWithResponseSend ( + IxPiuMhPiuId piuId, + IxPiuMhMessage message, + IxPiuMhMessageId solicitedMessageId, + IxPiuMhCallback solicitedCallback, + UINT32 maxSendRetries) +{ + IX_STATUS status = IX_SUCCESS; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhSendMessageWithResponseSend\n"); + + /* update statistical info */ + ixPiuMhSendStats[piuId].sendWithResponses++; + + /* check if the PIU's inFIFO is full - if so return an error */ + if (ixPiuMhSendInFifoIsFull (piuId, maxSendRetries)) + { + IX_PIUMH_TRACE0 (IX_PIUMH_WARNING, "PIU's inFIFO is full\n"); + return IX_FAIL; + } + + /* save the solicited callback */ + status = ixPiuMhSolicitedCbMgrCallbackSave ( + piuId, solicitedMessageId, solicitedCallback); + if (status != IX_SUCCESS) + { + IX_PIUMH_ERROR_REPORT ("Failed to save solicited callback\n"); + + /* update statistical info */ + ixPiuMhSendStats[piuId].callbackFulls++; + + return status; + } + + /* write the message to the PIU's inFIFO */ + status = ixPiuMhConfigInFifoWrite (piuId, message); + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhSendMessageWithResponseSend\n"); + + return status; +} + +/* + * Function definition: ixPiuMhSendShow + */ + +void ixPiuMhSendShow ( + IxPiuMhPiuId piuId) +{ + /* show the message send invocation counter */ + IX_PIUMH_SHOW ("Send invocations", + ixPiuMhSendStats[piuId].sends); + + /* show the message send with response invocation counter */ + IX_PIUMH_SHOW ("Send with response invocations", + ixPiuMhSendStats[piuId].sendWithResponses); + + /* show the fifo queue full occurrence counter */ + IX_PIUMH_SHOW ("Fifo queue full occurrences", + ixPiuMhSendStats[piuId].queueFulls); + + /* show the fifo queue full retry occurrence counter */ + IX_PIUMH_SHOW ("Fifo queue full retry occurrences", + ixPiuMhSendStats[piuId].queueFullRetries); + + /* show the fifo queue full maximum retries counter */ + IX_PIUMH_SHOW ("Maximum fifo queue full retries", + ixPiuMhSendStats[piuId].maxQueueFullRetries); + + /* show the callback list full occurrence counter */ + IX_PIUMH_SHOW ("Solicited callback list full occurrences", + ixPiuMhSendStats[piuId].callbackFulls); +} + +/* + * Function definition: ixPiuMhSendShowReset + */ + +void ixPiuMhSendShowReset ( + IxPiuMhPiuId piuId) +{ + /* reset the message send invocation counter */ + ixPiuMhSendStats[piuId].sends = 0; + + /* reset the message send with response invocation counter */ + ixPiuMhSendStats[piuId].sendWithResponses = 0; + + /* reset the fifo queue full occurrence counter */ + ixPiuMhSendStats[piuId].queueFulls = 0; + + /* reset the fifo queue full retry occurrence counter */ + ixPiuMhSendStats[piuId].queueFullRetries = 0; + + /* reset the max fifo queue full retries counter */ + ixPiuMhSendStats[piuId].maxQueueFullRetries = 0; + + /* reset the callback list full occurrence counter */ + ixPiuMhSendStats[piuId].callbackFulls = 0; +} diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMhSolicitedCbMgr.c b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMhSolicitedCbMgr.c new file mode 100644 index 0000000..c8e8fb1 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMhSolicitedCbMgr.c @@ -0,0 +1,436 @@ +/** + * @file IxPiuMhSolicitedCbMgr.c + * + * @author Intel Corporation + * @date 18 Jan 2002 + * + * @description Contents are the implementation of the private API for + * the Solicited Callback Manager module. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ +#ifndef IXPIUMHCONFIG_P_H +# define IXPIUMHSOLICITEDCBMGR_C +#else +# error "Error, IxPiuMhConfig_p.h should not be included before this defn." +#endif + +/* + * Put the system defined include files required. + */ + + +/* + * Put the user defined include files required. + */ + +#include "IxOsal.h" + +#include "IxPiuMhMacros_p.h" +#include "IxPiuMhSolicitedCbMgr_p.h" +#include "IxPiuMhConfig_p.h" +/* + * #defines and macros used in this file. + */ + +/* + * Typedefs whose scope is limited to this file. + */ + +/** + * @struct IxPiuMhSolicitedCallbackListEntry + * + * @brief This structure is used to store the information associated with + * an entry in the callback list. This consists of the ID of the send + * message (which indicates the ID of the corresponding response message) + * and the callback function pointer itself. + * + */ +typedef struct IxPiuMhSolicitedCallbackListEntry +{ + /** message ID */ + IxPiuMhMessageId messageId; + + /** callback function pointer */ + IxPiuMhCallback callback; + + /** pointer to next entry in the list */ + struct IxPiuMhSolicitedCallbackListEntry *next; +} IxPiuMhSolicitedCallbackListEntry; + +/** + * @struct IxPiuMhSolicitedCallbackList + * + * @brief This structure is used to maintain the list of response + * callbacks. The number of entries in this list will be variable, and + * they will be stored in a linked list fashion for ease of addition and + * removal. The entries themselves are statically allocated, and are + * organised into a "free" list and a "callback" list. Adding an entry + * means taking an entry from the "free" list and adding it to the + * "callback" list. Removing an entry means removing it from the + * "callback" list and returning it to the "free" list. + */ + +typedef struct +{ + /** pointer to the head of the free list */ + IxPiuMhSolicitedCallbackListEntry *freeHead; + + /** pointer to the head of the callback list */ + IxPiuMhSolicitedCallbackListEntry *callbackHead; + + /** pointer to the tail of the callback list */ + IxPiuMhSolicitedCallbackListEntry *callbackTail; + + /** array of entries - the first entry is used as a dummy entry to */ + /* avoid the scenario of having an empty list, hence '+ 1' */ + IxPiuMhSolicitedCallbackListEntry entries[IX_PIUMH_MAX_CALLBACKS + 1]; +} IxPiuMhSolicitedCallbackList; + +/** + * @struct IxPiuMhSolicitedCbMgrStats + * + * @brief This structure is used to maintain statistics for the Solicited + * Callback Manager module. + */ + +typedef struct +{ + UINT32 saves; /**< callback list saves */ + UINT32 retrieves; /**< callback list retrieves */ +} IxPiuMhSolicitedCbMgrStats; + +/* + * Variable declarations global to this file only. Externs are followed by + * static variables. + */ + +PRIVATE IxPiuMhSolicitedCallbackList +ixPiuMhSolicitedCbMgrCallbackLists[IX_PIUMH_NUM_PIUS]; + +PRIVATE IxPiuMhSolicitedCbMgrStats +ixPiuMhSolicitedCbMgrStats[IX_PIUMH_NUM_PIUS]; + +/* + * Extern function prototypes. + */ + +/* + * Static function prototypes. + */ + +/* + * Function definition: ixPiuMhSolicitedCbMgrInitialize + */ + +void ixPiuMhSolicitedCbMgrInitialize (void) +{ + IxPiuMhPiuId piuId; + UINT32 localIndex; + IxPiuMhSolicitedCallbackList *list = NULL; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhSolicitedCbMgrInitialize\n"); + + /* for each PIU ... */ + for (piuId = 0; piuId < IX_PIUMH_NUM_PIUS; piuId++) + { + /* initialise a pointer to the list for convenience */ + list = &ixPiuMhSolicitedCbMgrCallbackLists[piuId]; + + /* for each entry in the list, after the dummy entry ... */ + for (localIndex = 1; localIndex <= IX_PIUMH_MAX_CALLBACKS; localIndex++) + { + /* initialise the entry */ + list->entries[localIndex].messageId = 0x00; + list->entries[localIndex].callback = NULL; + + /* if this entry is before the last entry */ + if (localIndex < IX_PIUMH_MAX_CALLBACKS) + { + /* chain this entry to the following entry */ + list->entries[localIndex].next = + &(list->entries[localIndex + 1]); + } + else /* this entry is the last entry */ + { + /* the last entry isn't chained to anything */ + list->entries[localIndex].next = NULL; + } + } + + /* set the free list pointer to point to the first real entry */ + /* (all real entries begin chained together on the free list) */ + list->freeHead = &(list->entries[1]); + + /* set the callback list pointers to point to the dummy entry */ + /* (the callback list is initially empty) */ + list->callbackHead = &(list->entries[0]); + list->callbackTail = &(list->entries[0]); + } + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhSolicitedCbMgrInitialize\n"); +} + +/* + * Function definition: ixPiuMhSolicitedCbMgrUninitialize + */ +void ixPiuMhSolicitedCbMgrUninitialize (void) +{ + IxPiuMhPiuId piuId; + UINT32 localIndex; + IxPiuMhSolicitedCallbackList *list; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhSolicitedCbMgrUninitialize\n"); + + /* for each PIU ... */ + for (piuId = 0; piuId < IX_PIUMH_NUM_PIUS; piuId++) + { + /* initialise a pointer to the list for convenience */ + list = &ixPiuMhSolicitedCbMgrCallbackLists[piuId]; + + /* for each entry in the list, after the dummy entry ... */ + for (localIndex = 1; localIndex <= IX_PIUMH_MAX_CALLBACKS; localIndex++) + { + /* initialise the entry */ + list->entries[localIndex].messageId = 0x00; + list->entries[localIndex].callback = NULL; + + /* if this entry is before the last entry */ + if (IX_PIUMH_MAX_CALLBACKS > localIndex) + { + /* chain this entry to the following entry */ + list->entries[localIndex].next = + &(list->entries[localIndex + 1]); + } + else /* this entry is the last entry */ + { + /* the last entry isn't chained to anything */ + list->entries[localIndex].next = NULL; + } + } + /* set the free list pointer to point to the first real entry */ + /* (all real entries begin chained together on the free list) */ + list->freeHead = &(list->entries[1]); + + /* set the callback list pointers to point to the dummy entry */ + /* (the callback list is initially empty) */ + list->callbackHead = &(list->entries[0]); + list->callbackTail = &(list->entries[0]); + } + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhSolicitedCbMgrUninitialize\n"); + +} + +/* + * Function definition: ixPiuMhSolicitedCbMgrCallbackSave + */ + +IX_STATUS ixPiuMhSolicitedCbMgrCallbackSave ( + IxPiuMhPiuId piuId, + IxPiuMhMessageId solicitedMessageId, + IxPiuMhCallback solicitedCallback) +{ + IxPiuMhSolicitedCallbackList *list = NULL; + IxPiuMhSolicitedCallbackListEntry *callbackEntry = NULL; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhSolicitedCbMgrCallbackSave\n"); + + /* initialise a pointer to the list for convenience */ + list = &ixPiuMhSolicitedCbMgrCallbackLists[piuId]; + + /* check to see if there are any entries in the free list */ + if (list->freeHead == NULL) + { + IX_PIUMH_ERROR_REPORT ("Solicited callback list is full\n"); + return IX_FAIL; + } + + /* there is an entry in the free list we can use */ + + /* update statistical info */ + ixPiuMhSolicitedCbMgrStats[piuId].saves++; + + /* remove a callback entry from the start of the free list */ + callbackEntry = list->freeHead; + list->freeHead = callbackEntry->next; + + /* fill in the callback entry with the new data */ + callbackEntry->messageId = solicitedMessageId; + callbackEntry->callback = solicitedCallback; + + /* the new callback entry will be added to the tail of the callback */ + /* list, so it isn't chained to anything */ + callbackEntry->next = NULL; + + /* chain new callback entry to the last entry of the callback list */ + list->callbackTail->next = callbackEntry; + list->callbackTail = callbackEntry; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhSolicitedCbMgrCallbackSave\n"); + + return IX_SUCCESS; +} + +/* + * Function definition: ixPiuMhSolicitedCbMgrCallbackRetrieve + */ + +void ixPiuMhSolicitedCbMgrCallbackRetrieve ( + IxPiuMhPiuId piuId, + IxPiuMhMessageId solicitedMessageId, + IxPiuMhCallback *solicitedCallback) +{ + IxPiuMhSolicitedCallbackList *list = NULL; + IxPiuMhSolicitedCallbackListEntry *callbackEntry = NULL; + IxPiuMhSolicitedCallbackListEntry *previousEntry = NULL; + + /* initialise a pointer to the list for convenience */ + list = &ixPiuMhSolicitedCbMgrCallbackLists[piuId]; + + /* initialise the callback entry to the first entry of the callback */ + /* list - we must skip over the dummy entry, which is the previous */ + if (list != NULL) + { + callbackEntry = list->callbackHead->next; + previousEntry = list->callbackHead; + } + + /* traverse the callback list looking for an entry with a matching */ + /* message ID. note we also save the previous entry's pointer to */ + /* allow us to unchain the matching entry from the callback list */ + while ((callbackEntry != NULL) && + (callbackEntry->messageId != solicitedMessageId)) + { + previousEntry = callbackEntry; + callbackEntry = callbackEntry->next; + } + + /* if we didn't find a matching callback entry */ + if (callbackEntry == NULL) + { + /* return a NULL callback in the outgoing parameter */ + *solicitedCallback = NULL; + } + else /* we found a matching callback entry */ + { + /* update statistical info */ + ixPiuMhSolicitedCbMgrStats[piuId].retrieves++; + + /* return the callback in the outgoing parameter */ + *solicitedCallback = callbackEntry->callback; + + /* unchain callback entry by chaining previous entry to next */ + previousEntry->next = callbackEntry->next; + + /* if the callback entry is at the tail of the list */ + if (list->callbackTail == callbackEntry) + { + /* update the tail of the callback list */ + list->callbackTail = previousEntry; + } + + /* re-initialise the callback entry */ + callbackEntry->messageId = 0x00; + callbackEntry->callback = NULL; + + /* add the callback entry to the start of the free list */ + callbackEntry->next = list->freeHead; + list->freeHead = callbackEntry; + } +} + +/* + * Function definition: ixPiuMhSolicitedCbMgrShow + */ + +void ixPiuMhSolicitedCbMgrShow ( + IxPiuMhPiuId piuId) +{ + /* show the solicited callback list save counter */ + IX_PIUMH_SHOW ("Solicited callback list saves", + ixPiuMhSolicitedCbMgrStats[piuId].saves); + + /* show the solicited callback list retrieve counter */ + IX_PIUMH_SHOW ("Solicited callback list retrieves", + ixPiuMhSolicitedCbMgrStats[piuId].retrieves); +} + +/* + * Function definition: ixPiuMhSolicitedCbMgrShowReset + */ + +void ixPiuMhSolicitedCbMgrShowReset ( + IxPiuMhPiuId piuId) +{ + /* reset the solicited callback list save counter */ + ixPiuMhSolicitedCbMgrStats[piuId].saves = 0; + + /* reset the solicited callback list retrieve counter */ + ixPiuMhSolicitedCbMgrStats[piuId].retrieves = 0; +} diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMhSymbols.c b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMhSymbols.c new file mode 100644 index 0000000..e80f806 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMhSymbols.c @@ -0,0 +1,110 @@ +/* + * @file IxPiuMhSymbols.c + * + * @author Intel Corporation + * @date 04-Oct-2002 + * + * @brief Contents are declarations for exported symbols for linux kernel + * module builds. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +#ifdef __linux + +#include <linux/module.h> +#include <IxPiuMh.h> + +EXPORT_SYMBOL(ixPiuMhPhysicalAddressSet); + +EXPORT_SYMBOL(ixPiuMhInitialize); +EXPORT_SYMBOL(ixPiuMhUnload); +EXPORT_SYMBOL(ixPiuMhUnsolicitedCallbackRegister); +EXPORT_SYMBOL(ixPiuMhUnsolicitedCallbackForRangeRegister); +EXPORT_SYMBOL(ixPiuMhMessageSend); +EXPORT_SYMBOL(ixPiuMhMessageWithResponseSend); +EXPORT_SYMBOL(ixPiuMhMessagesReceive); +EXPORT_SYMBOL(ixPiuMhShow); +EXPORT_SYMBOL(ixPiuMhShowReset); +EXPORT_SYMBOL(ixPiuMhInterruptIdSet); + +extern void ixPiuMhIsr (void *parameter); +extern BOOL ixPiuMhConfigInFifoIsFull(IxPiuMhPiuId piuId); +extern BOOL ixPiuMhConfigOutFifoIsEmpty (IxPiuMhPiuId piuId); +extern void ixPiuMhConfigLockRelease (IxPiuMhPiuId piuId); +extern void ixPiuMhConfigLockGet (IxPiuMhPiuId piuId); +extern void ixPiuMhConfigOutFifoRead (IxPiuMhPiuId piuId, + IxPiuMhMessage *message); +extern void ixPiuMhConfigInFifoWrite (IxPiuMhPiuId piuId, + IxPiuMhMessage message); + + +EXPORT_SYMBOL(ixPiuMhIsr); +EXPORT_SYMBOL(ixPiuMhConfigInFifoIsFull); +EXPORT_SYMBOL(ixPiuMhConfigOutFifoIsEmpty); +EXPORT_SYMBOL(ixPiuMhConfigLockRelease); +EXPORT_SYMBOL(ixPiuMhConfigLockGet); +EXPORT_SYMBOL(ixPiuMhConfigOutFifoRead); +EXPORT_SYMBOL(ixPiuMhConfigInFifoWrite); + + +#endif /* __linux */ diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMhUnsolicitedCbMgr.c b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMhUnsolicitedCbMgr.c new file mode 100644 index 0000000..468b5e5 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMhUnsolicitedCbMgr.c @@ -0,0 +1,301 @@ +/** + * @file IxPiuMhUnsolicitedCbMgr.c + * + * @author Intel Corporation + * @date 18 Jan 2002 + * + * @description Contents are the implementation of the private API for + * the Unsolicited Callback Manager module. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + +/* + * Put the system defined include files required. + */ + + +/* + * Put the user defined include files required. + */ +#include "IxOsal.h" + +#include "IxPiuMhMacros_p.h" + +#include "IxPiuMhUnsolicitedCbMgr_p.h" + + +/* + * #defines and macros used in this file. + */ + +/* + * Typedefs whose scope is limited to this file. + */ + +/** + * @struct IxPiuMhUnsolicitedCallbackTable + * + * @brief This structure is used to maintain the list of registered + * callbacks. One entry exists for each message ID, and a NULL entry will + * signify that no callback has been registered for that ID. + */ + +typedef struct +{ + /** array of entries */ + IxPiuMhCallback entries[IX_PIUMH_MAX_MESSAGE_ID + 1]; +} IxPiuMhUnsolicitedCallbackTable; + +/** + * @struct IxPiuMhUnsolicitedCbMgrStats + * + * @brief This structure is used to maintain statistics for the Unsolicited + * Callback Manager module. + */ + +typedef struct +{ + UINT32 saves; /**< callback table saves */ + UINT32 overwrites; /**< callback table overwrites */ +} IxPiuMhUnsolicitedCbMgrStats; + +/* + * Variable declarations global to this file only. Externs are followed by + * static variables. + */ + +PRIVATE IxPiuMhUnsolicitedCallbackTable +ixPiuMhUnsolicitedCallbackTables[IX_PIUMH_NUM_PIUS]; + +PRIVATE IxPiuMhUnsolicitedCbMgrStats +ixPiuMhUnsolicitedCbMgrStats[IX_PIUMH_NUM_PIUS]; + +/* + * Extern function prototypes. + */ + +/* + * Static function prototypes. + */ + +/* + * Function definition: ixPiuMhUnsolicitedCbMgrInitialize + */ + +void ixPiuMhUnsolicitedCbMgrInitialize (void) +{ + IxPiuMhPiuId piuId = 0; + IxPiuMhUnsolicitedCallbackTable *table = NULL; + IxPiuMhMessageId messageId = 0; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhUnsolicitedCbMgrInitialize\n"); + + /* for each PIU ... */ + for (piuId = 0; piuId < IX_PIUMH_NUM_PIUS; piuId++) + { + /* initialise a pointer to the table for convenience */ + table = &ixPiuMhUnsolicitedCallbackTables[piuId]; + + /* for each message ID ... */ + for (messageId = IX_PIUMH_MIN_MESSAGE_ID; + messageId <= IX_PIUMH_MAX_MESSAGE_ID; messageId++) + { + /* initialise the callback for this message ID to NULL */ + table->entries[messageId] = NULL; + } + } + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhUnsolicitedCbMgrInitialize\n"); +} + +/* + * Function definition: ixPiuMhUnsolicitedCbMgrCallbackSave + */ +void ixPiuMhUnsolicitedCbMgrUninitialize (void) +{ + IxPiuMhPiuId piuId; + IxPiuMhUnsolicitedCallbackTable *table; + IxPiuMhMessageId messageId; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhUnsolicitedCbMgrUninitialize\n"); + + /* for each PIU ... */ + for (piuId = 0; piuId < IX_PIUMH_NUM_PIUS; piuId++) + { + /* initialise a pointer to the table for convenience */ + table = &ixPiuMhUnsolicitedCallbackTables[piuId]; + + /* for each message ID ... */ + for (messageId = IX_PIUMH_MIN_MESSAGE_ID; + messageId <= IX_PIUMH_MAX_MESSAGE_ID; messageId++) + { + /* initialise the callback for this message ID to NULL */ + table->entries[messageId] = NULL; + } + } + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhUnsolicitedCbMgrUninitialize\n"); +} + +/* + * Function definition: ixPiuMhUnsolicitedCbMgrCallbackSave + */ + +void ixPiuMhUnsolicitedCbMgrCallbackSave ( + IxPiuMhPiuId piuId, + IxPiuMhMessageId unsolicitedMessageId, + IxPiuMhCallback unsolicitedCallback) +{ + IxPiuMhUnsolicitedCallbackTable *table = NULL; + + /* initialise a pointer to the table for convenience */ + table = &ixPiuMhUnsolicitedCallbackTables[piuId]; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhUnsolicitedCbMgrCallbackSave\n"); + + /* update statistical info */ + ixPiuMhUnsolicitedCbMgrStats[piuId].saves++; + + /* check if there is a callback already registered for this PIU and */ + /* message ID */ + if (table->entries[unsolicitedMessageId] != NULL) + { + /* if we are overwriting an existing callback */ + if (unsolicitedCallback != NULL) + { + IX_PIUMH_TRACE2 (IX_PIUMH_DEBUG, "Unsolicited callback " + "overwriting existing callback for PIU ID %d " + "message ID 0x%02X\n", piuId, unsolicitedMessageId); + } + else /* if we are clearing an existing callback */ + { + IX_PIUMH_TRACE2 (IX_PIUMH_DEBUG, "NULL unsolicited callback " + "clearing existing callback for PIU ID %d " + "message ID 0x%02X\n", piuId, unsolicitedMessageId); + } + + /* update statistical info */ + ixPiuMhUnsolicitedCbMgrStats[piuId].overwrites++; + } + + /* save the callback into the table */ + table->entries[unsolicitedMessageId] = unsolicitedCallback; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhUnsolicitedCbMgrCallbackSave\n"); +} + +/* + * Function definition: ixPiuMhUnsolicitedCbMgrCallbackRetrieve + */ + +void ixPiuMhUnsolicitedCbMgrCallbackRetrieve ( + IxPiuMhPiuId piuId, + IxPiuMhMessageId unsolicitedMessageId, + IxPiuMhCallback *unsolicitedCallback) +{ + IxPiuMhUnsolicitedCallbackTable *table = NULL; + + /* initialise a pointer to the table for convenience */ + table = &ixPiuMhUnsolicitedCallbackTables[piuId]; + + /* retrieve the callback from the table */ + if (unsolicitedCallback != NULL) + { + *unsolicitedCallback = table->entries[unsolicitedMessageId]; + } +} + +/* + * Function definition: ixPiuMhUnsolicitedCbMgrShow + */ + +void ixPiuMhUnsolicitedCbMgrShow ( + IxPiuMhPiuId piuId) +{ + /* show the unsolicited callback table save counter */ + IX_PIUMH_SHOW ("Unsolicited callback table saves", + ixPiuMhUnsolicitedCbMgrStats[piuId].saves); + + /* show the unsolicited callback table overwrite counter */ + IX_PIUMH_SHOW ("Unsolicited callback table overwrites", + ixPiuMhUnsolicitedCbMgrStats[piuId].overwrites); +} + +/* + * Function definition: ixPiuMhUnsolicitedCbMgrShowReset + */ + +void ixPiuMhUnsolicitedCbMgrShowReset ( + IxPiuMhPiuId piuId) +{ + /* reset the unsolicited callback table save counter */ + ixPiuMhUnsolicitedCbMgrStats[piuId].saves = 0; + + /* reset the unsolicited callback table overwrite counter */ + ixPiuMhUnsolicitedCbMgrStats[piuId].overwrites = 0; +} diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/Makefile b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/Makefile new file mode 100644 index 0000000..3d4fcf1 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/Makefile @@ -0,0 +1,144 @@ +######################################################################### +# This Template Makefile will create the libraries, executables and module and place them in the output folder +# Remove the comments around the sections you wish to build for. +# +#Procedure +#1) Copy this template to the location of your source files +#2) "Common variables and defintions" must be filled out +#3) Edit as desired the "Libraries and executable section" and/or the "Linux kernel 2.6 Module section" depending on what you wish to build +#4) Remove the comments around the section and delete the other unnecessary section +#5) Save changes, return to command line and type "make". +# +# +# Targets supported +# all - builds everything and installs +# install - identical to all +# depend - build dependencies +# clean - clears all derived objects +# +# included makefiles +# common.mk - common defintions +# depend.mk - depend and cleandepend rules +# rules.mk - build rules. +# +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# Contact Information: +# Intel Corporation +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# +############################################################################ + +# Ensure The ICP_ENV_DIR environmental var is defined. +ifndef ICP_ENV_DIR +$(error ICP_ENV_DIR is undefined. Please set the path to your environment makefile \ + "-> setenv ICP_ENV_DIR <path>") +endif + +# Ensure The ICP_BUILDSYSTEM_PATH envorionmental var is defined. +ifndef ICP_BUILDSYSTEM_PATH +$(error ICP_BUILDSYSTEM_PATH is undefined. Please set the path to the top of the build structure \ + "-> setenv ICP_BUILDSYSTEM_PATH <path>") +endif + +#Add your project environment Makefile, extra comment +include $(ICP_ENV_DIR)/environment.mk + +#include the makefile with all the default and common Make variable definitions +include $(ICP_BUILDSYSTEM_PATH)/build_files/common.mk + +#Add the name for the executable, Library or Module output definitions +OUTPUT_NAME=$(ICP_TDM_MSG_HDLR_NAME) + +# List of Source Files to be compiled (to be in a single line or on different lines separated by a "\" and tab. +SOURCES= IxPiuMh.c \ + IxPiuMhConfig.c \ + IxPiuMhSend.c \ + IxPiuMhSolicitedCbMgr.c \ + IxPiuMhReceive.c \ + IxPiuMhDll.c \ + IxPiuMhUnsolicitedCbMgr.c + + +# Setup include directory +INCLUDES += -I $(src)/include \ + -I $(PWD)/include \ + -I $(ICP_API_DIR) \ + -I $(ICP_API_DIR)/accel_infra \ + -I $(ICP_COMP_PATH)/include \ + -I $(ICP_OSAL_DIR)/common/include \ + +ifeq ($(ICP_INTEL_DEV),YES) +INCLUDES += -I $(ICP_OSAL_DIR)/common/include/modules \ + -I $(ICP_OSAL_DIR)/common/include/modules/ddk \ + -I $(ICP_OSAL_DIR)/common/include/modules/bufferMgt \ + -I $(ICP_OSAL_DIR)/common/include/modules/ioMem +endif + +EXTRA_CFLAGS += -DENABLE_IOMEM -DENABLE_BUFFERMGT + + +#include your $(ICP_OS)_$(ICP_OS_LEVEL).mk file +include $(ICP_TDM_MSG_HDLR_DIR)/$(ICP_OS)_$(ICP_OS_LEVEL).mk + +# Install the module to the output dir +install: module + + +###################Include rules and dependency makefiles######################## +include $(ICP_BUILDSYSTEM_PATH)/build_files/rules.mk +###################End of Rules and dependency inclusion######################### + diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/include/IxPiuMhConfig_p.h b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/include/IxPiuMhConfig_p.h new file mode 100644 index 0000000..e4b2482 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/include/IxPiuMhConfig_p.h @@ -0,0 +1,686 @@ +/** + * @file IxPiuMhConfig_p.h + * + * @author Intel Corporation + * @date 18 Jan 2002 + * + * @brief This file contains the private API for the Configuration module. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + +/** + * @defgroup IxPiuMhConfig_p IxPiuMhConfig_p + * + * @brief The private API for the Configuration module. + * + * @{ + */ + +#ifndef IXPIUMHCONFIG_P_H +#define IXPIUMHCONFIG_P_H + +#include "IxOsal.h" + +#include "IxPiuMh.h" +#include "IxPiuMhMacros_p.h" + +/* + * inline definition + */ +/* enable function inlining for performances */ +#ifdef IXPIUMHSOLICITEDCBMGR_C +/* Non-inline functions will be defined in this translation unit. + Reason is that in GNU Compiler, if the Optimization is turn off, all extern inline + functions will not be compiled. +*/ +# ifndef __wince +# ifndef IXPIUMHCONFIG_INLINE +# define IXPIUMHCONFIG_INLINE +# endif +# else +# ifndef IXPIUMHCONFIG_INLINE +# define IXPIUMHCONFIG_INLINE IX_OSAL_INLINE_EXTERN +# endif +# endif /* __wince*/ + +#else + +# ifndef IXPIUMHCONFIG_INLINE +# ifdef _DIAB_TOOL + /* DIAB does not allow both the funtion prototype and + * defintion to use extern + */ +# define IXPIUMHCONFIG_INLINE IX_OSAL_INLINE +# else +# define IXPIUMHCONFIG_INLINE IX_OSAL_INLINE_EXTERN +# endif +# endif /* IXPIUMHCONFIG_INLINE */ +#endif /* IXPIUMHSOLICITEDCBMGR_C */ +/* + * Typedefs and #defines, etc. + */ + +typedef void (*IxPiuMhConfigIsr) (int); /**< ISR function pointer */ + +/** + * @struct IxPiuMhConfigPiuInfo + * + * @brief This structure is used to maintain the configuration information + * associated with an PIU. + */ + +typedef struct +{ + IxOsalMutex mutex; /**< mutex */ + UINT32 interruptId; /**< interrupt ID */ +#if defined(__ep805xx) + UINT32 physicalRegisterBase;/**< register physical base address */ +#endif + UINT32 virtualRegisterBase; /**< register virtual base address */ + UINT32 statusRegister; /**< status register virtual address */ + UINT32 controlRegister; /**< control register virtual address */ + UINT32 inFifoRegister; /**< inFIFO register virutal address */ + UINT32 outFifoRegister; /**< outFIFO register virtual address */ + IxPiuMhConfigIsr isr; /**< isr routine for handling interrupt */ + BOOL oldInterruptState; /**< old interrupt state (TRUE => enabled) */ +} IxPiuMhConfigPiuInfo; + + +/* + * #defines for function return types, etc. + */ + +#define IX_PIUMH_PIUSTAT_OFFSET (0x002C) /**< PIU status register offset */ +#define IX_PIUMH_PIUCTL_OFFSET (0x0030) /**< PIU control register offset */ +#define IX_PIUMH_PIUFIFO_OFFSET (0x0038) /**< PIU FIFO register offset */ + +/* PIU control register bit definitions */ +#define IX_PIUMH_PIU_CTL_OFE (1 << 16) /**< OutFifoEnable */ +#define IX_PIUMH_PIU_CTL_IFE (1 << 17) /**< InFifoEnable */ +#define IX_PIUMH_PIU_CTL_OFEWE (1 << 24) /**< OutFifoEnableWriteEnable */ +#define IX_PIUMH_PIU_CTL_IFEWE (1 << 25) /**< InFifoEnableWriteEnable */ + +/* PIU status register bit definitions */ +#define IX_PIUMH_PIU_STAT_OFNE (1 << 16) /**< OutFifoNotEmpty */ +#define IX_PIUMH_PIU_STAT_IFNF (1 << 17) /**< InFifoNotFull */ +#define IX_PIUMH_PIU_STAT_OFNF (1 << 18) /**< OutFifoNotFull */ +#define IX_PIUMH_PIU_STAT_IFNE (1 << 19) /**< InFifoNotEmpty */ +#define IX_PIUMH_PIU_STAT_MBINT (1 << 20) /**< Mailbox interrupt */ +#define IX_PIUMH_PIU_STAT_IFINT (1 << 21) /**< InFifo interrupt */ +#define IX_PIUMH_PIU_STAT_OFINT (1 << 22) /**< OutFifo interrupt */ +#define IX_PIUMH_PIU_STAT_WFINT (1 << 23) /**< WatchFifo interrupt */ + +/* message offsets */ +#define IX_PIUMH_MESSAGE_ID_OFFSET (24) + +/* Hardware defs for IXP23XX */ +#if defined(__ixp23xx) +#include <asm/hardware.h> +#include <asm/arch/irqs.h> + +/* PIU-0 interrupt */ +#define IX_PIU_IRQ_DBG0 (IRQ_IXP23XX_DBG0) + +/* PIU-1 interrupt */ +#define IX_PIU_IRQ_DBG1 (IRQ_IXP23XX_DBG1) + +/* PIU-0 Base Physical Address */ +#define IX_PIU_PIU0_PHYS (IXP23XX_PIU0_PHYS) + +/* PIU-1 Base Physical Address */ +#define IX_PIU_PIU1_PHYS (IXP23XX_PIU1_PHYS) + + +#endif /* #if DEVICE == ixp23xx */ + +#if defined(__ixp42X) || defined(__ixp46X) || defined(__ixp5XX) + +/**< PIU register base address */ +#define IX_PIUMH_PIU_BASE (IX_OSAL_IXP400_PERIPHERAL_PHYS_BASE) + +#define IX_PIUMH_PIUA_OFFSET (0x6000) /**< PIU-A register base offset */ +#define IX_PIUMH_PIUB_OFFSET (0x7000) /**< PIU-B register base offset */ +#if defined(__ixp42X) || defined(__ixp46X) && !defined(__ixp5XX) +#define IX_PIUMH_PIUC_OFFSET (0x8000) /**< PIU-C register base offset */ +#endif + +/** PIU-A register base address */ +#define IX_PIUMH_PIUA_BASE (IX_PIUMH_PIU_BASE + IX_PIUMH_PIUA_OFFSET) +/** PIU-B register base address */ +#define IX_PIUMH_PIUB_BASE (IX_PIUMH_PIU_BASE + IX_PIUMH_PIUB_OFFSET) +#if defined(__ixp42X) || defined(__ixp46X) && !defined(__ixp5XX) +/** PIU-C register base address */ +#define IX_PIUMH_PIUC_BASE (IX_PIUMH_PIU_BASE + IX_PIUMH_PIUC_OFFSET) +#endif + +/* PIU-A configuration */ + +/** PIU-A interrupt */ +#define IX_PIUMH_PIUA_INT (IX_OSAL_IXP400_PIUA_IRQ_LVL) +/** PIU-A FIFO register */ +#define IX_PIUMH_PIUA_FIFO (IX_PIUMH_PIUA_BASE + IX_PIUMH_PIUFIFO_OFFSET) +/** PIU-A control register */ +#define IX_PIUMH_PIUA_CTL (IX_PIUMH_PIUA_BASE + IX_PIUMH_PIUCTL_OFFSET) +/** PIU-A status register */ +#define IX_PIUMH_PIUA_STAT (IX_PIUMH_PIUA_BASE + IX_PIUMH_PIUSTAT_OFFSET) + +/* PIU-B configuration */ + +/** PIU-B interrupt */ +#define IX_PIUMH_PIUB_INT (IX_OSAL_IXP400_PIUB_IRQ_LVL) +/** PIU-B FIFO register */ +#define IX_PIUMH_PIUB_FIFO (IX_PIUMH_PIUB_BASE + IX_PIUMH_PIUFIFO_OFFSET) +/** PIU-B control register */ +#define IX_PIUMH_PIUB_CTL (IX_PIUMH_PIUB_BASE + IX_PIUMH_PIUCTL_OFFSET) +/** PIU-B status register */ +#define IX_PIUMH_PIUB_STAT (IX_PIUMH_PIUB_BASE + IX_PIUMH_PIUSTAT_OFFSET) + +#if defined(__ixp42X) || defined(__ixp46X) && !defined(__ixp5XX) +/* PIU-C configuration */ + +/** PIU-C interrupt */ +#define IX_PIUMH_PIUC_INT (IX_OSAL_IXP400_PIUC_IRQ_LVL) +/** PIU-C FIFO register */ +#define IX_PIUMH_PIUC_FIFO (IX_PIUMH_PIUC_BASE + IX_PIUMH_PIUFIFO_OFFSET) +/** PIU-C control register */ +#define IX_PIUMH_PIUC_CTL (IX_PIUMH_PIUC_BASE + IX_PIUMH_PIUCTL_OFFSET) +/** PIU-C status register */ +#define IX_PIUMH_PIUC_STAT (IX_PIUMH_PIUC_BASE + IX_PIUMH_PIUSTAT_OFFSET) +#endif + +#endif + +/* Hardware defs for tolapai */ +#if defined(__ep805xx) + +/* PIU-0 interrupt */ +#define IX_PIU_IRQ_DBG0 193 + +// TODO - below is physical address for PIU on FPGA +// now being set by the setup driver +#define IX_PIU_PIU0_PHYS 0 + +/* size of mapped memory block used by PIU */ +#define IX_PIU_MAPPED_MEMORY_SIZE 0x1000 + + + +#endif /* #if defined(__ep805xx) */ + + +/** + * Variable declarations. Externs are followed by static variables. + */ +extern IxPiuMhConfigPiuInfo ixPiuMhConfigPiuInfo[IX_PIUMH_NUM_PIUS]; + + +/* + * Prototypes for interface functions. + */ + +#if defined(__ep805xx) +/** + * @fn void ixPiuMhConfigPhysicalAddressSet( + * IxPiuMhPiuId piuId, + * UINT32 address) + * + * @brief This function sets the physical base address for the given piu + * + * @param IxPiuMhPiuId piuId (in) - the ID of the PIU whose physical base + * address will be set + * @param UINT32 address (in) - the address to set the physical address to + * + * @return No return value. + */ +void ixPiuMhConfigPhysicalAddressSet( + IxPiuMhPiuId piuId, + UINT32 address); + +/** + * @fn void ixPiuMhConfigInterruptIdSet( + * IxPiuMhPiuId piuId, + * UINT32 interruptId) + * + * @brief This function sets the interruptId for the given piu + * + * @param IxPiuMhPiuId piuId (in) - the ID of the PIU whose physical base + * address will be set + * @param UINT32 interruptId (in) - the interruptId + * + * @return No return value. + */ +void ixPiuMhConfigInterruptIdSet( + IxPiuMhPiuId piuId, + UINT32 interruptId); + +#endif // #if defined(__ep805xx) + +/** + * @fn void ixPiuMhConfigInitialize ( + IxPiuMhPiuInterrupts piuInterrupts) + * + * @brief This function initialises the Configuration module. + * + * @param IxPiuMhPiuInterrupts piuInterrupts (in) - whether or not to + * service the PIU "outFIFO not empty" interrupts. + * + * @return No return value. + */ + +void ixPiuMhConfigInitialize ( + IxPiuMhPiuInterrupts piuInterrupts); + +/** + * @fn void ixPiuMhConfigUninit (void) + * + * @brief This function uninitialises the Configuration module. + * + * @return No return value. + */ + +void ixPiuMhConfigUninit (void); + +/** + * @fn void ixPiuMhConfigIsrRegister ( + IxPiuMhPiuId piuId, + IxPiuMhConfigIsr isr) + * + * @brief This function registers an ISR to handle PIU "outFIFO not + * empty" interrupts. + * + * @param IxPiuMhPiuId piuId (in) - the ID of the PIU whose interrupt will + * be handled. + * @param IxPiuMhConfigIsr isr (in) - the ISR function pointer that the + * interrupt will trigger. + * + * @return No return value. + */ + +void ixPiuMhConfigIsrRegister ( + IxPiuMhPiuId piuId, + IxPiuMhConfigIsr isr); + +/** + * @fn void ixPiuMhConfigIsrUnregister (IxPiuMhPiuId piuId) + * + * @brief This function unregisters the ISR. + * + * @param IxPiuMhPiuId piuId (in) - the ID of the PIU whose interrupt will + * be unregistered. + * + * @return No return value. + */ +void ixPiuMhConfigIsrUnregister (IxPiuMhPiuId piuId); + +/** + * @fn BOOL ixPiuMhConfigPiuInterruptEnable ( + IxPiuMhPiuId piuId) + * + * @brief This function enables a PIU's "outFIFO not empty" interrupt. + * + * @param IxPiuMhPiuId piuId (in) - the ID of the PIU whose interrupt will + * be enabled. + * + * @return Returns the previous state of the interrupt (TRUE => enabled). + */ + +BOOL ixPiuMhConfigPiuInterruptEnable ( + IxPiuMhPiuId piuId); + +/** + * @fn BOOL ixPiuMhConfigPiuInterruptDisable ( + IxPiuMhPiuId piuId) + * + * @brief This function disables a PIU's "outFIFO not empty" interrupt + * + * @param IxPiuMhPiuId piuId (in) - the ID of the PIU whose interrupt will + * be disabled. + * + * @return Returns the previous state of the interrupt (TRUE => enabled). + */ + +BOOL ixPiuMhConfigPiuInterruptDisable ( + IxPiuMhPiuId piuId); + +/** + * @fn IxPiuMhMessageId ixPiuMhConfigMessageIdGet ( + IxPiuMhMessage message) + * + * @brief This function gets the ID of a message. + * + * @param IxPiuMhMessage message (in) - the message to get the ID of. + * + * @return the ID of the message + */ + +IxPiuMhMessageId ixPiuMhConfigMessageIdGet ( + IxPiuMhMessage message); + +/** + * @fn BOOL ixPiuMhConfigPiuIdIsValid ( + IxPiuMhPiuId piuId) + * + * @brief This function checks to see if a PIU ID is valid. + * + * @param IxPiuMhPiuId piuId (in) - the PIU ID to validate. + * + * @return True if the PIU ID is valid, otherwise False. + */ + +BOOL ixPiuMhConfigPiuIdIsValid ( + IxPiuMhPiuId piuId); + +/** + * @fn void ixPiuMhConfigLockGet ( + IxPiuMhPiuId piuId) + * + * @brief This function gets a lock for exclusive PIU interaction, and + * disables the PIU's "outFIFO not empty" interrupt. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU for which to get the + * lock and disable its interrupt. + * + * @return No return value. + */ + +void ixPiuMhConfigLockGet ( + IxPiuMhPiuId piuId); + +/** + * @fn void ixPiuMhConfigLockRelease ( + IxPiuMhPiuId piuId) + * + * @brief This function releases a lock for exclusive PIU interaction, and + * enables the PIU's "outFIFO not empty" interrupt. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU for which to release + * the lock and enable its interrupt. + * + * @return No return value. + */ + +void ixPiuMhConfigLockRelease ( + IxPiuMhPiuId piuId); + +/** + * @fn BOOL ixPiuMhConfigInFifoIsEmpty ( + IxPiuMhPiuId piuId) + * + * @brief This inline function checks if a PIU's inFIFO is empty. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU for which the inFIFO + * will be checked. + * + * @return True if the inFIFO is empty, otherwise False. + */ + +IXPIUMHCONFIG_INLINE BOOL ixPiuMhConfigInFifoIsEmpty ( + IxPiuMhPiuId piuId); + +/** + * @fn BOOL ixPiuMhConfigInFifoIsFull ( + IxPiuMhPiuId piuId) + * + * @brief This inline function checks if a PIU's inFIFO is full. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU for which the inFIFO + * will be checked. + * + * @return True if the inFIFO is full, otherwise False. + */ + +IXPIUMHCONFIG_INLINE BOOL ixPiuMhConfigInFifoIsFull ( + IxPiuMhPiuId piuId); + +/** + * @fn BOOL ixPiuMhConfigOutFifoIsEmpty ( + IxPiuMhPiuId piuId) + * + * @brief This inline function checks if a PIU's outFIFO is empty. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU for which the outFIFO + * will be checked. + * + * @return True if the outFIFO is empty, otherwise False. + */ + +IXPIUMHCONFIG_INLINE BOOL ixPiuMhConfigOutFifoIsEmpty ( + IxPiuMhPiuId piuId); + +/** + * @fn BOOL ixPiuMhConfigOutFifoIsFull ( + IxPiuMhPiuId piuId) + * + * @brief This inline function checks if a PIU's outFIFO is full. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU for which the outFIFO + * will be checked. + * + * @return True if the outFIFO is full, otherwise False. + */ + +IXPIUMHCONFIG_INLINE BOOL ixPiuMhConfigOutFifoIsFull ( + IxPiuMhPiuId piuId); + +/** + * @fn IX_STATUS ixPiuMhConfigInFifoWrite ( + IxPiuMhPiuId piuId, + IxPiuMhMessage message) + * + * @brief This function writes a message to a PIU's inFIFO. The caller + * must first check that the PIU's inFifo is not full. After writing the first + * word of the message, this function will keep polling PIU's inFIFO is not + * full to write the second word. If inFIFO is not available after maximum + * retries (IX_PIU_MH_MAX_NUM_OF_RETRIES), this function will return TIMEOUT + * status to indicate PIU hang / halt. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU for which the inFIFO + * will be written to. + * @param IxPiuMhMessage message (in) - The message to write. + * + * @return The function returns a status indicating success, failure or timeout. + */ + +IX_STATUS ixPiuMhConfigInFifoWrite ( + IxPiuMhPiuId piuId, + IxPiuMhMessage message); + +/** + * @fn IX_STATUS ixPiuMhConfigOutFifoRead ( + IxPiuMhPiuId piuId, + IxPiuMhMessage *message) + * + * @brief This function reads a message from a PIU's outFIFO. The caller + * must first check that the PIU's outFifo is not empty. After reading the first + * word of the message, this function will keep polling PIU's outFIFO is not + * empty to read the second word. If outFIFO is empty after maximum + * retries (IX_PIU_MH_MAX_NUM_OF_RETRIES), this function will return TIMEOUT + * status to indicate PIU hang / halt. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU for which the outFIFO + * will be read from. + * @param IxPiuMhMessage message (out) - The message read. + * + * @return The function returns a status indicating success, failure or timeout. + */ + +IX_STATUS ixPiuMhConfigOutFifoRead ( + IxPiuMhPiuId piuId, + IxPiuMhMessage *message); + +/** + * @fn void ixPiuMhConfigShow ( + IxPiuMhPiuId piuId) + * + * @brief This function will display the current state of the Configuration + * module. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU to display state + * information for. + * + * @return No return value. + */ + +void ixPiuMhConfigShow ( + IxPiuMhPiuId piuId); + +/** + * @fn void ixPiuMhConfigShowReset ( + IxPiuMhPiuId piuId) + * + * @brief This function will reset the current state of the Configuration + * module. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU to reset state + * information for. + * + * @return No return value. + */ + +void ixPiuMhConfigShowReset ( + IxPiuMhPiuId piuId); + +/* + * Inline functions + */ + +/* + * This inline function checks if a PIU's inFIFO is empty. + */ + +IXPIUMHCONFIG_INLINE +BOOL ixPiuMhConfigInFifoIsEmpty ( + IxPiuMhPiuId piuId) +{ + UINT32 ifne; + volatile UINT32 *statusReg = + (UINT32 *)ixPiuMhConfigPiuInfo[piuId].statusRegister; + + /* get the IFNE (InFifoNotEmpty) bit of the status register */ + IX_PIUMH_REGISTER_READ_BITS (statusReg, &ifne, IX_PIUMH_PIU_STAT_IFNE); + + /* if the IFNE status bit is unset then the inFIFO is empty */ + return (ifne == 0); +} + + +/* + * This inline function checks if a PIU's inFIFO is full. + */ +IXPIUMHCONFIG_INLINE +BOOL ixPiuMhConfigInFifoIsFull ( + IxPiuMhPiuId piuId) +{ + UINT32 ifnf; + volatile UINT32 *statusReg = + (UINT32 *)ixPiuMhConfigPiuInfo[piuId].statusRegister; + + /* get the IFNF (InFifoNotFull) bit of the status register */ + IX_PIUMH_REGISTER_READ_BITS (statusReg, &ifnf, IX_PIUMH_PIU_STAT_IFNF); + + /* if the IFNF status bit is unset then the inFIFO is full */ + return (ifnf == 0); +} + + +/* + * This inline function checks if a PIU's outFIFO is empty. + */ +IXPIUMHCONFIG_INLINE +BOOL ixPiuMhConfigOutFifoIsEmpty ( + IxPiuMhPiuId piuId) +{ + UINT32 ofne; + volatile UINT32 *statusReg = + (UINT32 *)ixPiuMhConfigPiuInfo[piuId].statusRegister; + + /* get the OFNE (OutFifoNotEmpty) bit of the status register */ + IX_PIUMH_REGISTER_READ_BITS (statusReg, &ofne, IX_PIUMH_PIU_STAT_OFNE); + + /* if the OFNE status bit is unset then the outFIFO is empty */ + return (ofne == 0); +} + +/* + * This inline function checks if a PIU's outFIFO is full. + */ +IXPIUMHCONFIG_INLINE +BOOL ixPiuMhConfigOutFifoIsFull ( + IxPiuMhPiuId piuId) +{ + UINT32 ofnf; + volatile UINT32 *statusReg = + (UINT32 *)ixPiuMhConfigPiuInfo[piuId].statusRegister; + + /* get the OFNF (OutFifoNotFull) bit of the status register */ + IX_PIUMH_REGISTER_READ_BITS (statusReg, &ofnf, IX_PIUMH_PIU_STAT_OFNF); + + /* if the OFNF status bit is unset then the outFIFO is full */ + return (ofnf == 0); +} + +#endif /* IXPIUMHCONFIG_P_H */ + +/** + * @} defgroup IxPiuMhConfig_p + */ diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/include/IxPiuMhMacros_p.h b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/include/IxPiuMhMacros_p.h new file mode 100644 index 0000000..e2aea6a --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/include/IxPiuMhMacros_p.h @@ -0,0 +1,319 @@ +/** + * @file IxPiuMhMacros_p.h + * + * @author Intel Corporation + * @date 21 Jan 2002 + * + * @brief This file contains the macros for the IxPiuMh component. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + +/** + * @defgroup IxPiuMhMacros_p IxPiuMhMacros_p + * + * @brief Macros for the IxPiuMh component. + * + * @{ + */ + +#ifndef IXPIUMHMACROS_P_H +#define IXPIUMHMACROS_P_H + +/* if we are running as a unit test */ +#ifdef IX_UNIT_TEST +#undef NDEBUG +#endif /* #ifdef IX_UNIT_TEST */ + +#include "IxOsal.h" + +/* + * #defines for function return types, etc. + */ + +#define IX_PIUMH_SHOW_TEXT_WIDTH (40) /**< text width for stats display */ +#define IX_PIUMH_SHOW_STAT_WIDTH (10) /**< stat width for stats display */ + +/** + * @def IX_PIUMH_SHOW + * + * @brief Macro for displaying a stat preceded by a textual description. + */ + +#define IX_PIUMH_SHOW(TEXT, STAT) \ + ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, \ + "%-40s: %10d\n", (int) TEXT, (int) STAT, 0, 0, 0, 0) + +/* + * Prototypes for interface functions. + */ + +/** + * @typedef IxPiuMhTraceTypes + * + * @brief Enumeration defining IxPiuMh trace levels + */ + +typedef enum +{ + IX_PIUMH_TRACE_OFF = IX_OSAL_LOG_LVL_NONE, /**< no trace */ + IX_PIUMH_WARNING = IX_OSAL_LOG_LVL_WARNING, /**< warning */ + IX_PIUMH_DEBUG = IX_OSAL_LOG_LVL_MESSAGE, /**< debug */ + IX_PIUMH_FN_ENTRY_EXIT = IX_OSAL_LOG_LVL_DEBUG3 /**< function entry/exit */ +} IxPiuMhTraceTypes; + +#ifdef IX_UNIT_TEST +#define IX_PIUMH_TRACE_LEVEL (IX_PIUMH_FN_ENTRY_EXIT) /**< trace level */ +#endif +#ifndef IX_UNIT_TEST +#define IX_PIUMH_TRACE_LEVEL (IX_PIUMH_TRACE_OFF) /**< trace level */ +#endif + +/** + * @def IX_PIUMH_TRACE0 + * + * @brief Trace macro taking 0 arguments. + */ + +#define IX_PIUMH_TRACE0(LEVEL, STR) \ + IX_PIUMH_TRACE6(LEVEL, STR, 0, 0, 0, 0, 0, 0) + +/** + * @def IX_PIUMH_TRACE1 + * + * @brief Trace macro taking 1 argument. + */ + +#define IX_PIUMH_TRACE1(LEVEL, STR, ARG1) \ + IX_PIUMH_TRACE6(LEVEL, STR, ARG1, 0, 0, 0, 0, 0) + +/** + * @def IX_PIUMH_TRACE2 + * + * @brief Trace macro taking 2 arguments. + */ + +#define IX_PIUMH_TRACE2(LEVEL, STR, ARG1, ARG2) \ + IX_PIUMH_TRACE6(LEVEL, STR, ARG1, ARG2, 0, 0, 0, 0) + +/** + * @def IX_PIUMH_TRACE3 + * + * @brief Trace macro taking 3 arguments. + */ + +#define IX_PIUMH_TRACE3(LEVEL, STR, ARG1, ARG2, ARG3) \ + IX_PIUMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, 0, 0, 0) + +/** + * @def IX_PIUMH_TRACE4 + * + * @brief Trace macro taking 4 arguments. + */ + +#define IX_PIUMH_TRACE4(LEVEL, STR, ARG1, ARG2, ARG3, ARG4) \ + IX_PIUMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, 0, 0) + +/** + * @def IX_PIUMH_TRACE5 + * + * @brief Trace macro taking 5 arguments. + */ + +#define IX_PIUMH_TRACE5(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, ARG5) \ + IX_PIUMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, ARG5, 0) + +/** + * @def IX_PIUMH_TRACE6 + * + * @brief Trace macro taking 6 arguments. + */ + +#define IX_PIUMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, ARG5, ARG6) \ +{ \ + if (LEVEL <= IX_PIUMH_TRACE_LEVEL) \ + { \ + (void) ixOsalLog (LEVEL, IX_OSAL_LOG_DEV_STDOUT, (STR), \ + (int)(ARG1), (int)(ARG2), (int)(ARG3), \ + (int)(ARG4), (int)(ARG5), (int)(ARG6)); \ + } \ +} + +/** + * @def IX_PIUMH_ERROR_REPORT + * + * @brief Error reporting facility. + */ + +#define IX_PIUMH_ERROR_REPORT(STR) \ +{ \ + (void) ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, \ + (STR), 0, 0, 0, 0, 0, 0); \ +} + +/* if we are running on XScale, i.e. real environment */ +#if (defined(__ep805xx) || CPU==XSCALE) && !defined(IX_UNIT_TEST) + +/** + * @def IX_PIUMH_REGISTER_READ + * + * @brief This macro reads a memory-mapped register. + */ + +#define IX_PIUMH_REGISTER_READ(registerAddress, value) \ +{ \ + *value = IX_OSAL_READ_LONG(registerAddress); \ +} + +/** + * @def IX_PIUMH_REGISTER_READ_BITS + * + * @brief This macro partially reads a memory-mapped register. + */ + +#define IX_PIUMH_REGISTER_READ_BITS(registerAddress, value, mask) \ +{ \ + *value = (IX_OSAL_READ_LONG(registerAddress) & mask); \ +} + +/** + * @def IX_PIUMH_REGISTER_WRITE + * + * @brief This macro writes a memory-mapped register. + */ + +#define IX_PIUMH_REGISTER_WRITE(registerAddress, value) \ +{ \ + IX_OSAL_WRITE_LONG(registerAddress, value); \ +} + +/** + * @def IX_PIUMH_REGISTER_WRITE_BITS + * + * @brief This macro partially writes a memory-mapped register. + */ + +#define IX_PIUMH_REGISTER_WRITE_BITS(registerAddress, value, mask) \ +{ \ + UINT32 orig = IX_OSAL_READ_LONG(registerAddress); \ + orig &= (~mask); \ + orig |= (value & mask); \ + IX_OSAL_WRITE_LONG(registerAddress, orig); \ +} + + +/* if we are running as a unit test */ +#else /* #if CPU==XSCALE */ + +#include "IxPiuMhTestRegister.h" + +/** + * @def IX_PIUMH_REGISTER_READ + * + * @brief This macro reads a memory-mapped register. + */ + +#define IX_PIUMH_REGISTER_READ(registerAddress, value) \ +{ \ + ixPiuMhTestRegisterRead (registerAddress, value); \ +} + +/** + * @def IX_PIUMH_REGISTER_READ_BITS + * + * @brief This macro partially reads a memory-mapped register. + */ + +#define IX_PIUMH_REGISTER_READ_BITS(registerAddress, value, mask) \ +{ \ + ixPiuMhTestRegisterReadBits (registerAddress, value, mask); \ +} + +/** + * @def IX_PIUMH_REGISTER_WRITE + * + * @brief This macro writes a memory-mapped register. + */ + +#define IX_PIUMH_REGISTER_WRITE(registerAddress, value) \ +{ \ + ixPiuMhTestRegisterWrite (registerAddress, value); \ +} + +/** + * @def IX_PIUMH_REGISTER_WRITE_BITS + * + * @brief This macro partially writes a memory-mapped register. + */ + +#define IX_PIUMH_REGISTER_WRITE_BITS(registerAddress, value, mask) \ +{ \ + ixPiuMhTestRegisterWriteBits (registerAddress, value, mask); \ +} + +#endif /* #if CPU==XSCALE */ + +#endif /* IXPIUMHMACROS_P_H */ + +/** + * @} defgroup IxPiuMhMacros_p + */ diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/include/IxPiuMhReceive_p.h b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/include/IxPiuMhReceive_p.h new file mode 100644 index 0000000..9ee3709 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/include/IxPiuMhReceive_p.h @@ -0,0 +1,173 @@ +/** + * @file IxPiuMhReceive_p.h + * + * @author Intel Corporation + * @date 18 Jan 2002 + * + * @brief This file contains the private API for the Receive module. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + +/** + * @defgroup IxPiuMhReceive_p IxPiuMhReceive_p + * + * @brief The private API for the Receive module. + * + * @{ + */ + +#ifndef IXPIUMHRECEIVE_P_H +#define IXPIUMHRECEIVE_P_H + +#include "IxPiuMh.h" +#include "IxOsalTypes.h" + +/* + * #defines for function return types, etc. + */ + +/* + * Prototypes for interface functions. + */ + +/** + * @fn void ixPiuMhReceiveInitialize (void) + * + * @brief This function registers an internal ISR to handle the PIUs' + * "outFIFO not empty" interrupts and receive messages from the PIUs when + * they become available. + * + * @return No return value. + */ + +void ixPiuMhReceiveInitialize (void); + +/** + * @fn void ixPiuMhReceiveUninitialize (void) + * + * @brief This function unregisters the internal ISR to handle the PIUs' + * "outFIFO not empty" interrupt. + * + * @return No return value. + */ + +void ixPiuMhReceiveUninitialize (void); + + +/** + * @fn void ixPiuMhReceiveMessagesReceive ( + IxPiuMhPiuId piuId) + * + * @brief This function reads messages from a particular PIU's outFIFO + * until the outFIFO is empty, and for each message looks first for an + * unsolicited callback, then a solicited callback, to pass the message + * back to the client. If no callback can be found the message is + * discarded and an error reported. This function will return TIMEOUT + * status if PIU hang / halt. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU to receive + * messages from. + * + * @return The function returns a status indicating success, failure or timeout. + */ + +IX_STATUS ixPiuMhReceiveMessagesReceive ( + IxPiuMhPiuId piuId); + +/** + * @fn void ixPiuMhReceiveShow ( + IxPiuMhPiuId piuId) + * + * @brief This function will display the current state of the Receive + * module. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU to display state + * information for. + * + * @return No return status. + */ + +void ixPiuMhReceiveShow ( + IxPiuMhPiuId piuId); + +/** + * @fn void ixPiuMhReceiveShowReset ( + IxPiuMhPiuId piuId) + * + * @brief This function will reset the current state of the Receive + * module. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU to reset state + * information for. + * + * @return No return status. + */ + +void ixPiuMhReceiveShowReset ( + IxPiuMhPiuId piuId); + +#endif /* IXPIUMHRECEIVE_P_H */ + +/** + * @} defgroup IxPiuMhReceive_p + */ diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/include/IxPiuMhSend_p.h b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/include/IxPiuMhSend_p.h new file mode 100644 index 0000000..d6a0352 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/include/IxPiuMhSend_p.h @@ -0,0 +1,185 @@ +/** + * @file IxPiuMhSend_p.h + * + * @author Intel Corporation + * @date 18 Jan 2002 + * + * @brief This file contains the private API for the Send module. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + +/** + * @defgroup IxPiuMhSend_p IxPiuMhSend_p + * + * @brief The private API for the Send module. + * + * @{ + */ + +#ifndef IXPIUMHSEND_P_H +#define IXPIUMHSEND_P_H + +#include "IxPiuMh.h" +#include "IxOsalTypes.h" + +/* + * #defines for function return types, etc. + */ + +/* + * Prototypes for interface functions. + */ + +/** + * @fn IX_STATUS ixPiuMhSendMessageSend ( + IxPiuMhPiuId piuId, + IxPiuMhMessage message, + UINT32 maxSendRetries) + * + * @brief This function writes a message to the specified PIU's inFIFO, + * and must be used when the message being sent does not solicit a response + * from the PIU. This function will return TIMEOUT status if PIU hang / halt. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU to send the message + * to. + * @param IxPiuMhMessage message (in) - The message to send. + * @param UINT32 maxSendRetries (in) - Max num. of retries to perform + * if the PIU's inFIFO is full. + * + * @return The function returns a status indicating success, failure or timeout. + */ + +IX_STATUS ixPiuMhSendMessageSend ( + IxPiuMhPiuId piuId, + IxPiuMhMessage message, + UINT32 maxSendRetries); + +/** + * @fn IX_STATUS ixPiuMhSendMessageWithResponseSend ( + IxPiuMhPiuId piuId, + IxPiuMhMessage message, + IxPiuMhMessageId solicitedMessageId, + IxPiuMhCallback solicitedCallback, + UINT32 maxSendRetries) + * + * @brief This function writes a message to the specified PIU's inFIFO, + * and must be used when the message being sent solicits a response from + * the PIU. The ID of the solicited response must be specified so that it + * can be recognised, and a callback provided to pass the response back to + * the client. This function will return TIMEOUT status if PIU hang / halt. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU to send the message + * to. + * @param IxPiuMhMessage message (in) - The message to send. + * @param IxPiuMhMessageId solicitedMessageId (in) - The ID of the + * solicited response. + * @param IxPiuMhCallback solicitedCallback (in) - The callback to pass the + * solicited response back to the client. + * @param UINT32 maxSendRetries (in) - Max num. of retries to perform + * if the PIU's inFIFO is full. + * + * @return The function returns a status indicating success, failure or timeout. + */ + +IX_STATUS ixPiuMhSendMessageWithResponseSend ( + IxPiuMhPiuId piuId, + IxPiuMhMessage message, + IxPiuMhMessageId solicitedMessageId, + IxPiuMhCallback solicitedCallback, + UINT32 maxSendRetries); + +/** + * @fn void ixPiuMhSendShow ( + IxPiuMhPiuId piuId) + * + * @brief This function will display the current state of the Send module. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU to display state + * information for. + * + * @return No return value. + */ + +void ixPiuMhSendShow ( + IxPiuMhPiuId piuId); + +/** + * @fn void ixPiuMhSendShowReset ( + IxPiuMhPiuId piuId) + * + * @brief This function will reset the current state of the Send module. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU to reset state + * information for. + * + * @return No return value. + */ + +void ixPiuMhSendShowReset ( + IxPiuMhPiuId piuId); + +#endif /* IXPIUMHSEND_P_H */ + +/** + * @} defgroup IxPiuMhSend_p + */ diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/include/IxPiuMhSolicitedCbMgr_p.h b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/include/IxPiuMhSolicitedCbMgr_p.h new file mode 100644 index 0000000..8f7ec58 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/include/IxPiuMhSolicitedCbMgr_p.h @@ -0,0 +1,203 @@ +/** + * @file IxPiuMhSolicitedCbMgr_p.h + * + * @author Intel Corporation + * @date 18 Jan 2002 + * + * @brief This file contains the private API for the Solicited Callback + * Manager module. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + +/** + * @defgroup IxPiuMhSolicitedCbMgr_p IxPiuMhSolicitedCbMgr_p + * + * @brief The private API for the Solicited Callback Manager module. + * + * @{ + */ + +#ifndef IXPIUMHSOLICITEDCBMGR_P_H +#define IXPIUMHSOLICITEDCBMGR_P_H + +#include "IxPiuMh.h" +#include "IxOsalTypes.h" + +/* + * #defines for function return types, etc. + */ + +/** Maximum number of solicited callbacks that can be stored in the list */ +#define IX_PIUMH_MAX_CALLBACKS (16) + +/* + * Prototypes for interface functions. + */ + +/** + * @fn void ixPiuMhSolicitedCbMgrInitialize (void) + * + * @brief This function initializes the Solicited Callback Manager module, + * setting up a callback data structure for each PIU. + * + * @return No return value. + */ + +void ixPiuMhSolicitedCbMgrInitialize (void); + +/** + * @fn void ixPiuMhSolicitedCbMgrUninitialize (void) + * + * @brief This function uninitializes the Solicited Callback Manager module. + * + * @return No return value. + */ + +void ixPiuMhSolicitedCbMgrUninitialize (void); + +/** + * @fn IX_STATUS ixPiuMhSolicitedCbMgrCallbackSave ( + IxPiuMhPiuId piuId, + IxPiuMhMessageId solicitedMessageId, + IxPiuMhCallback solicitedCallback) + * + * @brief This function saves a callback in the specified PIU's callback + * list. If the callback list is full the function will fail. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU in whose callback + * list the callback will be saved. + * @param IxPiuMhMessageId solicitedMessageId (in) - The ID of the message + * that this callback is for. + * @param IxPiuMhCallback solicitedCallback (in) - The callback function + * pointer to save. + * + * @return The function returns a status indicating success or failure. + */ + +IX_STATUS ixPiuMhSolicitedCbMgrCallbackSave ( + IxPiuMhPiuId piuId, + IxPiuMhMessageId solicitedMessageId, + IxPiuMhCallback solicitedCallback); + +/** + * @fn void ixPiuMhSolicitedCbMgrCallbackRetrieve ( + IxPiuMhPiuId piuId, + IxPiuMhMessageId solicitedMessageId, + IxPiuMhCallback *solicitedCallback) + * + * @brief This function retrieves the first ID-matching callback from the + * specified PIU's callback list. If no matching callback can be found the + * function will fail. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU from whose callback + * list the callback will be retrieved. + * @param IxPiuMhMessageId solicitedMessageId (in) - The ID of the message + * that the callback is for. + * @param IxPiuMhCallback solicitedCallback (out) - The callback function + * pointer retrieved. + * + * @return No return value. + */ + +void ixPiuMhSolicitedCbMgrCallbackRetrieve ( + IxPiuMhPiuId piuId, + IxPiuMhMessageId solicitedMessageId, + IxPiuMhCallback *solicitedCallback); + +/** + * @fn void ixPiuMhSolicitedCbMgrShow ( + IxPiuMhPiuId piuId) + * + * @brief This function will display the current state of the Solicited + * Callback Manager module. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU to display state + * information for. + * + * @return No return value. + */ + +void ixPiuMhSolicitedCbMgrShow ( + IxPiuMhPiuId piuId); + +/** + * @fn void ixPiuMhSolicitedCbMgrShowReset ( + IxPiuMhPiuId piuId) + * + * @brief This function will reset the current state of the Solicited + * Callback Manager module. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU to reset state + * information for. + * + * @return No return value. + */ + +void ixPiuMhSolicitedCbMgrShowReset ( + IxPiuMhPiuId piuId); + +#endif /* IXPIUMHSOLICITEDCBMGR_P_H */ + +/** + * @} defgroup IxPiuMhSolicitedCbMgr_p + */ diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/include/IxPiuMhUnsolicitedCbMgr_p.h b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/include/IxPiuMhUnsolicitedCbMgr_p.h new file mode 100644 index 0000000..5e4e187 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/include/IxPiuMhUnsolicitedCbMgr_p.h @@ -0,0 +1,202 @@ +/** + * @file IxPiuMhUnsolicitedCbMgr_p.h + * + * @author Intel Corporation + * @date 18 Jan 2002 + * + * @brief This file contains the private API for the Unsolicited Callback + * Manager module. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +/** + * @defgroup IxPiuMhUnsolicitedCbMgr_p IxPiuMhUnsolicitedCbMgr_p + * + * @brief The private API for the Unsolicited Callback Manager module. + * + * @{ + */ + +#ifndef IXPIUMHUNSOLICITEDCBMGR_P_H +#define IXPIUMHUNSOLICITEDCBMGR_P_H + +#include "IxPiuMh.h" +#include "IxOsalTypes.h" + +/* + * #defines for function return types, etc. + */ + +/* + * Prototypes for interface functions. + */ + +/** + * @fn void ixPiuMhUnsolicitedCbMgrInitialize (void) + * + * @brief This function initializes the Unsolicited Callback Manager + * module, setting up a callback data structure for each PIU. + * + * @return No return value. + */ + +void ixPiuMhUnsolicitedCbMgrInitialize (void); + +/** + * @fn void ixPiuMhUnsolicitedCbMgrUninitialize (void) + * + * @brief This function uninitializes the Unsolicited Callback Manager + * module. + * + * @return No return value. + */ + +void ixPiuMhUnsolicitedCbMgrUninitialize (void); + +/** + * @fn void ixPiuMhUnsolicitedCbMgrCallbackSave ( + IxPiuMhPiuId piuId, + IxPiuMhMessageId unsolicitedMessageId, + IxPiuMhCallback unsolicitedCallback) + * + * @brief This function saves a callback in the specified PIU's callback + * table. If a callback already exists for the specified ID then it will + * be overwritten. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU in whose callback + * table the callback will be saved. + * @param IxPiuMhMessageId unsolicitedMessageId (in) - The ID of the + * messages that this callback is for. + * @param IxPiuMhCallback unsolicitedCallback (in) - The callback function + * pointer to save. + * + * @return No return value. + */ + +void ixPiuMhUnsolicitedCbMgrCallbackSave ( + IxPiuMhPiuId piuId, + IxPiuMhMessageId unsolicitedMessageId, + IxPiuMhCallback unsolicitedCallback); + +/** + * @fn void ixPiuMhUnsolicitedCbMgrCallbackRetrieve ( + IxPiuMhPiuId piuId, + IxPiuMhMessageId unsolicitedMessageId, + IxPiuMhCallback *unsolicitedCallback) + * + * @brief This function retrieves the callback for the specified ID from + * the specified PIU's callback table. If no callback is registered for + * the specified ID and PIU then a callback value of NULL will be returned. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU from whose callback + * table the callback will be retrieved. + * @param IxPiuMhMessageId unsolicitedMessageId (in) - The ID of the + * messages that the callback is for. + * @param IxPiuMhCallback unsolicitedCallback (out) - The callback function + * pointer retrieved. + * + * @return No return value. + */ + +void ixPiuMhUnsolicitedCbMgrCallbackRetrieve ( + IxPiuMhPiuId piuId, + IxPiuMhMessageId unsolicitedMessageId, + IxPiuMhCallback *unsolicitedCallback); + +/** + * @fn void ixPiuMhUnsolicitedCbMgrShow ( + IxPiuMhPiuId piuId) + * + * @brief This function will display the current state of the Unsolicited + * Callback Manager module. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU to display state + * information for. + * + * @return No return value. + */ + +void ixPiuMhUnsolicitedCbMgrShow ( + IxPiuMhPiuId piuId); + +/** + * @fn void ixPiuMhUnsolicitedCbMgrShowReset ( + IxPiuMhPiuId piuId) + * + * @brief This function will reset the current state of the Unsolicited + * Callback Manager module. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU to reset state + * information for. + * + * @return No return value. + */ + +void ixPiuMhUnsolicitedCbMgrShowReset ( + IxPiuMhPiuId piuId); + +#endif /* IXPIUMHUNSOLICITEDCBMGR_P_H */ + +/** + * @} defgroup IxPiuMhUnsolicitedCbMgr_p + */ diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/linux_2.6_kernel_space.mk b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/linux_2.6_kernel_space.mk new file mode 100644 index 0000000..c59e1bd --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/linux_2.6_kernel_space.mk @@ -0,0 +1,80 @@ +################### +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# Contact Information: +# Intel Corporation +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# +################### + +#specific include directories in kernel space +INCLUDES+= -I $(ICP_OSAL_DIR)/platforms/EP805XX/include \ + -I $(ICP_OSAL_DIR)/platforms/EP805XX/os/linux/include \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/core \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules/ddk \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules/ioMem \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules/bufferMgt + + +SOURCES+= $(ICP_DEVICE)$(ICP_SLASH)linux_kernel_module.c + + +#Extra Flags Specific in kernel space e.g. include path or debug flags etc. e.g to add an include path EXTRA_CFLAGS += -I$(src)/../include +EXTRA_CFLAGS += $(INCLUDES) -DTOLAPAI -D__tolapai -DEP805XX -D__ep805xx -DIX_HW_COHERENT_MEMORY=1 +EXTRA_LDFLAGS+=-whole-archive + + diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/linux_kernel_module.c b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/linux_kernel_module.c new file mode 100644 index 0000000..3f05ff0 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/linux_kernel_module.c @@ -0,0 +1,85 @@ +/** + * @file linux_kernel_module.c + * + * @author Intel Corporation + * + * @description Contents are the kernel module file. + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ +#include <linux/module.h> + + +MODULE_DESCRIPTION("TDM Infrastructure Driver"); +MODULE_VERSION("1.0"); +MODULE_AUTHOR("Intel Corporation"); +MODULE_LICENSE("Dual BSD/GPL"); + +int init_module(void) +{ + return 0; +} + +void cleanup_module(void) +{ + +} + diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_queue_manager/IxQMgr.c b/Acceleration/library/icp_telephony/tdm_infrastructure_queue_manager/IxQMgr.c new file mode 100644 index 0000000..7078430 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_queue_manager/IxQMgr.c @@ -0,0 +1,2192 @@ +/****************************************************************************** + * @file IxQMgr.c + * + * @description Contents of this file provide the Software Queue Manager + * Component implementation. + * + * @ingroup qMgr + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + ******************************************************************************/ + +/** + * Put the system defined include files required. + */ + +/* + * Inlines are compiled as function when this is defined. + * N.B. Must be placed before #include of "IxQMgr.h" + */ +#ifndef IXQMGR_H +# define IXQMGRQACCESS_C +#else +# error +#endif + +/** + * Put the user defined include files required. + */ +#include "IxOsal.h" +#include "IxOsalIoMem.h" +#include "icp.h" +#include "IxQMgr.h" +#include "IxSwQueue.h" +#include "IxQMgrTrace_p.h" + +IxQMgrQueue ixQMgrQueues [IX_QMGR_MAX_NUM_QUEUES]; + +PRIVATE BOOL ixQMgrInitialised = FALSE; +PRIVATE UINT32 numQsConfigured; + +/* list of index to the first/last queue with notif enabled for each group */ +PRIVATE UINT32 ixQMgrFirstQInGrpList [IX_QMGR_MAX_NUM_DISPATCH_GRP]; +PRIVATE UINT32 ixQMgrLastQInGrpList [IX_QMGR_MAX_NUM_DISPATCH_GRP]; + +/* cached memory Info */ +PRIVATE void * ixQMgrGrpMemBaseFlush[IX_QMGR_MAX_NUM_DISPATCH_GRP]; +PRIVATE void * ixQMgrGrpMemBaseInvalid[IX_QMGR_MAX_NUM_DISPATCH_GRP]; +PRIVATE UINT32 ixQMgrGrpMemSize[IX_QMGR_MAX_NUM_DISPATCH_GRP]; + + + +PRIVATE IxOsalMutex qMgrConfigMutex; + +typedef struct +{ + UINT32 success; /* Number of successes */ + UINT32 fail; /* Number of failures */ +} IxQMgrStat; + +typedef struct +{ + IxQMgrStat numCfgs; + IxQMgrStat numReads; + IxQMgrStat numWrites; + IxQMgrStat numNotifEnable; + IxQMgrStat numNotifDisable; + IxQMgrStat numCallbackSet; + IxQMgrStat numWMSets; + IxQMgrStat numQSizeReconfig; +} IxQMgrStats; + +PRIVATE IxQMgrStats ixQMgrComponentStats; + + +#define IX_QMGR_QUEUE_CLEAR(qId) do { \ +ixQMgrQueues[qId].qSize = 0; \ +ixQMgrQueues[qId].qEntrySize = 0; \ +ixQMgrQueues[qId].queue.content = 0; \ +ixQMgrQueues[qId].group = IX_QMGR_MAX_NUM_DISPATCH_GRP; \ +ixQMgrQueues[qId].nextQId = IX_QMGR_MAX_NUM_QUEUES; \ +ixQMgrQueues[qId].prevQId = IX_QMGR_MAX_NUM_QUEUES; \ +ixQMgrQueues[qId].callback = dummyCallback; \ +ixQMgrQueues[qId].callbackId = 0; \ +ixQMgrQueues[qId].waterMark = 0; \ +ixQMgrQueues[qId].notifCond = IX_QMGR_Q_SOURCE_INVALID; \ +ixQMgrQueues[qId].htCountFormat = IX_QMGR_Q_COUNT_INVALID; \ +ixQMgrQueues[qId].htAlignment = IX_QMGR_Q_ALIGN_INVALID; \ +ixQMgrQueues[qId].shadowing = IX_QMGR_Q_NO_SHADOWING; \ +ixQMgrQueues[qId].shadowInfo.byteShadowTailCounter =0; \ +ixQMgrQueues[qId].shadowInfo.wordShadowTailCounter =0; \ +} while (0); + +#define QMGR_WORDS_PER_LINE 8 + +#define QMGR_DEFAULT_Q_NAME_LEN 13 + +/* find the nearest power of 2 of the input val */ +PRIVATE UINT32 +ixQMgrNearestPowerOfTwoGet_p(UINT32 val) +{ + UINT32 adjustedVal = 1; + + while (val > adjustedVal) + { + adjustedVal = adjustedVal << 1; + } + /* ensure the result is consistent with the input values */ + if (!(adjustedVal >= val) && (adjustedVal < (val << 1))) + { + IX_QMGR_REPORT_ERROR ("IxUtilNearestPowerOfTwo failed"); + } + return adjustedVal; +} + + +/* Dummy callback used if no callback has been configured by the client */ +void dummyCallback(IxQMgrQId qId, + IxQMgrCallbackId cbId) +{ + /* do nothing */ + IX_QMGR_TRACE2 (IX_QMGR_DEBUG, + "Dummy callback Queue %d, cb %d\n", + qId, + cbId); +} + + +/* Reset queue internal structure */ +void +ixQMgrResetQueue_p(IxQMgrQId qId) +{ + IxQMgrQueue *info = &ixQMgrQueues[qId]; + /* + * Queue may or may not have been in use - We can't clear counters if Q + * hasn't been configured. + */ + if(ixQMgrQueues[qId].queue.content) + { + if(info->htCountFormat == IX_QMGR_Q_COUNT_BYTES) + { + IX_SWQ_WA_CB_HEAD_RESET(info->queue); + IX_SWQ_WA_CB_TAIL_RESET(info->queue); + } + else + { + if(info->htAlignment == IX_QMGR_Q_ALIGN_WORD) + { + IX_SWQ_WA_CE_HEAD_RESET(info->queue); + IX_SWQ_WA_CE_TAIL_RESET(info->queue); + if (info->shadowing == IX_QMGR_Q_SHADOW_TAIL_ONLY) + { + *(info->shadowInfo.wordRealTailCounter) = 0; + } + } + else + { + IX_SWQ_BA_CE_HEAD_RESET(info->queue); + IX_SWQ_BA_CE_TAIL_RESET(info->queue); + if (info->shadowing == IX_QMGR_Q_SHADOW_TAIL_ONLY) + { + *(info->shadowInfo.byteRealTailCounter) = 0; + } + } + } + } + + IX_QMGR_QUEUE_CLEAR(qId); +} + +/** + * Initialise the QMgr. + */ +icp_status_t +ixQMgrInit (void) +{ + IX_STATUS mutexStatus = IX_SUCCESS; + icp_status_t status = ICP_STATUS_SUCCESS; + UINT32 index = 0; + UINT32 grpIndex = 0; + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Entering ixQMgrInit\n"); + if (ixQMgrInitialised) + { + status = ICP_STATUS_SUCCESS; + } + else + { + ixQMgrInitialised = TRUE; + /* Perform Initialisation */ + for (; index < IX_QMGR_MAX_NUM_QUEUES; index ++) + { + IX_QMGR_QUEUE_CLEAR(index); + } + for (;grpIndex < IX_QMGR_MAX_NUM_DISPATCH_GRP; grpIndex ++) + { + ixQMgrFirstQInGrpList[grpIndex] = IX_QMGR_MAX_NUM_QUEUES; + ixQMgrLastQInGrpList[grpIndex] = IX_QMGR_MAX_NUM_QUEUES; + } + memset (&ixQMgrComponentStats, 0, sizeof(ixQMgrComponentStats)); + ixQMgrInitialised = TRUE; + numQsConfigured = 0; + + mutexStatus = ixOsalMutexInit(&qMgrConfigMutex); + if (IX_SUCCESS != mutexStatus) + { + ixQMgrInitialised = FALSE; + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrInit: " + "Mutex unavailable\n"); + status = ICP_STATUS_FAIL; + } + } + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Exiting ixQMgrInit\n"); + return status; +} + +/** + * Uninitialise the QMgr. + */ +icp_status_t +ixQMgrUnload (void) +{ + IX_STATUS mutexStatus = IX_SUCCESS; + icp_status_t status = ICP_STATUS_SUCCESS; + UINT32 qId =0; + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Entering ixQMgrUnload\n"); + if (!ixQMgrInitialised) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrUnload: " + "ixQMgr component not initialised\n"); + status = ICP_STATUS_FAIL; + } + else + { + + mutexStatus = ixOsalMutexLock (&qMgrConfigMutex, IX_OSAL_WAIT_NONE); + if (IX_SUCCESS != mutexStatus) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrUnload: " + "Can not get Mutex - please retry\n"); + return ICP_STATUS_RESOURCE; + } + + /*ensure that there are not queues still configured*/ + for (qId =0; qId <IX_QMGR_MAX_NUM_QUEUES; qId ++) + { + /* + * IX_QMGR_MAX_NUM_DISPATCH_GRP is the default. + * if group == IX_QMGR_MAX_NUM_DISPATCH_GRP, then the queue has not + * been configured + */ + if (ixQMgrQueues[qId].group != IX_QMGR_MAX_NUM_DISPATCH_GRP) + { + ixOsalMutexUnlock (&qMgrConfigMutex); + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrUnload: ixQMgr component " + "cannot be unloaded as in use\n"); + return ICP_STATUS_FAIL; + } + } + + ixQMgrInitialised = FALSE; + numQsConfigured = 0; + + ixOsalMutexUnlock (&qMgrConfigMutex); + ixOsalMutexDestroy (&qMgrConfigMutex); + } + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Exiting ixQMgrUnload\n"); + return status; +} + + + + + +/** + * Describe queue configuration and statistics for active queues. + */ +void +ixQMgrShow (void) +{ + UINT32 grpIndex = 0; + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Entering ixQMgrShow\n"); + if (!ixQMgrInitialised) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrShow: " + "ixQMgr component not initialised\n"); + } + else + { + IX_QMGR_TRACE2 (IX_QMGR_DEBUG, + "%d Successful Reads, %d Failed Reads\n", + ixQMgrComponentStats.numReads.success, + ixQMgrComponentStats.numReads.fail); + IX_QMGR_TRACE2 (IX_QMGR_DEBUG, + "%d Successful Writes, %d Failed Writes\n", + ixQMgrComponentStats.numWrites.success, + ixQMgrComponentStats.numWrites.fail); + IX_QMGR_TRACE2 (IX_QMGR_DEBUG, + "%d Successful Notification Enables, " + "%d Failed Notification Enables\n", + ixQMgrComponentStats.numNotifEnable.success, + ixQMgrComponentStats.numNotifEnable.fail); + IX_QMGR_TRACE2 (IX_QMGR_DEBUG, + "%d Successful Notification Disables, " + "%d Failed Notification Disables\n", + ixQMgrComponentStats.numNotifDisable.success, + ixQMgrComponentStats.numNotifDisable.fail); + IX_QMGR_TRACE2 (IX_QMGR_DEBUG, + "%d Successful Callback Sets, " + "%d Failed Callback Sets\n", + ixQMgrComponentStats.numCallbackSet.success, + ixQMgrComponentStats.numCallbackSet.fail); + IX_QMGR_TRACE2 (IX_QMGR_DEBUG, + "%d Successful Watermark Sets, " + "%d Failed Watermark Sets\n", + ixQMgrComponentStats.numWMSets.success, + ixQMgrComponentStats.numWMSets.fail); + IX_QMGR_TRACE2 (IX_QMGR_DEBUG, + "%d Successful Q Size Reconfigures, " + "%d Failed Q Size Reconfigures\n", + ixQMgrComponentStats.numQSizeReconfig.success, + ixQMgrComponentStats.numQSizeReconfig.fail); + if (numQsConfigured > 1) + { + IX_QMGR_TRACE1 (IX_QMGR_DEBUG, + "Available Configured Queues: QId = 0..%d\n", + numQsConfigured-1); + } + else if (numQsConfigured == 1) + { + IX_QMGR_TRACE0 (IX_QMGR_DEBUG, + "Single Queue Configured QId = 0\n"); + } + else + { + IX_QMGR_TRACE0 (IX_QMGR_DEBUG, + "No Queues Confiured\n"); + } + for (grpIndex = 0;grpIndex < IX_QMGR_MAX_NUM_DISPATCH_GRP; grpIndex ++) + { + IX_QMGR_PRINT("First Q = %d for Dispatch grp %d\n", + ixQMgrFirstQInGrpList[grpIndex],grpIndex); + IX_QMGR_PRINT("Last Q = %d for Dispatch grp %d\n", + ixQMgrLastQInGrpList[grpIndex],grpIndex); + } + } + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Exiting ixQMgrShow\n"); +} + +/** + * Display Individual Queue Configuration and contents + */ +icp_status_t +ixQMgrQShow (IxQMgrQId qId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + UINT32 index = 0; + UINT32 line = 0; + UINT32 entryIndex = 0; + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Entering ixQMgrQShow\n"); + if (!ixQMgrInitialised) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrQShow: " + "ixQMgr component not initialised\n"); + status = ICP_STATUS_FAIL; + } + else if (qId >= IX_QMGR_MAX_NUM_QUEUES) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQShow: " + "invalid qId\n"); + status = ICP_STATUS_INVALID_PARAM; + } + else if( !IX_SWQ_INITIALISED(ixQMgrQueues[qId].queue)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQShow: " + "Q not configured\n"); + status = ICP_STATUS_INVALID_PARAM; + } + else + { + UINT32 numEntries; + + IX_QMGR_PRINT ("Queue Info:\n" + " Name: %s\n" + " Id: %d\n", + ixQMgrQueues[qId].qName, + qId); + IX_QMGR_PRINT (" Size = %u\n" + " EntrySize = %u\n" + " Group = %u\n", + (UINT32)ixQMgrQueues[qId].qSize, + (UINT32)ixQMgrQueues[qId].qEntrySize, + (UINT32)ixQMgrQueues[qId].group); + IX_QMGR_PRINT (" Watermark = %u\n" + " Notification Condition = %d\n", + (UINT32)ixQMgrQueues[qId].waterMark, + ixQMgrQueues[qId].notifCond); + IX_QMGR_PRINT (" Head and Tail Alignment = %u\n" + " Head and Tail count format = %u\n", + ixQMgrQueues[qId].htAlignment, + ixQMgrQueues[qId].htCountFormat); + IX_QMGR_PRINT (" Shadowing = %u\n", + ixQMgrQueues[qId].shadowing); + + if(ixQMgrQueues[qId].htCountFormat == IX_QMGR_Q_COUNT_BYTES) + { + IX_SWQ_WA_HEAD_INVALIDATE(ixQMgrQueues[qId].queue); + IX_SWQ_WA_TAIL_INVALIDATE(ixQMgrQueues[qId].queue); + + IX_SWQ_WA_CB_NUM_ENTRIES_GET(ixQMgrQueues[qId].queue, numEntries); + IX_QMGR_PRINT (" Num Entries in Q = %d\n" + " Current Head = 0x%08X at 0x%08X\n" + " Current Tail = 0x%08X at 0x%08X\n", + numEntries, + *(IX_SWQ_WA_CB_HEAD_PTR(ixQMgrQueues[qId].queue)), + (UINT32)IX_SWQ_WA_CB_HEAD_PTR(ixQMgrQueues[qId].queue), + *(IX_SWQ_WA_CB_TAIL_PTR(ixQMgrQueues[qId].queue)), + (UINT32)IX_SWQ_WA_CB_TAIL_PTR(ixQMgrQueues[qId].queue)); + } + else + { + if (ixQMgrQueues[qId].htAlignment == IX_QMGR_Q_ALIGN_WORD) + { + IX_SWQ_WA_HEAD_INVALIDATE(ixQMgrQueues[qId].queue); + IX_SWQ_WA_TAIL_INVALIDATE(ixQMgrQueues[qId].queue); + + IX_SWQ_WA_CE_NUM_ENTRIES_GET(ixQMgrQueues[qId].queue, + numEntries); + IX_QMGR_PRINT ( + " Num Entries in Q = %d\n" + " Current Head = 0x%08X at 0x%08X\n" + " Current Tail = 0x%08X at 0x%08X\n", + numEntries, + IX_SWQ_WA_CE_HEAD(ixQMgrQueues[qId].queue), + (UINT32)IX_SWQ_WA_CE_HEAD_PTR(ixQMgrQueues[qId].queue), + IX_SWQ_WA_CE_TAIL(ixQMgrQueues[qId].queue), + (UINT32)IX_SWQ_WA_CE_TAIL_PTR(ixQMgrQueues[qId].queue)); + + if (ixQMgrQueues[qId].shadowing == IX_QMGR_Q_SHADOW_TAIL_ONLY) + { + IX_SWQ_CACHE_INVALIDATE( + (ixQMgrQueues[qId].shadowInfo.wordRealTailCounter), + IX_QMGR_SIZEOF_WORD); + IX_QMGR_PRINT ( + " Real Tail Counter = 0x%08X at 0x%08X\n", + *(ixQMgrQueues[qId].shadowInfo.wordRealTailCounter), + (uint32_t)ixQMgrQueues[qId].shadowInfo.wordRealTailCounter); + } + } + else + { + IX_SWQ_BA_HEAD_INVALIDATE(ixQMgrQueues[qId].queue); + IX_SWQ_BA_TAIL_INVALIDATE(ixQMgrQueues[qId].queue); + IX_SWQ_CACHE_INVALIDATE( + (ixQMgrQueues[qId].shadowInfo.byteRealTailCounter), + IX_QMGR_SIZEOF_BYTE); + + IX_SWQ_BA_CE_NUM_ENTRIES_GET(ixQMgrQueues[qId].queue, + numEntries); + IX_QMGR_PRINT ( + " Num Entries in Q = %d\n" + " Current Head = 0x%02X at 0x%08X\n" + " Current Tail = 0x%02X at 0x%08X\n", + numEntries, + IX_SWQ_BA_CE_HEAD(ixQMgrQueues[qId].queue), + (UINT32)IX_SWQ_BA_CE_HEAD_PTR(ixQMgrQueues[qId].queue), + IX_SWQ_BA_CE_TAIL(ixQMgrQueues[qId].queue), + (UINT32)IX_SWQ_BA_CE_TAIL_PTR(ixQMgrQueues[qId].queue)); + + if (ixQMgrQueues[qId].shadowing == IX_QMGR_Q_SHADOW_TAIL_ONLY) + { + IX_QMGR_PRINT ( + " Real Tail Counter = 0x%02X at 0x%08X\n", + *(ixQMgrQueues[qId].shadowInfo.byteRealTailCounter), + (uint32_t)ixQMgrQueues[qId].shadowInfo.byteRealTailCounter); + } + } + } + IX_QMGR_PRINT (" Next Q Id = %d\n" + " Prev Q Id = %d\n" + " Queue Location = 0x%08X\n", + ixQMgrQueues[qId].nextQId, + ixQMgrQueues[qId].prevQId, + (UINT32)IX_SWQ_CONTENT_PTR(ixQMgrQueues[qId].queue)); + + IX_QMGR_PRINT(" Queue Entries:\n"); + /* print out 8 words on each line, reorg order of words depending on + * the entry size + */ + for (index = 0; + index < ((ixQMgrQueues[qId].qSize) * (ixQMgrQueues[qId].qEntrySize)); + index = index+QMGR_WORDS_PER_LINE) + { + IX_QMGR_PRINT ("%u: ", + index); + line = 0; + while ((line+index < + (ixQMgrQueues[qId].qSize) * (ixQMgrQueues[qId].qEntrySize)) + && (line < QMGR_WORDS_PER_LINE)) + + { + IX_QMGR_PRINT (" 0x"); + for (entryIndex = (ixQMgrQueues[qId].qEntrySize); + entryIndex > 0; + entryIndex --) + { + IX_QMGR_PRINT ("%08X", + IX_SWQ_ENTRY_IDXGET(ixQMgrQueues[qId].queue, + index+line+entryIndex-1)); + } + line += (ixQMgrQueues[qId].qEntrySize); + + } + IX_QMGR_PRINT("\n"); + } + } + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Exiting ixQMgrQShow\n"); + return status; +} + +/** + * Sets the base address and the size of the memory area that will + * be invalidated when the dispatch loop function will run. + */ +icp_status_t +ixQMgrGroupMemoryConfig (IxQMgrDispatchGroup group, + void * baseAddressToFlush, + void * baseAddressToInvalidate, + UINT32 size) +{ + if (!ixQMgrInitialised) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrGroupMemoryConfig: " + "ixQMgr component not initialised\n"); + return ICP_STATUS_FAIL; + } + + if (size == 0) + { + IX_QMGR_REPORT_ERROR ("ixQMgrGroupMemoryConfig: " + "invalid size parameter\n"); + return ICP_STATUS_INVALID_PARAM; + } + if (group >= IX_QMGR_MAX_NUM_DISPATCH_GRP) + { + IX_QMGR_REPORT_ERROR ("ixQMgrGroupMemoryConfig: " + "invalid group parameter\n"); + return ICP_STATUS_INVALID_PARAM; + } + if (baseAddressToFlush == NULL) + { + IX_QMGR_REPORT_ERROR ("ixQMgrGroupMemoryConfig: " + "invalid baseAddress parameter\n"); + return ICP_STATUS_INVALID_PARAM; + } + if (baseAddressToInvalidate == NULL) + { + IX_QMGR_REPORT_ERROR ("ixQMgrGroupMemoryConfig: " + "invalid baseAddress parameter\n"); + return ICP_STATUS_INVALID_PARAM; + } + ixQMgrGrpMemBaseFlush[group] = baseAddressToFlush; + ixQMgrGrpMemBaseInvalid[group] = baseAddressToInvalidate; + ixQMgrGrpMemSize[group] = size; + return ICP_STATUS_SUCCESS; +} + + +/* ------------------------------------------------------------ + Configuration related functions + ---------------------------------------------------------- */ + +icp_status_t +ixQMgrQConfig (char *qName, + IxQMgrQId *qId, + IxQMgrQSize qSize, + IxQMgrQEntrySizeInWords qEntrySize, + IxQMgrHeadAndTailCountFormat htCountFormat, + IxQMgrHeadAndTailAlignment htAlignment, + IxQMgrDispatchGroup group, + IxQMgrHeadAndTailShadowing shadowing, + void *qBaseAddress, + void *qHeadCountPtr, + void *qTailCountPtr) +{ + + void * head = NULL; + void * tail = NULL; + void * contentBuffer = NULL; + IX_STATUS status = IX_SUCCESS; + IxQMgrQId newQueueNum =IX_QMGR_MAX_NUM_QUEUES; /*set to invalid number*/ + UINT32 qLoopCounter =0; + + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Entering ixQMgrQConfig\n"); + + if (!ixQMgrInitialised) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrQConfig: " + "ixQMgr component not initialised\n"); + ixQMgrComponentStats.numCfgs.fail ++; + ixOsalMutexUnlock (&qMgrConfigMutex); + + return ICP_STATUS_FAIL; + } + else + { + status = ixOsalMutexLock (&qMgrConfigMutex, IX_OSAL_WAIT_NONE); + if (IX_SUCCESS != status) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrQConfig: " + "Can not get Mutex - please retry\n"); + return ICP_STATUS_RESOURCE; + } + + /*check that the max amount of queue's have not been configured*/ + if (numQsConfigured >= IX_QMGR_MAX_NUM_QUEUES) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQConfig: " + "Maximum number of Queues Configured\n"); + ixQMgrComponentStats.numCfgs.fail ++; + ixOsalMutexUnlock (&qMgrConfigMutex); + return ICP_STATUS_RESOURCE; + } + + /* + * Check to make sure that the qEntry size is not more then the + * max OR is not a power of two (i.e. not 1,2,4,8 etc.) + */ + if ((qEntrySize > IX_QMGR_Q_ENTRY_MAX_SIZE) || + (qEntrySize != ixQMgrNearestPowerOfTwoGet_p(qEntrySize))) + { + + IX_QMGR_REPORT_ERROR ("ixQMgrQConfig: " + "invalid qEntrySize parameter\n"); + ixQMgrComponentStats.numCfgs.fail ++; + ixOsalMutexUnlock (&qMgrConfigMutex); + return ICP_STATUS_INVALID_PARAM; + } + + if (((qSize * (qEntrySize*IX_QMGR_SIZEOF_WORD)) > IX_QMGR_Q_MAX_SIZE) || + (qSize != ixQMgrNearestPowerOfTwoGet_p(qSize))) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQConfig: " + "invalid qSize parameter, " + "for this entrySize\n"); + ixQMgrComponentStats.numCfgs.fail ++; + ixOsalMutexUnlock (&qMgrConfigMutex); + return ICP_STATUS_INVALID_PARAM; + } + + if (group >= IX_QMGR_MAX_NUM_DISPATCH_GRP) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQConfig: " + "invalid group parameter\n"); + ixQMgrComponentStats.numCfgs.fail ++; + ixOsalMutexUnlock (&qMgrConfigMutex); + return ICP_STATUS_INVALID_PARAM; + } + if (qBaseAddress == NULL) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQConfig: " + "invalid qBaseAddress parameter\n"); + ixQMgrComponentStats.numCfgs.fail ++; + ixOsalMutexUnlock (&qMgrConfigMutex); + return ICP_STATUS_INVALID_PARAM; + } + else + { + contentBuffer = qBaseAddress; + } + if (qHeadCountPtr == NULL) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQConfig: " + "invalid qHeadCountPtr parameter\n"); + ixQMgrComponentStats.numCfgs.fail ++; + ixOsalMutexUnlock (&qMgrConfigMutex); + return ICP_STATUS_INVALID_PARAM; + } + else + { + head = qHeadCountPtr; + } + if (qTailCountPtr == NULL) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQConfig: " + "invalid qTailCountPtr parameter\n"); + ixQMgrComponentStats.numCfgs.fail ++; + ixOsalMutexUnlock (&qMgrConfigMutex); + return ICP_STATUS_INVALID_PARAM; + } + + /*check HtAlignment parameter*/ + if(IX_QMGR_ENUM_IS_INVALID(htAlignment, IX_QMGR_Q_ALIGN_INVALID)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQConfig: " + "invalid htAlignment parameter\n"); + ixQMgrComponentStats.numCfgs.fail ++; + ixOsalMutexUnlock (&qMgrConfigMutex); + return ICP_STATUS_INVALID_PARAM; + } + + /*check Htcountformat parameter*/ + if(IX_QMGR_ENUM_IS_INVALID(htCountFormat, IX_QMGR_Q_COUNT_INVALID)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQConfig: " + "invalid htCountFormat parameter\n"); + ixQMgrComponentStats.numCfgs.fail ++; + ixOsalMutexUnlock (&qMgrConfigMutex); + return ICP_STATUS_INVALID_PARAM; + } + /*check for unsupported alignment and format combination*/ + if((htAlignment == IX_QMGR_Q_ALIGN_BYTE) && + (htCountFormat == IX_QMGR_Q_COUNT_BYTES)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQConfig: " + "Byte counting format is not supported with a" + "byte aligned Head and Tail\n"); + ixQMgrComponentStats.numCfgs.fail ++; + ixOsalMutexUnlock (&qMgrConfigMutex); + return ICP_STATUS_INVALID_PARAM; + } + + /*Check for unsupported shadowing parameter */ + if((shadowing != IX_QMGR_Q_NO_SHADOWING) && + (shadowing != IX_QMGR_Q_SHADOW_TAIL_ONLY)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQConfig: " + "invalid shadowing option: " + "IX_QMGR_Q_NO_SHADOWING and " + "IX_QMGR_Q_SHADOW_TAIL_ONLY currently " + "supported\n"); + ixQMgrComponentStats.numCfgs.fail ++; + ixOsalMutexUnlock (&qMgrConfigMutex); + return ICP_STATUS_INVALID_PARAM; + } + + /*Check for unsupported shadowing and count format combination */ + if((shadowing == IX_QMGR_Q_SHADOW_TAIL_ONLY) && + (htCountFormat == IX_QMGR_Q_COUNT_BYTES)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQConfig: " + "Shadowing is not supported on a queue that" + " has IX_QMGR_Q_COUNT_ENTRIES count format\n"); + ixQMgrComponentStats.numCfgs.fail ++; + ixOsalMutexUnlock (&qMgrConfigMutex); + return ICP_STATUS_INVALID_PARAM; + } + + /*find the first unconfigured queue in the array of queues*/ + /*Has to be one free as numQsConfiged < MAX_QUEUES*/ + for (qLoopCounter =0; + qLoopCounter <IX_QMGR_MAX_NUM_QUEUES; + qLoopCounter ++) + { + if(ixQMgrQueues[qLoopCounter].group == IX_QMGR_MAX_NUM_DISPATCH_GRP) + { + /*save the location of it*/ + newQueueNum = qLoopCounter; + /*no need to run the loop again*/ + break; + + } + } + /* + * if newQueueNum doesn't now have a valid q number then serious error. + * numqsconfiged indicated there was at least one unconfigured queue + * but we couldn't find it. + */ + if (newQueueNum == IX_QMGR_MAX_NUM_QUEUES) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQConfig: " + "Num of Queues corrupted\n"); + ixQMgrComponentStats.numCfgs.fail ++; + ixOsalMutexUnlock (&qMgrConfigMutex); + return ICP_STATUS_RESOURCE; + } + + + /* + * Check if head and tail is byte aligned that qSize will not overflow + * the head and tail. Word aligned type queues implicitly tested above. + */ + if ((htAlignment == IX_QMGR_Q_ALIGN_BYTE) + && (qSize > IX_QMGR_MAX_BYTE_COUNT)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQConfig: " + "invalid qSize parameter - for a byte aligned " + "queue\n"); + ixQMgrComponentStats.numCfgs.fail ++; + ixOsalMutexUnlock (&qMgrConfigMutex); + return ICP_STATUS_INVALID_PARAM; + } + + + /*Check if we should use real tail counter or shadow tail counter*/ + if (shadowing == IX_QMGR_Q_SHADOW_TAIL_ONLY) + { + if (htAlignment == IX_QMGR_Q_ALIGN_BYTE) + { + /*Set the tail to use our shadow tail*/ + tail = + &(ixQMgrQueues[newQueueNum].shadowInfo.byteShadowTailCounter); + /*Store the real tail as need for ixQMgrShadowAdvance/DeltaGet*/ + ixQMgrQueues[newQueueNum].shadowInfo.byteRealTailCounter = + qTailCountPtr; + } + else + { + /*Set the tail to use our shadow tail*/ + tail = + &(ixQMgrQueues[newQueueNum].shadowInfo.wordShadowTailCounter); + /*Store the real tail as need for ixQMgrShadowAdvance/DeltaGet*/ + ixQMgrQueues[newQueueNum].shadowInfo.wordRealTailCounter = + qTailCountPtr; + } + } + else + { + /* Already checked against it being NULL. No shadowing => set the + * tail to user supplied tail + */ + tail = qTailCountPtr; + } + + IX_QMGR_TRACE0 (IX_QMGR_DEBUG, + "Configure the Queue\n"); + + /* Configure the Queue */ + IX_SWQ_STATIC_INIT(ixQMgrQueues[newQueueNum].queue, + IxQMgrQEntryType, + qSize, + qEntrySize, + contentBuffer, + head, + tail, + htCountFormat, + htAlignment); + + + /* set/reset data for this Queue */ + if (NULL != qName) + { + strncpy(ixQMgrQueues[newQueueNum].qName,qName,IX_QMGR_MAX_QNAME_LEN); + } + else + { + strncpy(ixQMgrQueues[newQueueNum].qName, "No name Queue", + QMGR_DEFAULT_Q_NAME_LEN); + } + ixQMgrQueues[newQueueNum].callback= dummyCallback; + ixQMgrQueues[newQueueNum].callbackId = 0; + ixQMgrQueues[newQueueNum].waterMark = 0; + ixQMgrQueues[newQueueNum].group = group; + ixQMgrQueues[newQueueNum].notifCond = IX_QMGR_Q_SOURCE_INVALID; + ixQMgrQueues[newQueueNum].qSize = qSize; + ixQMgrQueues[newQueueNum].qEntrySize = qEntrySize; + ixQMgrQueues[newQueueNum].nextQId = IX_QMGR_MAX_NUM_QUEUES; + ixQMgrQueues[newQueueNum].prevQId = IX_QMGR_MAX_NUM_QUEUES; + ixQMgrQueues[newQueueNum].htCountFormat = htCountFormat; + ixQMgrQueues[newQueueNum].htAlignment = htAlignment; + ixQMgrQueues[newQueueNum].shadowing = shadowing; + + *qId = newQueueNum; + + numQsConfigured ++; + ixQMgrComponentStats.numCfgs.success ++; + + } + + ixOsalMutexUnlock (&qMgrConfigMutex); + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Exiting ixQMgrQConfig\n"); + return ICP_STATUS_SUCCESS; +} + +icp_status_t +ixQMgrQWriteRollbackWithChecks(IxQMgrQId qId, + UINT32 numEntries) +{ + IxQMgrQueue *info = NULL; + + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Entering ixQMgrQWriteRollbackWithChecks\n"); + if (!ixQMgrInitialised) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrQWriteRollbackWithChecks: " + "ixQMgr component not initialised\n"); + return ICP_STATUS_FAIL; + } + if (qId >= IX_QMGR_MAX_NUM_QUEUES) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQWriteRollbackWithChecks: " + "invalid qId\n"); + return ICP_STATUS_INVALID_PARAM; + } + + info = &ixQMgrQueues[qId]; + if (!IX_SWQ_INITIALISED(info->queue)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQWriteRollbackWithChecks: " + "Queue not configured\n"); + return ICP_STATUS_INVALID_PARAM; + } + + if (numEntries == 0) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQWriteRollbackWithChecks: " + "Not possible to rollback by 0 entries\n"); + return ICP_STATUS_INVALID_PARAM; + } + + if (info->htCountFormat == IX_QMGR_Q_COUNT_BYTES) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQWriteRollbackWithChecks: " + "Queue is not a count by entry queue\n"); + return ICP_STATUS_RESOURCE; + } + + if(numEntries > info->qSize) + { + /* + * Can't rollback by more entries then the max amount of possible + * entries in a queue. + */ + IX_QMGR_REPORT_ERROR ("ixQMgrQWriteRollbackWithChecks: " + "Not possible to rollback head counter by more " + " than the max possible amount of " + "entries in the queue\n"); + return ICP_STATUS_FAIL; + } + /* + * As this queue is using shadowing, the check in inline function will be + * against the shadow tail counter. We'll add a check against the real tail + * counter in this function + */ + + if (info->htAlignment == IX_QMGR_Q_ALIGN_BYTE) + { + /* + * if numEntries is greater then the (head - realTail), + * then this is not allowed + */ + IX_SWQ_CACHE_INVALIDATE((info->shadowInfo.byteRealTailCounter), + IX_QMGR_SIZEOF_BYTE); + + if(numEntries > + (((IX_SWQ_BE_SHARED_BYTE_READ(IX_SWQ_BA_CE_HEAD_PTR(info->queue)))) - + (*(info->shadowInfo.byteRealTailCounter)))) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQWriteRollbackWithChecks: " + "Not possible to rollback head counter by " + "more than the delta between the head and " + "real tail\n"); + return ICP_STATUS_FAIL; + } + } + else + { + /* + * if numEntries is greater then the (head - realTail), + * then this is not allowed + */ + IX_SWQ_CACHE_INVALIDATE((info->shadowInfo.wordRealTailCounter), + IX_QMGR_SIZEOF_WORD); + + if(numEntries > + ((IX_SWQ_BE_SHARED_LONG_READ(IX_SWQ_WA_CE_HEAD_PTR(info->queue))) - + (IX_SWQ_BE_SHARED_LONG_READ(info->shadowInfo.wordRealTailCounter)))) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQWriteRollbackWithChecks: " + "Not possible to rollback head counter by " + "more than the delta between the head and " + "real tail\n"); + return ICP_STATUS_FAIL; + } + } + + /*All checks have passed. Call the inline function*/ + return ixQMgrQWriteRollback(qId, numEntries); +} + + +icp_status_t +ixQMgrShadowAdvanceWithChecks(IxQMgrQId qId, + IxQMgrHeadAndTailShadowing shadowingCounterType, + UINT32 numEntries) +{ + IxQMgrQueue *info = NULL; + + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Entering ixQMgrShadowAdvanceWithChecks\n"); + + if (!ixQMgrInitialised) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrShadowAdvanceWithChecks: " + "ixQMgr component not initialised\n"); + return ICP_STATUS_FAIL; + } + if (qId >= IX_QMGR_MAX_NUM_QUEUES) + { + IX_QMGR_REPORT_ERROR ("ixQMgrShadowAdvanceWithChecks: " + "invalid qId\n"); + return ICP_STATUS_INVALID_PARAM; + } + + info = &ixQMgrQueues[qId]; + if (!IX_SWQ_INITIALISED(info->queue)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrShadowAdvanceWithChecks: " + "Queue not configured\n"); + return ICP_STATUS_INVALID_PARAM; + } + + if(shadowingCounterType != IX_QMGR_Q_SHADOW_TAIL_ONLY) + { + IX_QMGR_REPORT_ERROR ("ixQMgrShadowAdvanceWithChecks: " + "IX_QMGR_Q_SHADOW_TAIL_ONLY is the only " + "valid enum value supported\n"); + return ICP_STATUS_INVALID_PARAM; + } + + if (numEntries == 0) + { + IX_QMGR_REPORT_ERROR ("ixQMgrShadowAdvanceWithChecks: " + "Not possible to advance the shadow " + " register by 0\n"); + return ICP_STATUS_INVALID_PARAM; + } + + if (info->htCountFormat == IX_QMGR_Q_COUNT_BYTES) + { + IX_QMGR_REPORT_ERROR ("ixQMgrShadowAdvanceWithChecks: " + "Queue is not a count by entry queue\n"); + return ICP_STATUS_RESOURCE; + } + + if (info->shadowing != IX_QMGR_Q_SHADOW_TAIL_ONLY) + { + IX_QMGR_REPORT_ERROR ("ixQMgrShadowAdvanceWithChecks: " + "Queue does not use tail shadowing\n"); + return ICP_STATUS_RESOURCE; + } + if(numEntries > info->qSize) + { + /* + * They're can't be more more of delta between the shadow tail + * and the real tail then there are entries + */ + IX_QMGR_REPORT_ERROR ("ixQMgrShadowAdvanceWithChecks: " + "Not possible to advance the shadow " + "register by more than" + " the amount of entries in the queue\n"); + return ICP_STATUS_FAIL; + } + + /*All checks have passed. Call the inline function*/ + return ixQMgrShadowAdvance(qId, shadowingCounterType, numEntries); +} + + +icp_status_t +ixQMgrShadowDeltaGetWithChecks( + IxQMgrQId qId, + IxQMgrHeadAndTailShadowing shadowingCounterType, + UINT32 *numEntries) +{ + IxQMgrQueue *info = NULL; + + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Entering ixQMgrShadowDeltaGetWithChecks\n"); + + if (!ixQMgrInitialised) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrShadowDeltaGetWithChecks: " + "ixQMgr component not initialised\n"); + return ICP_STATUS_FAIL; + } + if (qId >= IX_QMGR_MAX_NUM_QUEUES) + { + IX_QMGR_REPORT_ERROR ("ixQMgrShadowDeltaGetWithChecks: " + "invalid qId\n"); + return ICP_STATUS_INVALID_PARAM; + } + + info = &ixQMgrQueues[qId]; + if (!IX_SWQ_INITIALISED(info->queue)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrShadowDeltaGetWithChecks: " + "Queue not configured\n"); + return ICP_STATUS_INVALID_PARAM; + } + + if(shadowingCounterType != IX_QMGR_Q_SHADOW_TAIL_ONLY) + { + IX_QMGR_REPORT_ERROR ("ixQMgrShadowDeltaGetWithChecks: " + "IX_QMGR_Q_SHADOW_TAIL_ONLY only supported\n"); + return ICP_STATUS_INVALID_PARAM; + } + + if (info->htCountFormat != IX_QMGR_Q_COUNT_ENTRIES) + { + IX_QMGR_REPORT_ERROR ("ixQMgrShadowDeltaGetWithChecks: " + "Queue is not a count by entry queue\n"); + return ICP_STATUS_RESOURCE; + } + + if (info->shadowing != IX_QMGR_Q_SHADOW_TAIL_ONLY) + { + IX_QMGR_REPORT_ERROR ("ixQMgrShadowDeltaGetWithChecks: " + "Queue does not use tail shadowing\n"); + return ICP_STATUS_RESOURCE; + } + if(numEntries == NULL) + { + IX_QMGR_REPORT_ERROR ("ixQMgrShadowDeltaGetWithChecks: " + "numEntries == NULL \n"); + return ICP_STATUS_INVALID_PARAM; + } + + + /*All checks have passed. Call the inline function*/ + return ixQMgrShadowDeltaGet(qId, shadowingCounterType, numEntries); +} + + + +/** + * Unconfigure a group + */ +icp_status_t +ixQMgrUnconfigGroup(IxQMgrDispatchGroup group) +{ + UINT32 qId =0; + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Entering ixQMgrUnconfigGroup\n"); + + if (!ixQMgrInitialised) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrUnconfigGroup: " + "ixQMgr component not initialised\n"); + return ICP_STATUS_FAIL; + } + + if (group >= IX_QMGR_MAX_NUM_DISPATCH_GRP) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrUnconfigGroup: " + "invalid group\n"); + return ICP_STATUS_INVALID_PARAM; + } + + + /*find each queue in the group and reset it */ + for (qId =0; qId < IX_QMGR_MAX_NUM_QUEUES; qId ++) + { + if (ixQMgrQueues[qId].group == group) + { + /*reset the queue*/ + ixQMgrResetQueue_p(qId); + /*decrement the numQsConfigured */ + numQsConfigured --; + } + } + + /*no queues in the group anymore, so reset the group lists*/ + ixQMgrLastQInGrpList[group] = IX_QMGR_MAX_NUM_QUEUES; + ixQMgrFirstQInGrpList[group] = IX_QMGR_MAX_NUM_QUEUES; + + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Exiting ixQMgrUnconfigGroup\n"); + + return ICP_STATUS_SUCCESS; +} + + + +/* Check the number of entries in the queue depending on its type */ +inline icp_status_t +ixQMgrQEmptyCheck (IxQMgrQueue *info) +{ + if (info->htCountFormat == IX_QMGR_Q_COUNT_BYTES) + { + /*Check to see if the queue is empty */ + if (!IX_SWQ_WA_CB_QUEUE_EMPTY(info->queue)) + { + return ICP_STATUS_RESOURCE; + } + } + else + { + if(info->htAlignment == IX_QMGR_Q_ALIGN_WORD) + { + + IX_SWQ_WA_HEAD_INVALIDATE(info->queue); + IX_SWQ_WA_TAIL_INVALIDATE(info->queue); + /*Check to see if the queue is empty */ + if (!IX_SWQ_WA_CE_QUEUE_EMPTY(info->queue)) + { + return ICP_STATUS_RESOURCE; + } + } + else + { + IX_SWQ_BA_HEAD_INVALIDATE(info->queue); + IX_SWQ_BA_TAIL_INVALIDATE(info->queue); + /*Check to see if the queue is empty */ + if (!IX_SWQ_BA_CE_QUEUE_EMPTY(info->queue)) + { + return ICP_STATUS_RESOURCE; + } + } + } + return ICP_STATUS_SUCCESS; +} + + +/* Initialise the Queue appropriately depending on the Queue Type */ +inline void +ixQMgrQInit(IxQMgrQueue *info, + IxQMgrQSize qSize) +{ + if (info->htCountFormat == IX_QMGR_Q_COUNT_BYTES) + { + IX_SWQ_STATIC_INIT(info->queue, + IxQMgrQEntryType, + qSize, + info->qEntrySize, + IX_SWQ_CONTENT_PTR(info->queue), + (void *)IX_SWQ_WA_CB_HEAD_PTR(info->queue), + (void *)IX_SWQ_WA_CB_TAIL_PTR(info->queue), + info->htCountFormat, + info->htAlignment); + } + else + { + if(info->htAlignment == IX_QMGR_Q_ALIGN_WORD) + { + IX_SWQ_STATIC_INIT(info->queue, + IxQMgrQEntryType, + qSize, + info->qEntrySize, + IX_SWQ_CONTENT_PTR(info->queue), + (void *)IX_SWQ_WA_CE_HEAD_PTR(info->queue), + (void *)IX_SWQ_WA_CE_TAIL_PTR(info->queue), + info->htCountFormat, + info->htAlignment); + } + else + { + IX_SWQ_STATIC_INIT(info->queue, + IxQMgrQEntryType, + qSize, + info->qEntrySize, + IX_SWQ_CONTENT_PTR(info->queue), + (void *)IX_SWQ_BA_CE_HEAD_PTR(info->queue), + (void *)IX_SWQ_BA_CE_TAIL_PTR(info->queue), + info->htCountFormat, + info->htAlignment); + } + } +} + +icp_status_t +ixQMgrQSizeReconfig (IxQMgrQId qId, IxQMgrQSize qSize) +{ + IxQMgrQueue *info = NULL; + + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Entering ixQMgrQSizeReconfig\n"); + if (!ixQMgrInitialised) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrQSizeReconfig: " + "ixQMgr component not initialised\n"); + ixQMgrComponentStats.numQSizeReconfig.fail ++; + return ICP_STATUS_FAIL; + } + + /*check that the QId has already been configured*/ + if ((qId >= IX_QMGR_MAX_NUM_QUEUES) || + (ixQMgrQueues[qId].group == IX_QMGR_MAX_NUM_DISPATCH_GRP)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQSizeReconfig: " + "Invalid Q \n"); + ixQMgrComponentStats.numQSizeReconfig.fail ++; + return ICP_STATUS_INVALID_PARAM; + } + + info = &ixQMgrQueues[qId]; + + /*Check to ensure qSize is not too big and is a power of two */ + if (((qSize * (info->qEntrySize)) > IX_QMGR_Q_MAX_SIZE) || + (qSize != ixQMgrNearestPowerOfTwoGet_p(qSize))) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQConfig: " + "invalid qSize parameter\n"); + ixQMgrComponentStats.numQSizeReconfig.fail ++; + return ICP_STATUS_INVALID_PARAM; + } + + + /* + * Check if head and tail is byte aligned that the qSize will not overflow + * the head and tail. Word aligned type queues implicitly tested above. + */ + if ((info->htAlignment == IX_QMGR_Q_ALIGN_BYTE) + && (qSize > IX_QMGR_MAX_BYTE_COUNT)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQSizeReconfig: " + "invalid qSize parameter - for a byte " + "aligned queue\n"); + ixQMgrComponentStats.numQSizeReconfig.fail ++; + return ICP_STATUS_INVALID_PARAM; + } + + + if (ICP_STATUS_SUCCESS != ixQMgrQEmptyCheck(info)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQSizeReconfig: " + "Q is not empty \n"); + ixQMgrComponentStats.numQSizeReconfig.fail ++; + return ICP_STATUS_RESOURCE; + } + + /*Check to see if notifications are disabled for the queue*/ + if (info->notifCond != IX_QMGR_Q_SOURCE_INVALID) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQSizeReconfig: " + "Q Notifications are not disabled\n"); + ixQMgrComponentStats.numQSizeReconfig.fail ++; + return ICP_STATUS_RESOURCE; + } + + /*Reset the waterMark and the head and tail*/ + info->waterMark = 0; + + /* + * Call the appropriate MACROS to reonfigure the lowlevel queue with the + * new qSize and all other parameters the same as the previous configure + */ + ixQMgrQInit(info,qSize); + + /*change the high level queue struct qSize*/ + info->qSize = qSize; + + + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Exiting ixQMgrQSizeReconfig\n"); + ixQMgrComponentStats.numQSizeReconfig.success ++; + return ICP_STATUS_SUCCESS; +} + +/** + * Return the size of a queue in entries + */ +icp_status_t +ixQMgrQSizeGet (IxQMgrQId qId, + IxQMgrQSize *qSize) +{ + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Entering ixQMgrQSizeGet\n"); + if (!ixQMgrInitialised) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrQSizeGet: " + "ixQMgr component not initialised\n"); + return ICP_STATUS_FAIL; + } + else if (qId >= IX_QMGR_MAX_NUM_QUEUES) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQSizeGet: " + "invalid qId\n"); + return ICP_STATUS_INVALID_PARAM; + } + else if (qSize == NULL) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQSizeGet: " + "invalid pointer to a qSize\n"); + return ICP_STATUS_INVALID_PARAM; + } + else + { + if (!IX_SWQ_INITIALISED(ixQMgrQueues[qId].queue)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQSizeGet: " + "Q not configured\n"); + return ICP_STATUS_INVALID_PARAM; + } + else + { + *qSize = ixQMgrQueues[qId].qSize; + } + } + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Exiting ixQMgrQSizeGet\n"); + return ICP_STATUS_SUCCESS; +} + + +/** + * Set the Watermark of a queue + */ +icp_status_t +ixQMgrWatermarkSet (IxQMgrQId qId, + IxQMgrWMLevel waterM) +{ + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Entering ixQMgrWatermarkSet\n"); + if (!ixQMgrInitialised) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrWatermarkSet: " + "ixQMgr component not initialised\n"); + ixQMgrComponentStats.numWMSets.fail ++; + return ICP_STATUS_FAIL; + } + else if (qId >= IX_QMGR_MAX_NUM_QUEUES) + { + IX_QMGR_REPORT_ERROR ("ixQMgrWatermarkSet: " + "invalid qId\n"); + ixQMgrComponentStats.numWMSets.fail ++; + return ICP_STATUS_INVALID_PARAM; + } + else + { + if( !IX_SWQ_INITIALISED(ixQMgrQueues[qId].queue)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrWatermarkSet: " + "Q not configured\n"); + ixQMgrComponentStats.numWMSets.fail ++; + return ICP_STATUS_INVALID_PARAM; + } + else if ((waterM >= IX_SWQ_SIZE(ixQMgrQueues[qId].queue)) || + (waterM == 0)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrWatermarkSet: " + "invalid Watermark\n"); + ixQMgrComponentStats.numWMSets.fail ++; + return ICP_STATUS_INVALID_PARAM; + } + + ixQMgrQueues[qId].waterMark = waterM; + IX_QMGR_TRACE2 (IX_QMGR_DEBUG, + "Setting WM for Q %d to %d\n", + qId, + ixQMgrQueues[qId].waterMark); + ixQMgrComponentStats.numWMSets.success ++; + + } + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Exiting ixQMgrWatermarkSet\n"); + return ICP_STATUS_SUCCESS; +} + +/* ------------------------------------------------------------ + Queue access related functions + ------------------------------------------------------------ */ + +/** + * Read an entry from a queue + */ +icp_status_t +ixQMgrQReadWithChecks (IxQMgrQId qId, + IxQMgrQEntryType *entryPtr) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Entering ixQMgrQReadWithChecks\n"); + if (!ixQMgrInitialised) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrQReadWithChecks: " + "ixQMgr component not initialised\n"); + + ixQMgrComponentStats.numReads.fail ++; + return ICP_STATUS_FAIL; + } + if ( qId >= IX_QMGR_MAX_NUM_QUEUES) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQReadWithChecks: " + "Invalid QId\n"); + ixQMgrComponentStats.numReads.fail ++; + return ICP_STATUS_INVALID_PARAM; + } + if ( entryPtr == NULL) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQReadWithChecks: " + "Invalid entryPtr\n"); + ixQMgrComponentStats.numReads.fail ++; + return ICP_STATUS_INVALID_PARAM; + } + /* Check Q is Initialised, Check Q is not empty */ + if (!IX_SWQ_INITIALISED(ixQMgrQueues[qId].queue)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQReadWithChecks: " + "Queue not initialised\n"); + ixQMgrComponentStats.numReads.fail ++; + return ICP_STATUS_INVALID_PARAM; + + } + else + { + status = ixQMgrQRead (qId, + entryPtr); + } + if (status == ICP_STATUS_SUCCESS) + { + ixQMgrComponentStats.numReads.success ++; + } + else + { + IX_QMGR_REPORT_ERROR ("ixQMgrQReadWithChecks: " + "Queue Empty\n"); + ixQMgrComponentStats.numReads.fail ++; + } + + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Exiting ixQMgrQReadWithChecks\n"); + return status; +} + + +/** + * Write an entry to a Software Queue + */ +icp_status_t +ixQMgrQWriteWithChecks (IxQMgrQId qId, + IxQMgrQEntryType *entry) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Entering ixQMgrQWriteWithChecks\n"); + if (!ixQMgrInitialised) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrQWriteWithChecks: " + "ixQMgr component not initialised\n"); + ixQMgrComponentStats.numWrites.fail ++; + return ICP_STATUS_FAIL; + } + if ( qId >= IX_QMGR_MAX_NUM_QUEUES) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQWriteWithChecks: " + "Invalid QId\n"); + ixQMgrComponentStats.numWrites.fail ++; + return ICP_STATUS_INVALID_PARAM; + } + if ( entry == NULL) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQWriteWithChecks: " + "Invalid entry\n"); + ixQMgrComponentStats.numWrites.fail ++; + return ICP_STATUS_INVALID_PARAM; + } + + if (!IX_SWQ_INITIALISED(ixQMgrQueues[qId].queue)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQWriteWithChecks: " + "Queue not initialised\n"); + ixQMgrComponentStats.numWrites.fail ++; + return ICP_STATUS_INVALID_PARAM; + } + else + { + /* Use inline function after checking */ + status = ixQMgrQWrite (qId, entry); + } + + if (status == ICP_STATUS_SUCCESS) + { + ixQMgrComponentStats.numWrites.success ++; + } + else + { + IX_QMGR_REPORT_ERROR ("ixQMgrQWriteWithChecks: " + "Queue Overflow\n"); + ixQMgrComponentStats.numWrites.fail ++; + } + + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Exiting ixQMgrQWriteWithChecks\n"); + return status; +} + +/** + * Get a snapshot of the number of entries in a queue + */ +icp_status_t +ixQMgrQNumEntriesGetWithChecks (IxQMgrQId qId, + UINT32 *numEntries) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Entering ixQMgrQNumEntriesGetWithChecks\n"); + if (!ixQMgrInitialised) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrQNumEntriesGetWithChecks: " + "ixQMgr component not initialised\n"); + return ICP_STATUS_FAIL; + } + if ( qId >= IX_QMGR_MAX_NUM_QUEUES) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQNumEntriesGetWithChecks: " + "Invalid QId\n"); + return ICP_STATUS_INVALID_PARAM; + } + if ( numEntries == NULL ) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQNumEntriesGetWithChecks: " + "Invalid NumEntries\n"); + return ICP_STATUS_INVALID_PARAM; + } + if (!IX_SWQ_INITIALISED(ixQMgrQueues[qId].queue)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQNumEntriesGetWithChecks: " + "Q not configured\n"); + return ICP_STATUS_INVALID_PARAM; + } + else + { + /* Read Entry using inline function */ + status = ixQMgrQNumEntriesGet (qId, + numEntries); + } + + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Exiting ixQMgrQNumEntriesGetWithChecks\n"); + return status; +} + +/** + * Get a queues status + */ +icp_status_t +ixQMgrQStatusGetWithChecks (IxQMgrQId qId, + IxQMgrQState *qState) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Entering ixQMgrQStatusGetWithchecks\n"); + if (!ixQMgrInitialised) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrQStatusGetWithChecks:" + "ixQMgr component not initialised\n"); + return ICP_STATUS_FAIL; + } + else if (qState == NULL) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQWriteWithChecks: " + "Invalid qState Addr\n"); + return ICP_STATUS_INVALID_PARAM; + } + else if (qId >= IX_QMGR_MAX_NUM_QUEUES) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQStatusGetWithChecks: " + "Invalid QId\n"); + return ICP_STATUS_INVALID_PARAM; + } + else + { + if (!IX_SWQ_INITIALISED(ixQMgrQueues[qId].queue)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQWriteWithChecks: " + "Q Not Configured\n"); + return ICP_STATUS_INVALID_PARAM; + } + else + { + status = ixQMgrQStatusGet (qId, + qState); + } + } + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Exiting ixQMgrQStatusGetWithChecks\n"); + return status; +} + + + +/* ------------------------------------------------------------ + Queue dispatch related functions + ---------------------------------------------------------- */ + +/** + * Enable notification on a queue for a specified queue State + */ +icp_status_t +ixQMgrNotificationEnable (IxQMgrQId qId, + IxQMgrNotificationCondition sourceId) +{ + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Entering ixQMgrNotificationEnable\n"); + if (!ixQMgrInitialised) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrNotificationEnable: " + "ixQMgr component not initialised\n"); + ixQMgrComponentStats.numNotifEnable.fail ++; + return ICP_STATUS_FAIL; + } + else if (IX_QMGR_ENUM_IS_INVALID(sourceId, IX_QMGR_Q_SOURCE_INVALID)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrNotificationenable:" + "invalid Condition\n"); + ixQMgrComponentStats.numNotifEnable.fail ++; + return ICP_STATUS_INVALID_PARAM; + } + else if (qId >= IX_QMGR_MAX_NUM_QUEUES) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrNotificationenable:" + "invalid Q Id\n"); + ixQMgrComponentStats.numNotifEnable.fail ++; + return ICP_STATUS_INVALID_PARAM; + } + else + { + if (!IX_SWQ_INITIALISED(ixQMgrQueues[qId].queue)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrNotificationEnable:" + "Q not initialised\n"); + ixQMgrComponentStats.numNotifEnable.fail ++; + return ICP_STATUS_INVALID_PARAM; + } + else if (ixQMgrQueues[qId].notifCond != IX_QMGR_Q_SOURCE_INVALID) + { + IX_QMGR_REPORT_ERROR ("ixQMgrNotificationEnable:" + "A Condition is already enabled\n"); + ixQMgrComponentStats.numNotifEnable.fail ++; + return ICP_STATUS_FAIL; + } + + /* set condition to trigger a notification */ + ixQMgrQueues[qId].notifCond = sourceId; + + /* add queue to group list for notification */ + ixQMgrQueues[qId].prevQId = IX_QMGR_MAX_NUM_QUEUES; + ixQMgrQueues[qId].nextQId = + ixQMgrFirstQInGrpList[ixQMgrQueues[qId].group]; + + if ( ixQMgrFirstQInGrpList[ixQMgrQueues[qId].group] != + IX_QMGR_MAX_NUM_QUEUES) + { + /* Group already has queues with notif enabled */ + ixQMgrQueues[ixQMgrQueues[qId].nextQId].prevQId = qId; + ixQMgrFirstQInGrpList[ixQMgrQueues[qId].group] = qId; + } + else + { + ixQMgrFirstQInGrpList[ixQMgrQueues[qId].group] = qId; + ixQMgrLastQInGrpList[ixQMgrQueues[qId].group] = qId; + } + IX_QMGR_TRACE3 (IX_QMGR_DEBUG, + "ixQMgrNotificationEnable: " + "Enabled Notification on Q %d\n belonging to group %d, " + "Starting Q %d\n", + qId, + ixQMgrQueues[qId].group, + ixQMgrFirstQInGrpList[ixQMgrQueues[qId].group]); + ixQMgrComponentStats.numNotifEnable.success ++; + + } + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Exiting ixQMgrNotificationEnable\n"); + return ICP_STATUS_SUCCESS; +} + +/** + * Disable notifications on a queue + */ +icp_status_t +ixQMgrNotificationDisable (IxQMgrQId qId) +{ + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Entering ixQMgrNotificationDisable\n"); + if (!ixQMgrInitialised) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrNotificationDisable: " + "ixQMgr component not initialised\n"); + ixQMgrComponentStats.numNotifDisable.fail ++; + return ICP_STATUS_FAIL; + } + else if ( qId >= IX_QMGR_MAX_NUM_QUEUES) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrNotificationDisable: " + "invalid Qid\n"); + ixQMgrComponentStats.numNotifDisable.fail ++; + return ICP_STATUS_INVALID_PARAM; + } + + /* Check Q is Initialised*/ + else + { + if (!IX_SWQ_INITIALISED(ixQMgrQueues[qId].queue)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrNotificationDisable: " + "Q not configured\n"); + ixQMgrComponentStats.numNotifDisable.fail ++; + return ICP_STATUS_INVALID_PARAM; + } + else if (ixQMgrQueues[qId].notifCond != IX_QMGR_Q_SOURCE_INVALID) + { + /* Notification was enabled on this queue so, + set condition to INVALID, + this will disable notification when Dispatcher runs */ + ixQMgrQueues[qId].notifCond = IX_QMGR_Q_SOURCE_INVALID; + + /* remove Queue from group list */ + if ( ixQMgrFirstQInGrpList[ixQMgrQueues[qId].group] == qId) + { + ixQMgrFirstQInGrpList[ixQMgrQueues[qId].group] + = ixQMgrQueues[qId].nextQId; + } + + if (ixQMgrQueues[qId].nextQId != IX_QMGR_MAX_NUM_QUEUES) + { + ixQMgrQueues[ixQMgrQueues[qId].nextQId].prevQId = + ixQMgrQueues[qId].prevQId; + } + + + if ( ixQMgrLastQInGrpList[ixQMgrQueues[qId].group] == qId) + { + ixQMgrLastQInGrpList[ixQMgrQueues[qId].group] + = ixQMgrQueues[qId].prevQId; + } + + if (ixQMgrQueues[qId].prevQId != IX_QMGR_MAX_NUM_QUEUES) + { + ixQMgrQueues[ixQMgrQueues[qId].prevQId].nextQId = + ixQMgrQueues[qId].nextQId; + } + + + ixQMgrComponentStats.numNotifDisable.success ++; + ixQMgrQueues[qId].nextQId = IX_QMGR_MAX_NUM_QUEUES; + ixQMgrQueues[qId].prevQId = IX_QMGR_MAX_NUM_QUEUES; + } + } + + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Exiting ixQMgrNotificationDisable\n"); + return ICP_STATUS_SUCCESS; +} + +/** + * Run the callback dispatcher, + * the first queue enabled for notification will be the first to be serviced. + */ +void +ixQMgrDispatcherLoopRun (IxQMgrDispatchGroup group) +{ + IxQMgrQId qId = 0; + IxQMgrQState qState; + IxQMgrNotificationCondition condition; + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Entering ixQMgrDispatcherLoopRun\n"); + +#ifndef NDEBUG + if (!ixQMgrInitialised) + { + IX_QMGR_REPORT_ERROR ("ixQMgrDispatcherLoopRun: " + "ixQMgr component not initialised\n"); + return; + } + else if (group >= IX_QMGR_MAX_NUM_DISPATCH_GRP) + { + IX_QMGR_REPORT_ERROR ("ixQMgrDispatcherLoopRun: " + "invalid group\n"); + return; + } +#endif + + /* preload the counters for the group of queues */ + IX_OSAL_CACHE_PRELOAD(ixQMgrGrpMemBaseInvalid[group], + ixQMgrGrpMemSize[group]); + + IX_QMGR_TRACE0 (IX_QMGR_DEBUG, + "ixQMgrDispatcherLoopRun: start searching...\n"); + qId = ixQMgrLastQInGrpList[group]; + while ( qId < IX_QMGR_MAX_NUM_QUEUES) + { + /* check if notification is enabled */ + if (ixQMgrQueues[qId].notifCond != IX_QMGR_Q_SOURCE_INVALID) + { + IX_QMGR_TRACE0 (IX_QMGR_DEBUG, + "ixQMgrDispatcherLoopRun: Notif enabled on this " + "queue\n"); + /* check state */ + ixQMgrQStatusGet(qId, &qState); + condition = ixQMgrQueues[qId].notifCond; + + if (condition == qState) + { + IX_QMGR_TRACE3 (IX_QMGR_DEBUG, + "ixQMgrDispatcherLoopRun: " + "Notification enabled on Queue %d, State %d, " + "Condition %d\n", + qId, + qState, + condition); + /* call callback function */ + ixQMgrQueues[qId].callback (qId, ixQMgrQueues[qId].callbackId); + } + else if (condition == IX_QMGR_Q_SOURCE_ID_NOT_E) + { + if (qState != IX_QMGR_Q_STATE_E) + { + IX_QMGR_TRACE3 (IX_QMGR_DEBUG, + "ixQMgrDispatcherLoopRun: " + "Notification enabled on Queue %d, " + "State %d, Condition %d\n", + qId, + qState, + condition); + /* call callback function */ + ixQMgrQueues[qId].callback (qId, + ixQMgrQueues[qId].callbackId); + } + } + else if (condition == IX_QMGR_Q_SOURCE_ID_NOT_F) + { + if (qState != IX_QMGR_Q_STATE_F) + { + IX_QMGR_TRACE3 (IX_QMGR_DEBUG, + "ixQMgrDispatcherLoopRun: " + "Notification enabled on Queue %d, " + "State %d, Condition %d\n", + qId, + qState, + condition); + /* call callback function */ + ixQMgrQueues[qId].callback (qId, + ixQMgrQueues[qId].callbackId); + } + } + } + qId = ixQMgrQueues[qId].prevQId; + } + IX_SWQ_CACHE_FLUSH(ixQMgrGrpMemBaseFlush[group], ixQMgrGrpMemSize[group]); + IX_SWQ_CACHE_INVALIDATE(ixQMgrGrpMemBaseInvalid[group], + ixQMgrGrpMemSize[group]); + + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Exiting ixQMgrDispatcherLoopRun\n"); +} + + +/** + * Run the callback dispatcher in the reverse order of notif enabling + * the first queue enabled for notification will be the last to be serviced. + */ +void +ixQMgrDispatcherLoopRunReverse (IxQMgrDispatchGroup group) +{ + IxQMgrQId qId = 0; + IxQMgrQState qState; + IxQMgrNotificationCondition condition; + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Entering ixQMgrDispatcherLoopRunReverse\n"); +#ifndef NDEBUG + if (!ixQMgrInitialised) + { + IX_QMGR_REPORT_ERROR ("ixQMgrDispatcherLoopRunReverse: " + "ixQMgr component not initialised\n"); + return; + } + else if (group >= IX_QMGR_MAX_NUM_DISPATCH_GRP) + { + IX_QMGR_REPORT_ERROR ("ixQMgrDispatcherLoopRunReverse: " + "invalid group\n"); + return; + } +#endif + + /* preload the counters for the group of queues */ + IX_OSAL_CACHE_PRELOAD(ixQMgrGrpMemBaseInvalid[group], + ixQMgrGrpMemSize[group]); + + IX_QMGR_TRACE0 (IX_QMGR_DEBUG, + "ixQMgrDispatcherLoopRunReverse: start searching...\n"); + qId = ixQMgrFirstQInGrpList[group]; + while ( qId < IX_QMGR_MAX_NUM_QUEUES) + { + /* check if notification is enabled */ + if (ixQMgrQueues[qId].notifCond != IX_QMGR_Q_SOURCE_INVALID) + { + IX_QMGR_TRACE0 (IX_QMGR_DEBUG, + "ixQMgrDispatcherLoopRunReverse: Notif enabled on " + "this queue\n"); + /* check state */ + ixQMgrQStatusGet(qId, &qState); + condition = ixQMgrQueues[qId].notifCond; + + if (condition == qState) + { + IX_QMGR_TRACE3 (IX_QMGR_DEBUG, + "ixQMgrDispatcherLoopRunReverse: " + "Notification enabled on Queue %d, State %d, " + "Condition %d\n", + qId, + qState, + condition); + /* call callback function */ + ixQMgrQueues[qId].callback (qId, ixQMgrQueues[qId].callbackId); + } + else if (condition == IX_QMGR_Q_SOURCE_ID_NOT_E) + { + if (qState != IX_QMGR_Q_STATE_E) + { + IX_QMGR_TRACE3 (IX_QMGR_DEBUG, + "ixQMgrDispatcherLoopRunReverse: " + "Notification enabled on Queue %d, " + "State %d, Condition %d\n", + qId, + qState, + condition); + /* call callback function */ + ixQMgrQueues[qId].callback (qId, + ixQMgrQueues[qId].callbackId); + } + } + else if (condition == IX_QMGR_Q_SOURCE_ID_NOT_F) + { + if (qState != IX_QMGR_Q_STATE_F) + { + IX_QMGR_TRACE3 (IX_QMGR_DEBUG, + "ixQMgrDispatcherLoopRunReverse: " + "Notification enabled on Queue %d, " + "State %d, Condition %d\n", + qId, + qState, + condition); + /* call callback function */ + ixQMgrQueues[qId].callback (qId, + ixQMgrQueues[qId].callbackId); + } + } + } + qId = ixQMgrQueues[qId].nextQId; + } + IX_SWQ_CACHE_FLUSH(ixQMgrGrpMemBaseFlush[group], ixQMgrGrpMemSize[group]); + IX_SWQ_CACHE_INVALIDATE(ixQMgrGrpMemBaseInvalid[group], + ixQMgrGrpMemSize[group]); + + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Exiting ixQMgrDispatcherLoopRunReverse\n"); +} + + +/** + * Set the notification callback for a queue + */ +icp_status_t +ixQMgrNotificationCallbackSet (IxQMgrQId qId, + IxQMgrCallback callback, + IxQMgrCallbackId callbackId) +{ + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Entering ixQMgrNotificationCallbackSet\n"); + if (!ixQMgrInitialised) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrNotificationCallbackSet :" + "ixQMgr component not initialised\n"); + ixQMgrComponentStats.numCallbackSet.fail ++; + return ICP_STATUS_FAIL; + } + else if (qId >= IX_QMGR_MAX_NUM_QUEUES) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrNotificationCallbackSet :" + "invalid Q Id\n"); + ixQMgrComponentStats.numCallbackSet.fail ++; + return ICP_STATUS_INVALID_PARAM; + } + else if (callback == NULL) + { + IX_QMGR_REPORT_ERROR ("ixQMgrNotificationCallbackSet :" + "invalid callback\n"); + ixQMgrComponentStats.numCallbackSet.fail ++; + return ICP_STATUS_INVALID_PARAM; + } + else + { + /* Check Q is Initialised, Source parameter is Valid*/ + if (!IX_SWQ_INITIALISED(ixQMgrQueues[qId].queue)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrNotificationCallbackSet :" + "Q not configured\n"); + ixQMgrComponentStats.numCallbackSet.fail ++; + return ICP_STATUS_INVALID_PARAM; + } + else + { + /* set condition to trigger a notification */ + ixQMgrQueues[qId].callback = callback; + ixQMgrQueues[qId].callbackId = callbackId; + ixQMgrComponentStats.numCallbackSet.success ++; + } + } + + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Exiting ixQMgrNotificationCallbackSet\n"); + return ICP_STATUS_SUCCESS; +} + diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_queue_manager/IxQMgrSymbols.c b/Acceleration/library/icp_telephony/tdm_infrastructure_queue_manager/IxQMgrSymbols.c new file mode 100644 index 0000000..c2f5571 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_queue_manager/IxQMgrSymbols.c @@ -0,0 +1,116 @@ +/***************************************************************************** + * @file IxQMgrSymbols.c + * + * @description Contents of this file provide the Software Queue Manager + * Component exported symbols. + * + * @ingroup qMgr + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + ****************************************************************************/ + + +#ifdef __linux + + +#include <IxOsal.h> + +#include <linux/module.h> +#include <IxQMgr.h> + +EXPORT_SYMBOL(ixQMgrInit); +EXPORT_SYMBOL(ixQMgrUnload); +EXPORT_SYMBOL(ixQMgrShow); +EXPORT_SYMBOL(ixQMgrQShow); +EXPORT_SYMBOL(ixQMgrGroupMemoryConfig); +EXPORT_SYMBOL(ixQMgrQConfig); +EXPORT_SYMBOL(ixQMgrQSizeReconfig); +EXPORT_SYMBOL(ixQMgrUnconfigGroup); +EXPORT_SYMBOL(ixQMgrQSizeGet); +EXPORT_SYMBOL(ixQMgrWatermarkSet); +EXPORT_SYMBOL(ixQMgrQReadWithChecks); +EXPORT_SYMBOL(ixQMgrQRead); +EXPORT_SYMBOL(ixQMgrQBurstRead); +EXPORT_SYMBOL(ixQMgrQReadAdvance); +EXPORT_SYMBOL(ixQMgrQWriteWithChecks); +EXPORT_SYMBOL(ixQMgrQWrite); +EXPORT_SYMBOL(ixQMgrQBurstWrite); +EXPORT_SYMBOL(ixQMgrQNumEntriesGetWithChecks); +EXPORT_SYMBOL(ixQMgrQNumEntriesGet); +EXPORT_SYMBOL(ixQMgrQStatusGetWithChecks); +EXPORT_SYMBOL(ixQMgrQStatusGet); +EXPORT_SYMBOL(ixQMgrNotificationEnable); +EXPORT_SYMBOL(ixQMgrNotificationDisable); +EXPORT_SYMBOL(ixQMgrDispatcherLoopRun); +EXPORT_SYMBOL(ixQMgrDispatcherLoopRunReverse); +EXPORT_SYMBOL(ixQMgrNotificationCallbackSet); +EXPORT_SYMBOL(ixQMgrShadowAdvanceWithChecks); +EXPORT_SYMBOL(ixQMgrShadowAdvance); +EXPORT_SYMBOL(ixQMgrShadowDeltaGetWithChecks); +EXPORT_SYMBOL(ixQMgrShadowDeltaGet); +EXPORT_SYMBOL(ixQMgrQWriteRollbackWithChecks); +EXPORT_SYMBOL(ixQMgrQWriteRollback); +EXPORT_SYMBOL(ixQMgrQueues); + +#endif diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_queue_manager/Makefile b/Acceleration/library/icp_telephony/tdm_infrastructure_queue_manager/Makefile new file mode 100644 index 0000000..5ce26ab --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_queue_manager/Makefile @@ -0,0 +1,123 @@ +######################################################################### +# +# Targets supported +# all - builds everything and installs +# install - identical to all +# depend - build dependencies +# clean - clears derived objects except the .depend files +# distclean- clears all derived objects and the .depend file +# +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# Contact Information: +# Intel Corporation +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# +############################################################################ + + +# Ensure The ICP_ENV_DIR environmental var is defined. +ifndef ICP_ENV_DIR +$(error ICP_ENV_DIR is undefined. Please set the path to your environment makefile \ + "-> setenv ICP_ENV_DIR <path>") +endif + +#Add your project environment Makefile +include $(ICP_ENV_DIR)/environment.mk + + +#include the makefile with all the default and common Make variable definitions +include $(ICP_BUILDSYSTEM_PATH)/build_files/common.mk + + +#Add the name for the executable, Library or Module output definitions +OUTPUT_NAME=$(ICP_TDM_QMGR_NAME) + + +# List of Source Files to be compiled (to be in a single line or on different lines separated by a "\" and tab. +SOURCES=IxQMgr.c \ + + +#common includes between all supported OSes +INCLUDES+= -I $(PWD)/include \ + -I $(src)/include \ + -I $(ICP_API_DIR) \ + -I $(ICP_API_DIR)/accel_infra \ + -I $(ICP_OSAL_DIR)/common/include + +ifeq ($(ICP_INTEL_DEV),YES) +INCLUDES+= -I $(ICP_OSAL_DIR)/common/include/modules \ + -I $(ICP_OSAL_DIR)/common/include/modules/ddk \ + -I $(ICP_OSAL_DIR)/common/include/modules/bufferMgt \ + -I $(ICP_OSAL_DIR)/common/include/modules/ioMem +endif + +EXTRA_CFLAGS += -DENABLE_IOMEM -DENABLE_BUFFERMGT + +#include your $(ICP_OS)_$(ICP_OS_LEVEL).mk file +include $(ICP_TDM_QMGR_DIR)/$(ICP_OS)_$(ICP_OS_LEVEL).mk + + + +# On the line directly below list the outputs you wish to build for, +# e.g "lib_static lib_shared exe module" as show below +install: module + + + +###################Include rules makefiles######################## +include $(ICP_BUILDSYSTEM_PATH)/build_files/rules.mk +###################End of Rules inclusion######################### diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_queue_manager/include/IxQMgrTrace_p.h b/Acceleration/library/icp_telephony/tdm_infrastructure_queue_manager/include/IxQMgrTrace_p.h new file mode 100644 index 0000000..1b4572c --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_queue_manager/include/IxQMgrTrace_p.h @@ -0,0 +1,255 @@ +/** + * @file IxQMgrTrace_p.h + * + * @date 01-Mar-04 + * + * @brief Private API for Queue Manager Tracing + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + + +/** + * @defgroup IxQMgr IxQMgrTracing_p + * + * @brief Private API for Queue Manager Error and Debug Tracing + * + * @{ + */ + +#ifndef IXQMGRTRACE_P_H +#define IXQMGRTRACE_P_H + +#include "IxOsal.h" + + +/** + * Prototypes for interface functions. + */ + +/** + * @typedef IxQMgrTraceTypes + * @brief Enumeration defining Queue Manager trace levels + */ + +typedef enum +{ + IX_QMGR_TRACE_OFF, /**< NO TRACE */ + IX_QMGR_DEBUG, /**< Select traces of interest */ + IX_QMGR_FN_ENTRY_EXIT /**< ALL function entry/exit traces */ +} IxQMgrTraceTypes; + +/** + * #defines for function return types, etc. + */ + +/** + * @def IX_QMGR_TRACE_LEVEL + * + * @brief Queue Manager debug trace level + */ +#ifndef IX_CONFIGURATION_unit_test +#define IX_QMGR_TRACE_LEVEL IX_QMGR_TRACE_OFF +#else +#define IX_QMGR_TRACE_LEVEL IX_QMGR_FN_ENTRY_EXIT +#endif + +/** + * @def IX_QMGR_REPORT_ERROR + * + * @brief Mechanism for reporting Queue Manager software errors + * + * @param char* [in] STR - Error string to report + * + * This macro sends the error string passed to ixOsalLog + * + * @return none + */ +#define IX_QMGR_REPORT_ERROR(STR) ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, STR, 0, 0, 0, 0, 0, 0); + +/** + * @def IX_QMGR_REPORT_ERROR_2 + * + * @brief Mechanism for reporting Queue Manager software errors + * with 2 arguments + * + * @param char* [in] STR - Error string to report + * @param argType [in] ARG1 - Argument to trace + * @param argType [in] ARG2 - Argument to trace + * + * This macro sends the error string passed to ixOsalLog + * + * @return none + */ +#define IX_QMGR_REPORT_ERROR_2(STR,ARG1,ARG2) ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, STR, ARG1, ARG2, 0, 0, 0, 0); + +/** + * @def IX_QMGR_TRACE0 + * + * @brief Mechanism for tracing debug for the Queue Manager component, for no + * arguments + * + * @param unsigned [in] LEVEL - one of IxQMgrTraceTypes enumerated values + * @param char* [in] STR - Trace string + * + * This macro sends the trace string passed to ixOsalLog + * + * @return none + */ +#define IX_QMGR_TRACE0(LEVEL, STR) \ +{ \ + if (LEVEL <= IX_QMGR_TRACE_LEVEL) \ + { \ + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, STR, 0, 0, 0, 0, 0, 0); \ + } \ +} + +/* + * @def IX_QMGR_TRACE1 + * + * @brief Mechanism for tracing debug for the Queue Manager component, with one + * argument + * + * @param unsigned [in] LEVEL - one of IxQMgrTraceTypes enumerated values + * @param char* [in] STR - Trace string + * @param argType [in] ARG1 - Argument to trace + * + * This macro sends the trace string passed to ixOsalLog + * + * @return none + */ +#define IX_QMGR_TRACE1(LEVEL, STR, ARG1) \ +{ \ + if (LEVEL <= IX_QMGR_TRACE_LEVEL) \ + { \ + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, STR, (int) ARG1, 0, 0, 0, 0, 0); \ + } \ +} + +/** + * @def IX_QMGR_TRACE2 + * + * @brief Mechanism for tracing debug for the Queue Manager component, with two + * arguments + * + * @param unsigned [in] LEVEL - one of IxQMgrTraceTypes enumerated values + * @param char* [in] STR - Trace string + * @param argType [in] ARG1 - Argument to trace + * @param argType [in] ARG2 - Argument to trace + * + * This macro sends the trace string passed to ixOsalLog + * + * @return none + */ +#define IX_QMGR_TRACE2(LEVEL, STR, ARG1, ARG2) \ +{ \ + if (LEVEL <= IX_QMGR_TRACE_LEVEL) \ + { \ + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, STR, (int) ARG1, (int) ARG2, 0, 0, 0, 0); \ + } \ +} + +/** + * @def IX_QMGR_TRACE3 + * + * @brief Mechanism for tracing debug for the Queue Manager component, with two + * arguments + * + * @param unsigned [in] LEVEL - one of IxQMgrTraceTypes enumerated values + * @param char* [in] STR - Trace string + * @param argType [in] ARG1 - Argument to trace + * @param argType [in] ARG2 - Argument to trace + * @param argType [in] ARG3 - Argument to trace + * + * This macro sends the trace string passed to ixOsalLog + * + * @return none + */ +#define IX_QMGR_TRACE3(LEVEL, STR, ARG1, ARG2, ARG3) \ +{ \ + if (LEVEL <= IX_QMGR_TRACE_LEVEL) \ + { \ + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, STR, (int) ARG1, (int) ARG2, (int) ARG3, 0, 0, 0); \ + } \ +} + + + +/** + * @def IX_QMGR_PRINT + * + * @brief macro to separate the Queue Manager component from the OS specific + * printing function. this is solely for debug purposes during development + * and integration + * + * @return none + */ +#ifdef __KERNEL__ +#define IX_QMGR_PRINT printk +#else +#define IX_QMGR_PRINT printf +#endif /* __KERNEL__ */ + +#endif /* IXQMGRTRACE_H */ + +/** + * @} defgroup IxQMgr + */ diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_queue_manager/linux_2.6_kernel_space.mk b/Acceleration/library/icp_telephony/tdm_infrastructure_queue_manager/linux_2.6_kernel_space.mk new file mode 100644 index 0000000..f5ad46a --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_queue_manager/linux_2.6_kernel_space.mk @@ -0,0 +1,77 @@ +################### +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# Contact Information: +# Intel Corporation +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# +################### + +#specific include directories in kernel space +INCLUDES+= -I $(ICP_OSAL_DIR)/platforms/EP805XX/include \ + -I $(ICP_OSAL_DIR)/platforms/EP805XX/os/linux/include \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/core \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules/ddk \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules/ioMem \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules/bufferMgt + + + +#Extra Flags Specific in kernel space e.g. include path or debug flags etc. e.g to add an include path EXTRA_CFLAGS += -I$(src)/../include +EXTRA_CFLAGS += -DEP805XX -D__ep805xx -D__tolapai -DTOLAPAI -DIX_HW_COHERENT_MEMORY=1 $(INCLUDES) +EXTRA_LDFLAGS+=-whole-archive + diff --git a/Acceleration/library/icp_telephony/tdm_io_access/Makefile b/Acceleration/library/icp_telephony/tdm_io_access/Makefile new file mode 100644 index 0000000..04fc632 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/Makefile @@ -0,0 +1,136 @@ +############################################################################ +# Targets supported +# all - builds everything and installs +# install - identical to all +# depend - build dependencies +# clean - clears derived objects except the .depend files +# distclean- clears all derived objects and the .depend file +# +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# +############################################################################ + + +# Ensure The ENV_DIR environmental var is defined. +ifndef ICP_ENV_DIR +$(error ICP_ENV_DIR is undefined. Please set the path to your environment makefile \ + "-> setenv ENV_DIR <path>") +endif + +#Add your project environment Makefile, extra comment +include $(ICP_ENV_DIR)/environment.mk + + +#include the makefile with all the default and common Make variable definitions +include $(ICP_BUILDSYSTEM_PATH)/build_files/common.mk + + +#Add the name for the executable, Library or Module output definitions +OUTPUT_NAME=$(ICP_TDM_IO_NAME) + +# List of Source Files to be compiled (to be in a single line or on different lines separated by a "\" and tab. +SOURCES= icp_hssacc_common.c \ + icp_hssacc_channel_list.c \ + icp_hssacc_channel_config.c \ + icp_hssacc_voice_bypass.c \ + icp_hssacc_service.c \ + icp_hssacc_queues_config.c \ + icp_hssacc_rx_datapath.c \ + icp_hssacc_tx_datapath.c \ + icp_hssacc_port_config.c \ + icp_hssacc_port_hdma_reg_mgr.c \ + icp_hssacc_common_timeslot_allocation.c \ + $(ICP_DEVICE)$(ICP_SLASH)icp_hssacc_timeslot_allocation.c \ + $(ICP_DEVICE)$(ICP_SLASH)icp_hssacc_address_translate.c \ + $(ICP_DEVICE)$(ICP_SLASH)icp_hssacc_param_check.c + + +# Setup include directory +INCLUDES += -I $(src)/include \ + -I $(PWD)/include \ + -I $(ICP_API_DIR) \ + -I $(ICP_API_DIR)/hss \ + -I $(ICP_API_DIR)/accel_infra \ + -I $(ICP_OSAL_DIR)/common/include + +ifeq ($(ICP_INTEL_DEV),YES) +INCLUDES += -I $(ICP_OSAL_DIR)/common/include/modules \ + -I $(ICP_OSAL_DIR)/common/include/modules/ddk \ + -I $(ICP_OSAL_DIR)/common/include/modules/bufferMgt \ + -I $(ICP_OSAL_DIR)/common/include/modules/ioMem +endif + +EXTRA_CFLAGS += -DENABLE_IOMEM -DENABLE_BUFFERMGT + + +#include your $(ICP_OS)_$(ICP_OS_LEVEL).mk file +include $(ICP_TDM_IO_DIR)/$(ICP_OS)_$(ICP_OS_LEVEL).mk + + +# Install the module to the output dir +install: module + + +###################Include rules and dependency makefiles######################## +include $(ICP_BUILDSYSTEM_PATH)/build_files/rules.mk +###################End of Rules and dependency inclusion######################### + + + + diff --git a/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_address_translate.c b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_address_translate.c new file mode 100644 index 0000000..73a1269 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_address_translate.c @@ -0,0 +1,178 @@ +/****************************************************************************** + * @file icp_hssacc_address_translate.c + * + * @description Content of this file provides the definition of + * address translation functions from the virtual + * address space to the physical and vice-versa + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + ******************************************************************************/ + +#include "IxOsal.h" + +#include "icp.h" +#include "icp_hssacc_common.h" +#include "icp_hssacc_address_translate.h" +#include "icp_hssacc_trace.h" + +uint32_t +HssAccVirtToPhysAddressTranslateAndSwap(void* pVirtAddr) +{ + uint32_t physAddr = 0; + /* Convert the table base address to a physical address */ + physAddr = HssAccVirtToPhysAddressTranslate (pVirtAddr); +#ifdef SW_SWAPPING + /* Now convert the physical address to network order */ + physAddr = IX_OSAL_SWAP_BE_SHARED_LONG(physAddr); +#endif + return physAddr; +} + +void * +HssAccPhysToVirtAddressSwapAndTranslate(uint32_t physAddr) +{ + void * pVirtAddr = NULL; +#ifdef SW_SWAPPING + /* Now convert the physical address back to little endian mode */ + physAddr = IX_OSAL_SWAP_BE_SHARED_LONG(physAddr); +#endif + /* Convert the physical address to a virtual address*/ + pVirtAddr = HssAccPhysToVirtAddressTranslate (physAddr); + + return pVirtAddr; +} + + + +uint32_t +HssAccVirtToPhysAddressTranslate(void * const pVirtAddr) +{ + uint32_t physAddr = 0; + /* Convert the table base address to a physical address */ + physAddr = (uint32_t)IX_OSAL_MMU_VIRT_TO_PHYS (pVirtAddr); + + return physAddr; +} + + +void * +HssAccPhysToVirtAddressTranslate(const uint32_t physAddr) +{ + void * pVirtAddr = NULL; + + /* Convert the physical address to a table base address*/ + pVirtAddr = (void*)IX_OSAL_MMU_PHYS_TO_VIRT (physAddr); + + return pVirtAddr; +} + + + +void * +HssAccDmaMemAllocate(uint32_t sizeBytes, + uint32_t * physOffset) +{ + void * pVirtAddr = NULL; + *physOffset = 0; + pVirtAddr = (void *)IX_OSAL_CACHE_DMA_MALLOC(sizeBytes); + if (NULL != pVirtAddr) + { + *physOffset = HssAccVirtToPhysAddressTranslate(pVirtAddr); + } + return pVirtAddr; + +} + +/* This function perform an endianness swap on each word of the provided buffer + it assumed that the buffer size is a multiple of word size */ +void +HssAccDataEndiannessSwap(IX_OSAL_MBUF * const buffer) +{ +#ifdef SW_SWAPPING + uint32_t index = 0; + uint32_t * dataPtr = (uint32_t*)IX_OSAL_MBUF_MDATA(buffer); +#endif + ICP_HSSACC_TRACE_1 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccDataEndiannessSwap" + " for Buffer 0x%08X\n", + (uint32_t)buffer); +#ifdef SW_SWAPPING + if ( 0 != (IX_OSAL_MBUF_PKT_LEN(buffer) % ICP_HSSACC_WORD_SIZE)) + { + ICP_HSSACC_REPORT_ERROR("HssAccDataEndiannessSwap - Buffer Provided" + " has a size that is not a multiple of a " + "word size\n"); + } + for (; + index < (IX_OSAL_MBUF_PKT_LEN(buffer) / ICP_HSSACC_WORD_SIZE); + index ++) + { + dataPtr[index] = IX_OSAL_SWAP_BE_SHARED_LONG(dataPtr[index]); + } +#endif + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccDataEndiannessSwap\n"); +} diff --git a/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_channel_config.c b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_channel_config.c new file mode 100644 index 0000000..4f4da9b --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_channel_config.c @@ -0,0 +1,2174 @@ +/****************************************************************************** + * + * @file icp_hssacc_channel_config.c + * + * @description Contents of this file is the channel configuration module which + * include the implementation of the channel configuration API. + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + *****************************************************************************/ +#include "IxOsal.h" + +#include "icp.h" +#include "icp_hssacc.h" +#include "icp_hssacc_queues_config.h" +#include "icp_hssacc_trace.h" +#include "icp_hssacc_common.h" +#include "icp_hssacc_channel_config.h" +#include "icp_hssacc_channel_list.h" +#include "icp_hssacc_timeslot_allocation.h" +#include "icp_hssacc_address_translate.h" +#include "icp_hssacc_tx_datapath.h" +#include "icp_hssacc_rx_datapath.h" + + +/* Stats */ +typedef struct icp_hssacc_channel_config_stats_s +{ + icp_hssacc_msg_with_resp_stats_t chanCfg; + icp_hssacc_msg_with_resp_stats_t chanEnable; + icp_hssacc_msg_with_resp_stats_t chanDisable; + icp_hssacc_msg_with_resp_stats_t hdlcChanCfg; + icp_hssacc_msg_with_resp_stats_t voiceChanCfg; + icp_hssacc_msg_with_resp_stats_t offsetTableLoad; + icp_hssacc_msg_with_resp_stats_t hdlcMaxRxCfg; +} icp_hssacc_channel_config_stats_t; + +typedef enum + { + ICP_HSSACC_VOICE_NB_CHAN_SIZE = 1, + ICP_HSSACC_VOICE_NBL_CHAN_SIZE = 2, + ICP_HSSACC_VOICE_WB_CHAN_SIZE = 4, + ICP_HSSACC_VOICE_UWB_CHAN_SIZE = 8 + } icp_hssacc_voice_supported_sizes_t; + + +/* definition in Bytes of the maximum sample size for each type of voice + channel.for example, G711 30msec sample is the factor for determining max + size for a narrowband channel */ + +#define ICP_HSSACC_VOICE_NB_MAX_SAMPLE_SIZE (240) +#define ICP_HSSACC_VOICE_NBL_MAX_SAMPLE_SIZE (480) +#define ICP_HSSACC_VOICE_WB_MAX_SAMPLE_SIZE (960) +#define ICP_HSSACC_VOICE_UWB_MAX_SAMPLE_SIZE (1920) + + +#define ICP_HSSACC_FCS_4_BYTE_WIDTH (4) +#define ICP_HSSACC_FCS_2_BYTE_WIDTH (2) + +/* + * Sets the enable bit in the timeslot word of HSS port provision table. + */ +#define ICP_HSSACC_HDMA_TIMESLOT_ENABLE (BIT_SET(23)) + +/* + * The channel ID must be shifted by this offset in the HSS port + * provision table + */ +#define ICP_HSSACC_HDMA_CHANNEL_OFFSET (16) + + + + +/* + * ---------------------------------------------------------------------------- + * Struct types + * ---------------------------------------------------------------------------- + */ +/* + * ---------------------------------------------------------------------------- + * Global variables + * ---------------------------------------------------------------------------- + */ + +/* Tracks the current channel state and configuration */ +TDM_PRIVATE icp_hssacc_channel_config_t +hssAccChannelConfig[ICP_HSSACC_MAX_NUM_CHANNELS]; + + +/* This variable holds the number of channels currently allocated. */ +TDM_PRIVATE unsigned hssAccNumChansAllocated = 0; + +TDM_PRIVATE icp_hssacc_channel_config_stats_t hssAccChanCfgStats; + +TDM_PRIVATE icp_boolean_t channelConfigModuleInitialised = ICP_FALSE; + + +/* + * ---------------------------------------------------------------------------- + * Static function declarations + * ---------------------------------------------------------------------------- + */ + +TDM_PRIVATE icp_status_t +HssAccChannelConfigHdlcServiceMsgSend (unsigned channelId); + +TDM_PRIVATE icp_status_t +HssAccChannelConfigVoiceServiceMsgSend (unsigned channelId); + + +TDM_PRIVATE icp_status_t +HssAccChannelConfigHdlcMaxFrameSizeSend (unsigned channelId); + +TDM_PRIVATE icp_status_t +HssAccChannelConfigMsgSend (unsigned channelId); + +TDM_PRIVATE void +HssAccChannelConfigStateReset (unsigned channelId); + + +/***************************************************************************** + * Abstract: + * The timeslot map for a given channel cannot span multiple TDM trunks, + * i.e. all timeslots pertaining to a channel must reside solely on + * line0_timeslot_bit_map, line1_timeslot_bit_map, line2_timeslot_bit_map + * or line3_timeslot_bit_map. + * This function enforces this policy as well as checking that at least 1 + * TS as been assigned. + *****************************************************************************/ +inline icp_status_t HssAccTimeslotErrorCheck (icp_hssacc_timeslot_map_t tsMap) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTimeslotErrorCheck\n"); + if (tsMap.line0_timeslot_bit_map != 0) + { + if ( (tsMap.line1_timeslot_bit_map | tsMap.line2_timeslot_bit_map | + tsMap.line3_timeslot_bit_map) != 0 ) + { + ICP_HSSACC_REPORT_ERROR ("HssAccTimeslotErrorCheck - The channel " + "timeslot mapping cannot span " + "TDM lines!\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } + else if (tsMap.line1_timeslot_bit_map != 0) + { + if ( (tsMap.line2_timeslot_bit_map | + tsMap.line3_timeslot_bit_map) != 0 ) + { + ICP_HSSACC_REPORT_ERROR ("HssAccTimeslotErrorCheck - The channel " + "timeslot mapping cannot span " + "TDM lines!\n"); + status = ICP_STATUS_INVALID_PARAM; } + } + else if (tsMap.line2_timeslot_bit_map != 0) + { + if ( (tsMap.line3_timeslot_bit_map) != 0 ) + { + ICP_HSSACC_REPORT_ERROR ("HssAccTimeslotErrorCheck - The channel " + "timeslot mapping cannot span " + "TDM lines!\n"); + status = ICP_STATUS_INVALID_PARAM; } + } + else if (tsMap.line3_timeslot_bit_map == 0) + { + ICP_HSSACC_REPORT_ERROR ("HssAccTimeslotErrorCheck - Invalid timeslot" + " configuration, no slots were chosen!\n"); + status = ICP_STATUS_INVALID_PARAM; + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTimeslotErrorCheck\n"); + + return status; +} + + +/****************************************************************************** + * Abstract: + * counts the number of timeslots requested by the channel, + * determines the HSS line that the timeslots reside on and copies the + * appropriate line's TDM map to the variable chanTsMap. at least one TS + * must be assigned for this function to function correctly. + * + ****************************************************************************/ +void HssAccTimeslotConfigGet(icp_hssacc_timeslot_map_t tsMap, + unsigned * numTs, + icp_hssacc_line_t * lineId, + uint32_t * chanTsMap, + unsigned * firstTsPosition, + unsigned * lastTsPosition) +{ + unsigned tempNumTs = 0; + uint32_t bitMap = 0; + icp_boolean_t firstFound = ICP_FALSE; + + (*lastTsPosition) = 0; + (*firstTsPosition) = 0; + if (tsMap.line0_timeslot_bit_map != 0) + { + *lineId = ICP_HSSACC_LINE_0; + *chanTsMap = tsMap.line0_timeslot_bit_map; + } + else if (tsMap.line1_timeslot_bit_map != 0) + { + *lineId = ICP_HSSACC_LINE_1; + *chanTsMap = tsMap.line1_timeslot_bit_map; + } + else if (tsMap.line2_timeslot_bit_map != 0) + { + *lineId = ICP_HSSACC_LINE_2; + *chanTsMap = tsMap.line2_timeslot_bit_map; + } + else if (tsMap.line3_timeslot_bit_map != 0) + { + *lineId = ICP_HSSACC_LINE_3; + *chanTsMap = tsMap.line3_timeslot_bit_map; + } + bitMap = *chanTsMap; + tempNumTs += (bitMap & 1); + if (bitMap & 1) + { + firstFound = ICP_TRUE; + } + bitMap >>= 1; + while (bitMap) + { + tempNumTs += (bitMap & 1); + (*lastTsPosition) ++; + if ((ICP_FALSE == firstFound) && + (bitMap & 1)) + { + firstFound = ICP_TRUE; + (*firstTsPosition) = (*lastTsPosition); + } + bitMap >>= 1; + } + *numTs = tempNumTs; +} + +/****************************************************************************** + * Abstract: + * Initialises all global variables used during channel configuration. + * Allocates memory for the channel offset tables. + * Initialises the channel configuration mutex. + * + *****************************************************************************/ +icp_status_t +HssAccChannelConfigInit(void) +{ + unsigned channelId = 0; + icp_status_t status = ICP_STATUS_SUCCESS; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelConfigInit\n"); + + if (ICP_TRUE == channelConfigModuleInitialised) + { + ICP_HSSACC_REPORT_ERROR ("HssAccChannelConfigInit - " + "Module is already Initialised\n"); + status = ICP_STATUS_FAIL; + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Initialise the channel configuration struct */ + for (channelId = 0; + channelId < ICP_HSSACC_MAX_NUM_CHANNELS; + channelId ++) + { + HssAccChannelConfigStateReset(channelId); + } + + /* All channels are available */ + hssAccNumChansAllocated = 0; + } + + if (ICP_STATUS_SUCCESS == status) + { + status = HssAccTsAllocInit(); + } + if (ICP_STATUS_SUCCESS == status) + { + /* Reset the Messaging Stats */ + HssAccChannelConfigStatsReset(); + + /* Reset the Timeslot Allocation submodule Stats */ + HssAccTsAllocStatsReset(); + + HssAccChannelListsReset(); + + channelConfigModuleInitialised = ICP_TRUE; + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelConfigInit\n"); + return status; +} + + +/****************************************************************************** + * Abstract: + * shuts down the channel Configuration sub-component of HSS Acc. + * it will reset all internal variables. + * + *****************************************************************************/ +icp_status_t +HssAccChannelConfigShutdown(void) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelConfigShutdown\n"); + if (ICP_FALSE == channelConfigModuleInitialised) + { + ICP_HSSACC_REPORT_ERROR ("HssAccChannelConfigShutdown - " + "Service is not initialised\n"); + status = ICP_STATUS_FAIL; + } + if (ICP_STATUS_SUCCESS == status) + { + HssAccTsAllocShutdown(); + /* just in case, set the number of used channels to the max so that + no one can allocate new channels */ + hssAccNumChansAllocated = ICP_HSSACC_MAX_NUM_CHANNELS; + channelConfigModuleInitialised = ICP_FALSE; + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelConfigShutdown\n"); + return status; +} + +/****************************************************************************** + * Abstract: + * Allocate a channel on the specified port using the specified + * timeslots. + * + *****************************************************************************/ +icp_status_t +icp_HssAccChannelAllocate (unsigned *pChannelId, + unsigned portId, + icp_hssacc_timeslot_map_t tsMap, + icp_hssacc_channel_type_t channelType) +{ + unsigned channelSize = 0; + unsigned channelId = ICP_HSSACC_MAX_NUM_CHANNELS; + icp_hssacc_line_t lineId = ICP_HSSACC_LINE_DELIMITER; + uint32_t channelTsMap = 0; + icp_status_t status = ICP_STATUS_SUCCESS; + icp_boolean_t suitableChanIdFound = ICP_FALSE; + icp_boolean_t mutexLocked = ICP_FALSE; + unsigned lastTsPos = 0; + unsigned firstTsPos = ICP_HSSACC_MAX_TIMESLOTS_PER_TDM_LINE; + + ICP_HSSACC_TRACE_3 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccChannelAllocate - " + "\n\tchannelPtr 0x%08X on port %u of type %u\n", + (unsigned)pChannelId, portId, channelType); + if (ICP_FALSE == channelConfigModuleInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelAllocate - " + "service not Initialised\n"); + status = ICP_STATUS_FAIL; + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Sanity check the parameters */ + if ( (NULL == pChannelId) || + (portId >= ICP_HSSACC_MAX_NUM_PORTS) || + ICP_HSSACC_ENUM_INVALID (channelType, + ICP_HSSACC_CHAN_TYPE_DELIMITER) ) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelAllocate - invalid " + "parameter\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } + if (ICP_STATUS_SUCCESS == status) + { + if (HssAccPortStateGet(portId) != ICP_HSSACC_PORT_ENABLED) + { + ICP_HSSACC_REPORT_ERROR_1 ("icp_HssAccChannelAllocate - specified " + "port %u should be Enabled\n", + portId); + status = ICP_STATUS_RESOURCE; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Verify that client requested a valid timeslot configuration */ + status = HssAccTimeslotErrorCheck (tsMap); + } + if (ICP_STATUS_SUCCESS == status) + { + /* + Extract all information from the timeslot mapping for this channel; + this includes the number of timeslots that the channel wants to use, + and the line on which the timeslots reside. + */ + HssAccTimeslotConfigGet (tsMap, &channelSize, + &lineId, &channelTsMap, + &firstTsPos, &lastTsPos); + + ICP_HSSACC_TRACE_2 (ICP_HSSACC_DEBUG, + "icp_HssAccChannelAllocate -" + " Timeslot Config with Size=%u and lastTsPos=%u\n", + channelSize, + lastTsPos); + + /* Check that the line used and timeslots used are compatible + with the port speed */ + status = HssAccPortLineValidCheck(portId, lineId, + firstTsPos, lastTsPos); + } + + if (ICP_STATUS_SUCCESS == status) + { + /* If this is a voice channel then it can only use + 1, 2 or 4 timeslots */ + if ( (ICP_HSSACC_CHAN_TYPE_VOICE == channelType) && + (channelSize != ICP_HSSACC_VOICE_NB_CHAN_SIZE && + channelSize != ICP_HSSACC_VOICE_NBL_CHAN_SIZE && + channelSize != ICP_HSSACC_VOICE_WB_CHAN_SIZE)) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelAllocate - " + "invalid number of timeslots. " + "A voice channel can only use" + " 1, 2 or 4 timeslots.\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Grab the HssAcc mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_LOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelAllocated - " + "failed to lock HssAcc Mutex\n"); + + status = ICP_STATUS_MUTEX; + } + else + { + mutexLocked = ICP_TRUE; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + /* + * All channels may be used, so check before looping + * through each channel ID + */ + if (ICP_HSSACC_MAX_NUM_CHANNELS == hssAccNumChansAllocated) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelAllocate - " + "All channels have" + " been allocated!\n"); + status = ICP_STATUS_RESOURCE; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Verify that the timeslots requested aren't owned by another channel */ + if (ICP_FALSE == HssAccTsAvailableVerify (portId, lineId, channelTsMap)) + { + /* The timeslots are in use by another channel */ + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelAllocate - The requested " + "timeslots have been reserved by " + "another channel\n"); + status = ICP_STATUS_RESOURCE; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + /* + * If the code makes it to here there must be + * at least one channel not in use; find it. + * channelId going out of bounds checked for + * paranoias sake. + */ + channelId = 0; + while ((ICP_HSSACC_MAX_NUM_CHANNELS > channelId) && + (ICP_FALSE == suitableChanIdFound)) + { + if (ICP_HSSACC_CHANNEL_UNINITIALISED == + hssAccChannelConfig[channelId].state) + { + hssAccNumChansAllocated ++; + suitableChanIdFound = ICP_TRUE; + } + else + { + channelId ++; + } + } + + /* Save the channel ID to return to the client */ + *pChannelId = channelId; + + + /* Save these timeslots as in use by this channel */ + HssAccTsRegister (channelId, portId, + lineId, channelTsMap); + + hssAccChannelConfig[channelId].size = channelSize; + hssAccChannelConfig[channelId].lineId = lineId; + hssAccChannelConfig[channelId].timeslotMap = channelTsMap; + + } + + if (ICP_STATUS_SUCCESS == status) + { + + /* Update the channel configuration */ + hssAccChannelConfig[channelId].state = ICP_HSSACC_CHANNEL_ALLOCATED; + hssAccChannelConfig[channelId].type = channelType; + hssAccChannelConfig[channelId].portId = portId; + + HssAccTxDatapathChanTypeUpdate(channelId, + channelType); + + /* Update the channel offset tables with these timeslots */ + status = HssAccTsAllocUpdate (portId, + hssAccChannelConfig); + + if (ICP_STATUS_SUCCESS == status) + { + /* Update the Queue Manager Info */ + status = HssAccQueueConfigQSizeUpdate(channelId, channelType); + } + if (ICP_STATUS_SUCCESS == status) + { + status = HssAccChannelListAdd(portId, channelId, channelSize); + } + if (ICP_STATUS_SUCCESS != status) + { + /* Revert Back */ + HssAccTsUnregister (portId, + hssAccChannelConfig[channelId].lineId, + hssAccChannelConfig[channelId].timeslotMap); + + /* Clear the timeslot allocation but keep the port, we + need it for generating the new tables */ + hssAccChannelConfig[channelId].lineId = ICP_HSSACC_LINE_DELIMITER; + hssAccChannelConfig[channelId].timeslotMap = 0; + hssAccChannelConfig[channelId].size = 0; + + hssAccChannelConfig[channelId].state = + ICP_HSSACC_CHANNEL_UNINITIALISED; + hssAccNumChansAllocated --; + + ICP_HSSACC_REPORT_ERROR("icp_HssAccChannelAllocate - Failure " + "in updating the TDM I/O Unit with " + "the new channel\n"); + } + } + + /* Free the HssAcc mutex */ + if (ICP_TRUE == mutexLocked) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelAllocate - " + "failed to release HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + } + if (ICP_STATUS_SUCCESS == status) + { + /* In case this channel was previously allocated and has + leftover stats */ + status = icp_HssAccChannelStatsReset(channelId); + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccChannelAllocate\n"); + return status; +} + + + + +/****************************************************************************** + * Abstract: + * Configure the specified channel with the service agnostic parameters. + * + *****************************************************************************/ +icp_status_t +icp_HssAccChannelConfigure (unsigned channelId, + icp_hssacc_data_polarity_t channelDataPolarity, + icp_hssacc_bit_endian_t channelBitEndianness, + icp_boolean_t channelByteSwapping, + icp_hssacc_bit_robbing_t rBitEnable, + icp_hssacc_robbed_bit_value_t rBitValue, + icp_hssacc_robbed_bit_location_t rBitLocation) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + icp_boolean_t mutexLocked = ICP_FALSE; + + ICP_HSSACC_TRACE_1 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccChannelConfigure for channel %u\n", + channelId); + + if (ICP_FALSE == channelConfigModuleInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelConfigure - " + "Service is not Initialised\n"); + status = ICP_STATUS_FAIL; + } + + if (ICP_STATUS_SUCCESS == status) + { + if ((ICP_HSSACC_MAX_NUM_CHANNELS <= channelId) || + ICP_HSSACC_ENUM_INVALID (channelBitEndianness, + ICP_HSSACC_BIT_ENDIAN_DELIMITER) || + ICP_HSSACC_ENUM_INVALID (rBitEnable, + ICP_HSSACC_BIT_ROBBING_DELIMITER) || + ICP_HSSACC_ENUM_INVALID (channelDataPolarity, + ICP_HSSACC_DATA_POLARITY_DELIMITER)) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelConfigure - invalid " + "parameter\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + if (ICP_HSSACC_BIT_ROBBING_ONE_BIT == rBitEnable) + { + if (ICP_HSSACC_CHAN_TYPE_VOICE == + hssAccChannelConfig[channelId].type) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelConfigure - robbed " + "Bit cannot be used for a " + "voice channel\n"); + status = ICP_STATUS_INVALID_PARAM; + } + + if (ICP_HSSACC_ENUM_INVALID (rBitValue, + ICP_HSSACC_ROBBED_BIT_DELIMITER) || + ICP_HSSACC_ENUM_INVALID (rBitLocation, + ICP_HSSACC_ROBBED_BIT_POS_DELIMITER)) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelConfigure - invalid " + "robbed Bit parameter\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } + } + + + if (ICP_STATUS_SUCCESS == status) + { + /* Grab the HssAcc mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_LOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelConfigure - " + "failed to lock HssAcc Mutex\n"); + + status = ICP_STATUS_MUTEX; + } + else + { + mutexLocked = ICP_TRUE; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + if (ICP_HSSACC_CHANNEL_ALLOCATED != hssAccChannelConfig[channelId].state) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelConfigure - Channel " + "is not in the correct state " + "for configuration\n"); + status = ICP_STATUS_RESOURCE; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + hssAccChannelConfig[channelId].dataPolarity = channelDataPolarity; + hssAccChannelConfig[channelId].bitEndian = channelBitEndianness; + hssAccChannelConfig[channelId].byteSwap = channelByteSwapping; + hssAccChannelConfig[channelId].bitRobbing = rBitEnable; + hssAccChannelConfig[channelId].rBitValue = rBitValue; + hssAccChannelConfig[channelId].rBitLocation = rBitLocation; + hssAccChannelConfig[channelId].state = ICP_HSSACC_CHANNEL_CONFIGURED; + status = HssAccChannelConfigMsgSend(channelId); + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR("icp_HssAccChannelConfigure - " + "failed to set channel configuration " + "in TDM I/O Unit\n"); + hssAccChannelConfig[channelId].state = ICP_HSSACC_CHANNEL_ALLOCATED; + } + } + + if (ICP_TRUE == mutexLocked) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelConfigure - " + "failed to release HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccChannelConfigure\n"); + return status; +} + + + + + +/****************************************************************************** + * Abstract: + * Configure the HDLC service specific parameters for the + * specified channel. + *****************************************************************************/ +icp_status_t +icp_HssAccChannelHdlcServiceConfigure ( + unsigned channelId, + icp_hssacc_hdlc_crc_bit_width_t hdlcCrcBitWidth, + icp_hssacc_hdlc_sof_flag_type_t hdlcSofFlagType, + icp_hssacc_hdlc_idle_pattern_t hdlcRxIdlePattern, + icp_hssacc_hdlc_idle_pattern_t hdlcTxIdlePattern, + unsigned hdlcMaximumFrameSize) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + icp_boolean_t mutexLocked = ICP_FALSE; + uint32_t maxHdlcServFrameSize = 0; + + ICP_HSSACC_TRACE_1 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccChannelHdlcServiceConfigure " + "for channel %u\n", + channelId); + + if (ICP_FALSE == channelConfigModuleInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelHdlcServiceConfigure - " + "Service is not Initialised\n"); + status = ICP_STATUS_FAIL; + } + + if (ICP_STATUS_SUCCESS == status) + { + if ((ICP_HSSACC_MAX_NUM_CHANNELS <= channelId) || + ICP_HSSACC_ENUM_INVALID (hdlcCrcBitWidth, + ICP_HSSACC_HDLC_CRC_BIT_WIDTH_DELIMITER) || + ICP_HSSACC_ENUM_INVALID (hdlcSofFlagType, + ICP_HSSACC_HDLC_SOF_FLAG_TYPE_DELIMITER) || + ICP_HSSACC_ENUM_INVALID (hdlcRxIdlePattern, + ICP_HSSACC_HDLC_IDLE_PATTERN_DELIMITER) || + ICP_HSSACC_ENUM_INVALID (hdlcTxIdlePattern, + ICP_HSSACC_HDLC_IDLE_PATTERN_DELIMITER)) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelHdlcServiceConfigure - " + "invalid parameter\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } + + + + if (ICP_STATUS_SUCCESS == status) + { + /* Grab the HssAcc mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_LOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelHdlcServiceConfigure - " + "failed to lock HssAcc Mutex\n"); + + status = ICP_STATUS_MUTEX; + } + else + { + mutexLocked = ICP_TRUE; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + if (0 == hdlcMaximumFrameSize) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelHdlcServiceConfigure - " + "Maximum HDLC Frame Size cannot be zero\n"); + status = ICP_STATUS_INVALID_PARAM; + } + + maxHdlcServFrameSize = + HssAccRxDatapathMaxServiceFrameSizeGet(ICP_HSSACC_CHAN_TYPE_HDLC); + if (0 == maxHdlcServFrameSize) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelHdlcServiceConfigure - " + "Maximum HDLC Frame Size for the HDLC " + "Service is invalid\n"); + status = ICP_STATUS_INVALID_PARAM; + } + + if (hdlcMaximumFrameSize > maxHdlcServFrameSize) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelHdlcServiceConfigure - " + "Maximum HDLC Frame Size for this channel" + " is greater than that for the Service\n"); + status = ICP_STATUS_INVALID_PARAM; + } + + + } + + + if (ICP_STATUS_SUCCESS == status) + { + if (ICP_HSSACC_CHANNEL_CONFIGURED != + hssAccChannelConfig[channelId].state) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelHdlcServiceConfigure - " + "Channel is not in the appropriate " + "State\n"); + ICP_HSSACC_TRACE_1 (ICP_HSSACC_DEBUG, + "icp_HssAccChannelHdlcServiceConfigure - " + "Channel is in State (%u)\n", + hssAccChannelConfig[channelId].state); + status = ICP_STATUS_RESOURCE; + } + } + + + if (ICP_STATUS_SUCCESS == status) + { + if (ICP_HSSACC_CHAN_TYPE_VOICE == hssAccChannelConfig[channelId].type) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelHdlcServiceConfigure - " + "attempting to configure HDLC Service " + "for an allocated Voice Channel\n"); + status = ICP_STATUS_RESOURCE; + } + } + + + if (ICP_STATUS_SUCCESS == status) + { + + hssAccChannelConfig[channelId].sofFlagType = hdlcSofFlagType; + hssAccChannelConfig[channelId].hdlcTxIdlePattern = hdlcTxIdlePattern; + hssAccChannelConfig[channelId].hdlcRxIdlePattern = hdlcRxIdlePattern; + hssAccChannelConfig[channelId].hdlcMaxFrSize = hdlcMaximumFrameSize; + hssAccChannelConfig[channelId].hdlcCrcBitWidth = hdlcCrcBitWidth; + + + status = HssAccChannelConfigHdlcServiceMsgSend(channelId); + + if (ICP_STATUS_SUCCESS == status) + { + status = HssAccChannelConfigHdlcMaxFrameSizeSend (channelId); + } + + if (ICP_STATUS_SUCCESS == status) + { + hssAccChannelConfig[channelId].state = + ICP_HSSACC_CHANNEL_SERVICE_CONFIGURED; + } + } + + /* Free the channel configuration mutex */ + if (ICP_TRUE == mutexLocked) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelHdlcServiceConfigure - " + "failed to release HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + } + + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccChannelHdlcServiceConfigure\n"); + return status; +} + + + +/***************************************************************************** + * Abstract: + * Configure the Voice service specific parameters for the + * specified channel. + * + *****************************************************************************/ +icp_status_t +icp_HssAccChannelVoiceServiceConfigure ( + unsigned channelId, + icp_hssacc_channel_voice_tx_idle_action_t txIdleAction, + uint8_t voiceIdlePattern, + unsigned voicePacketSize) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + unsigned maxAllowedPacketSize = 0; + icp_boolean_t mutexLocked = ICP_FALSE; + uint32_t maxVoiceServSampleSize = 0; + + ICP_HSSACC_TRACE_1 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccChannelVoiceServiceConfigure " + "for channel %u\n", + channelId); + + if (ICP_FALSE == channelConfigModuleInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelVoiceServiceConfigure - " + "Service is not Initialised\n"); + status = ICP_STATUS_FAIL; + } + + if (ICP_STATUS_SUCCESS == status) + { + if ((ICP_HSSACC_MAX_NUM_CHANNELS <= channelId) || + ICP_HSSACC_ENUM_INVALID (txIdleAction, + ICP_HSSACC_VOICE_TX_IDLE_DELIMITER)) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelVoiceServiceConfigure - " + "invalid parameter\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + + /* Grab the HssAcc mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_LOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelVoiceServiceConfigure - " + "failed to lock HssAcc Mutex\n"); + + status = ICP_STATUS_MUTEX; + } + else + { + mutexLocked = ICP_TRUE; + } + + } + + if (ICP_STATUS_SUCCESS == status) + { + if (ICP_HSSACC_CHANNEL_CONFIGURED != + hssAccChannelConfig[channelId].state) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelVoiceServiceConfigure -" + " Channel not in the appropriate state\n"); + ICP_HSSACC_TRACE_1 (ICP_HSSACC_DEBUG, + "icp_HssAccChannelVoiceServiceConfigure - " + "Channel is in State (%u)\n", + hssAccChannelConfig[channelId].state); + status = ICP_STATUS_RESOURCE; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + if (ICP_HSSACC_CHAN_TYPE_HDLC == hssAccChannelConfig[channelId].type) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelVoiceServiceConfigure - " + "attempting to configure Voice Service " + "for an allocated HDLC Channel\n"); + status = ICP_STATUS_RESOURCE; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + switch (hssAccChannelConfig[channelId].size) + { + case ICP_HSSACC_VOICE_NB_CHAN_SIZE: + maxAllowedPacketSize = ICP_HSSACC_VOICE_NB_MAX_SAMPLE_SIZE; + break; + case ICP_HSSACC_VOICE_NBL_CHAN_SIZE: + maxAllowedPacketSize = ICP_HSSACC_VOICE_NBL_MAX_SAMPLE_SIZE; + break; + case ICP_HSSACC_VOICE_WB_CHAN_SIZE: + maxAllowedPacketSize = ICP_HSSACC_VOICE_WB_MAX_SAMPLE_SIZE; + break; + case ICP_HSSACC_VOICE_UWB_CHAN_SIZE: + maxAllowedPacketSize = ICP_HSSACC_VOICE_UWB_MAX_SAMPLE_SIZE; + break; + default: + /* unreachable due to verification in Allocation function */ + break; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + if (maxAllowedPacketSize < voicePacketSize) + { + ICP_HSSACC_REPORT_ERROR_2 ("icp_HssAccChannelVoiceServiceConfigure -" + " Voice Sample Size (%u) too large for " + "channel (max Allowed is %u)\n", + voicePacketSize, + maxAllowedPacketSize); + status = ICP_STATUS_INVALID_PARAM; + } + if (0 == voicePacketSize) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelVoiceServiceConfigure -" + " Voice Sample Size cannot be zero\n"); + status = ICP_STATUS_INVALID_PARAM; + } + maxVoiceServSampleSize = + HssAccRxDatapathMaxServiceFrameSizeGet(ICP_HSSACC_CHAN_TYPE_VOICE); + if (0 == maxVoiceServSampleSize) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelVoiceServiceConfigure - " + "Maximum Voice Sample Size for the Voice " + "Service is invalid\n"); + status = ICP_STATUS_INVALID_PARAM; + } + + if (voicePacketSize > maxVoiceServSampleSize) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelVoiceServiceConfigure - " + "Maximum Voice Sample Size for this channel" + " is greater than that for the Service\n"); + status = ICP_STATUS_INVALID_PARAM; + } + + } + + + if (ICP_STATUS_SUCCESS == status) + { + + hssAccChannelConfig[channelId].voiceSampleSize = voicePacketSize; + hssAccChannelConfig[channelId].voiceIdlePattern = voiceIdlePattern; + hssAccChannelConfig[channelId].txIdleAction = txIdleAction; + hssAccChannelConfig[channelId].numBypasses = 0; + + status = HssAccChannelConfigVoiceServiceMsgSend (channelId); + + if (ICP_STATUS_SUCCESS == status) + { + hssAccChannelConfig[channelId].state = + ICP_HSSACC_CHANNEL_SERVICE_CONFIGURED; + } + } + if (ICP_TRUE == mutexLocked) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelVoiceServiceConfigure - " + "failed to release HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccChannelVoiceServiceConfigure\n"); + return status; +} + + + + + + +/***************************************************************************** + * Abstract: + * Bring the specified channel UP, this will enable traffic flow on the + * channel. + * + *****************************************************************************/ +icp_status_t +icp_HssAccChannelUp (unsigned channelId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IxPiuMhMessage message; + icp_boolean_t mutexLocked = ICP_FALSE; + ICP_HSSACC_TRACE_1 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccChannelUp for channel %u\n", + channelId); + if (ICP_FALSE == channelConfigModuleInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelUp - " + "Service is not Initialised\n"); + status = ICP_STATUS_FAIL; + } + if (ICP_STATUS_SUCCESS == status) + { + if (ICP_HSSACC_MAX_NUM_CHANNELS <= channelId) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelUp - invalid " + "channel Number\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } + if (ICP_STATUS_SUCCESS == status) + { + if ((ICP_HSSACC_CHANNEL_SERVICE_CONFIGURED != + hssAccChannelConfig[channelId].state) && + (ICP_HSSACC_CHANNEL_DOWN != + hssAccChannelConfig[channelId].state)) + + { + ICP_HSSACC_REPORT_ERROR_1 ("icp_HssAccChannelUp - channel %u " + "is not in an appropriate state " + "for enabling\n", + channelId); + ICP_HSSACC_TRACE_2 (ICP_HSSACC_DEBUG, + "icp_HssAccChannelUp - channel %u " + "is state (%u) for enabling\n", + channelId, + hssAccChannelConfig[channelId].state); + status = ICP_STATUS_RESOURCE; + } + } + if (ICP_STATUS_SUCCESS == status) + { + /* Grab the HssAcc mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_LOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelUp - " + "failed to lock HssAcc Mutex\n"); + + status = ICP_STATUS_MUTEX; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + mutexLocked = ICP_TRUE; + + /* Construct the message to load the table */ + HssAccComTdmIOUnitCmd8byteMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_CHAN_FLOW_ENABLE, + channelId, + ICP_HSSACC_TDM_IO_UNIT_FLOW_DIR_BOTH, + 0, 0, 0, 0, 0, + &message); + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_CHAN_FLOW_ENABLE_RESPONSE, + &(hssAccChanCfgStats.chanEnable), + NULL); + + + if (ICP_STATUS_SUCCESS == status) + { + hssAccChannelConfig[channelId].state = ICP_HSSACC_CHANNEL_ENABLED; + } + } + + /* Free the HssAcc mutex */ + if (ICP_TRUE == mutexLocked) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelUp - " + "failed to release HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccChannelUp\n"); + return status; +} + + + +/***************************************************************************** + * Abstract: + * Bring down the specified channel. this will stop all traffic on + * that channel. + * + *****************************************************************************/ +icp_status_t +icp_HssAccChannelDown (unsigned channelId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IxPiuMhMessage message; + icp_boolean_t mutexLocked = ICP_FALSE; + ICP_HSSACC_TRACE_1 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccChannelDown for channel %u\n", + channelId); + if (ICP_FALSE == channelConfigModuleInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelDown - " + "Service is not Initialised\n"); + status = ICP_STATUS_FAIL; + } + if (ICP_STATUS_SUCCESS == status) + { + if (ICP_HSSACC_MAX_NUM_CHANNELS <= channelId) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelDown - invalid " + "channel\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } + if (ICP_STATUS_SUCCESS == status) + { + + /* Grab the HssAcc mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_LOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelDown - " + "failed to lock HssAcc Mutex\n"); + + status = ICP_STATUS_MUTEX; + } + else + { + mutexLocked = ICP_TRUE; + } + + } + + if (ICP_STATUS_SUCCESS == status) + { + if (ICP_HSSACC_CHANNEL_ENABLED != hssAccChannelConfig[channelId].state) + { + ICP_HSSACC_REPORT_ERROR_1 ("icp_HssAccChannelDown - " + "channel %u is not enabled\n", + channelId); + status = ICP_STATUS_RESOURCE; + } + } + if (ICP_STATUS_SUCCESS == status) + { + if (0 != hssAccChannelConfig[channelId].numBypasses) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelDown - channel is " + "used as part of a bypass, " + "disable bypass first\n"); + status = ICP_STATUS_RESOURCE; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + /* change the channel state so that the datapath puts + rx buffers onto the rx free queue and not into the + channel ring */ + hssAccChannelConfig[channelId].state = + ICP_HSSACC_CHANNEL_DOWN_TRANSITION; + + /* Construct the message to load the table */ + HssAccComTdmIOUnitCmd8byteMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_CHAN_FLOW_DISABLE, + channelId, + ICP_HSSACC_TDM_IO_UNIT_FLOW_DIR_BOTH, + 0, 0, 0, 0, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = + HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_CHAN_FLOW_DISABLE_RESPONSE, + &(hssAccChanCfgStats.chanDisable), + NULL); + + if (ICP_STATUS_SUCCESS == status) + { + hssAccChannelConfig[channelId].state = + ICP_HSSACC_CHANNEL_DOWN; + } + else + { + /* restore state to enabled as the channel down failed */ + hssAccChannelConfig[channelId].state = + ICP_HSSACC_CHANNEL_ENABLED; + } + } + + /* Free the HssAcc mutex */ + if (ICP_TRUE == mutexLocked) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelDown - " + "failed to release HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccChannelDown\n"); + return status; +} + + + + + + + +/***************************************************************************** + * Abstract: + * Delete the specified Channel. + * + *****************************************************************************/ +icp_status_t +icp_HssAccChannelDelete (unsigned channelId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + icp_boolean_t mutexLocked = ICP_FALSE; + ICP_HSSACC_TRACE_1 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccChannelDelete for channel %u\n", + channelId); + + if (ICP_FALSE == channelConfigModuleInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelDelete - " + "Service is not Initialised\n"); + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccChannelDelete\n"); + return ICP_STATUS_FAIL; + } + + if (ICP_HSSACC_MAX_NUM_CHANNELS <= channelId) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelDelete - invalid " + "channel\n"); + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccChannelDelete\n"); + return ICP_STATUS_INVALID_PARAM; + } + + + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_LOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelDelete - " + "failed to lock HssAcc Mutex\n"); + + status = ICP_STATUS_MUTEX; + } + else + { + mutexLocked = ICP_TRUE; + } + + + if (ICP_STATUS_SUCCESS == status) + { + if (!((ICP_HSSACC_CHANNEL_CONFIGURED == + hssAccChannelConfig[channelId].state) || + (ICP_HSSACC_CHANNEL_SERVICE_CONFIGURED == + hssAccChannelConfig[channelId].state) || + (ICP_HSSACC_CHANNEL_ALLOCATED == + hssAccChannelConfig[channelId].state))) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelDelete - channel " + "not available for deletion\n"); + status = ICP_STATUS_RESOURCE; + } + } + if (ICP_STATUS_SUCCESS == status) + { + + status = HssAccChannelListRemove(hssAccChannelConfig[channelId].portId, + channelId, + hssAccChannelConfig[channelId].size); + } + if (ICP_STATUS_SUCCESS == status) + { + /* Reset config, may have to actually send message to the + TDM I/O Unit to completely remove conf */ + HssAccTsUnregister (hssAccChannelConfig[channelId].portId, + hssAccChannelConfig[channelId].lineId, + hssAccChannelConfig[channelId].timeslotMap); + + /* Clear the timeslot allocation but keep the port, we + need it for generating the new tables */ + hssAccChannelConfig[channelId].lineId = ICP_HSSACC_LINE_DELIMITER; + hssAccChannelConfig[channelId].timeslotMap = 0; + hssAccChannelConfig[channelId].size = 0; + + /* Clear Timeslot Allocation for this channel */ + status = HssAccTsAllocDelete(channelId, + hssAccChannelConfig); + + /* Deregister rx callback */ + HssAccChannelRxCallbackDeregister(channelId); + + /* Deregister tx callback */ + HssAccTxDatapathChanTxDoneCallbackDeregister(channelId); + + } + if (ICP_STATUS_SUCCESS == status) + { + hssAccNumChansAllocated --; + + /* Clear the internal state */ + HssAccChannelConfigStateReset(channelId); + } + + /* Free the HssAcc mutex */ + if (ICP_TRUE == mutexLocked) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelDelete - " + "failed to release HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccChannelDelete\n"); + return status; +} + +/***************************************************************************** + * Abstract: + * Sends the channel Common Configuration message to the TDM I/O Unit. + * + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccChannelConfigMsgSend (unsigned channelId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IxPiuMhMessage message; + uint16_t sdcCtrl = 0; + uint8_t sdcCtrlMsB = 0; + uint8_t sdcCtrlLsB = 0; + uint32_t inversion = ICP_HSSACC_TDM_IO_UNIT_SDC_BIT_INVERT_OFF; + uint8_t channelType = 0; + uint8_t bitReverse = ICP_HSSACC_TDM_IO_UNIT_SDC_BIT_NO_REVERSE; + uint8_t byteSwap = ICP_HSSACC_TDM_IO_UNIT_SDC_BYTE_NO_SWAP; + uint8_t bitRobbing = ICP_HSSACC_TDM_IO_UNIT_SDC_RBIT_OFF; + uint8_t rBitValue = ICP_HSSACC_TDM_IO_UNIT_SDC_RBIT_VALUE_ZERO; + uint8_t rBitLocation = ICP_HSSACC_TDM_IO_UNIT_SDC_RBIT_LOC_SEVEN; + + ICP_HSSACC_TRACE_1 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelConfigMsgSend for channel %u\n", + channelId); + /* Build SDC Ctrl Register for the TDM I/O Unit */ + if (ICP_HSSACC_DATA_POLARITY_INVERT == + hssAccChannelConfig[channelId].dataPolarity) + { + inversion = ICP_HSSACC_TDM_IO_UNIT_SDC_BIT_INVERT_ON; + } + + if (ICP_HSSACC_CHAN_TYPE_VOICE == hssAccChannelConfig[channelId].type) + { + channelType = ICP_HSSACC_TDM_IO_UNIT_SDC_CHAN_TYPE_VOICE; + } + else + { + channelType = ICP_HSSACC_TDM_IO_UNIT_SDC_CHAN_TYPE_HDLC; + } + + /* if channel endianness is LSB then bit reversion required */ + if (ICP_HSSACC_BIT_ENDIAN_LSB == hssAccChannelConfig[channelId].bitEndian) + { + bitReverse = ICP_HSSACC_TDM_IO_UNIT_SDC_BIT_REVERSE; + } + + if (ICP_TRUE == hssAccChannelConfig[channelId].byteSwap) + { + byteSwap = ICP_HSSACC_TDM_IO_UNIT_SDC_BYTE_SWAP; + } + + if (ICP_HSSACC_BIT_ROBBING_ONE_BIT == + hssAccChannelConfig[channelId].bitRobbing) + { + bitRobbing = ICP_HSSACC_TDM_IO_UNIT_SDC_RBIT_ONE_BIT_ON; + } + + if (ICP_HSSACC_ROBBED_BIT_ONE == hssAccChannelConfig[channelId].rBitValue) + { + rBitValue = ICP_HSSACC_TDM_IO_UNIT_SDC_RBIT_VALUE_ONE; + } + + if (ICP_HSSACC_ROBBED_BIT_POS_0 == + hssAccChannelConfig[channelId].rBitLocation) + { + rBitLocation = ICP_HSSACC_TDM_IO_UNIT_SDC_RBIT_LOC_ZERO; + } + + sdcCtrl = (bitRobbing << + ICP_HSSACC_TDM_IO_UNIT_SDC_BIT_ROBBING_OFFSET) | + (rBitLocation << + ICP_HSSACC_TDM_IO_UNIT_SDC_RBIT_LOC_OFFSET) | + (rBitValue << + ICP_HSSACC_TDM_IO_UNIT_SDC_RBIT_VAL_OFFSET) | + (inversion << ICP_HSSACC_TDM_IO_UNIT_SDC_INVERT_OFFSET) | + (channelType << ICP_HSSACC_TDM_IO_UNIT_SDC_CHAN_TYPE_OFFSET) | + (bitReverse << ICP_HSSACC_TDM_IO_UNIT_SDC_BIT_REVERSE_OFFSET) | + (byteSwap << ICP_HSSACC_TDM_IO_UNIT_SDC_BYTE_SWAP_OFFSET); + ICP_HSSACC_TRACE_1(ICP_HSSACC_DEBUG, + "Created SDC Ctrl Register 0x%04X\n", + sdcCtrl); + + sdcCtrlMsB = (sdcCtrl & ICP_HSSACC_TDM_IO_UNIT_SDC_CTRL_MSB_MASK) >> + ICP_HSSACC_TDM_IO_UNIT_SDC_CTRL_MSB_OFFSET; + + sdcCtrlLsB = sdcCtrl & ICP_HSSACC_TDM_IO_UNIT_SDC_CTRL_LSB_MASK; + /* Construct the message to load the table */ + HssAccComTdmIOUnitCmd8byteMsgCreate (ICP_HSSACC_TDM_IO_UNIT_HSS_CHAN_CFG, + channelId, + hssAccChannelConfig[channelId].type, + hssAccChannelConfig[channelId].size, + sdcCtrlMsB, + sdcCtrlLsB, + 0, + 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HSS_CHAN_CFG_RESPONSE, + &(hssAccChanCfgStats.chanCfg), + NULL); + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelConfigMsgSend\n"); + return status; +} + + + + +/***************************************************************************** + * Abstract: + * Create the Transmit HDLC configuration register to be passed to the + * TDM I/O Unit. + * + *****************************************************************************/ +TDM_PRIVATE uint8_t +HssAccChannelHdlcTxCfgRegCreate (unsigned channelId) +{ + uint8_t cfgReg = 0; + /* will always post tx-hdlc block bit flip in SDC co-proc */ + uint8_t bitFlip = ICP_HSSACC_TDM_IO_UNIT_HDLC_CFG_BIT_FLIP; + uint8_t sofFlagType = ICP_HSSACC_TDM_IO_UNIT_HDLC_SOF_SHARED; + uint8_t hdlcCrcBitWidth = ICP_HSSACC_TDM_IO_UNIT_HDLC_16_BIT_CRC; + uint8_t hdlcTxIdlePattern = ICP_HSSACC_TDM_IO_UNIT_HDLC_IDLE_FLAG; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelHdlcTxCfgRegCreate\n"); + + if (ICP_HSSACC_HDLC_IDLE_PATTERN_ONES == + hssAccChannelConfig[channelId].hdlcTxIdlePattern) + { + hdlcTxIdlePattern = ICP_HSSACC_TDM_IO_UNIT_HDLC_IDLE_ONES; + } + + if (ICP_HSSACC_HDLC_CRC_BIT_WIDTH_32 == + hssAccChannelConfig[channelId].hdlcCrcBitWidth) + { + hdlcCrcBitWidth = ICP_HSSACC_TDM_IO_UNIT_HDLC_32_BIT_CRC; + } + if (ICP_HSSACC_HDLC_SOF_ONE_FLAG == + hssAccChannelConfig[channelId].sofFlagType) + { + sofFlagType = ICP_HSSACC_TDM_IO_UNIT_HDLC_SOF_ONE; + } + else if (ICP_HSSACC_HDLC_SOF_TWO_FLAGS == + hssAccChannelConfig[channelId].sofFlagType) + { + sofFlagType = ICP_HSSACC_TDM_IO_UNIT_HDLC_SOF_TWO; + } + + cfgReg = + (sofFlagType << + ICP_HSSACC_TDM_IO_UNIT_HDLC_TX_CFG_SF_OFFSET) | + (hdlcCrcBitWidth << + ICP_HSSACC_TDM_IO_UNIT_HDLC_TX_CFG_FCS_OFFSET) | + (hdlcTxIdlePattern << + ICP_HSSACC_TDM_IO_UNIT_HDLC_TX_CFG_IM_OFFSET) | + (bitFlip << + ICP_HSSACC_TDM_IO_UNIT_HDLC_TX_CFG_POSTBF_OFFSET); + + ICP_HSSACC_TRACE_1 (ICP_HSSACC_DEBUG, + "HssAccChannelHdlcTxCfgRegCreate 0x%02X\n", + cfgReg); + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelHdlcTxCfgRegCreate\n"); + return cfgReg; +} + +/***************************************************************************** + * Abstract: + * Create the Receive HDLC configuration register to be passed to the + * TDM I/O Unit. + * + *****************************************************************************/ +TDM_PRIVATE uint8_t +HssAccChannelHdlcRxCfgRegCreate (unsigned channelId) +{ + uint8_t cfgReg = 0; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelHdlcRxCfgRegCreate\n"); + + + cfgReg = + (hssAccChannelConfig[channelId].hdlcCrcBitWidth << + ICP_HSSACC_TDM_IO_UNIT_HDLC_RX_CFG_FCS_OFFSET) | + (hssAccChannelConfig[channelId].hdlcRxIdlePattern << + ICP_HSSACC_TDM_IO_UNIT_HDLC_RX_CFG_IM_OFFSET); + + /* always pre rx-hdlc block bit flip in SDC co-proc */ + cfgReg |= (ICP_HSSACC_TDM_IO_UNIT_HDLC_CFG_BIT_FLIP << + ICP_HSSACC_TDM_IO_UNIT_HDLC_RX_CFG_PREBF_OFFSET); + + ICP_HSSACC_TRACE_1 (ICP_HSSACC_DEBUG, + "HssAccChannelHdlcRxCfgRegCreate 0x%02X\n", cfgReg); + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelHdlcRxCfgRegCreate\n"); + return cfgReg; +} + + + +/***************************************************************************** + * Abstract: + * Sends the channel HDLC Service Configuration message to + * the TDM I/O Unit + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccChannelConfigHdlcServiceMsgSend (unsigned channelId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IxPiuMhMessage message; + uint32_t fcsSizeB = ICP_HSSACC_FCS_4_BYTE_WIDTH; + uint8_t txCfg = 0, rxCfg = 0; + ICP_HSSACC_TRACE_1 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelConfigHdlcServiceMsgSend " + "for channel %u\n", + channelId); + + if (ICP_HSSACC_HDLC_CRC_BIT_WIDTH_16 == + hssAccChannelConfig[channelId].hdlcCrcBitWidth) + { + fcsSizeB = ICP_HSSACC_FCS_2_BYTE_WIDTH; + } + + + /* Construct the TxCfg and RxCfg registers for the TDM I/O Unit */ + txCfg = HssAccChannelHdlcTxCfgRegCreate(channelId); + + rxCfg = HssAccChannelHdlcRxCfgRegCreate(channelId); + + /* Construct the message to load the table */ + HssAccComTdmIOUnitCmd8byteMsgCreate (ICP_HSSACC_TDM_IO_UNIT_HDLC_CHAN_CFG, + channelId, + 0, + 0, + 0, + rxCfg, + txCfg, + fcsSizeB, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HDLC_CHAN_CFG_RESPONSE, + &(hssAccChanCfgStats.hdlcChanCfg), + NULL); + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelConfigHdlcServiceMsgSend\n"); + return status; +} + + + + + +/***************************************************************************** + * Abstract: + * Sends the channel HDLC Maximum Receive Frame Size configuration message + * to the TDM I/O Unit. + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccChannelConfigHdlcMaxFrameSizeSend (unsigned channelId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IxPiuMhMessage message; + uint32_t hdlcMaximumFrameSize = 0; + ICP_HSSACC_TRACE_1 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelConfigHdlcMaxFrameSizeSend " + "for channel %u\n", + channelId); + + hdlcMaximumFrameSize = + hssAccChannelConfig[channelId].hdlcMaxFrSize << + ICP_HSSACC_TDM_IO_UNIT_SHORT0_OFFSET; + + /* Construct the message to load the table */ + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_HDLC_CHAN_RX_MAX_SIZE_WR, + channelId, + 0, + 0, + hdlcMaximumFrameSize, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HDLC_CHAN_RX_MAX_SIZE_WR_RESPONSE, + &(hssAccChanCfgStats.hdlcMaxRxCfg), + NULL); + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelConfigHdlcMaxFrameSizeSend\n"); + return status; +} + + +/***************************************************************************** + * Abstract: + * Sends the channel Voice Service Configuration message to + * the TDM I/O Unit + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccChannelConfigVoiceServiceMsgSend (unsigned channelId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IxPiuMhMessage message; + uint32_t msgWord = 0; + ICP_HSSACC_TRACE_1 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelConfigVoiceServiceMsgSend " + "for channel %u\n", + channelId); + msgWord = + (hssAccChannelConfig[channelId].voiceIdlePattern << + ICP_HSSACC_TDM_IO_UNIT_BYTE0_OFFSET) | + (hssAccChannelConfig[channelId].txIdleAction << + ICP_HSSACC_TDM_IO_UNIT_BYTE1_OFFSET) | + hssAccChannelConfig[channelId].voiceSampleSize; + + /* Construct the message for Channel Voice parameters setting + in the TDM I/O Unit */ + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_VOICE_CHAN_CFG, + channelId, + 0, + 0, + msgWord, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_VOICE_CHAN_CFG_RESPONSE, + &(hssAccChanCfgStats.voiceChanCfg), + NULL); + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelConfigVoiceServiceMsgSend\n"); + return status; +} + + + + + + +/***************************************************************************** + * Abstract: + * determines if it is valid to configure a bypass using the + * specified channel. + * + *****************************************************************************/ +icp_boolean_t +HssAccChannelConfigValidBypass(const unsigned channelId, + const unsigned portId) +{ + icp_boolean_t validChannel = ICP_FALSE; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelConfigValidBypass\n"); + + + ICP_HSSACC_TRACE_3 (ICP_HSSACC_DEBUG, + "HssAccChannelConfigValidBypass - " + "Channel %u of size %u and state %u " + "selected for Bypass\n", + channelId, + hssAccChannelConfig[channelId].size, + hssAccChannelConfig[channelId].state); + + if ((ICP_HSSACC_CHAN_TYPE_VOICE == hssAccChannelConfig[channelId].type) && + (ICP_HSSACC_VOICE_NB_CHAN_SIZE == hssAccChannelConfig[channelId].size) && + (ICP_HSSACC_CHANNEL_ENABLED == hssAccChannelConfig[channelId].state) && + (portId == hssAccChannelConfig[channelId].portId)) + { + validChannel = ICP_TRUE; + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelConfigValidBypass\n"); + return validChannel; +} + + + +/***************************************************************************** + * Abstract: + * reset the Channel configuration stats + * + *****************************************************************************/ +void +HssAccChannelConfigStatsReset (void) +{ + memset (&hssAccChanCfgStats, 0, sizeof(icp_hssacc_channel_config_stats_t)); + HssAccChannelListsStatsReset (); + +} + +/***************************************************************************** + * Abstract: + * Display stats for channel configuration + * + *****************************************************************************/ +void +HssAccChannelConfigStatsShow (void) +{ + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nChannel Configuration Statistics:\nChannel Config messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccChanCfgStats.chanCfg); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nHDLC Channel Config messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccChanCfgStats.hdlcChanCfg); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nVoice Channel Config messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccChanCfgStats.voiceChanCfg); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\noffset Table Load\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccChanCfgStats.offsetTableLoad); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nHDLC Max Receive Frame Size Cfg messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccChanCfgStats.hdlcMaxRxCfg); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nChannel Enable messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccChanCfgStats.chanEnable); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nChannel Disable messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccChanCfgStats.chanDisable); + + /* Also print out the Timeslot Allocation submodule stats */ + HssAccTsAllocStatsShow (); + +} + + +/***************************************************************************** + * Abstract: + * display the state of the specified channel + * + *****************************************************************************/ +void +HssAccChannelConfigStateShow (unsigned channelId) +{ + if (ICP_HSSACC_CHANNEL_UNINITIALISED == + hssAccChannelConfig[channelId].state) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nChannel %u is Uninitialised.\n", + channelId, 0, 0, 0, 0, 0); + } + else + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nChannel %u is Allocated on port %u Line %u with " + "%u Timeslots\nTimeslot Map is 0x%08X\n", + channelId, + hssAccChannelConfig[channelId].portId, + hssAccChannelConfig[channelId].lineId, + hssAccChannelConfig[channelId].size, + hssAccChannelConfig[channelId].timeslotMap, 0); + + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Channel has been Configured with:\n" + "\tData Inversion %u\n" + "\tBit Endianness %u\n" + "\tByte Endianness %u\n", + hssAccChannelConfig[channelId].dataPolarity, + hssAccChannelConfig[channelId].bitEndian, + hssAccChannelConfig[channelId].byteSwap, 0, 0, 0); + if (ICP_HSSACC_BIT_ROBBING_ONE_BIT == + hssAccChannelConfig[channelId].bitRobbing) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Bit Robbing is Enabled with a value of %u and " + "a position of %d\n", + hssAccChannelConfig[channelId].rBitValue, + hssAccChannelConfig[channelId].rBitLocation == + ICP_HSSACC_ROBBED_BIT_POS_7 ? 7 + : (hssAccChannelConfig[channelId].rBitLocation == + ICP_HSSACC_ROBBED_BIT_POS_0 ? 0 : -1), + 0, 0, 0, 0); + } + + if (ICP_HSSACC_CHAN_TYPE_VOICE == hssAccChannelConfig[channelId].type) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Channel is Allocated for Voice\n", 0, 0, 0, 0, 0, 0); + } + else + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Channel is Allocated for HDLC\n", 0, 0, 0, 0, 0, 0); + } + switch (hssAccChannelConfig[channelId].state) + { + case ICP_HSSACC_CHANNEL_ALLOCATED: + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Channel has only been allocated\n", 0, 0, 0, 0, 0, 0); + break; + + } + case ICP_HSSACC_CHANNEL_CONFIGURED: + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Channel has been allocated and configured with " + "general settings\n", + 0, 0, 0, 0, 0, 0); + break; + + } + case ICP_HSSACC_CHANNEL_SERVICE_CONFIGURED: + case ICP_HSSACC_CHANNEL_DOWN: + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Channel has been allocated and service " + "specific parameters have been set\n", 0, 0, 0, 0, 0, 0); + break; + + } + case ICP_HSSACC_CHANNEL_ENABLED: + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Channel is Enabled\n", 0, 0, 0, 0, 0, 0); + break; + + } + case ICP_HSSACC_CHANNEL_UNINITIALISED: + default: + { + /* This statement is unreachable due to previous error checking */ + ICP_HSSACC_REPORT_ERROR("HssAccChannelConfigStateShow - " + "Invalid Channel State to be printed\n"); + break; + } + } + } +} + +/***************************************************************************** + * Abstract: + * reset all the internal data regarding the specified channel + * + *****************************************************************************/ +TDM_PRIVATE void +HssAccChannelConfigStateReset (unsigned channelId) +{ + hssAccChannelConfig[channelId].state = ICP_HSSACC_CHANNEL_UNINITIALISED; + hssAccChannelConfig[channelId].type = ICP_HSSACC_CHAN_TYPE_DELIMITER; + hssAccChannelConfig[channelId].size = 0; + hssAccChannelConfig[channelId].portId = ICP_HSSACC_MAX_NUM_PORTS; + hssAccChannelConfig[channelId].lineId = ICP_HSSACC_LINE_DELIMITER; + hssAccChannelConfig[channelId].timeslotMap = 0; + hssAccChannelConfig[channelId].sdcCtrlReg = 0; + hssAccChannelConfig[channelId].rxCfg = 0; + hssAccChannelConfig[channelId].txCfg = 0; + hssAccChannelConfig[channelId].dataPolarity = ICP_HSSACC_DATA_POLARITY_SAME; + hssAccChannelConfig[channelId].bitEndian = ICP_HSSACC_BIT_ENDIAN_DELIMITER; + hssAccChannelConfig[channelId].byteSwap = ICP_FALSE; + hssAccChannelConfig[channelId].bitRobbing = ICP_HSSACC_BIT_ROBBING_DELIMITER; + hssAccChannelConfig[channelId].rBitValue = ICP_HSSACC_ROBBED_BIT_DELIMITER; + hssAccChannelConfig[channelId].rBitLocation = + ICP_HSSACC_ROBBED_BIT_POS_DELIMITER; + hssAccChannelConfig[channelId].hdlcMaxFrSize = 0; + hssAccChannelConfig[channelId].numBypasses = 0; + hssAccChannelConfig[channelId].sofFlagType = + ICP_HSSACC_HDLC_SOF_FLAG_TYPE_DELIMITER; + hssAccChannelConfig[channelId].hdlcTxIdlePattern = + ICP_HSSACC_HDLC_IDLE_PATTERN_DELIMITER; + hssAccChannelConfig[channelId].hdlcRxIdlePattern = + ICP_HSSACC_HDLC_IDLE_PATTERN_DELIMITER; + hssAccChannelConfig[channelId].voiceSampleSize = 0; + hssAccChannelConfig[channelId].voiceIdlePattern = 0; + hssAccChannelConfig[channelId].txIdleAction = + ICP_HSSACC_VOICE_TX_IDLE_DELIMITER; + hssAccChannelConfig[channelId].hdlcCrcBitWidth = + ICP_HSSACC_HDLC_CRC_BIT_WIDTH_DELIMITER; +} + +/***************************************************************************** + * Abstract: + * returns the configured channel type for the specified channel + * + *****************************************************************************/ +icp_hssacc_channel_type_t +HssAccChannelConfigTypeQuery (unsigned channelId) +{ + return hssAccChannelConfig[channelId].type; +} + + +/***************************************************************************** + * Abstract: + * set the specified channels as part of a bypass. + * + *****************************************************************************/ +void +HssAccChannelBypassPairSet(unsigned srcChannelId, + unsigned destChannelId) +{ + hssAccChannelConfig[srcChannelId].numBypasses ++; + hssAccChannelConfig[destChannelId].numBypasses ++; +} + + +/***************************************************************************** + * Abstract: + * clear the bypassed state for the specified channels + * + *****************************************************************************/ +void +HssAccChannelBypassPairClear(unsigned srcChannelId, + unsigned destChannelId) +{ + hssAccChannelConfig[srcChannelId].numBypasses --; + hssAccChannelConfig[destChannelId].numBypasses --; +} + + +/***************************************************************************** + * Abstract: + * returns the state of the specified channel + * + *****************************************************************************/ +icp_hssacc_channel_state_t +HssAccChannelConfigStateQuery (unsigned channelId) +{ + return hssAccChannelConfig[channelId].state; +} + + +/***************************************************************************** + * Abstract: + * used by the datapath modules to notify for a change of channel state + * following the retrieval of all buffers in the channel queues. + * + *****************************************************************************/ +void +HssAccChannelConfigBuffersClearedNotify (unsigned channelId) +{ + if (ICP_HSSACC_CHANNEL_DOWN == hssAccChannelConfig[channelId].state) + { + hssAccChannelConfig[channelId].state = + ICP_HSSACC_CHANNEL_SERVICE_CONFIGURED; + } +} + + + + +/***************************************************************************** + * Abstract: + * return ICP_TRUE if there are any allocated channels on + * the specified port. + * + *****************************************************************************/ +icp_boolean_t +HssAccChannelConfigUsedChansOnPortFind (const unsigned portId) +{ + icp_boolean_t chanFound = ICP_FALSE; + unsigned index = 0; + + for (index = 0; index < ICP_HSSACC_MAX_NUM_CHANNELS; index ++) + { + if ((ICP_HSSACC_CHANNEL_UNINITIALISED != + hssAccChannelConfig[index].state) && + (portId == hssAccChannelConfig[index].portId)) + { + ICP_HSSACC_TRACE_2 (ICP_HSSACC_DEBUG, + "HssAccChannelConfigUsedChansOnPortFind - " + "Channel %u allocated on port %u\n", + index, + portId); + chanFound = ICP_TRUE; + break; + } + } + + return chanFound; +} + + diff --git a/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_channel_list.c b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_channel_list.c new file mode 100644 index 0000000..5843de9 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_channel_list.c @@ -0,0 +1,911 @@ +/***************************************************************************** + * + * @file icp_hssacc_channel_list.c + * + * @description Contents of this file is the implementation of the channel + * list manipulation functionality. + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + *****************************************************************************/ + + +#include "icp.h" +#include "icp_hssacc.h" +#include "icp_hssacc_trace.h" +#include "icp_hssacc_common.h" + + + + + +/** + * Typedefs whose scope is limited to this file. + */ + + +/* Structure holding list configuration data for one channel */ +typedef struct icp_hssacc_channel_list_data_s +{ + uint16_t prevChannelId; + uint16_t nextChannelId; + icp_hssacc_channel_list_t listId; +} icp_hssacc_channel_list_data_t; + + + +/* Stats for List Management*/ +typedef struct icp_hssacc_channel_list_stats_s +{ + icp_hssacc_msg_with_resp_stats_t nextChannelWrite; + icp_hssacc_msg_with_resp_stats_t portCfgChannel; +} icp_hssacc_channel_list_stats_t; + + +/* channel List Data for each channel */ +TDM_PRIVATE icp_hssacc_channel_list_data_t +hssAccChannelData[ICP_HSSACC_MAX_NUM_CHANNELS]; + +/* Track which channel is the last of the list for each list + on each port */ +TDM_PRIVATE uint32_t +hssAccLastChannelOnList[ICP_HSSACC_MAX_NUM_PORTS] +[ICP_HSSACC_CHANNEL_LIST_DELIMITER]; + +/* Internal Messaging Stats for this sub-module */ +TDM_PRIVATE icp_hssacc_channel_list_stats_t hssAccChannelListStats; + +/* Track the amount of IO transactions represented by each + list on each port */ +TDM_PRIVATE uint32_t +hssAccPortChannelListUsage[ICP_HSSACC_MAX_NUM_PORTS] +[ICP_HSSACC_CHANNEL_LIST_DELIMITER]; + +/* Construct and send the NextChanWrite message to the TDM IO Unit */ +TDM_PRIVATE icp_status_t +HssAccChannelNextChanWriteMsgSend (unsigned prevChannelId, + unsigned nextChannelId, + uint8_t txRxIndicator, + uint8_t nullFlag); + + +/* + * Function Prototype: HssAccChanIOUsageCalc + * Description: this function calculates the number + * of IO transactions that a specific channelSize implies + */ +inline unsigned HssAccChanIOUsageCalc(unsigned chanSize) +{ + unsigned channelUsageIO = + chanSize / ICP_HSSACC_TDM_IO_UNIT_MAX_TRANSACTION_SIZE_WRDS; + channelUsageIO ++; + if ( (chanSize % ICP_HSSACC_TDM_IO_UNIT_MAX_TRANSACTION_SIZE_WRDS) > 1 ) + { + channelUsageIO ++; + } + return channelUsageIO; +} + + + + +/* + * Function Prototype: HssAccChannelListMap + * Description: this function maps internal sub-module + * list IDs to TDM I/O Unit list IDs + */ +inline icp_status_t +HssAccChannelListMap (icp_hssacc_channel_list_t listId, + icp_hssacc_tdm_io_unit_channel_list_t *txList, + icp_hssacc_tdm_io_unit_channel_list_t *rxList) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + switch (listId) + { + case ICP_HSSACC_CHANNEL_LIST_PRIMARY: + *txList = ICP_HSSACC_TDM_IO_UNIT_LIST_TX_PRIMARY; + *rxList = ICP_HSSACC_TDM_IO_UNIT_LIST_RX_PRIMARY; + break; + case ICP_HSSACC_CHANNEL_LIST_SECONDARY_0: + *txList = ICP_HSSACC_TDM_IO_UNIT_LIST_TX_SECONDARY_0; + *rxList = ICP_HSSACC_TDM_IO_UNIT_LIST_RX_SECONDARY_0; + break; + case ICP_HSSACC_CHANNEL_LIST_SECONDARY_1: + *txList = ICP_HSSACC_TDM_IO_UNIT_LIST_TX_SECONDARY_1; + *rxList = ICP_HSSACC_TDM_IO_UNIT_LIST_RX_SECONDARY_1; + break; + case ICP_HSSACC_CHANNEL_LIST_DELIMITER: + default: + ICP_HSSACC_REPORT_ERROR("HssAccChannelListMap - " + "Invalid List ID provided\n"); + status = ICP_STATUS_FAIL; + break; + } + return status; +} + +/* + * Function Prototype: HssAccChannelFirstChanAdd + * Description: this function will add a channel to an empty list of + * channels processed on the port. + */ +TDM_PRIVATE icp_status_t +HssAccChannelFirstChanAdd (unsigned hssPortId, + unsigned channelId, + icp_hssacc_channel_list_t listId, + icp_hssacc_channel_list_data_t *pListData); + +/* + * Function Prototype: HssAccChannelLastChanAdd + * Description: this function will add a channel to the end of a list of + * channels processed on the port. + */ +TDM_PRIVATE icp_status_t +HssAccChannelLastChanAdd (unsigned hssPortId, + unsigned channelId, + icp_hssacc_channel_list_t listId, + icp_hssacc_channel_list_data_t *pListData); + +/* + * Function Prototype: HssAccChannelFirstChanDel + * Description: this function will remove a channel that is at + * the start of a list of channels processed on the port. + */ +TDM_PRIVATE icp_status_t +HssAccChannelFirstChanDel (unsigned hssPortId, + unsigned channelId, + icp_hssacc_channel_list_t listId, + icp_hssacc_channel_list_data_t *pListData); + +/* + * Function Prototype: HssAccChannelLastChanDel + * Description: this function will remove a channel that is at the + * end of a list of channels processed on the port. + */ +TDM_PRIVATE icp_status_t +HssAccChannelLastChanDel (unsigned hssPortId, + icp_hssacc_channel_list_t listId, + icp_hssacc_channel_list_data_t *pListData); + +/* + * Function Prototype: HssAccChannelMiddleChanDel + * Description: this function will remove a channel that is in + * the middle of a list of channels processed on the port. + */ +TDM_PRIVATE icp_status_t +HssAccChannelMiddleChanDel (icp_hssacc_channel_list_data_t *pListData); + + +/* + * Function Prototype: HssAccChannelListsStatsReset + * Reset the Stats for this sub-module + */ +void +HssAccChannelListsStatsReset (void) +{ + memset (&hssAccChannelListStats,0,sizeof(icp_hssacc_channel_list_stats_t)); +} + + + +/* + * Function Definition: HssAccChannelListsReset + */ +void HssAccChannelListsReset (void) +{ + unsigned index = 0; + icp_hssacc_channel_list_t listId = ICP_HSSACC_CHANNEL_LIST_DELIMITER; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelListsReset\n"); + /* Initialise internal data, + set last channel IDs for each HSS Port to INVALID_CHAN */ + for (index = 0; index < ICP_HSSACC_MAX_NUM_PORTS; index ++) + { + for (listId = 0; listId < ICP_HSSACC_CHANNEL_LIST_DELIMITER; listId ++) + { + hssAccLastChannelOnList[index][listId] = ICP_HSSACC_INVALID_CHAN; + hssAccPortChannelListUsage[index][listId] = 0; + } + } + for (index = 0; index < ICP_HSSACC_MAX_NUM_CHANNELS; index ++) + { + hssAccChannelData[index].prevChannelId = ICP_HSSACC_INVALID_CHAN; + hssAccChannelData[index].nextChannelId = ICP_HSSACC_INVALID_CHAN; + hssAccChannelData[index].listId = ICP_HSSACC_CHANNEL_LIST_DELIMITER; + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelListsReset\n"); +} + + + +/* Function definition: HssAccNextChannelListGet + Description: Figures out the next linked list to use when + commissioning a new channel + ASSUMPTION: The channel data for the specified channel must be valid */ +TDM_PRIVATE icp_hssacc_channel_list_t +HssAccNextChannelListGet (uint32_t hssPortId) +{ + /* Get the List Id (symmetrical for Tx and Rx) */ + + icp_hssacc_channel_list_t smallestList = ICP_HSSACC_CHANNEL_LIST_PRIMARY; + uint16_t smallestSize = + hssAccPortChannelListUsage[hssPortId][ICP_HSSACC_CHANNEL_LIST_PRIMARY]; + + if (smallestSize > + hssAccPortChannelListUsage[hssPortId] + [ICP_HSSACC_CHANNEL_LIST_SECONDARY_0]) + { + smallestList = ICP_HSSACC_CHANNEL_LIST_SECONDARY_0; + smallestSize = + hssAccPortChannelListUsage[hssPortId] + [ICP_HSSACC_CHANNEL_LIST_SECONDARY_0]; + } + +#if !defined(IXP23XX) || defined(UNIT_TEST) + if (smallestSize > + hssAccPortChannelListUsage[hssPortId] + [ICP_HSSACC_CHANNEL_LIST_SECONDARY_1]) + { + smallestList = ICP_HSSACC_CHANNEL_LIST_SECONDARY_1; + } +#endif + return smallestList; + +} + + +icp_status_t +HssAccChannelListAdd (unsigned hssPortId, + unsigned chanId, + unsigned chanSize) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + icp_hssacc_channel_list_t listId = ICP_HSSACC_CHANNEL_LIST_DELIMITER; + icp_hssacc_channel_list_data_t *pListData = NULL; + unsigned channelUsageIO = 0; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelListAdd\n"); + + /* check the channel isnt already in a list */ + pListData = &(hssAccChannelData[chanId]); + + if (pListData->listId != ICP_HSSACC_CHANNEL_LIST_DELIMITER) + { + ICP_HSSACC_REPORT_ERROR_2 ("HssAccChannelListAdd - " + "Channel %d already part of list %d\n", + chanId, + pListData->listId); + status = ICP_STATUS_FAIL; + } + + if (ICP_STATUS_SUCCESS == status) + { + /* find a list to add to */ + listId = HssAccNextChannelListGet(hssPortId); + + ICP_HSSACC_TRACE_4 (ICP_HSSACC_DEBUG, + "HssAccChannelListAdd - Adding Channel %d" + " to List %d on Port %d, current last chan is %d\n", + chanId, + listId, + hssPortId, + hssAccLastChannelOnList[hssPortId][listId]); + + if (hssAccLastChannelOnList[hssPortId][listId] == + ICP_HSSACC_INVALID_CHAN) + { + ICP_HSSACC_TRACE_0 (ICP_HSSACC_DEBUG, + "HssAccChannelListAdd - List is empty\n"); + + status = HssAccChannelFirstChanAdd (hssPortId, + chanId, + listId, + pListData); + } + else + { + ICP_HSSACC_TRACE_0 (ICP_HSSACC_DEBUG, + "HssAccChannelListAdd - Add to end of list\n"); + + status = HssAccChannelLastChanAdd (hssPortId, + chanId, + listId, + pListData); + } + } + + if (ICP_STATUS_SUCCESS == status) + { + /* list is selected depending on usage. usage is determined depending on + the amount estimated amount of IO transactions generated for that + list. for each channel, IO transactions is defined as + channelSizeInWords/transactionSize + 1 or 2 + (if modulus greater than 1). */ + channelUsageIO = HssAccChanIOUsageCalc(chanSize); + + hssAccPortChannelListUsage[hssPortId][listId] += channelUsageIO; + + } + + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelListAdd\n"); + return status; +} + + + + +icp_status_t +HssAccChannelListRemove (unsigned hssPortId, + unsigned chanId, + unsigned chanSize) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + icp_hssacc_channel_list_t listId = ICP_HSSACC_CHANNEL_LIST_DELIMITER; + icp_hssacc_channel_list_data_t *pListData = NULL; + unsigned channelUsageIO = 0; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelListRemove\n"); + /* Get Channel Data and check that it is in a list */ + pListData = &(hssAccChannelData[chanId]); + + listId = pListData->listId; + if (listId == ICP_HSSACC_CHANNEL_LIST_DELIMITER) + { + ICP_HSSACC_REPORT_ERROR_1 ("HssAccChannelListRemove - " + "Channel %d not part of any list\n", + chanId); + + status = ICP_STATUS_FAIL; + } + + + if (ICP_STATUS_SUCCESS == status) + { + + /* The channel to be deleted is the first channel on this list */ + if (pListData->prevChannelId == ICP_HSSACC_INVALID_CHAN) + { + status = HssAccChannelFirstChanDel (hssPortId, + chanId, + listId, + pListData); + } + /* The channel to be deleted is not the first channel on this list */ + else + { + if (hssAccLastChannelOnList[hssPortId][listId] == chanId) + { + /* we are deleting the last channel of the list */ + status = HssAccChannelLastChanDel (hssPortId, + listId, + pListData); + } + else + { + /* we are deleting a channel from the middle of the list */ + status = HssAccChannelMiddleChanDel (pListData); + } + } + } + + /* for the channel we are deleting, set its next pointer to point to NULL to + * avoid the possibility of an infinite loop when it is added later */ + if (ICP_STATUS_SUCCESS == status) + { + /* first set the tx 'next' pointer to NULL */ + status = + HssAccChannelNextChanWriteMsgSend ( + chanId, + 0, + IX_HSSACC_TDM_IO_UNIT_LIST_INDICATOR_TX, + ICP_HSSACC_TDM_IO_UNIT_CHAN_DEL_FLAG); + } + + if (ICP_STATUS_SUCCESS == status) + { + /* now set the rx 'next' pointer to NULL */ + status = + HssAccChannelNextChanWriteMsgSend ( + chanId, + 0, + IX_HSSACC_TDM_IO_UNIT_LIST_INDICATOR_RX, + ICP_HSSACC_TDM_IO_UNIT_CHAN_DEL_FLAG); + } + + if (ICP_STATUS_SUCCESS == status) + { + /* list is selected depending on usage. usage is determined depending on + the estimated amount of IO transactions generated for that + list. for each channel, IO transactions is defined as + channelSizeInWords/transactionSize+1 or 2 (if module greater + than 1).*/ + channelUsageIO = HssAccChanIOUsageCalc(chanSize); + + hssAccPortChannelListUsage[hssPortId][listId] -= channelUsageIO; + + } + + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelListRemove\n"); + return status; +} + + + + + + + +/* + * Function definition: HssAccChannelNextChanWriteMsgSend + */ +TDM_PRIVATE icp_status_t +HssAccChannelNextChanWriteMsgSend (unsigned prevChannelId, + unsigned nextChannelId, + uint8_t txRxIndicator, + uint8_t nullFlag) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IxPiuMhMessage message; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelNextChanWriteMsgSend\n"); + + /* Create the message for the TDM I/O Unit */ + HssAccComTdmIOUnitCmd8byteMsgCreate (ICP_HSSACC_TDM_IO_UNIT_NEXT_CHAN_WRITE, + prevChannelId, + 0, 0, + nextChannelId, + nullFlag, + txRxIndicator, + 0, + &message); + + + /* Send the message to the TDM I/O Unit */ + status = + HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_NEXT_CHAN_WRITE_RESPONSE, + &(hssAccChannelListStats.nextChannelWrite), + NULL); + + + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1 ("HssAccChannelNextChanWriteMsgSend - " + "Messaging failure for channel %d\n", + prevChannelId); + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelNextChanWriteMsgSend\n"); + return status; +} + + + + + +/* + * Function definition: HssAccChannelPortCfgMsgSend + */ +TDM_PRIVATE icp_status_t +HssAccChannelPortCfgMsgSend (unsigned hssPortId, + unsigned channelId, + icp_hssacc_channel_list_t listId, + uint8_t nullFlag) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IxPiuMhMessage message; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelPortCfgMsgSend\n"); + + /* Create the message for the TDM I/O Unit*/ + HssAccComTdmIOUnitCmd8byteMsgCreate (ICP_HSSACC_TDM_IO_UNIT_HSS_PORT_CFG, + hssPortId, + 0, 0, + channelId, + nullFlag, + listId, + 0, + &message); + /* Send the message to the TDM I/O Unit */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HSS_PORT_CFG_RESPONSE, + &(hssAccChannelListStats.portCfgChannel), + NULL); + + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_2 ("HssAccChannelPortCfgMsgSend - Messaging " + "failure for port %d, channel %d\n", + hssPortId, + channelId); + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelPortCfgMsgSend\n"); + return status; +} + + +/* + * Function definition: HssAccChannelFirstChanAdd + */ +TDM_PRIVATE icp_status_t +HssAccChannelFirstChanAdd (unsigned hssPortId, + unsigned channelId, + icp_hssacc_channel_list_t listId, + icp_hssacc_channel_list_data_t *pListData) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + icp_hssacc_tdm_io_unit_channel_list_t rxList, txList = + ICP_HSSACC_TDM_IO_UNIT_LIST_DELIMITER; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelFirstChanAdd\n"); + + status = HssAccChannelListMap (listId, &txList, &rxList); + + if (ICP_STATUS_SUCCESS == status) + { + + status = + HssAccChannelPortCfgMsgSend (hssPortId, + channelId, + txList, + ICP_HSSACC_TDM_IO_UNIT_CHAN_ADD_FLAG); + } + if (ICP_STATUS_SUCCESS == status) + { + status = + HssAccChannelPortCfgMsgSend (hssPortId, + channelId, + rxList, + ICP_HSSACC_TDM_IO_UNIT_CHAN_ADD_FLAG); + } + + if (ICP_STATUS_SUCCESS == status) + { + pListData->listId = listId; + pListData->prevChannelId = ICP_HSSACC_INVALID_CHAN; + pListData->nextChannelId = ICP_HSSACC_INVALID_CHAN; + + hssAccLastChannelOnList[hssPortId][listId] = channelId; + + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelFirstChanAdd\n"); + return status; +} + +/* + * Function definition: HssAccChannelLastChanAdd + */ +TDM_PRIVATE icp_status_t +HssAccChannelLastChanAdd (unsigned hssPortId, + unsigned channelId, + icp_hssacc_channel_list_t listId, + icp_hssacc_channel_list_data_t *pListData) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + unsigned prevChannelId = 0; + icp_hssacc_channel_list_data_t *pPrevChanList = NULL; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelLastChanAdd\n"); + + prevChannelId = hssAccLastChannelOnList[hssPortId][listId]; + + status = + HssAccChannelNextChanWriteMsgSend (prevChannelId, + channelId, + IX_HSSACC_TDM_IO_UNIT_LIST_INDICATOR_TX, + ICP_HSSACC_TDM_IO_UNIT_CHAN_ADD_FLAG); + + if (ICP_STATUS_SUCCESS == status) + { + + status = + HssAccChannelNextChanWriteMsgSend( + prevChannelId, + channelId, + IX_HSSACC_TDM_IO_UNIT_LIST_INDICATOR_RX, + ICP_HSSACC_TDM_IO_UNIT_CHAN_ADD_FLAG); + } + + if (status == ICP_STATUS_SUCCESS) + { + pListData->listId = listId; + pListData->prevChannelId = prevChannelId; + pListData->nextChannelId = ICP_HSSACC_INVALID_CHAN; + pPrevChanList = &(hssAccChannelData[prevChannelId]); + pPrevChanList->nextChannelId = channelId; + + hssAccLastChannelOnList[hssPortId][listId] = channelId; + + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelLastChanAdd\n"); + return status; +} + + + +/* + * Function definition: HssAccChannelFirstChanDel + */ +TDM_PRIVATE icp_status_t +HssAccChannelFirstChanDel (unsigned hssPortId, + unsigned channelId, + icp_hssacc_channel_list_t listId, + icp_hssacc_channel_list_data_t *pListData) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + icp_hssacc_tdm_io_unit_channel_list_t rxList, txList = + ICP_HSSACC_TDM_IO_UNIT_LIST_DELIMITER; + unsigned nextChannelId = 0; + icp_hssacc_channel_list_data_t *pNextChanListData = NULL; + + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelFirstChanDel\n"); + + status = HssAccChannelListMap(listId, &txList, &rxList); + + if (ICP_STATUS_SUCCESS != status) + { + return status; + } + + /* Check if it is also the only channel processed on this list */ + if (hssAccLastChannelOnList[hssPortId][listId] == channelId) + { + /* ChannelId parameter will be ignored by the TDM I/O Unit in + this case */ + status = + HssAccChannelPortCfgMsgSend (hssPortId, + 0, + txList, + ICP_HSSACC_TDM_IO_UNIT_CHAN_DEL_FLAG); + + if (ICP_STATUS_SUCCESS == status) + { + status = + HssAccChannelPortCfgMsgSend (hssPortId, + 0, + rxList, + ICP_HSSACC_TDM_IO_UNIT_CHAN_DEL_FLAG); + + } + + if (ICP_STATUS_SUCCESS == status) + { + pListData->listId = ICP_HSSACC_CHANNEL_LIST_DELIMITER; + hssAccLastChannelOnList[hssPortId][listId] = ICP_HSSACC_INVALID_CHAN; + + } + } + else + { + + /* Get information for the next channel on the list */ + nextChannelId = pListData->nextChannelId; + + status = + HssAccChannelPortCfgMsgSend (hssPortId, + nextChannelId, + txList, + ICP_HSSACC_TDM_IO_UNIT_CHAN_ADD_FLAG); + if (ICP_STATUS_SUCCESS == status) + { + status = + HssAccChannelPortCfgMsgSend (hssPortId, + nextChannelId, + rxList, + ICP_HSSACC_TDM_IO_UNIT_CHAN_ADD_FLAG); + } + + if (status == ICP_STATUS_SUCCESS) + { + /* current channel is decoupled from the list */ + pListData->listId = ICP_HSSACC_CHANNEL_LIST_DELIMITER; + pListData->nextChannelId = ICP_HSSACC_INVALID_CHAN; + /* next channel now becomes the first channel on the list */ + pNextChanListData = &(hssAccChannelData[nextChannelId]); + pNextChanListData->prevChannelId = ICP_HSSACC_INVALID_CHAN; + } + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelFirstChanDel\n"); + + return status; +} + +/* + * Function definition: HssAccChannelLastChanDel + */ +TDM_PRIVATE icp_status_t +HssAccChannelLastChanDel (unsigned hssPortId, + icp_hssacc_channel_list_t listId, + icp_hssacc_channel_list_data_t *pListData) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + unsigned prevChannelId = 0; + icp_hssacc_channel_list_data_t *pPrevChanListData = NULL; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelLastChanDel\n"); + + prevChannelId = pListData->prevChannelId; + pPrevChanListData = &(hssAccChannelData[prevChannelId]); + + + status = + HssAccChannelNextChanWriteMsgSend (prevChannelId, + 0, + IX_HSSACC_TDM_IO_UNIT_LIST_INDICATOR_TX, + ICP_HSSACC_TDM_IO_UNIT_CHAN_DEL_FLAG); + + if (ICP_STATUS_SUCCESS == status) + { + status = + HssAccChannelNextChanWriteMsgSend ( + prevChannelId, + 0, + IX_HSSACC_TDM_IO_UNIT_LIST_INDICATOR_RX, + ICP_HSSACC_TDM_IO_UNIT_CHAN_DEL_FLAG); + } + if (status == ICP_STATUS_SUCCESS) + { + pListData->listId = ICP_HSSACC_CHANNEL_LIST_DELIMITER; + pListData->prevChannelId = ICP_HSSACC_INVALID_CHAN; + + /* The Previous channel in the list now becomes the last */ + pPrevChanListData->nextChannelId = ICP_HSSACC_INVALID_CHAN; + hssAccLastChannelOnList[hssPortId][listId] = prevChannelId; + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelLastChanDel\n"); + return status; +} + +/* + * Function definition: HssAccChannelMiddleChanDel + */ +TDM_PRIVATE icp_status_t +HssAccChannelMiddleChanDel (icp_hssacc_channel_list_data_t *pListData) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + unsigned prevChannelId, nextChannelId = ICP_HSSACC_INVALID_CHAN; + icp_hssacc_channel_list_data_t *pPrevChanListData, *pNextChanListData = NULL; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelMiddleChanDel\n"); + + prevChannelId = pListData->prevChannelId; + nextChannelId = pListData->nextChannelId; + pPrevChanListData = &(hssAccChannelData[prevChannelId]); + pNextChanListData = &(hssAccChannelData[nextChannelId]); + + + + status = + HssAccChannelNextChanWriteMsgSend (prevChannelId, + nextChannelId, + IX_HSSACC_TDM_IO_UNIT_LIST_INDICATOR_TX, + ICP_HSSACC_TDM_IO_UNIT_CHAN_ADD_FLAG); + if (ICP_STATUS_SUCCESS == status) + { + status = + HssAccChannelNextChanWriteMsgSend ( + prevChannelId, + nextChannelId, + IX_HSSACC_TDM_IO_UNIT_LIST_INDICATOR_RX, + ICP_HSSACC_TDM_IO_UNIT_CHAN_ADD_FLAG); + } + + if (status == ICP_STATUS_SUCCESS) + { + pListData->listId = ICP_HSSACC_CHANNEL_LIST_DELIMITER; + pListData->nextChannelId = ICP_HSSACC_INVALID_CHAN; + pListData->prevChannelId = ICP_HSSACC_INVALID_CHAN; + + pPrevChanListData->nextChannelId = nextChannelId; + pNextChanListData->prevChannelId = prevChannelId; + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelMiddleChanDel\n"); + + return status; +} + + +unsigned +HssAccChannelListLastPortChannelGet (uint32_t portId, + icp_hssacc_channel_list_t listId) +{ + return hssAccLastChannelOnList[portId][listId]; +} + + +unsigned +HssAccChannelListPrevChannelOnListGet(uint32_t channelId) +{ + return hssAccChannelData[channelId].prevChannelId; +} diff --git a/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_common.c b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_common.c new file mode 100644 index 0000000..25dc112 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_common.c @@ -0,0 +1,464 @@ +/****************************************************************************** + * @file icp_hssacc_common.c + * + * @description Content of this file provides the implementation of + * common functionality used by all modules of the HSS Access component + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + *****************************************************************************/ + +#include "IxOsal.h" + +#include "icp.h" +#include "icp_hssacc.h" +#include "icp_hssacc_common.h" +#include "icp_hssacc_trace.h" + +/* + * The command ID offset for TDM I/O Unit messages + */ +#define HSSACC_TDM_IO_UNIT_CMD_ID_OFFSET (ICP_HSSACC_TDM_IO_UNIT_BYTE0_OFFSET) + +/* + * The mask for the command ID in TDM I/O Unit messages + */ +#define HSSACC_TDM_IO_UNIT_CMD_ID_MASK \ + (0xFF << HSSACC_TDM_IO_UNIT_CMD_ID_OFFSET) + +/* + * The length of time to sleep while waiting for the TDM I/O Unit to + * respond (in milliseconds) + */ +#define HSSACC_TDM_IO_UNIT_WAIT_SLEEP_TIMEOUT (10) + +/* + * The number of times the HssAcc component will sleep while waiting for a + * response message from the TDM I/O Unit before triggering a time-out. + */ +#define HSSACC_TDM_IO_UNIT_MAX_NUM_SLEEPS (100) + + +/***************************************************************************** + * Abstract: + * This struct is used to notify a function that the TDM I/O unit has + * replied to the message previously submitted to it. + * Typically, the function that submitted the message will poll + * respReceived. When this flag is set (in the context of this callback), + * the polling client knows that a response has been generated for the + * message it submitted. + * + * Fields: + * respMsg - A 2 element array which is used to save the message response. + * respReceived - A boolean flag used to notify the polling client of the + * TDM I/O Unit's response. + * + *****************************************************************************/ +typedef struct icp_hss_acc_tdm_io_unit_resp_msg_s +{ + IxPiuMhMessage respMsg; + volatile icp_boolean_t respReceived; +} icp_hss_acc_tdm_io_unit_resp_msg_t; + + +/***************************************************************************** + * Abstract: + * Static variable used to store the most recent message response from the + * the TDM I/O Unit. + * + *****************************************************************************/ +TDM_PRIVATE icp_hss_acc_tdm_io_unit_resp_msg_t tdmIOUnitResponseMessage; + + +/* + * Function prototypes + */ +TDM_PRIVATE +void HssAccTdmIOUnitCmdRespCallback( + IxPiuMhPiuId piuId, + IxPiuMhMessage msg); + +TDM_PRIVATE +icp_status_t +HssAccComTdmIOUnitCmdMsgWait (volatile icp_boolean_t *const flagToWaitFor); + +TDM_PRIVATE +icp_status_t +HssAccComTdmIOUnitCmdMsgSend( + IxPiuMhMessage message, + icp_boolean_t reqResp, + volatile icp_boolean_t *const flagToWaitFor, + IxPiuMhCallback respCallback, + uint8_t solicitedPiuMsgId); + + +/***************************************************************************** + * Abstract: + * Constructs a 4-byte, 1-word TDM I/O Unit message. + * + * + *****************************************************************************/ +void +HssAccComTdmIOUnitCmd4byte1wordMsgCreate (uint32_t byte0, + uint32_t byte1, + uint32_t byte2, + uint32_t byte3, + uint32_t word, + IxPiuMhMessage *pMessage) +{ + /* create the message */ + pMessage->data[0] = + (byte3 << ICP_HSSACC_TDM_IO_UNIT_BYTE3_OFFSET) | + (byte2 << ICP_HSSACC_TDM_IO_UNIT_BYTE2_OFFSET) | + (byte1 << ICP_HSSACC_TDM_IO_UNIT_BYTE1_OFFSET) | + (byte0 << ICP_HSSACC_TDM_IO_UNIT_BYTE0_OFFSET); + pMessage->data[1] = word; + ICP_HSSACC_TRACE_2 (ICP_HSSACC_DEBUG, + "HssAccComTdmIOUnitCmd4byte1wordMsgCreate " + "0x%08X 0x%08X\n", + pMessage->data[0], pMessage->data[1]); +} + + +/***************************************************************************** + * Abstract: + * Constructs an 8-byte TDM I/O Unit message. + * + * + *****************************************************************************/ +void +HssAccComTdmIOUnitCmd8byteMsgCreate (uint32_t byte0, + uint32_t byte1, + uint32_t byte2, + uint32_t byte3, + uint32_t byte4, + uint32_t byte5, + uint32_t byte6, + uint32_t byte7, + IxPiuMhMessage *pMessage) +{ + + + /* Create the TDM I/O Unit message format */ + pMessage->data[0] = + (byte3 << ICP_HSSACC_TDM_IO_UNIT_BYTE3_OFFSET) | + (byte2 << ICP_HSSACC_TDM_IO_UNIT_BYTE2_OFFSET) | + (byte1 << ICP_HSSACC_TDM_IO_UNIT_BYTE1_OFFSET) | + (byte0 << ICP_HSSACC_TDM_IO_UNIT_BYTE0_OFFSET); + + pMessage->data[1] = + (byte7 << ICP_HSSACC_TDM_IO_UNIT_BYTE3_OFFSET) | + (byte6 << ICP_HSSACC_TDM_IO_UNIT_BYTE2_OFFSET) | + (byte5 << ICP_HSSACC_TDM_IO_UNIT_BYTE1_OFFSET) | + (byte4 << ICP_HSSACC_TDM_IO_UNIT_BYTE0_OFFSET); + + ICP_HSSACC_TRACE_2(ICP_HSSACC_DEBUG, + "HssAccComTdmIOUnitCmd8byteMsgCreate 0x%08X 0x%08X\n", + pMessage->data[0], pMessage->data[1]); +} + + + + + +/***************************************************************************** + * Abstract: + * Submits a message to the TDM I/O Unit, waits for a response and verifies + * that the correct response was received, response word is + * passed back to client + * + * + *****************************************************************************/ +icp_status_t +HssAccComTdmIOUnitMsgSendAndRecv(IxPiuMhMessage message, + uint8_t response, + icp_hssacc_msg_with_resp_stats_t * stats, + uint32_t * responseWord) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + uint8_t cmdType = 0; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTdmIOUnitMsgSendAndRecv\n"); + status = + HssAccComTdmIOUnitCmdMsgSend (message, + TRUE, + &(tdmIOUnitResponseMessage.respReceived), + HssAccTdmIOUnitCmdRespCallback, + response); + if (ICP_STATUS_SUCCESS == status) + { + stats->numTdmIOUnitMessagesSent ++; + stats->numTdmIOUnitRespReceived ++; + /* Extract the command ID from the message */ + cmdType = ( (tdmIOUnitResponseMessage.respMsg.data[0] & + HSSACC_TDM_IO_UNIT_CMD_ID_MASK) >> + HSSACC_TDM_IO_UNIT_CMD_ID_OFFSET ); + + if (cmdType != response) + { + stats->numTdmIOUnitInvalidResp ++; + ICP_HSSACC_REPORT_ERROR_2("HssAccComTdmIOUnitmsgSendAndRecv - " + "TDM I/O Unit provided invalid response\n" + "Expected %u Cmd and got %u\n", + cmdType, response); + status = ICP_STATUS_FATAL; + } + } + else if (ICP_STATUS_FATAL == status) + { + stats->numTdmIOUnitMessagesSent ++; + stats->numTdmIOUnitTimeoutErrs ++; + } + + if (ICP_STATUS_SUCCESS == status) + { + if (NULL != responseWord) + { + *responseWord = + tdmIOUnitResponseMessage.respMsg.data[1]; + } + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTdmIOUnitMsgSendAndRecv\n"); + return status; +} + + +/***************************************************************************** + * Abstract: + * This callback is triggered by the TDM I/O unit in response to a message. + * + * + *****************************************************************************/ +TDM_PRIVATE +void HssAccTdmIOUnitCmdRespCallback(IxPiuMhPiuId piuId, + IxPiuMhMessage msg) +{ + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTdmIOUnitCmdRespCallback\n"); + + tdmIOUnitResponseMessage.respMsg = msg; + + ICP_HSSACC_TRACE_3 (ICP_HSSACC_DEBUG, + "HssAccTdmIOUnitCmdRespCallback 0x%08X 0x%08X " + "from TDM I/O Unit %u\n", + msg.data[0], msg.data[1], + piuId); + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTdmIOUnitCmdRespCallback\n"); + + /* This must be the last step in the callback */ + tdmIOUnitResponseMessage.respReceived = TRUE; +} + + +/***************************************************************************** + * Abstract: + * Sleeps until the specified flag is set (this occurs in + * HssAccTdmIOUnitCmdRespCallback), or times out and returns an error. + * + * + *****************************************************************************/ +TDM_PRIVATE +icp_status_t +HssAccComTdmIOUnitCmdMsgWait (volatile icp_boolean_t *const flagToWaitFor) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + uint32_t numSleepsWithNoResp = 0; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccComTdmIOUnitCmdMsgWait\n"); + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_DEBUG, + "HssAccComTdmIOUnitCmdMsgWait - " + "Waiting on the TDM I/O Unit to respond...\n"); + + /* wait until a response is received */ + while (numSleepsWithNoResp < HSSACC_TDM_IO_UNIT_MAX_NUM_SLEEPS) + { + if (TRUE == *flagToWaitFor) + { + ICP_HSSACC_TRACE_0 (ICP_HSSACC_DEBUG, + "HssAccComTdmIOUnitCmdMsgWait - " + "TDM I/O Unit responded\n"); + break; + } + numSleepsWithNoResp ++; + ixOsalSleep (HSSACC_TDM_IO_UNIT_WAIT_SLEEP_TIMEOUT); + } + + /* check for timeout */ + if (HSSACC_TDM_IO_UNIT_MAX_NUM_SLEEPS == numSleepsWithNoResp) + { + ICP_HSSACC_REPORT_ERROR("HssAccComTdmIOUnitCmdMsgWait - " + "TDM I/O Unit failed to respond in time\n"); + status = ICP_STATUS_FATAL; + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccComTdmIOUnitCmdMsgWait\n"); + + return status; +} + + +/***************************************************************************** + * Abstract: + * Submits a message to the TDM I/O Unit and waits for the specified + * response from the TDM I/O Unit (if specified). + * + * + *****************************************************************************/ +TDM_PRIVATE +icp_status_t +HssAccComTdmIOUnitCmdMsgSend( + IxPiuMhMessage message, + icp_boolean_t reqResp, + volatile icp_boolean_t *const flagToWaitFor, + IxPiuMhCallback respCallback, + uint8_t solicitedPiuMsgId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IX_STATUS mhStatus = IX_SUCCESS; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccComTdmIOUnitCmdMsgSend\n"); + + ICP_HSSACC_TRACE_2 (ICP_HSSACC_DEBUG, + "HssAccComTdmIOUnitCmdMsgSend\n", + message.data[0], message.data[1]); + + /* check if a response is required */ + if (TRUE == reqResp) + { + ICP_HSSACC_TRACE_0 (ICP_HSSACC_DEBUG, + "HssAccComTdmIOUnitCmdMsgSend - " + "Calling ixPiuMhMessageWithResponseSend\n"); + + /* Send the message to the Programmable I/O Unit + (TDM I/O Unit in this case) */ + *flagToWaitFor = FALSE; + mhStatus = ixPiuMhMessageWithResponseSend(IX_PIUMH_PIUID_PIU0, + message, + solicitedPiuMsgId, + respCallback, + IX_PIUMH_SEND_RETRIES_DEFAULT); + } + else + { + ICP_HSSACC_TRACE_0 (ICP_HSSACC_DEBUG, + "HssAccComTdmIOUnitCmdMsgSend - " + "Calling ixPiuMhMessageSend\n"); + + /* Send the message to the PiuMh */ + mhStatus = ixPiuMhMessageSend (IX_PIUMH_PIUID_PIU0, + message, + IX_PIUMH_SEND_RETRIES_DEFAULT); + } + + /* check the return from the Message Handler and block for response if + requested */ + if (IX_SUCCESS != mhStatus) + { + /* report the error */ + ICP_HSSACC_REPORT_ERROR ("HssAccComTdmIOUnitCmdMsgSend - " + "Message Handler failed to send\n"); + /* set return status */ + status = ICP_STATUS_FAIL; + } + else + { + /* wait for a response from the TDM I/O Unit if one is expected */ + if (TRUE == reqResp) + { + status = HssAccComTdmIOUnitCmdMsgWait (flagToWaitFor); + } + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccComTdmIOUnitCmdMsgSend\n"); + + return status; +} + + + + +/***************************************************************************** + * Abstract: + * Single message stat struct show + * + * + *****************************************************************************/ +void HssAccSingleMessageStatsShow (icp_hssacc_msg_with_resp_stats_t stat) +{ + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, + IX_OSAL_LOG_DEV_STDOUT, + "\n\t%u messages Sent\n\t%u messages received\n\t" + "%u invalid responses\t\n%u timeouts\n", + stat.numTdmIOUnitMessagesSent, stat.numTdmIOUnitRespReceived, + stat.numTdmIOUnitInvalidResp, stat.numTdmIOUnitTimeoutErrs, 0, 0); +} diff --git a/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_common_timeslot_allocation.c b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_common_timeslot_allocation.c new file mode 100644 index 0000000..074d372 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_common_timeslot_allocation.c @@ -0,0 +1,441 @@ +/****************************************************************************** + * + * @file icp_hssacc_common_timeslot_allocation.c + * + * @description Content of this file is the implementation of the Timeslot + * allocation and de-allocation functionality used for channel Allocation + * and deletion common accross all platforms. + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + *****************************************************************************/ +#include "IxOsal.h" + +#include "icp_hssacc.h" +#include "icp_hssacc_common.h" +#include "icp_hssacc_trace.h" +#include "icp_hssacc_timeslot_allocation.h" +#include "icp_hssacc_port_config.h" +#include "icp_hssacc_channel_config.h" + + + + +/* Base address of the TDM I/O Unit channel offset table */ +TDM_PRIVATE void * hssAccHdmaProvTableVirtAddr = NULL; + +TDM_PRIVATE void * hssAccTdmIoUnitOffsetTableVirtAddr = NULL; + +/* Tracks which channel is using which timeslot(s). */ +TDM_PRIVATE unsigned +hssAccChanTimeslotUsage[ICP_HSSACC_MAX_NUM_PORTS] +[ICP_HSSACC_MAX_TIMESLOTS_PER_PORT]; + + +void * HssAccTsAllocHdmaProvTableVirtAddrGet (void) +{ + return hssAccHdmaProvTableVirtAddr; +} + + + +void * HssAccTsAllocTdmIoUnitOffsetTableVirtAddrGet (void) +{ + return hssAccTdmIoUnitOffsetTableVirtAddr; +} + + + +/** + * Function Definition + */ +icp_status_t HssAccTsAllocInit (void) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + unsigned portId = ICP_HSSACC_MAX_NUM_PORTS; + unsigned tsIndex = 0; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTsAllocInit\n"); + + /* Mark all timeslots as unreserved */ + for (portId = 0; portId < ICP_HSSACC_MAX_NUM_PORTS; portId ++) + { + for (tsIndex = 0; + tsIndex < ICP_HSSACC_MAX_TIMESLOTS_PER_PORT; + tsIndex ++) + { + hssAccChanTimeslotUsage[portId][tsIndex] = + ICP_HSSACC_INVALID_CHAN; + } + } + + hssAccHdmaProvTableVirtAddr = + (void*)IX_OSAL_CACHE_DMA_MALLOC (ICP_HSSACC_TDM_IO_UNIT_PROV_TABLE_SZ); + if (NULL == hssAccHdmaProvTableVirtAddr) + { + ICP_HSSACC_REPORT_ERROR ("HssAccTsAllocInit - TDM I/O Unit Timeslot " + "Provision table allocation failed\n"); + status = ICP_STATUS_FAIL; + } + + + + hssAccTdmIoUnitOffsetTableVirtAddr = + (void*)IX_OSAL_CACHE_DMA_MALLOC (ICP_HSSACC_TDM_IO_UNIT_OFFSET_TABLE_SZ); + + if (NULL == hssAccTdmIoUnitOffsetTableVirtAddr) + { + ICP_HSSACC_REPORT_ERROR ("HssAccTsAllocInit - TDM I/O Unit Channel " + "Offset table allocation failed\n"); + status = ICP_STATUS_FAIL; + } + + if (ICP_STATUS_SUCCESS == status) + { + status = HssAccTsAllocPlatformInit (); + } + else + { + /* Best Effort shutdown */ + HssAccTsAllocShutdown(); + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTsAllocInit\n"); + return status; +} + + +/** + * Function Definition + */ +void HssAccTsAllocShutdown (void) +{ + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTsAllocShutdown\n"); + + if (NULL != hssAccHdmaProvTableVirtAddr) + { + IX_OSAL_CACHE_DMA_FREE(hssAccHdmaProvTableVirtAddr); + hssAccHdmaProvTableVirtAddr = NULL; + } + if (NULL != hssAccTdmIoUnitOffsetTableVirtAddr) + { + IX_OSAL_CACHE_DMA_FREE(hssAccTdmIoUnitOffsetTableVirtAddr); + hssAccTdmIoUnitOffsetTableVirtAddr = NULL; + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTsAllocShutdown\n"); +} + + + + + +/** + * Function definition: HssAccTsAllocTableSwap + */ +icp_status_t HssAccTsAllocTableSwap (unsigned hssPortId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IxPiuMhMessage message; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTsAllocTableSwap\n"); + + /* Create Message for TDM I/O Unit */ + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_PORT_PROV_TABLE_SWAP, + 0, + hssPortId, + 0, + 0, + &message); + /* Send the message */ + status = + HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_PORT_PROV_TABLE_SWAP_DONE, + HssAccTsAllocSwapStatsGet(), + NULL); + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTsAllocTableSwap\n"); + + return status; +} + + + + + +/** + * Function definition: HssAccTsAllocDelete + */ +icp_status_t +HssAccTsAllocDelete (unsigned channelId, + icp_hssacc_channel_config_t * hssChannelData) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTsAllocDelete\n"); + + + /* Update the timeslot Allocation tables */ + status = HssAccTsAllocUpdate(hssChannelData[channelId].portId, + hssChannelData); + if (status != ICP_STATUS_SUCCESS) + { + ICP_HSSACC_REPORT_ERROR ("HssAccTsAllocDelete -" + " Error updating HDMA Timeslot Tables\n"); + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTsAllocDelete\n"); + return status; +} + + +/** + * Function definition: HssAccOffsetTableWordRead + */ +icp_status_t +HssAccTsAllocOffsetTableWordRead (icp_boolean_t readShadowTable, + uint16_t tableOffset, + uint32_t *tableWord) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IxPiuMhMessage message; + uint8_t tableSwitch = 0; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTsAllocOffsetTableWordRead\n"); + + if (ICP_TRUE == readShadowTable) + { + tableSwitch = 1; + } + + /* Create Message for TDM I/O Unit */ + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_OFFS_TABLE_READ, + tableSwitch, + 0, + 0, + tableOffset, + &message); + /* Send the message */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_OFFS_TABLE_READ_RESPONSE, + HssAccTsAllocOffsetTableReadStatsGet(), + tableWord); + + + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR("HssAccTsAllocOffsetTableWordRead - " + "Failed to retrieve Table data from " + "TDM I/O Unit\n"); + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTsAllocOffsetTableWordRead\n"); + + return status; +} + + + + +/***************************************************************************** + * Abstract: + * Marks the specified timeslots as registered by the specified channel. + * + *****************************************************************************/ +void +HssAccTsRegister(unsigned channelId, + unsigned portId, + icp_hssacc_line_t lineId, + uint32_t tsMap) +{ + unsigned tsIndex = 0; + unsigned offset = 0; + + ICP_HSSACC_TRACE_3 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTsRegister " + "on port %u line %u tsMap 0x%08X\n", + portId, lineId, tsMap); + + offset = lineId * ICP_HSSACC_MAX_TIMESLOTS_PER_TDM_LINE; + + /* Reserve the timeslot(s) */ + for (tsIndex = 0; + tsIndex < ICP_HSSACC_MAX_TIMESLOTS_PER_TDM_LINE; + tsIndex ++) + { + if (tsMap & BIT_SET(tsIndex)) + { + ICP_HSSACC_TRACE_2(ICP_HSSACC_DEBUG, + "HssAccTsRegister - " + "Registering timeslot %u on port %u\n", + offset + tsIndex, portId); + hssAccChanTimeslotUsage[portId][offset + tsIndex] = channelId; + } + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTsRegister\n"); +} + +/***************************************************************************** + * Abstract: + * Frees the specified timeslots. + * + *****************************************************************************/ +void +HssAccTsUnregister(unsigned portId, + icp_hssacc_line_t lineId, + uint32_t tsMap) +{ + unsigned tsIndex = 0; + unsigned offset = lineId * + ICP_HSSACC_MAX_TIMESLOTS_PER_TDM_LINE; + + ICP_HSSACC_TRACE_3 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTsUnregister " + "on port %u line %u timeslots 0x%08X\n", + portId, + lineId, + tsMap); + + for (tsIndex = 0; + tsIndex < ICP_HSSACC_MAX_TIMESLOTS_PER_TDM_LINE; + tsIndex ++) + { + if (tsMap & BIT_SET(tsIndex)) + { + hssAccChanTimeslotUsage[portId] + [offset + tsIndex] = ICP_HSSACC_INVALID_CHAN; + } + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTsUnregister\n"); +} + +/***************************************************************************** + * Abstract: + * Checks if the requested timeslots are available for use by a channel. + * + *****************************************************************************/ +icp_boolean_t +HssAccTsAvailableVerify(unsigned portId, + icp_hssacc_line_t lineId, + uint32_t tsMap) +{ + unsigned tsIndex = 0; + unsigned offset = 0; + icp_boolean_t timeslotsAvailable = ICP_TRUE; + + ICP_HSSACC_TRACE_3 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTsAvailableVerify" + " on port %u line %u and tsMap 0x%08X\n", + portId, + lineId, + tsMap); + + /* + * There are 4 lines per HSS port and each line has 32 timeslots. Since + * timeslot usage is recorded per port, need to offset by N*32, where + * N is the HSS line number. + */ + offset = lineId * ICP_HSSACC_MAX_TIMESLOTS_PER_TDM_LINE; + + while ((ICP_TRUE == timeslotsAvailable) && + (tsIndex < ICP_HSSACC_MAX_TIMESLOTS_PER_TDM_LINE)) + { + if ( (tsMap & BIT_SET(tsIndex)) && + (ICP_HSSACC_INVALID_CHAN != + hssAccChanTimeslotUsage[portId][offset + tsIndex]) + ) + { + ICP_HSSACC_TRACE_2(ICP_HSSACC_DEBUG, + "Found a Timeslot already used on port %u, " + "TS %u\n", + portId, + offset + tsIndex); + timeslotsAvailable = ICP_FALSE; + } + tsIndex ++; + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTsAvailableVerify\n"); + + return timeslotsAvailable; +} + diff --git a/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_param_check.c b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_param_check.c new file mode 100644 index 0000000..d8cba6d --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_param_check.c @@ -0,0 +1,95 @@ +/****************************************************************************** + * + * @file icp_hssacc_param_check.c + * + * @description Content of this file is the implementation of parameter checking + * as valid for this specific platform. Other platforms may not support the same + * set of clock modes. + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + ******************************************************************************/ + +#include "icp.h" +#include "icp_hssacc.h" +#include "icp_hssacc_port_config.h" +#include "icp_hssacc_common.h" + + +icp_boolean_t +HssAccPortConfigTxClkModeInvalid(icp_hssacc_clk_mode_t clkMode) +{ + return ICP_HSSACC_ENUM_INVALID(clkMode,ICP_HSSACC_CLK_MODE_DELIMITER); +} + +icp_boolean_t +HssAccPortConfigRxClkModeInvalid(icp_hssacc_clk_mode_t clkMode) +{ + /* For Tolapai Rx, all listed modes are supported */ + return ICP_HSSACC_ENUM_INVALID(clkMode,ICP_HSSACC_CLK_MODE_DELIMITER); +} + + + diff --git a/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_port_config.c b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_port_config.c new file mode 100644 index 0000000..652c9b1 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_port_config.c @@ -0,0 +1,1175 @@ +/****************************************************************************** + * @file icp_hssacc_port_config.c + * + * @description Contents of this file provide the implementation of the + * Port Configuration functionality for the HSS Access component + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + *****************************************************************************/ + +/* ---------------------------------------------------------------------------- + * Includes + * ---------------------------------------------------------------------------- + */ +#include "IxOsal.h" + +#include "icp_hssacc.h" +#include "icp_hssacc_port_config.h" +#include "icp_hssacc_common.h" +#include "icp_hssacc_trace.h" +#include "icp_hssacc_port_hdma_reg_mgr.h" +#include "icp_hssacc_timeslot_allocation.h" +#include "icp_hssacc_address_translate.h" + +/* + * ---------------------------------------------------------------------------- + * Macros + * ---------------------------------------------------------------------------- + */ +#define ICP_HSSACC_PORT_API_CONFIG_RESET(cfg) do { \ + cfg.frmSyncType = ICP_HSSACC_FRM_PULSE_SYNC_TYPE_DELIMITER; \ + cfg.frmSyncIO = ICP_HSSACC_FRM_PULSE_SYNC_IO_TYPE_DELIMITER;\ + cfg.frmSyncClkEdge = ICP_HSSACC_CLK_EDGE_TYPE_DELIMITER;\ + cfg.dataClkEdge = ICP_HSSACC_CLK_EDGE_TYPE_DELIMITER;\ + cfg.clkMode = ICP_HSSACC_CLK_MODE_DELIMITER;\ + cfg.frmPulseUsage = ICP_HSSACC_FRM_PULSE_USAGE_TYPE_DELIMITER;\ + cfg.dataPolarity = ICP_HSSACC_DATA_POLARITY_DELIMITER;\ + cfg.drainMode = ICP_HSSACC_TX_PINS_DRAIN_MODE_TYPE_DELIMITER;\ + cfg.refFrame = ICP_HSSACC_REF_FRAME_DELIMITER;\ + cfg.dataPinsEnable = ICP_HSSACC_DATA_PINS_TYPE_DELIMITER;\ + cfg.loopback = ICP_FALSE;\ + cfg.frm_offset = 0;\ + cfg.fBitType = ICP_HSSACC_TX_FBIT_TYPE_DELIMITER; \ + cfg.fBitEnable = ICP_FALSE;\ + cfg.unassignedType = ICP_HSSACC_UNASSIGNED_DATA_DRIVE_DELIMITER; \ + cfg.interleaving = ICP_HSSACC_INTERLEAVING_TYPE_DELIMITER; \ +} while (0); + +#define ICP_HSSACC_PORT_ADD_CONFIG_RESET(addCfg) do { \ + addCfg.dataRate = ICP_HSSACC_DATA_RATE_EQUALS_CLK_RATE; \ + addCfg.frmPulseWidth = ICP_HSSACC_RX_DFLT_FRM_PULSE_WIDTH; \ +} while (0); + + + +/* + * ---------------------------------------------------------------------------- + * Struct types + * ---------------------------------------------------------------------------- + */ + + +/* Stats */ +typedef struct icp_hssacc_port_config_stats_s +{ + icp_hssacc_msg_with_resp_stats_t configTableLoad; + icp_hssacc_msg_with_resp_stats_t portEnable; + icp_hssacc_msg_with_resp_stats_t portDisable; +} icp_hssacc_port_config_stats_t; + +/* + * ---------------------------------------------------------------------------- + * Global variables + * ---------------------------------------------------------------------------- + */ + +/* Flag used to test whether the Port Config sub-component is initialised */ +TDM_PRIVATE icp_boolean_t portConfigInitialised = ICP_FALSE; + +/* Tracks the current port state and configuration */ +TDM_PRIVATE icp_hssacc_port_internal_config_t +hssAccPortConfig[ICP_HSSACC_MAX_NUM_PORTS]; + +/* Base address of the Port Config tables */ +TDM_PRIVATE void * hssAccPortConfigTablesBaseVirtAddr = NULL; + +TDM_PRIVATE icp_hssacc_port_config_stats_t hssAccPortConfigStats; + + + +/* + * ---------------------------------------------------------------------------- + * Static function declarations + * ---------------------------------------------------------------------------- + */ +TDM_PRIVATE icp_status_t +HssAccPortConfigTableUpdate(unsigned portId); + + +TDM_PRIVATE icp_status_t +HssAccPortConfigTableLoad(unsigned portId, + void * tableVirtAddr, + uint8_t msgId, + uint8_t msgRespId); + + +TDM_PRIVATE icp_status_t +HssAccPortStateSet(unsigned portId, + uint8_t msgId, + uint8_t msgRespId, + icp_hssacc_msg_with_resp_stats_t * stats); + + +/* + * ---------------------------------------------------------------------------- + * Function definitions + * ---------------------------------------------------------------------------- + */ +/****************************************************************************** + * Abstract: + * Initialises all global variables used for port configuration. + * Allocates memory for the HDMA port configuration tables. + * Initialises the port configuration mutex. + *****************************************************************************/ +icp_status_t +HssAccPortConfigInit(void) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + unsigned portId = 0; + icp_hssacc_hdma_port_config_t * pHdmaConfigTables = NULL; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccPortConfigInit\n"); + + if (ICP_TRUE == portConfigInitialised) + { + ICP_HSSACC_REPORT_ERROR ("HssAccPortConfigInit - " + "component has already been initialised\n"); + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccPortConfigInit\n"); + return ICP_STATUS_FAIL; + } + + /* Allocate memory for the port config tables */ + hssAccPortConfigTablesBaseVirtAddr = + (void*)IX_OSAL_CACHE_DMA_MALLOC (ICP_HSSACC_MAX_NUM_PORTS* + sizeof(icp_hssacc_hdma_port_config_t)); + + if (NULL == hssAccPortConfigTablesBaseVirtAddr) + { + ICP_HSSACC_REPORT_ERROR ("HssAccPortConfigInit - " + "malloc for port config tables failed\n"); + status = ICP_STATUS_FAIL; + } + else + { + pHdmaConfigTables = + (icp_hssacc_hdma_port_config_t *)hssAccPortConfigTablesBaseVirtAddr; + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Initialise the port configuration struct */ + for (portId = 0; portId < ICP_HSSACC_MAX_NUM_PORTS; portId ++) + { + hssAccPortConfig[portId].state = ICP_HSSACC_PORT_UNCONFIGURED; + hssAccPortConfig[portId].hdmaPortCfgTableVirtAddr = + &pHdmaConfigTables[portId]; + hssAccPortConfig[portId].clkSpeed = ICP_HSSACC_CLK_SPEED_DELIMITER; + + /* Rx dir config */ + ICP_HSSACC_PORT_API_CONFIG_RESET(hssAccPortConfig[portId].rx.cfg); + ICP_HSSACC_PORT_ADD_CONFIG_RESET(hssAccPortConfig[portId].rx.addCfg); + + + /* Tx dir config */ + ICP_HSSACC_PORT_API_CONFIG_RESET(hssAccPortConfig[portId].tx.cfg); + ICP_HSSACC_PORT_ADD_CONFIG_RESET(hssAccPortConfig[portId].tx.addCfg); + + } + /* Initialise the internal Stats */ + HssAccPortConfigStatsReset(); + portConfigInitialised = ICP_TRUE; + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccPortConfigInit\n"); + return status; +} + + +/****************************************************************************** + * Abstract: + * Shutdown this sub-module: free any memory ... + * + *****************************************************************************/ +icp_status_t +HssAccPortConfigShutdown(void) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + unsigned portId = 0; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccPortConfigShutdown\n"); + + if (ICP_FALSE == portConfigInitialised) + { + ICP_HSSACC_REPORT_ERROR ("HssAccPortConfigShutdown - " + "component has not been initialised\n"); + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccPortConfigShutdown\n"); + return ICP_STATUS_FAIL; + } + for (portId = 0; portId < ICP_HSSACC_MAX_NUM_PORTS; portId ++) + { + if (hssAccPortConfig[portId].state == ICP_HSSACC_PORT_ENABLED) + { + ICP_HSSACC_REPORT_ERROR_1 ("HssAccPortConfigShutdown - " + "port %d is still enabled, " + "shut it down first\n", + portId); + status = ICP_STATUS_FAIL; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Free memory allocated for the port config tables */ + IX_OSAL_CACHE_DMA_FREE(hssAccPortConfigTablesBaseVirtAddr); + hssAccPortConfigTablesBaseVirtAddr = NULL; + + for (portId = 0; portId < ICP_HSSACC_MAX_NUM_PORTS; portId ++) + { + hssAccPortConfig[portId].state = ICP_HSSACC_PORT_UNCONFIGURED; + hssAccPortConfig[portId].hdmaPortCfgTableVirtAddr = NULL; + } + + portConfigInitialised = ICP_FALSE; + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccPortConfigShutdown\n"); + return status; +} + + +/****************************************************************************** + * Abstract: + * returns the number of supported HSS ports + * + *****************************************************************************/ +unsigned +icp_HssAccNumSupportedPortsGet ( void ) +{ + return ICP_HSSACC_MAX_NUM_PORTS; +} + + + +/****************************************************************************** + * Abstract: + * saves the specified configuration for the specified port + * + *****************************************************************************/ +icp_status_t +icp_HssAccPortConfig (unsigned portId, + icp_hssacc_port_config_params_t *configParams) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + icp_boolean_t mutexLocked = ICP_FALSE; + icp_hssacc_port_config_t * pTxPortConfig = &(configParams->txPortConfig); + icp_hssacc_port_config_t * pRxPortConfig = &(configParams->rxPortConfig); + + + ICP_HSSACC_TRACE_1 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccPortConfig - port %d\n", + portId); + + /* Check if port config component has been initialised */ + if (ICP_FALSE == portConfigInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortConfig - port config component " + "has not been initialised\n"); + status = ICP_STATUS_FAIL; + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Check Port Number */ + if (portId >= ICP_HSSACC_MAX_NUM_PORTS) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortConfig - " + "port number is invalid\n"); + status = ICP_STATUS_INVALID_PARAM; + } + + + if (NULL == configParams) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortConfig - invalid " + "port settings pointer\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } + + + if (ICP_STATUS_SUCCESS == status) + { + + if (ICP_HSSACC_ENUM_INVALID(configParams->clkSpeed, + ICP_HSSACC_CLK_SPEED_DELIMITER)) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortConfig - " + "port clock speed is invalid\n"); + status = ICP_STATUS_INVALID_PARAM; + } + + /* TX Check */ + if (ICP_HSSACC_ENUM_INVALID(pTxPortConfig->frmSyncType, + ICP_HSSACC_FRM_PULSE_SYNC_TYPE_DELIMITER) || + ICP_HSSACC_ENUM_INVALID(pTxPortConfig->frmSyncIO, + ICP_HSSACC_FRM_PULSE_SYNC_IO_TYPE_DELIMITER)|| + (pTxPortConfig->frmSyncIO == + ICP_HSSACC_FRM_PULSE_SYNC_IO_TYPE_INVALID_VALUE) || + ICP_HSSACC_ENUM_INVALID(pTxPortConfig->frmSyncClkEdge, + ICP_HSSACC_CLK_EDGE_TYPE_DELIMITER) || + ICP_HSSACC_ENUM_INVALID(pTxPortConfig->dataClkEdge, + ICP_HSSACC_CLK_EDGE_TYPE_DELIMITER) || + ICP_HSSACC_ENUM_INVALID(pTxPortConfig->frmPulseUsage, + ICP_HSSACC_FRM_PULSE_USAGE_TYPE_DELIMITER) || + ICP_HSSACC_ENUM_INVALID(pTxPortConfig->dataPolarity, + ICP_HSSACC_DATA_POLARITY_DELIMITER) || + ICP_HSSACC_ENUM_INVALID(pTxPortConfig->drainMode, + ICP_HSSACC_TX_PINS_DRAIN_MODE_TYPE_DELIMITER) || + ICP_HSSACC_ENUM_INVALID(pTxPortConfig->refFrame, + ICP_HSSACC_REF_FRAME_DELIMITER) || + ICP_HSSACC_ENUM_INVALID(pTxPortConfig->dataPinsEnable, + ICP_HSSACC_DATA_PINS_TYPE_DELIMITER) || + ICP_HSSACC_ENUM_INVALID(pTxPortConfig->fBitType, + ICP_HSSACC_TX_FBIT_TYPE_DELIMITER) || + ICP_HSSACC_ENUM_INVALID(pTxPortConfig->unassignedType, + ICP_HSSACC_UNASSIGNED_DATA_DRIVE_DELIMITER) || + ICP_HSSACC_ENUM_INVALID(pTxPortConfig->interleaving, + ICP_HSSACC_INTERLEAVING_TYPE_DELIMITER) || +#ifdef IXP23xx + (ICP_TRUE == pTxPortConfig->loopback) || +#endif + HssAccPortConfigTxClkModeInvalid(pTxPortConfig->clkMode) ) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortConfig - one or more Tx port " + "config parameters is invalid\n"); + status = ICP_STATUS_INVALID_PARAM; + } + + + + /* RX Check */ + if (ICP_HSSACC_ENUM_INVALID(pRxPortConfig->frmSyncType, + ICP_HSSACC_FRM_PULSE_SYNC_TYPE_DELIMITER) || + ICP_HSSACC_ENUM_INVALID(pRxPortConfig->frmSyncIO, + ICP_HSSACC_FRM_PULSE_SYNC_IO_TYPE_DELIMITER)|| + (pRxPortConfig->frmSyncIO == + ICP_HSSACC_FRM_PULSE_SYNC_IO_TYPE_INVALID_VALUE) || + ICP_HSSACC_ENUM_INVALID(pRxPortConfig->frmSyncClkEdge, + ICP_HSSACC_CLK_EDGE_TYPE_DELIMITER) || + ICP_HSSACC_ENUM_INVALID(pRxPortConfig->dataClkEdge, + ICP_HSSACC_CLK_EDGE_TYPE_DELIMITER) || + ICP_HSSACC_ENUM_INVALID(pRxPortConfig->frmPulseUsage, + ICP_HSSACC_FRM_PULSE_USAGE_TYPE_DELIMITER) || + ICP_HSSACC_ENUM_INVALID(pRxPortConfig->dataPolarity, + ICP_HSSACC_DATA_POLARITY_DELIMITER) || + ICP_HSSACC_ENUM_INVALID(pRxPortConfig->interleaving, + ICP_HSSACC_INTERLEAVING_TYPE_DELIMITER) || + HssAccPortConfigRxClkModeInvalid(pRxPortConfig->clkMode) ) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortConfig - one or more Rx port " + "config parameters is invalid\n"); + status = ICP_STATUS_INVALID_PARAM; + } + + if ((pRxPortConfig->refFrame != + ICP_HSSACC_REF_FRAME_NOT_SELECTED) && + (pRxPortConfig->frmSyncIO == + ICP_HSSACC_FRM_PULSE_SYNC_IO_TYPE_INPUT)) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortConfig - Rx Reference Frame " + "selection is invalid for the Frame " + "pulse source setting\n"); + status = ICP_STATUS_INVALID_PARAM; + } + + if ((pTxPortConfig->refFrame != + ICP_HSSACC_REF_FRAME_NOT_SELECTED) && + (pTxPortConfig->frmSyncIO == + ICP_HSSACC_FRM_PULSE_SYNC_IO_TYPE_INPUT)) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortConfig - Tx Reference Frame " + "selection is invalid for the Frame " + "pulse source setting\n"); + status = ICP_STATUS_INVALID_PARAM; + } + + + if ((ICP_HSSACC_CLK_SPEED_1544KHZ != configParams->clkSpeed) && + (pRxPortConfig->fBitEnable || + pTxPortConfig->fBitEnable)) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortConfig - " + "FBit is only supported for T1 speed\n"); + status = ICP_STATUS_INVALID_PARAM; + } + + if ((pRxPortConfig->fBitEnable && + (ICP_HSSACC_FRM_PULSE_USAGE_DISABLED == + pRxPortConfig->frmPulseUsage)) || + (pTxPortConfig->fBitEnable && + (ICP_HSSACC_FRM_PULSE_USAGE_DISABLED == + pTxPortConfig->frmPulseUsage))) + { + ICP_HSSACC_REPORT_ERROR("icp_HssAccPortConfig - " + "fBit and Frameless operation " + "not permitted\n"); + status = ICP_STATUS_INVALID_PARAM; + } + + + if ((ICP_TRUE == pRxPortConfig->loopback) && + (ICP_TRUE == pTxPortConfig->loopback)) + { + ICP_HSSACC_REPORT_ERROR("icp_HssAccPortConfig -" + " The port cannot be configured for " + "both Remote and Internal loopback\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Lock the HssAcc mutex and update port configuration */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_LOCK()) + { + ICP_HSSACC_REPORT_ERROR("icp_HssAccPortConfig - " + "Mutex Lock Error\n"); + status = ICP_STATUS_MUTEX; + } + else + { + mutexLocked = ICP_TRUE; + } + + } + + if (ICP_STATUS_SUCCESS == status) + { + if ((0 == memcmp(&(hssAccPortConfig[portId].rx.cfg), + pRxPortConfig, + sizeof(icp_hssacc_port_config_t))) && + (0 == memcmp (&(hssAccPortConfig[portId].tx.cfg), + pTxPortConfig, + sizeof(icp_hssacc_port_config_t)))) + { + /* Supplied config is identical to what is already configured */ + ICP_HSSACC_TRACE_0 (ICP_HSSACC_DEBUG, + "icp_HssAccPortConfig - port already " + "configured with identical settings\n"); + } + else + { + + /* Check if port is in a valid state for configuration */ + if (ICP_HSSACC_PORT_UNCONFIGURED != hssAccPortConfig[portId].state) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortConfig - " + "port has already been " + "configured at some stage\n"); + status = ICP_STATUS_FAIL; + } + else + { + /* Store Port Config Parameters in static memory */ + hssAccPortConfig[portId].clkSpeed = configParams->clkSpeed; + /* Rx dir config */ + memcpy (&(hssAccPortConfig[portId].rx.cfg), + pRxPortConfig, + sizeof(icp_hssacc_port_config_t)); + + /* Tx dir config */ + memcpy (&(hssAccPortConfig[portId].tx.cfg), + pTxPortConfig, + sizeof(icp_hssacc_port_config_t)); + + hssAccPortConfig[portId].state = ICP_HSSACC_PORT_CONFIGURED; + + } + } + } + + if (ICP_TRUE == mutexLocked) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR("icp_HssAccPortConfig - " + "Mutex Unlock Error\n"); + status = ICP_STATUS_MUTEX; + } + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccPortConfig\n"); + return status; +} + + + + +/****************************************************************************** + * Abstract: + * Enable traffic on the specified TDM port + * + *****************************************************************************/ +icp_status_t +icp_HssAccPortUp (unsigned portId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + icp_boolean_t mutexLocked = ICP_FALSE; + + ICP_HSSACC_TRACE_1 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccPortUp - port %d\n", + portId); + + /* Check if port config component has been initialised */ + if (ICP_FALSE == portConfigInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortUp - port config component " + "has not been initialised\n"); + status = ICP_STATUS_FAIL; + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Check Port Number */ + if (portId >= ICP_HSSACC_MAX_NUM_PORTS) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortUp - " + "port number is invalid\n"); + + status = ICP_STATUS_INVALID_PARAM; + } + } + + + if (ICP_STATUS_SUCCESS == status) + { + /* Lock the HssAcc mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_LOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortUp - " + "failed to lock HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + else + { + mutexLocked = ICP_TRUE; + } + } + + + if (ICP_STATUS_SUCCESS == status) + { + /* Check if port is already enabled */ + if (ICP_HSSACC_PORT_ENABLED == hssAccPortConfig[portId].state) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortUp - " + "failed to unlock HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + + /* this port is already enabled so we dont need to do anything */ + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccPortUp\n"); + return status; + } + + if (ICP_HSSACC_PORT_UNCONFIGURED == hssAccPortConfig[portId].state) + { + ICP_HSSACC_REPORT_ERROR_2 ("icp_HssAccPortUp - " + "port is not in an appropriate State - " + "port %d, state %d\n", + portId, + hssAccPortConfig[portId].state); + status = ICP_STATUS_FAIL; + } + } + + + if (ICP_STATUS_SUCCESS == status) + { + status = HssAccPortConfigTableUpdate(portId); + + } + + if (ICP_STATUS_SUCCESS == status) + { + status = HssAccTsAllocInitialAllocationUpdate(portId); + } + + if (ICP_STATUS_SUCCESS == status) + { + status = HssAccPortStateSet(portId, + ICP_HSSACC_TDM_IO_UNIT_PORT_ENABLE, + ICP_HSSACC_TDM_IO_UNIT_PORT_ENABLE_RESPONSE, + &(hssAccPortConfigStats.portEnable)); + } + if (ICP_STATUS_SUCCESS == status) + { + hssAccPortConfig[portId].state = ICP_HSSACC_PORT_ENABLED; + } + + if (ICP_TRUE == mutexLocked) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortUp - " + "failed to unlock HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccPortUp\n"); + return status; + +} + + +/****************************************************************************** + * Abstract: + * Disables traffic on the specified TDM port. + * + *****************************************************************************/ +icp_status_t +icp_HssAccPortDown (unsigned portId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + + ICP_HSSACC_TRACE_1 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccPortDown - port %d\n", + portId); + + /* Check if port config component has been initialised */ + if (ICP_FALSE == portConfigInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortDown - port config component " + "has not been initialised\n"); + status = ICP_STATUS_FAIL; + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Check Port Number */ + if (portId >= ICP_HSSACC_MAX_NUM_PORTS) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortDown - " + "port number is invalid\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } + + /* Check if port is enabled */ + if (ICP_STATUS_SUCCESS == status) + { + + /* Lock the HssAcc mutex and update port loopback configuration */ + if (ICP_STATUS_SUCCESS == ICP_HSSACC_MUTEX_LOCK()) + { + if ((ICP_HSSACC_PORT_ENABLED == hssAccPortConfig[portId].state) && + (!HssAccChannelConfigUsedChansOnPortFind(portId))) + { + status = + HssAccPortStateSet(portId, + ICP_HSSACC_TDM_IO_UNIT_PORT_DISABLE, + ICP_HSSACC_TDM_IO_UNIT_PORT_DISABLE_RESPONSE, + &(hssAccPortConfigStats.portDisable)); + + if (ICP_STATUS_SUCCESS == status) + { + + hssAccPortConfig[portId].state = ICP_HSSACC_PORT_CONFIGURED; + } + else + { + ICP_HSSACC_REPORT_ERROR_1 ("icp_HssAccPortDown - " + "unable to bring down port %d\n", + portId); + } + } + else if (ICP_HSSACC_PORT_CONFIGURED != + hssAccPortConfig[portId].state) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortDown - " + "there are still allocated channels on" + " this port\n"); + status = ICP_STATUS_RESOURCE; + } + + /* Unlock the HssAcc configuration mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortDown - " + "failed to unlock HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + + } + else + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortDown - " + "failed to lock HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccPortDown\n"); + return status; + +} + + +/****************************************************************************** + * Abstract: + * Update the port configuration table in the TDM I/O Unit for this port. + * + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccPortConfigTableUpdate(unsigned portId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + icp_hssacc_hdma_port_config_t * pPortCfgTable = NULL; + + ICP_HSSACC_TRACE_2 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccPortConfigTableUpdate for " + "port %d at speed %d\n", + portId, + hssAccPortConfig[portId].clkSpeed); + /* Get the base address of the port config tables */ + pPortCfgTable = hssAccPortConfig[portId].hdmaPortCfgTableVirtAddr; + + /* Clear the contents of the HDMA port config table */ + memset (pPortCfgTable, 0, + sizeof(icp_hssacc_hdma_port_config_t)); + +#ifdef IXP23XX + /* Need to Create the LUT for IXP23XX as it is part of the + Port Config Table,creating tables with all TimeSlots assigned */ + status = HssAccHdmaMgrLUTCreate(hssAccPortConfig[portId].clkSpeed, + pPortCfgTable->tx_LUT); + if (ICP_STATUS_SUCCESS == status) + { + status = HssAccHdmaMgrLUTCreate(hssAccPortConfig[portId].clkSpeed, + pPortCfgTable->rx_LUT); + } + HssAccHdmaMgrVCRCreate(&(pPortCfgTable->tx_vcr)); + HssAccHdmaMgrVCRCreate(&(pPortCfgTable->rx_vcr)); +#endif + + if (ICP_STATUS_SUCCESS == status) + { + HssAccHdmaMgrPCRCreate (ICP_HSSACC_HDMA_TX_REG_TYPE, + &(hssAccPortConfig[portId].tx), + &(pPortCfgTable->tx_pcr)); + HssAccHdmaMgrICRCreate (ICP_HSSACC_HDMA_TX_REG_TYPE, + portId, + &(pPortCfgTable->tx_icr)); + HssAccHdmaMgrClkCRCreate (hssAccPortConfig[portId].clkSpeed, + &(pPortCfgTable->clkcr)); + + status = HssAccHdmaMgrFCRCreate (ICP_HSSACC_HDMA_TX_REG_TYPE, + hssAccPortConfig[portId].clkSpeed, + &(hssAccPortConfig[portId].tx), + &(pPortCfgTable->tx_fcr)); + } + if (ICP_STATUS_SUCCESS == status) + { + HssAccHdmaMgrPCRCreate (ICP_HSSACC_HDMA_RX_REG_TYPE, + &(hssAccPortConfig[portId].rx), + &(pPortCfgTable->rx_pcr)); + + HssAccHdmaMgrICRCreate (ICP_HSSACC_HDMA_RX_REG_TYPE, + portId, + &(pPortCfgTable->rx_icr)); + + if ((hssAccPortConfig[portId].tx.cfg.frmPulseUsage != + ICP_HSSACC_FRM_PULSE_USAGE_ENABLED) || + (hssAccPortConfig[portId].rx.cfg.frmPulseUsage != + ICP_HSSACC_FRM_PULSE_USAGE_ENABLED)) + { + HssAccHdmaMgrCWRCreate (hssAccPortConfig[portId].clkSpeed, + &(pPortCfgTable->cwr)); + } + + status = HssAccHdmaMgrFCRCreate (ICP_HSSACC_HDMA_RX_REG_TYPE, + hssAccPortConfig[portId].clkSpeed, + &(hssAccPortConfig[portId].rx), + &(pPortCfgTable->rx_fcr)); + + } + + if (ICP_STATUS_SUCCESS == status) + { + + /* Flush the new table to memory */ + IX_OSAL_CACHE_FLUSH (pPortCfgTable, + sizeof(icp_hssacc_hdma_port_config_t)); + + /* Load the new HDMA port config table for this port */ + status = + HssAccPortConfigTableLoad ( + portId, + pPortCfgTable, + ICP_HSSACC_TDM_IO_UNIT_PORT_CFG_TABLE_LOAD, + ICP_HSSACC_TDM_IO_UNIT_PORT_CFG_TABLE_LOAD_RESPONSE); + } + + if (ICP_STATUS_FATAL == status) + { + ICP_HSSACC_REPORT_ERROR ("HssAccPortConfigTableUpdate - HDMA port " + "config table update - Fatal Error " + "communicating with the TDM I/O unit\n"); + } + + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccPortConfigTableUpdate\n"); + return status; +} + +/****************************************************************************** + * Abstract: + * Send Port Configuration message to the TDM I/O Unit + * + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccPortConfigTableLoad(unsigned portId, + void * tableVirtAddr, + uint8_t msgId, + uint8_t msgRespId) +{ + uint32_t physAddr = 0; + IxPiuMhMessage message; + icp_status_t status = ICP_STATUS_SUCCESS; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccPortConfigTableLoad\n"); + + + + /* Convert the table base address to a physical address */ + physAddr = + HssAccVirtToPhysAddressTranslate(tableVirtAddr); + + if (0 == physAddr) + { + ICP_HSSACC_REPORT_ERROR("HssAccPortConfigTableLoad - Translation of " + "Virtual Address resulted in NULL value\n"); + status = ICP_STATUS_FAIL; + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Construct the message to load the table */ + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + msgId, + 0, + portId, + (sizeof(icp_hssacc_hdma_port_config_t) / ICP_HSSACC_WORD_SIZE), + physAddr, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + msgRespId, + &(hssAccPortConfigStats.configTableLoad), + NULL); + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccPortConfigTableLoad\n"); + + return status; +} + + +/****************************************************************************** + * Abstract: + * Set the state of the TDM port within the TDM I/O Unit. + * + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccPortStateSet(unsigned portId, + uint8_t msgId, + uint8_t msgRespId, + icp_hssacc_msg_with_resp_stats_t * stats) +{ + IxPiuMhMessage message; + icp_status_t status = ICP_STATUS_SUCCESS; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccPortStateSet\n"); + + /* Construct the message to load the table */ + HssAccComTdmIOUnitCmd4byte1wordMsgCreate (msgId, + 0, + portId, + 0, + 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv(message, + msgRespId, + stats, + NULL); + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccPortStateSet\n"); + + return status; +} + + + +/****************************************************************************** + * Abstract: + * check the validity of the line and last timeslot to be used using + * the known internal port configuration. + * + *****************************************************************************/ +icp_status_t +HssAccPortLineValidCheck (unsigned portId, + icp_hssacc_line_t lineId, + unsigned firstTsPos, + unsigned lastTsPos) +{ + icp_status_t status = ICP_STATUS_RESOURCE; + ICP_HSSACC_TRACE_3 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccPortLineValidCheck for " + "Port %d, line %d and TS %d\n", + portId, + lineId, + lastTsPos); + + if (ICP_HSSACC_LINE_0 != lineId) + { + if (((ICP_HSSACC_LINE_1 == lineId) || + (ICP_HSSACC_LINE_3 == lineId) || + (ICP_HSSACC_LINE_2 == lineId)) && + (ICP_HSSACC_CLK_SPEED_8192KHZ == hssAccPortConfig[portId].clkSpeed)) + { + ICP_HSSACC_TRACE_1 (ICP_HSSACC_DEBUG, + "HssAccPortLineValidCheck - " + "Line %d config Valid\n", + lineId); + status = ICP_STATUS_SUCCESS; + } + else + { + ICP_HSSACC_REPORT_ERROR ("HssAccPortLineValidCheck - Line specified " + "is not valid for current Clock speed\n"); + } + } + else + { + if ((ICP_HSSACC_CLK_SPEED_1544KHZ == + hssAccPortConfig[portId].clkSpeed) && + ((lastTsPos > ICP_HSSACC_TIMESLOTS_PER_T1_LINE) || + (firstTsPos == 0))) + { + ICP_HSSACC_REPORT_ERROR ("HssAccPortLineValidCheck - " + "Attempting to allocate Invalid " + "Timeslots for a T1 line\n"); + } + else + { + ICP_HSSACC_TRACE_0 (ICP_HSSACC_DEBUG, + "HssAccPortLineValidCheck - " + "Line 0 config Valid\n"); + status = ICP_STATUS_SUCCESS; + } + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccPortLineValidCheck\n"); + return status; +} + +/****************************************************************************** + * Abstract: + * return the current state of the specified port + * + *****************************************************************************/ +icp_hssacc_port_state_t +HssAccPortStateGet ( unsigned portId) +{ + return hssAccPortConfig[portId].state; +} + + +/****************************************************************************** + * Abstract: + * Reset the internal stats for this sub-module + * + *****************************************************************************/ +void +HssAccPortConfigStatsReset (void) +{ + memset (&hssAccPortConfigStats, 0, sizeof(icp_hssacc_port_config_stats_t)); +} + + + +/****************************************************************************** + * Abstract: + * display all the internal stats for this sub-module + * + *****************************************************************************/ +void +HssAccPortConfigStatsShow (void) +{ + unsigned portId = 0; + icp_hssacc_hdma_port_config_t * portConfig = NULL; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccPortConfigStatsShow\n"); + if (ICP_TRUE == portConfigInitialised) + { + for (portId = 0; portId < ICP_HSSACC_MAX_NUM_PORTS; portId ++) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nPort %d:\n", + portId, + 0, 0, 0, 0, 0); + + if (ICP_HSSACC_PORT_UNCONFIGURED == hssAccPortConfig[portId].state) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\tnot configured\n", + 0, 0, 0, 0, 0, 0); + } + else + { + portConfig = (hssAccPortConfig[portId].hdmaPortCfgTableVirtAddr); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nPort %d in State %d, Configuration:" + "\n\ttx_pcr 0x%08X" + "\n\trx_pcr 0x%08X" + "\n\ttx_fcr 0x%08X" + "\n\trx_fcr 0x%08X", + portId, hssAccPortConfig[portId].state, + portConfig->tx_pcr, + portConfig->rx_pcr, + portConfig->tx_fcr, + portConfig->rx_fcr); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\n\ttx_icr 0x%08X\n\trx_icr 0x%08X" + "\n\tclkcr 0x%08X\n\tcwr 0x%08X\n", + portConfig->tx_icr, + portConfig->rx_icr, + portConfig->clkcr, + portConfig->cwr, 0, 0); + + switch (hssAccPortConfig[portId].clkSpeed) + { + case ICP_HSSACC_CLK_SPEED_1544KHZ: + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\tPort Speed Configured For 1.544MHZ\n", + 0, 0, 0, 0, 0, 0); + break; + case ICP_HSSACC_CLK_SPEED_2048KHZ: + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\tPort Speed Configured For 2.048MHZ\n", + 0, 0, 0, 0, 0, 0); + break; + case ICP_HSSACC_CLK_SPEED_8192KHZ: + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\tPort Speed Configured For 8.192MHZ\n", + 0, 0, 0, 0, 0, 0); + break; + default: + break; + } + } + } + + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nPort Configuration Statistics:\n" + "Config Table Load Messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccPortConfigStats.configTableLoad); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nPort Up Messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccPortConfigStats.portEnable); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nPort Down Messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccPortConfigStats.portDisable); + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccPortConfigStatsShow\n"); + +} diff --git a/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_port_hdma_reg_mgr.c b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_port_hdma_reg_mgr.c new file mode 100644 index 0000000..66ea618 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_port_hdma_reg_mgr.c @@ -0,0 +1,546 @@ +/****************************************************************************** + * @file icp_hssacc_port_hdma_reg_mgr.c + * + * @description Contents of this file is the implementation of the HSS + * Port registers Creation from API parameters and internal settings. + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + *****************************************************************************/ + +#include "IxOsal.h" + +#include "icp_hssacc.h" +#include "icp_hssacc_port_config.h" +#include "icp_hssacc_trace.h" +#include "icp_hssacc_common.h" +#include "icp_hssacc_port_hdma_reg_mgr.h" + + +/** + * Typedefs whose scope is limited to this file. + */ + +/* Structure holding HDMA Co-p system clock divider definitions */ +typedef struct icp_hssacc_hdma_sys_clk_s +{ + uint16_t main; + uint16_t num; + uint16_t denom; +} icp_hssacc_hdma_sys_clk_t; + + + +/* HSS Co-p clock divider from the TDM I/O Unit system clk */ +TDM_PRIVATE icp_hssacc_hdma_sys_clk_t +hssAccHdmaSysClk[ICP_HSSACC_CLK_SPEED_DELIMITER] = + { + ICP_HSSACC_HDMA_SYSCLK_1544KHZ, + ICP_HSSACC_HDMA_SYSCLK_2048KHZ, + ICP_HSSACC_HDMA_SYSCLK_8192KHZ + }; + +TDM_PRIVATE uint32_t +tdmPbaAddresses[ICP_HSSACC_HDMA_REG_TYPE_DELIMITER] + [ICP_HSSACC_MAX_NUM_PORTS] = + { + { + ICP_HSSACC_TDM_IO_UNIT_HSS_HDMA_RX_PBA_0, + ICP_HSSACC_TDM_IO_UNIT_HSS_HDMA_RX_PBA_1, + ICP_HSSACC_TDM_IO_UNIT_HSS_HDMA_RX_PBA_2 +#ifdef IXP23XX +, + ICP_HSSACC_TDM_IO_UNIT_HSS_HDMA_RX_PBA_3 +#endif + }, + { + ICP_HSSACC_TDM_IO_UNIT_HSS_HDMA_TX_PBA_0, + ICP_HSSACC_TDM_IO_UNIT_HSS_HDMA_TX_PBA_1, + ICP_HSSACC_TDM_IO_UNIT_HSS_HDMA_TX_PBA_2 +#ifdef IXP23XX +, + ICP_HSSACC_TDM_IO_UNIT_HSS_HDMA_TX_PBA_3 +#endif + } + } ; + + + +/** + * Function definition: HssAccHdmaMgrPCRCreate + */ +void +HssAccHdmaMgrPCRCreate (icp_hssacc_hdma_reg_trans_t type, + const icp_hssacc_port_full_config_t *portConfig, + uint32_t *pcr) +{ + + + uint32_t offsetInReg = ICP_HSSACC_TDM_IO_UNIT_HDMA_RX_PCR_LB_OFFSET; + uint32_t clkDirection = ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_CLKDIR_OUTPUT; +#ifdef EP805XX + uint32_t clkSelect = ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_CS_INT; +#endif + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccHdmaMgrPCRCreate\n"); + + *pcr = 0; + + if (ICP_HSSACC_CLK_MODE_INPUT_EXTERNAL == portConfig->cfg.clkMode) + { + clkDirection = ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_CLKDIR_INPUT; + } +#ifdef EP805XX + /* A single API parameter maps to 2 fields of this register + map 1 to 2 here starting with default values above */ + if (ICP_HSSACC_CLK_MODE_OUTPUT_REF == portConfig->cfg.clkMode) + { + clkSelect = ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_CS_EXT_REF; + } +#endif + + + + /* create the common parts of the HSS co-p pcr register */ + /* note: portDataBitEndianness is now ICP_HSSACC_BIT_ENDIAN_MSB + at all times */ + *pcr = + (portConfig->cfg.frmSyncType << + ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_FT_OFFSET) | + (portConfig->cfg.frmSyncIO << + ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_FS_OFFSET) | + (portConfig->cfg.frmSyncClkEdge << + ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_FE_OFFSET) | + (portConfig->cfg.dataClkEdge << + ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_DE_OFFSET) | + (clkDirection << + ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_CLKDIR_OFFSET)| + (portConfig->cfg.frmPulseUsage << + ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_FR_OFFSET) | + (portConfig->addCfg.dataRate << + ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_RATE_OFFSET) | + (portConfig->cfg.dataPolarity << + ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_DP_OFFSET) | + (ICP_HSSACC_BIT_ENDIAN_MSB << + ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_BITEND_OFFSET)| +#ifdef EP805XX + (portConfig->cfg.refFrame << + ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_REFF_OFFSET) | + (clkSelect << + ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_CS_OFFSET) | +#endif + (portConfig->addCfg.frmPulseWidth - 1); + /* width varies from 1 to 8 but input value to co-proc is 0 to 7*/ + + + /* check the tx specific parameters */ + if (ICP_HSSACC_HDMA_TX_REG_TYPE == type) + { + offsetInReg = ICP_HSSACC_TDM_IO_UNIT_HDMA_TX_PCR_LB_OFFSET; + /* create the tx specific parts of the HSS co-p pcr register */ + *pcr |= + (portConfig->cfg.drainMode << + ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_OD_OFFSET) | + (portConfig->cfg.dataPinsEnable << + ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_EN_OFFSET) | + (portConfig->cfg.fBitType << + ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_FB_OFFSET) | + (0 << ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_56KTYPE_OFFSET) | + (portConfig->cfg.unassignedType << + ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_UTYPE_OFFSET) | + (0 << ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_56KEND_OFFSET ) | + (0 << ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_56KSEL_OFFSET ); + } + if (ICP_TRUE == portConfig->cfg.loopback) + { + *pcr |= (ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_LB_ON + << offsetInReg); + } + + ICP_HSSACC_TRACE_1 (ICP_HSSACC_DEBUG, + "HssAccHdmaMgrPCRCreate - " + "PCR = 0x%08X\n", *pcr); + +#ifdef SW_SWAPPING + *pcr = IX_OSAL_SWAP_BE_SHARED_LONG(*pcr); +#endif + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccHdmaMgrPCRCreate\n"); +} + +/** + * Function definition: HssAccHdmaMgrFCRCreate + */ +icp_status_t +HssAccHdmaMgrFCRCreate (icp_hssacc_hdma_reg_trans_t type, + icp_hssacc_clk_speed_t clkSpeed, + const icp_hssacc_port_full_config_t *portConfig, + uint32_t *fcr) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + uint8_t size = 0; + uint16_t offsetMaxVal = 0; + uint32_t offset = 0; + uint32_t fBitEnable = 0; + /* Used to indicate if this Hss Port is using MVIP or not */ + icp_hssacc_hdma_mvip_switch_t mvipSwitch = + ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_MVIP_SWITCH_DELIMITER; + /* Used to indicate if this Hss Port is using quad MVIP or not */ + icp_hssacc_hdma_mvip_setting_t mvipSetting = + ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_MVIP_SETTING_DELIMITER; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccHdmaMgrFCRCreate\n"); + + switch (clkSpeed) + { + case ICP_HSSACC_CLK_SPEED_1544KHZ: + size = ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_FRAME_SIZE_T1_IN_TS; + mvipSwitch = ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_MVIP_SWITCH_OFF; + offsetMaxVal = ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_FRAME_SIZE_T1_IN_BITS; + if (portConfig->cfg.frm_offset >= offsetMaxVal) + { + ICP_HSSACC_REPORT_ERROR ("HssAccHdmaMgrFCRCreate - frmOffset >=" + " T1 frame size\n"); + status = ICP_STATUS_INVALID_PARAM; + } + break; + + case ICP_HSSACC_CLK_SPEED_2048KHZ: + size = ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_FRAME_SIZE_E1_IN_TS; + mvipSwitch = ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_MVIP_SWITCH_OFF; + offsetMaxVal = ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_FRAME_SIZE_E1_IN_BITS; + if (portConfig->cfg.frm_offset >= offsetMaxVal) + { + ICP_HSSACC_REPORT_ERROR ("HssAccHdmaMgrFCRCreate - frmOffset >=" + " E1 frame size\n"); + status = ICP_STATUS_INVALID_PARAM; + } + break; + + + case ICP_HSSACC_CLK_SPEED_8192KHZ: + size = ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_FRAME_SIZE_E1_IN_TS; + mvipSwitch = ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_MVIP_SWITCH_ON; + mvipSetting = ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_MVIP_SETTING_QUAD; + offsetMaxVal = + ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_FRAME_SIZE_QUAD_MVIP_IN_BITS; + /* No need to check if (offset > offsetMaxVal), the service I/F has + done this already. */ + break; + + default: + /* clkSpeed is already error checked so this default is unreachable */ + ICP_HSSACC_REPORT_ERROR_1 ("HssAccHdmaMgrFCRCreate - Invalid clock " + "speed (%d) in clkSpeed struct\n", + clkSpeed); + status = ICP_STATUS_INVALID_PARAM; + } + + if ( ICP_STATUS_SUCCESS == status ) + { + offset = portConfig->cfg.frm_offset; + if (ICP_HSSACC_HDMA_TX_REG_TYPE == type) + { + if (ICP_HSSACC_DATA_RATE_EQUALS_CLK_RATE == + portConfig->addCfg.dataRate) + { + offset += + ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_OFFSET_TX_ADD_CLK_RATE; + } + else if (ICP_HSSACC_DATA_RATE_HALF_CLK_RATE == + portConfig->addCfg.dataRate) + { + offset += + ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_OFFSET_TX_ADD_HALF_CLK_RATE; + } + /* + It is the modulus of the frame size that the frame pulse + delineates, which is expected to fit into the offset bits + of the FCR + */ + offset %= offsetMaxVal; + + /* With FBit Enabled, offset values of 0-7 are illegal */ + if (ICP_TRUE == portConfig->cfg.fBitEnable) + { + offset += ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_OFFSET_FBIT_ADDITION; + } + } + + } + + + if (ICP_STATUS_SUCCESS == status) + { + + if (ICP_TRUE == portConfig->cfg.fBitEnable) + { + fBitEnable = 1; + } + + *fcr = 0; + /* create the HSS co-proc 32bit register format */ + *fcr = + (fBitEnable << ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_FBIT_OFFSET) | + (size << ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_FRAME_SIZE_OFFSET) | + (mvipSwitch << ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_MVIP_SWITCH_OFFSET) | + (portConfig->cfg.interleaving << + ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_INT_OFFSET) | + (offset << ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_OFFSET_OFFSET); + + if (ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_MVIP_SWITCH_ON == mvipSwitch) + { + *fcr |= mvipSetting << + ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_MVIP_SETTING_OFFSET; + } + ICP_HSSACC_TRACE_1 (ICP_HSSACC_DEBUG, + "HssAccHdmaMgrFCRCreate - " + "FCR = 0x%08X\n", *fcr); + +#ifdef SW_SWAPPING + *fcr = IX_OSAL_SWAP_BE_SHARED_LONG(*fcr); +#endif + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccHdmaMgrFCRCreate\n"); + return status; +} + + + +/** + * Function definition: HssAccHdmaMgrICRCreate + */ +void +HssAccHdmaMgrICRCreate (icp_hssacc_hdma_reg_trans_t type, + unsigned hssPortId, + uint32_t *icr) +{ + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccHdmaMgrICRCreate\n"); + + *icr = + (ICP_HSSACC_TDM_IO_UNIT_HSS_HDMA_PID_SHIFT << + ICP_HSSACC_TDM_IO_UNIT_HDMA_ICR_PID_OFFSET) | + (tdmPbaAddresses[type][hssPortId] << + ICP_HSSACC_TDM_IO_UNIT_HDMA_ICR_PBA_OFFSET); + +#ifdef IXP23XX + *icr |= + (ICP_HSSACC_TDM_IO_UNIT_HSS_PING_PONG_ENABLED << + ICP_HSSACC_TDM_IO_UNIT_HDMA_ICR_PINGPONG_OFFSET) | + (ICP_HSSACC_TDM_IO_UNIT_HSS_VCH_ENABLED << + ICP_HSSACC_TDM_IO_UNIT_HDMA_ICR_VOICE_CHANNELISATION_OFFSET); +#endif + ICP_HSSACC_TRACE_1 (ICP_HSSACC_DEBUG, + "HssAccHdmaMgrICRCreate - ICR = 0x%08X\n", + *icr); + +#ifdef SW_SWAPPING + *icr = IX_OSAL_SWAP_BE_SHARED_LONG(*icr); +#endif + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccHdmaMgrICRCreate\n"); +} + + +/** + * Function definition: HssAccHdmaMgrClkCRCreate + */ +void +HssAccHdmaMgrClkCRCreate (icp_hssacc_clk_speed_t clkSpeed, + uint32_t *clkCR) +{ + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccHdmaMgrClkCRCreate\n"); + *clkCR = + (hssAccHdmaSysClk[clkSpeed].main << + ICP_HSSACC_TDM_IO_UNIT_HDMA_CLKCR_MAIN_OFFSET) | + (hssAccHdmaSysClk[clkSpeed].num << + ICP_HSSACC_TDM_IO_UNIT_HDMA_CLKCR_NUM_OFFSET) | + (hssAccHdmaSysClk[clkSpeed].denom << + ICP_HSSACC_TDM_IO_UNIT_HDMA_CLKCR_DENOM_OFFSET); + ICP_HSSACC_TRACE_1 (ICP_HSSACC_DEBUG, + "HssAccHdmaMgrClkCRCreate - CLKCR = 0x%08X\n", + *clkCR); + +#ifdef SW_SWAPPING + *clkCR = IX_OSAL_SWAP_BE_SHARED_LONG(*clkCR); +#endif + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccHdmaMgrClkCRCreate\n"); +} + + +#ifdef IXP23XX +/** + * Function definition: HssAccHdmaMgrVCRCreate + */ +void +HssAccHdmaMgrVCRCreate (uint32_t *vcr) +{ + uint8_t voiceOffset = 0; + uint8_t lineIndex = 0; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccHdmaMgrVCRCreate\n"); + + for(lineIndex = 0; + lineIndex < ICP_HSSACC_MAX_TDM_LINES_PER_PORT; + lineIndex ++) + { + if(lineIndex != 0 ) + { + (*vcr) |= + (voiceOffset << + ((lineIndex - 1) * + ICP_HSSACC_TDM_IO_UNIT_HDMA_VCR_FRAME_BASE_OFFSET)); + } + voiceOffset += ICP_HSSACC_TDM_IO_UNIT_HSS_SUB_FRAME_DELTA_OFFSET; + + } + + ICP_HSSACC_TRACE_1 (ICP_HSSACC_DEBUG, + "HssAccHdmaMgrVCRCreate VCR = 0x%08X\n", + *vcr); + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccHdmaMgrVCRCreate\n"); +} +#endif + + +/** + * Function definition: HssAccHdmaMgrCWRCreate + */ +void +HssAccHdmaMgrCWRCreate (icp_hssacc_clk_speed_t clkSpeed, + uint32_t *cwr) +{ + uint8_t timeslotsOnLastLine = 0; + uint8_t numOfActiveLines = 0; + uint32_t cwLocation = 0; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccHdmaMgrCWRCreate\n"); + switch (clkSpeed) + { + case ICP_HSSACC_CLK_SPEED_1544KHZ: + timeslotsOnLastLine = ICP_HSSACC_TIMESLOTS_PER_T1_LINE; + numOfActiveLines = 1; + break; + case ICP_HSSACC_CLK_SPEED_2048KHZ: + timeslotsOnLastLine = ICP_HSSACC_MAX_TIMESLOTS_PER_TDM_LINE; + numOfActiveLines = 1; + break; + case ICP_HSSACC_CLK_SPEED_8192KHZ: + timeslotsOnLastLine = ICP_HSSACC_MAX_TIMESLOTS_PER_TDM_LINE; + numOfActiveLines = ICP_HSSACC_MAX_TDM_LINES_PER_PORT; + break; + default: + /* Code is not reachable under normal operation */ + ICP_HSSACC_REPORT_ERROR ("HssAccHdmaMgrCWRCreate - invalid" + " clock speed\n"); + return; + } + + + *cwr = /* first, shift in the enabling of the CW conditions */ + (ICP_HSSACC_TDM_IO_UNIT_HSS_TX_CW1_ENABLED << + ICP_HSSACC_TDM_IO_UNIT_HDMA_CWR_TX_CW1_ENABLE_OFFSET) | + (ICP_HSSACC_TDM_IO_UNIT_HSS_TX_CW2_DISABLED << + ICP_HSSACC_TDM_IO_UNIT_HDMA_CWR_TX_CW2_ENABLE_OFFSET) | + (ICP_HSSACC_TDM_IO_UNIT_HSS_RX_CW1_ENABLED << + ICP_HSSACC_TDM_IO_UNIT_HDMA_CWR_RX_CW1_ENABLE_OFFSET) | + (ICP_HSSACC_TDM_IO_UNIT_HSS_RX_CW2_DISABLED << + ICP_HSSACC_TDM_IO_UNIT_HDMA_CWR_RX_CW2_ENABLE_OFFSET) ; + + /* Calculate the location where the TDM I/O Unit is to be woken up, + it is at the last timeslot used on the last active line (timeslot + location start from 0) */ + cwLocation = (timeslotsOnLastLine - 1) + + ((numOfActiveLines - 1) * ICP_HSSACC_MAX_TIMESLOTS_PER_TDM_LINE); + /* Now shift in the addresses of the CW offsets */ + *cwr |= + (cwLocation << + ICP_HSSACC_TDM_IO_UNIT_HDMA_CWR_TX_CW1_ADDRESS_OFFSET) | + (cwLocation << + ICP_HSSACC_TDM_IO_UNIT_HDMA_CWR_RX_CW1_ADDRESS_OFFSET); + + ICP_HSSACC_TRACE_1 (ICP_HSSACC_DEBUG, + "HssAccHdmaMgrCWRCreate CWR = 0x%08X\n", + *cwr); + +#ifdef SW_SWAPPING + *cwr = IX_OSAL_SWAP_BE_SHARED_LONG(*cwr); +#endif + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccHdmaMgrCWRCreate\n"); +} diff --git a/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_queues_config.c b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_queues_config.c new file mode 100644 index 0000000..93766d5 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_queues_config.c @@ -0,0 +1,1501 @@ +/****************************************************************************** + * @file icp_hssacc_queues_config.c + * + * @description Contents of this file provide the implementation of the + * Tx and Rx Queues Configuration functionality + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + *****************************************************************************/ +#include "IxOsal.h" + +#include "IxQMgr.h" +#include "icp_hssacc.h" +#include "icp_hssacc_common.h" +#include "icp_hssacc_trace.h" +#include "icp_hssacc_rx_datapath.h" +#include "icp_hssacc_queues_config.h" +#include "icp_hssacc_address_translate.h" + +/* + * ---------------------------------------------------------------------------- + * Macros + * ---------------------------------------------------------------------------- + */ + +/* + * Macros that are used to distinguish between the voice and HDLC callback + * routines. The same macros are used for both the Rx queues and the Rx free + * queues. + */ +#define ICP_HSSACC_VOICE_RX_QMGR_CB_ID (0) +#define ICP_HSSACC_HDLC_RX_QMGR_CB_ID (1) + + + +#define ICP_HSSACC_CACHE_MASK (IX_OSAL_CACHE_LINE_SIZE-1) + +#define ICP_HSSACC_Q_NAME_SIZE 16 +#define ICP_HSSACC_Q_TYPE_NAME_SIZE 12 + + + +/* Defines Virtual and Physical values for the same memory block */ +typedef struct icp_hssacc_mem_base_addr_s +{ + void * virt; + uint32_t physOffset; +} icp_hssacc_mem_base_addr_t; + +/* + * ---------------------------------------------------------------------------- + * Static variable declarations + * ---------------------------------------------------------------------------- + */ +/* Flag used to test whether the queues have been initialised or not. */ +TDM_PRIVATE icp_boolean_t queuesConfigured = FALSE; + + +/* + * Holds the address of the memory allocated for the queue counters. + */ +TDM_PRIVATE icp_hssacc_mem_base_addr_t readCountersBaseAddress = + { + NULL, 0 + }; + +TDM_PRIVATE icp_hssacc_mem_base_addr_t writeCountersBaseAddress = + { + NULL, 0 + }; + +/* + * the virtual Addresses of each block that will have its physical + * address sent to the TDM I/O Unit + */ +/* Block containing the Tx Queues for ALL channels */ +TDM_PRIVATE icp_hssacc_mem_base_addr_t +txQsAddrArray[ICP_HSSACC_MAX_NUM_CHANNELS]; + +/* Block with Rx and RxFree for HDLC */ +TDM_PRIVATE icp_hssacc_mem_base_addr_t rxHdlcQsBlockAddr = + { + NULL, 0 + }; +/* Block with Rx and RxFree for VOICE */ +TDM_PRIVATE icp_hssacc_mem_base_addr_t rxVoiceQsBlockAddr = + { + NULL, 0 + }; + +/* Stores the list of Queue IDs as provided by the QMgr + this will be used to access the queues later. + we have 1 queue for each channel on Tx and 2 queues on Rx per + service supported */ +TDM_PRIVATE IxQMgrQId +hssAccQueueIds[ICP_HSSACC_MAX_NUM_CHANNELS + ICP_HSSACC_NUM_RECEIVE_QS]; + + +TDM_PRIVATE icp_hssacc_queues_config_stats_t hssAccQueuesCfgStats; + +/* + * ---------------------------------------------------------------------------- + * Static function declarations + * ---------------------------------------------------------------------------- + */ +TDM_PRIVATE void +HssAccQueueMemoryAlloc(icp_hssacc_mem_base_addr_t * txQsMemBaseArray, + icp_hssacc_mem_base_addr_t * pRxHdlcQsMemBase, + icp_hssacc_mem_base_addr_t * pRxVoiceQsMemBase, + icp_hssacc_mem_base_addr_t * pReadCounterMemBase, + icp_hssacc_mem_base_addr_t * pWriteCounterMemBase); + +TDM_PRIVATE icp_status_t +HssAccQueuesConfig(void); + +TDM_PRIVATE icp_status_t +HssAccQueueConfigMsgSubmit(uint32_t qBasePhysOffset, + uint32_t qDepth, + uint8_t msgId, + uint8_t msgRespId, + icp_hssacc_msg_with_resp_stats_t * stat); + +TDM_PRIVATE icp_status_t +HssAccTxQueuesConfigMsgsSubmit(icp_hssacc_mem_base_addr_t * qTxQBaseAddresses, + icp_hssacc_msg_with_resp_stats_t * stat); + +TDM_PRIVATE icp_status_t +HssAccQueueCounterConfigMsgSubmit(uint32_t qCounterPhysOffset, + uint8_t msgId, + uint8_t msgRespId, + icp_hssacc_msg_with_resp_stats_t * stat); + +TDM_PRIVATE icp_status_t +HssAccTdmIOUnitQueuesConfig(void); + +TDM_PRIVATE icp_status_t +HssAccTdmIOUnitQueueCountersConfig(void); + + +/* + * ---------------------------------------------------------------------------- + * Public function definitions + * ---------------------------------------------------------------------------- + */ +/****************************************************************************** + * Abstract: + * Allocates memory for all of the queues shared between the access layer + * and the TDM I/O unit. Also allocates memory for the head and tail + * counters for each queue. + * Verifies that the memory allocated is aligned on a cache line boundary. + * Registers each queue with QMgr and configures the queue watermark, etc. + * Submits the queue details to the TDM I/O unit. + * + * + *****************************************************************************/ +icp_status_t +HssAccQueuesInit(void) +{ + unsigned channel = 0; + icp_status_t status = ICP_STATUS_SUCCESS; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccQueuesInit\n"); + + if (TRUE == queuesConfigured) + { + ICP_HSSACC_REPORT_ERROR ("HssAccQueuesInit - Queues already " + "configured\n"); + return ICP_STATUS_SUCCESS; + } + + /* Allocate a block of memory for the queues and the head & tail counters */ + HssAccQueueMemoryAlloc (txQsAddrArray, + &rxHdlcQsBlockAddr, + &rxVoiceQsBlockAddr, + &readCountersBaseAddress, + &writeCountersBaseAddress); + + /* Check if the memory was correctly allocated */ + for (channel = 0; channel < ICP_HSSACC_MAX_NUM_CHANNELS; channel++) + { + if (NULL == txQsAddrArray[channel].virt) + { + ICP_HSSACC_REPORT_ERROR_1 ("HssAccQueuesInit - " + "Failed to allocate Tx queue memory" + " for channel %d\n", + channel); + status = ICP_STATUS_FAIL; + break; + } + } + + if ((NULL == rxHdlcQsBlockAddr.virt) || + (NULL == rxVoiceQsBlockAddr.virt)) + { + ICP_HSSACC_REPORT_ERROR ("HssAccQueuesInit - " + "Failed to allocate Rx queues memory\n"); + + status = ICP_STATUS_FAIL; + } + + if ((NULL == readCountersBaseAddress.virt) || + (NULL == writeCountersBaseAddress.virt)) + { + ICP_HSSACC_REPORT_ERROR ("HssAccQueuesInit - " + "Failed to allocate queue counter memory\n"); + + status = ICP_STATUS_FAIL; + } + + if (status == ICP_STATUS_SUCCESS) + { + /* Allocated memory must start on a cache boundary */ + for (channel = 0; + channel < ICP_HSSACC_MAX_NUM_CHANNELS; + channel ++) + { + if ((((uint32_t)txQsAddrArray[channel].virt & + ICP_HSSACC_CACHE_MASK) != 0)) + { + ICP_HSSACC_REPORT_ERROR_1 ("HssAccQueuesInit - " + "Allocated Tx queue memory" + " for channel %d is NOT on" + " a cache line boundary\n", + channel); + ICP_HSSACC_TRACE_1 (ICP_HSSACC_DEBUG, + "\tTx queue " + "base memory 0x%08X\n\t", + (uint32_t)txQsAddrArray[channel].virt); + + status = ICP_STATUS_RESOURCE; + break; + } + } + + if ((((uint32_t)rxHdlcQsBlockAddr.virt & ICP_HSSACC_CACHE_MASK) != 0) || + (((uint32_t)rxVoiceQsBlockAddr.virt & ICP_HSSACC_CACHE_MASK) != 0) || + (((uint32_t)readCountersBaseAddress.virt & + ICP_HSSACC_CACHE_MASK) != 0) || + (((uint32_t)writeCountersBaseAddress.virt & + ICP_HSSACC_CACHE_MASK) != 0) ) + { + ICP_HSSACC_REPORT_ERROR ("HssAccQueuesInit - Allocated Memory " + "must start on a cache line boundary\n"); + + ICP_HSSACC_TRACE_2 (ICP_HSSACC_DEBUG, + "\tqueue " + "read counter memory 0x%x\n\t" + "write counter memory 0x%x\n\t", + (uint32_t)readCountersBaseAddress.virt, + (uint32_t)writeCountersBaseAddress.virt); + ICP_HSSACC_TRACE_2 (ICP_HSSACC_DEBUG, + "\tRx Hdlc queue memory 0x%x and Rx " + "Voice queue memory 0x%x\n\t ", + (uint32_t)rxHdlcQsBlockAddr.virt, + (uint32_t)rxVoiceQsBlockAddr.virt); + + status = ICP_STATUS_RESOURCE; + } + } + + if (status == ICP_STATUS_SUCCESS) + { + /* + * Carve up the memory between the queues and submit the queue + * configuration (for each queue) to the QMgr. + */ + status = HssAccQueuesConfig (); + + } + if (ICP_STATUS_SUCCESS == status) + { + /* + * Now that the Qmgr queues have been initialised, inform the + * TDM I/O Unit of the base address and size of each of the queues. + */ + status = HssAccTdmIOUnitQueuesConfig (); + } + if (ICP_STATUS_SUCCESS == status) + { + /* + * Now that the Qmgr queues have been initialised, and the queue base + * addresses submitted to the TDM I/O unit, submit the base address + * of each of the counters to TDM I/O unit. + */ + status = HssAccTdmIOUnitQueueCountersConfig (); + } + + /* This statement verifies that all queue initialisation steps succeeded */ + if (ICP_STATUS_SUCCESS == status) + { + /* all queues initialised and configured */ + queuesConfigured = TRUE; + } + else + { + ICP_HSSACC_REPORT_ERROR( "HssAccQueuesInit - Cleanup\n"); + HssAccQueuesShutdown(); + } + + /* Reset the Stats */ + HssAccQueuesConfigStatsReset(); + + ICP_HSSACC_TRACE_0( ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccQueuesInit\n" ); + + return status; +} + + +/***************************************************************************** + * Abstract: + * Frees the memory allocated for the queues and the queue counters, and + * resets the queue configuration flag. + * + * + *****************************************************************************/ +icp_status_t +HssAccQueuesShutdown(void) +{ + unsigned channel = 0; + icp_status_t status = ICP_STATUS_SUCCESS; + + ICP_HSSACC_TRACE_0(ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccQueuesShutdown\n" ); + + + /* Best Effort cleanup, we dont care about success or failure + at this stage. we still try to cleanup everything. */ + status = ixQMgrUnconfigGroup(IX_QMGR_DISPATCH_TX_HSS); + + status |= ixQMgrUnconfigGroup(IX_QMGR_DISPATCH_VOICE_RX_HSS); + + status |= ixQMgrUnconfigGroup(IX_QMGR_DISPATCH_HDLC_RX_HSS); + + /* Only Free the memory that was allocated */ + for (channel = 0; channel < ICP_HSSACC_MAX_NUM_CHANNELS; channel++) + { + if (NULL != txQsAddrArray[channel].virt) + { + /* Free the memory allocated for the queues */ + IX_OSAL_CACHE_DMA_FREE(txQsAddrArray[channel].virt); + txQsAddrArray[channel].virt = NULL; + + ICP_HSSACC_TRACE_1(ICP_HSSACC_DEBUG, + "HssAccQueuesShutdown - Free memory" + " for Tx Channel %d\n", + channel); + + } + } + + if (NULL != rxHdlcQsBlockAddr.virt) + { + IX_OSAL_CACHE_DMA_FREE (rxHdlcQsBlockAddr.virt); + rxHdlcQsBlockAddr.virt = NULL; + ICP_HSSACC_TRACE_0(ICP_HSSACC_DEBUG, + "HssAccQueuesShutdown - Free Rx Hdlc memory\n"); + + } + + if (NULL != rxVoiceQsBlockAddr.virt) + { + IX_OSAL_CACHE_DMA_FREE (rxVoiceQsBlockAddr.virt); + rxVoiceQsBlockAddr.virt = NULL; + ICP_HSSACC_TRACE_0(ICP_HSSACC_DEBUG, + "HssAccQueuesShutdown - Free Rx Voice memory\n"); + + } + + if (NULL != readCountersBaseAddress.virt) + { + /* Free the memory allocated for the queue counters */ + IX_OSAL_CACHE_DMA_FREE (readCountersBaseAddress.virt); + readCountersBaseAddress.virt = NULL; + ICP_HSSACC_TRACE_0(ICP_HSSACC_DEBUG, + "HssAccQueuesShutdown - Free Read Counter memory\n"); + + } + + + if (NULL != writeCountersBaseAddress.virt) + { + /* Free the memory allocated for the queue counters */ + IX_OSAL_CACHE_DMA_FREE (writeCountersBaseAddress.virt); + writeCountersBaseAddress.virt = NULL; + ICP_HSSACC_TRACE_0( ICP_HSSACC_DEBUG, + "HssAccQueuesShutdown - Free Write Counter memory\n"); + + } + + /* Reset the queue configuration flag */ + queuesConfigured = FALSE; + + + ICP_HSSACC_TRACE_0( ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccQueuesShutdown\n" ); + return status; +} + +/***************************************************************************** + * Abstract: + * Allocates memory for all of the queues shared between the access layer + * and the TDM I/O unit. Also allocates memory for the head and tail + * counters for each queue. + * The memory is allocated on a cache line boundary, and each queue is an + * integer multiple of the cache line size. This guarantees that each queue + * is cache-aligned. + * The counter memory is also allocated on a cache boundary, and each set + * of counters is cache-aligned. + * + *****************************************************************************/ +TDM_PRIVATE void +HssAccQueueMemoryAlloc(icp_hssacc_mem_base_addr_t * txQsMemBaseArray, + icp_hssacc_mem_base_addr_t * pRxHdlcQsMemBase, + icp_hssacc_mem_base_addr_t * pRxVoiceQsMemBase, + icp_hssacc_mem_base_addr_t * pReadCounterMemBase, + icp_hssacc_mem_base_addr_t * pWriteCounterMemBase) +{ + /* + * Malloc enough memory for the following queues: + * Voice RX free Q + * Voice RX Q + * HDLC RX free Q + * HDLC RX Q + * Max Num Chan TX Qs (1 per channel) + * And the Following Counters: + * Max Num Chan Tx Tail 8 bit ctrs (1 per chan) + * Max Num Chan Tx Head 8 bit ctrs (1 per chan) + * Voice Rx Free Head and Tail (32 bits each) + * HDLC Rx Free Head and Tail (32 bits each) + * Voice Rx Head and Tail (32 bits each) + * HDLC Rx Head and Tail (32 bits each) + */ + + + /* + * Note 1: the rx free Q and the rx Q must be contiguous in memory. + * Note 2: the rx free Q and the rx Q must have the same depth. + * Note 3: a TX queue for an HDLC channel may be deeper than a TX queue for + * a Voice channel. Thus, the default TX queue depth will be that of an + * HDLC channel. The watermark will be moved accordingly to accomodate + * both depths. + * Each queue should be aligned on a cache line boundary, and should be a + * multiple of the cache line size. + */ + + uint32_t bytesToAlloc = 0; + unsigned channel = 0; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccQueueMemoryAlloc\n"); + + + /* Calculate the total amount of memory needed for each Tx queue */ + bytesToAlloc = ICP_HSSACC_TX_QUEUE_SIZE_IN_BYTES; + + for (channel = 0; channel < ICP_HSSACC_MAX_NUM_CHANNELS; channel++) + { + /* All queues must use memory that is aligned on a cache line boundary */ + txQsMemBaseArray[channel].virt = + HssAccDmaMemAllocate(bytesToAlloc, + &(txQsMemBaseArray[channel].physOffset)); + ICP_HSSACC_TRACE_4 (ICP_HSSACC_DEBUG, + "HssAccQueueMemoryAlloc - Allocated Tx Queue Mem from " + "0x%08X (phys 0x%08X) with Size %d bytes" + " for chan %d\n", + (uint32_t)(txQsMemBaseArray[channel].virt), + txQsMemBaseArray[channel].physOffset, + bytesToAlloc, + channel); + } + + /* Calculate the total amount of memory needed for Rx Hdlc queues */ + bytesToAlloc = ICP_HSSACC_HDLC_RX_QUEUE_SIZE_IN_BYTES + + ICP_HSSACC_HDLC_RX_FREE_QUEUE_SIZE_IN_BYTES; + + /* All queues must use memory that is aligned on a cache line boundary */ + pRxHdlcQsMemBase->virt = + HssAccDmaMemAllocate(bytesToAlloc, + &(pRxHdlcQsMemBase->physOffset)); + ICP_HSSACC_TRACE_3 (ICP_HSSACC_DEBUG, + "HssAccQueueMemoryAlloc - Allocated Rx Hdlc Queue Mem " + "from 0x%08X (phys 0x%08X) with Size %d bytes\n", + (uint32_t)pRxHdlcQsMemBase->virt, + pRxHdlcQsMemBase->physOffset, + bytesToAlloc); + + + /* Calculate the total amount of memory needed for the Rx Voice queues */ + bytesToAlloc = ICP_HSSACC_VOICE_RX_QUEUE_SIZE_IN_BYTES + + ICP_HSSACC_VOICE_RX_FREE_QUEUE_SIZE_IN_BYTES; + + /* All queues must use memory that is aligned on a cache line boundary */ + pRxVoiceQsMemBase->virt = + HssAccDmaMemAllocate(bytesToAlloc, + &(pRxVoiceQsMemBase->physOffset)); + ICP_HSSACC_TRACE_3 (ICP_HSSACC_DEBUG, + "HssAccQueueMemoryAlloc - Allocated Rx Voice Queue Mem " + "from 0x%08X (phys 0x%08X) with Size %d bytes\n", + (uint32_t)pRxVoiceQsMemBase->virt, + pRxVoiceQsMemBase->physOffset, + bytesToAlloc); + + /* + * Allocate memory in DRAM for the queue head & tail counters. + * The read (from the access layer perspective) counters need to be arranged + * as follows: + * "max num chans" bytes (packed) for the Tx tail counters. These + * "max num chans" bytes must be contiguous in memory. + * 4-byte Voice Rx free tail and 4-byte Rx head counters, which must be + * contiguous in memory and aligned on a cache line boundary. + * 4-byte HDLC Rx free tail and 4-byte Rx head counters, which must + * be contiguous in memory and aligned on a cache line boundary. + * + * The write counters need to be arranged as follows: + * "max num chans" bytes (packed) for the Tx head counters. + * 4-byte Voice Rx free head and 4-byte Rx tail counters, which must be + * contiguous in memory and aligned on a cache line boundary. + * 4-byte HDLC Rx free head and 4-byte Rx tail counters, which must + * be contiguous in memory and aligned on a cache line boundary. + * + */ + bytesToAlloc = sizeof(icp_hssacc_queue_reader_counters_t); + + pReadCounterMemBase->virt = + HssAccDmaMemAllocate(bytesToAlloc, + &(pReadCounterMemBase->physOffset)); + ICP_HSSACC_TRACE_3 (ICP_HSSACC_DEBUG, + "HssAccQueueMemoryAlloc - Allocated Read Counter Memory " + "from 0x%08X (phys 0x%08X) with Size %d bytes\n", + (uint32_t)pReadCounterMemBase->virt, + pReadCounterMemBase->physOffset, + bytesToAlloc); + + bytesToAlloc = sizeof(icp_hssacc_queue_write_counters_t); + + pWriteCounterMemBase->virt = + HssAccDmaMemAllocate(bytesToAlloc, + &(pWriteCounterMemBase->physOffset)); + ICP_HSSACC_TRACE_3 (ICP_HSSACC_DEBUG, + "HssAccQueueMemoryAlloc - Allocated Write Counter Memory " + "from 0x%08X (phys 0x%08X) with Size %d bytes\n", + (uint32_t)pWriteCounterMemBase->virt, + pWriteCounterMemBase->physOffset, + bytesToAlloc); + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccQueueMemoryAlloc\n"); + return; +} + + +/***************************************************************************** + * Abstract: + * Divides the queue memory between each of the queues and does likewise + * with the queue counter memory. + * Registers each queue with the QMgr and configures each queue. + * Configures the address of the counters to flush and invalidate for each + * iteration of the dispatcher loop. The counters read by the access layer + * will be invalidated and the counters written by the access layer will be + * flushed. + * + * + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccQueuesConfig(void) +{ + uint32_t channel, qBaseOffset = 0; + IxQMgrQId qId = 0; + icp_status_t status = ICP_STATUS_SUCCESS; + icp_hssacc_queue_write_counters_t *pWriteCounters = NULL; + icp_hssacc_queue_reader_counters_t *pReadCounters = NULL; + uint8_t *pTxQueueHead = NULL; + uint8_t *pTxQueueTail = NULL; + uint32_t *pRxQueueHead = NULL; + uint32_t *pRxQueueTail = NULL; + uint32_t invalidateAddress = 0; + uint32_t flushAddress = 0; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccQueuesConfig\n "); + + /* Cast the counter structure to the memory allocated for the counters */ + pWriteCounters = + (icp_hssacc_queue_write_counters_t *)writeCountersBaseAddress.virt; + pReadCounters = + (icp_hssacc_queue_reader_counters_t *)readCountersBaseAddress.virt; + + invalidateAddress = (uint32_t)(pReadCounters->txTail); + flushAddress = (uint32_t)(pWriteCounters->txHead); + + /* + * This function sets the address of the counters to be + * flushed/invalidated each time the QMgrDispatcher runs. + * The QMgr dispatcher will only check the queues that have been + * registered with it. In this case only the Rx queues will be serviced + * by the dispatcher. + */ + + /* configure the address and size to be flushed/invalidated */ + if (ixQMgrGroupMemoryConfig (IX_QMGR_DISPATCH_TX_HSS, + (void *)flushAddress, + (void *)invalidateAddress, + sizeof(pReadCounters->txTail)) + != ICP_STATUS_SUCCESS) + { + ICP_HSSACC_REPORT_ERROR("HssAccQueuesConfig - Failed Tx Queue group " + "configuration\n"); + return ICP_STATUS_FAIL; + } + + invalidateAddress = (uint32_t)&(pReadCounters->voiceRxCounters); + flushAddress = (uint32_t)&(pWriteCounters->voiceRxCounters); + + /* configure the address and size to be flushed/invalidated for + voice receive q's */ + if (ixQMgrGroupMemoryConfig (IX_QMGR_DISPATCH_VOICE_RX_HSS, + (void *)flushAddress, + (void *)invalidateAddress, + sizeof(pReadCounters->voiceRxCounters)) + != ICP_STATUS_SUCCESS) + { + ICP_HSSACC_REPORT_ERROR("HssAccQueuesConfig - Failed Voice Rx " + "Queue group configuration\n"); + return ICP_STATUS_FAIL; + } + + /* + * Increment addresses by size of receive queue counter block + */ + invalidateAddress = (uint32_t)&(pReadCounters->hdlcRxCounters); + flushAddress = (uint32_t)&(pWriteCounters->hdlcRxCounters); + + /* configure the address and size to be flushed/invalidated for HDLC + receive q's */ + if (ixQMgrGroupMemoryConfig (IX_QMGR_DISPATCH_HDLC_RX_HSS, + (void *)flushAddress, + (void *)invalidateAddress, + sizeof(pReadCounters->hdlcRxCounters)) + != ICP_STATUS_SUCCESS) + { + ICP_HSSACC_REPORT_ERROR("HssAccQueuesConfig - Failed HDLC Rx Queue group " + "configuration\n"); + return ICP_STATUS_FAIL; + } + + + /* + * The queues are allocated in memory in the following blocks: + * 1: "max num chans" Tx queues + * 2:Voice Rx Free queue + * Voice Rx queue + * 3:HDLC Rx Free queue + * HDLC Rx queue + * 4:Read Counters + * 5: Write Counters + */ + + /* + * Configure the Tx queues + */ + for (channel = 0; + channel < ICP_HSSACC_MAX_NUM_CHANNELS; + channel ++) + { + + char qName[ICP_HSSACC_Q_NAME_SIZE] = "HssAcc Tx Q "; + + /* Append the queue number to its string identifier */ + snprintf (&qName[ICP_HSSACC_Q_TYPE_NAME_SIZE], + ICP_HSSACC_Q_NAME_SIZE - ICP_HSSACC_Q_TYPE_NAME_SIZE, + "%u", channel); + + /* Set the address of the head and tail counters for this queue */ + pTxQueueHead = &(pWriteCounters->txHead[channel]); + pTxQueueTail = &(pReadCounters->txTail[channel]); + + status = + ixQMgrQConfig (qName, + &qId, + ICP_HSSACC_TX_QUEUE_DEPTH, + ICP_HSSACC_QUEUE_DESC_SIZE_IN_WORDS, + IX_QMGR_Q_COUNT_ENTRIES, + IX_QMGR_Q_ALIGN_BYTE, + IX_QMGR_DISPATCH_TX_HSS, + IX_QMGR_Q_SHADOW_TAIL_ONLY, + txQsAddrArray[channel].virt, + pTxQueueHead, + pTxQueueTail); + + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_2 ("HssAccQueuesConfig - Failed to configure " + "Tx Q %u. ixQMgrQConfig() returned %u\n", + channel, status); + return ICP_STATUS_FAIL; + } + + hssAccQueueIds[channel] = qId; + status = ixQMgrWatermarkSet (qId, ICP_HSSACC_TX_WATERMARK); + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_2 ("HssAccQueuesConfig - Failed to set " + "watermark for Tx Q " + "%u. ixQMgrWatermarkSet() returned %u\n", + channel, status); + + return ICP_STATUS_FAIL; + } + } + /* + * The TDM I/O Unit expects the voice Rx & Rx free queues to be contiguous + * in memory, with the Rx free queue preceeding the Rx queue. However, the + * voice Rx queue should be serviced before the voice Rx free queue. + * The order in which a queue is registered with the dispatcher determines + * the order in which it will be serviced by the QMgr dispatcher. + * hence all Receive Queues are first allocated then registered. registration + * is done at a later stage. + */ + + /* + * Voice Rx free queue + */ + + pRxQueueHead = &(pWriteCounters->voiceRxCounters.rxFreeHead); + pRxQueueTail = &(pReadCounters->voiceRxCounters.rxFreeTail); + + status = ixQMgrQConfig ("Voice Rx Free Q", + &qId, + ICP_HSSACC_VOICE_RX_FREE_QUEUE_DEPTH, + ICP_HSSACC_QUEUE_DESC_SIZE_IN_WORDS, + IX_QMGR_Q_COUNT_ENTRIES, + IX_QMGR_Q_ALIGN_WORD, + IX_QMGR_DISPATCH_VOICE_RX_HSS, + IX_QMGR_Q_NO_SHADOWING, + (void*)rxVoiceQsBlockAddr.virt, + pRxQueueHead, + pRxQueueTail); + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1 ("HssAccQueuesConfig - Failed to configure " + "voice Rx free queue." + " ixQMgrQConfig() returned %u\n", status); + return ICP_STATUS_FAIL; + } + hssAccQueueIds[ICP_HSSACC_VOICE_RX_FREE_Q] = qId; + + /* + * Voice Rx queue + */ + qBaseOffset = ICP_HSSACC_VOICE_RX_FREE_QUEUE_SIZE_IN_BYTES; + + pRxQueueHead = &(pReadCounters->voiceRxCounters.rxHead); + pRxQueueTail = &(pWriteCounters->voiceRxCounters.rxTail); + + status = + ixQMgrQConfig ("Voice Rx Q", + &qId, + ICP_HSSACC_VOICE_RX_QUEUE_DEPTH, + ICP_HSSACC_RX_QUEUE_ENTRY_SIZE_IN_WORDS, + IX_QMGR_Q_COUNT_ENTRIES, + IX_QMGR_Q_ALIGN_WORD, + IX_QMGR_DISPATCH_VOICE_RX_HSS, + IX_QMGR_Q_NO_SHADOWING, + (void*)(qBaseOffset + (uint32_t)rxVoiceQsBlockAddr.virt), + pRxQueueHead, + pRxQueueTail); + + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1 ("HssAccQueuesConfig - Failed to configure " + "voice Rx queue." + " ixQMgrQConfig() returned %u\n", + status); + return ICP_STATUS_FAIL; + } + + hssAccQueueIds[ICP_HSSACC_VOICE_RX_Q] = qId; + status = ixQMgrWatermarkSet (qId, ICP_HSSACC_VOICE_RX_WATERMARK); + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1 ("HssAccQueuesConfig - Failed to set watermark " + "for voice Rx queue." + " ixQMgrWatermarkSet() returned %u\n", + status); + return ICP_STATUS_FAIL; + } + + /* Register the callback for this Q */ + status = ixQMgrNotificationCallbackSet (qId, + HssAccRxQServiceCallback, + ICP_HSSACC_VOICE_RX_QMGR_CB_ID); + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1 ("HssAccQueuesConfig - Failed to set " + "Notification callback function for voice " + "Rx Q. ixQMgrWatermarkSet() returned %u\n", + status); + return ICP_STATUS_FAIL; + } + + /* + * HDLC Rx free queue + */ + + pRxQueueHead = &(pWriteCounters->hdlcRxCounters.rxFreeHead); + pRxQueueTail = &(pReadCounters->hdlcRxCounters.rxFreeTail); + + status = ixQMgrQConfig ("HDLC Rx Free Q", + &qId, + ICP_HSSACC_HDLC_RX_FREE_QUEUE_DEPTH, + ICP_HSSACC_QUEUE_DESC_SIZE_IN_WORDS, + IX_QMGR_Q_COUNT_ENTRIES, + IX_QMGR_Q_ALIGN_WORD, + IX_QMGR_DISPATCH_HDLC_RX_HSS, + IX_QMGR_Q_NO_SHADOWING, + (void*)rxHdlcQsBlockAddr.virt, + pRxQueueHead, + pRxQueueTail); + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1 ("HssAccQueuesConfig - Failed to configure " + "HDLC Rx free queue." + " ixQMgrQConfig() returned %u\n", status); + return ICP_STATUS_FAIL; + } + + hssAccQueueIds[ICP_HSSACC_HDLC_RX_FREE_Q] = qId; + + + /* + * HDLC Rx queue + */ + qBaseOffset = ICP_HSSACC_HDLC_RX_FREE_QUEUE_SIZE_IN_BYTES; + + pRxQueueHead = &(pReadCounters->hdlcRxCounters.rxHead); + pRxQueueTail = &(pWriteCounters->hdlcRxCounters.rxTail); + + status = + ixQMgrQConfig ("HDLC Rx Q", + &qId, + ICP_HSSACC_HDLC_RX_QUEUE_DEPTH, + ICP_HSSACC_RX_QUEUE_ENTRY_SIZE_IN_WORDS, + IX_QMGR_Q_COUNT_ENTRIES, + IX_QMGR_Q_ALIGN_WORD, + IX_QMGR_DISPATCH_HDLC_RX_HSS, + IX_QMGR_Q_NO_SHADOWING, + (void*)(qBaseOffset + (uint32_t)rxHdlcQsBlockAddr.virt), + pRxQueueHead, + pRxQueueTail); + + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1 ("HssAccQueuesConfig - Failed to configure " + "HDLC Rx queue." + " ixQMgrQConfig() returned %u\n", + status); + return ICP_STATUS_FAIL; + } + + hssAccQueueIds[ICP_HSSACC_HDLC_RX_Q] = qId; + status = ixQMgrWatermarkSet (qId, ICP_HSSACC_HDLC_RX_WATERMARK); + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1 ("HssAccQueuesConfig - Failed to set watermark " + "for HDLC Rx queue." + " ixQMgrWatermarkSet() returned %u\n", + status); + return ICP_STATUS_FAIL; + } + + + /* Register the callback for this Q */ + status = ixQMgrNotificationCallbackSet (qId, + HssAccRxQServiceCallback, + ICP_HSSACC_HDLC_RX_QMGR_CB_ID); + + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1 ("HssAccQueuesConfig - Failed to set " + "Notification callback function for HDLC " + "Rx Q. ixQMgrWatermarkSet() returned %u\n", + status); + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccQueuesConfig\n"); + + return status; +} + + + +/****************************************************************************** + * Abstract: + * Enables Notification on the Receive Queues. order of is critical here + * as it will determine the order of servicing in the Queue Manager Dispatcher. + * + *****************************************************************************/ +icp_status_t +HssAccRxQueuesNotificationEnable(void) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccRxQueuesNotificationEnable\n"); + + status = ixQMgrNotificationEnable (hssAccQueueIds[ICP_HSSACC_VOICE_RX_Q], + IX_QMGR_Q_SOURCE_ID_NOT_E); + if (ICP_STATUS_SUCCESS == status) + { + status = ixQMgrNotificationEnable (hssAccQueueIds[ICP_HSSACC_HDLC_RX_Q], + IX_QMGR_Q_SOURCE_ID_NOT_E); + } + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR("HssAccRxQueuesNotificationEnable - " + "Failed to enable notifications\n"); + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccRxQueuesNotificationEnable\n"); + return status; +} + + + +/****************************************************************************** + * Abstract: + * Configures all the receive queues used by the TDM I/O unit, + * i.e. it converts the virtual base address of the queue into a + * physical address and passes this address down to the TDM I/O unit. + * It also configures the depth of the queue. + * + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccQueueConfigMsgSubmit(uint32_t qBasePhysOffset, + uint32_t qDepth, + uint8_t msgId, + uint8_t msgRespId, + icp_hssacc_msg_with_resp_stats_t * stat) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IxPiuMhMessage message; + uint8_t qSizeByte1, qSizeByte0 = 0; + + ICP_HSSACC_TRACE_4 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccQueueConfigMsgSubmit - Offset=0x%08X " + "qDepth=0x%04X msg=0x%02X msgResp=0x%02X\n", + (uint32_t)qBasePhysOffset, qDepth, msgId, msgRespId); + + qSizeByte1 = (qDepth&ICP_HSSACC_TDM_IO_UNIT_BYTE2_MASK) >> + ICP_HSSACC_TDM_IO_UNIT_BYTE2_OFFSET; + + qSizeByte0 = qDepth&ICP_HSSACC_TDM_IO_UNIT_BYTE3_MASK; + + /* Construct the message to configure the queue */ + HssAccComTdmIOUnitCmd4byte1wordMsgCreate (msgId, + 0, + qSizeByte1, + qSizeByte0, + qBasePhysOffset, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv(message, + msgRespId, + stat, + NULL); + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccQueueConfigMsgSubmit\n"); + + return status; +} + + +/****************************************************************************** + * Abstract: + * Configures all the base addresses for the Tx Queues. + * + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccTxQueuesConfigMsgsSubmit(icp_hssacc_mem_base_addr_t * pTxQBaseAddresses, + icp_hssacc_msg_with_resp_stats_t * stat) +{ + + unsigned channel = 0; + icp_status_t status = ICP_STATUS_SUCCESS; + IxPiuMhMessage message; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTxQueuesConfigMsgsSubmit\n"); + + for (channel = 0; channel < ICP_HSSACC_MAX_NUM_CHANNELS; channel++) + { + ICP_HSSACC_TRACE_2 (ICP_HSSACC_DEBUG, + "HssAccTxQueuesConfigMsgsSubmit - configuring " + "channel %d with Offset=0x%08X\n", + channel, + pTxQBaseAddresses[channel].physOffset); + + /* Construct the message to configure the queue */ + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_TX_CHAN_Q_ADDR_CFG, + channel, + 0, + 0, + pTxQBaseAddresses[channel].physOffset, + &message); + + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = + HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_TX_CHAN_Q_ADDR_CFG_RESPONSE, + stat, + NULL); + + if (ICP_STATUS_SUCCESS != status) + { + /* Error will reported in calling function */ + ICP_HSSACC_TRACE_1 (ICP_HSSACC_DEBUG, + "HssAccTxQueuesConfigMsgsSubmit - Failed " + "configuring channel %d\n", + channel); + break; + } + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTxQueuesConfigMsgsSubmit\n"); + + return status; + +} + + +/****************************************************************************** + * Abstract: + * Converts the virtual address of the queue counter into a physical + * address and submits this address to the TDM I/O unit. + * + * + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccQueueCounterConfigMsgSubmit(uint32_t qCounterPhysOffset, + uint8_t msgId, + uint8_t msgRespId, + icp_hssacc_msg_with_resp_stats_t * stat) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IxPiuMhMessage message; + + ICP_HSSACC_TRACE_2 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccQueueCounterConfigMsgSubmit - " + "msg 0x%02X offset 0x%08X\n", + msgId, qCounterPhysOffset); + + + /* Construct the message to configure the queue */ + HssAccComTdmIOUnitCmd4byte1wordMsgCreate (msgId, + 0, + 0, + 0, + qCounterPhysOffset, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv(message, + msgRespId, + stat, + NULL); + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccQueueCounterConfigMsgSubmit\n"); + + return status; +} + +/***************************************************************************** + * Abstract: + * Configures all of the queues used by the TDM I/O unit, i.e. it + * passes the phys address down to the TDM I/O unit. It also configures the + * depth of each queue. + * + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccTdmIOUnitQueuesConfig (void) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + uint32_t qDepth = 0; + + ICP_HSSACC_TRACE_0(ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTdmIOUnitQueuesConfig\n"); + + /* + * Configure the address and depth of all of the queues shared between + * the HssAcc I/O library and the TDM I/O unit. + */ + + /* configure Tx queues */ + qDepth = ((ICP_HSSACC_HDLC_TX_QUEUE_DEPTH_POW_2) << + ICP_HSSACC_TDM_IO_UNIT_BYTE2_OFFSET) + | (ICP_HSSACC_VOICE_TX_QUEUE_DEPTH_POW_2); + + status = + HssAccQueueConfigMsgSubmit (0, + qDepth, + ICP_HSSACC_TDM_IO_UNIT_TX_Q_CFG, + ICP_HSSACC_TDM_IO_UNIT_TX_Q_CFG_RESPONSE, + &(hssAccQueuesCfgStats.txQCfg)); + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1("Failed to submit Tx queue Depths " + "status = %u\n", + status); + } + + if (ICP_STATUS_SUCCESS == status) + { + status = + HssAccTxQueuesConfigMsgsSubmit(txQsAddrArray, + &(hssAccQueuesCfgStats.txChanQAddrCfg)); + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1("Failed to submit Tx queue Base " + "Addresses status = %u\n", + status); + } + } + + + if (ICP_STATUS_SUCCESS == status) + { + /* Configure the base address of the Voice Rx free & Rx queues */ + status = + HssAccQueueConfigMsgSubmit( + rxVoiceQsBlockAddr.physOffset, + ICP_HSSACC_VOICE_RX_QUEUE_DEPTH, + ICP_HSSACC_TDM_IO_UNIT_VOICE_RX_Q_CFG, + ICP_HSSACC_TDM_IO_UNIT_VOICE_RX_Q_CFG_RESPONSE, + &(hssAccQueuesCfgStats.voiceRxQCfg)); + + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1("Failed to submit voice Rx queue base " + "address. status = %u\n", status); + } + } + + /* Configure the base address of the HDLC Rx free & Rx queues */ + if (ICP_STATUS_SUCCESS == status) + { + status = + HssAccQueueConfigMsgSubmit( + rxHdlcQsBlockAddr.physOffset, + ICP_HSSACC_HDLC_RX_QUEUE_DEPTH, + ICP_HSSACC_TDM_IO_UNIT_HDLC_RX_Q_CFG, + ICP_HSSACC_TDM_IO_UNIT_HDLC_RX_Q_CFG_RESPONSE, + &(hssAccQueuesCfgStats.hdlcRxQCfg)); + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1("Failed to submit HDLC Rx queue base " + "address. status = %u\n", status); + } + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTdmIOUnitQueuesConfig\n"); + return status; +} + + +/***************************************************************************** + * Abstract: + * Submits the base address of each of the queue counters to the TDM I/O + * unit. + * + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccTdmIOUnitQueueCountersConfig (void) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + icp_hssacc_queue_write_counters_t *pWriteCounters = NULL; + icp_hssacc_queue_reader_counters_t *pReadCounters = NULL; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTdmIOUnitQueueCountersConfig\n"); + + /* + * Map the counter struct to the address of the memory allocated for the + * counters. + */ + pWriteCounters = + (icp_hssacc_queue_write_counters_t *)writeCountersBaseAddress.physOffset; + pReadCounters = + (icp_hssacc_queue_reader_counters_t *)readCountersBaseAddress.physOffset; + + /* Configure the address of the TX head counters */ + status = + HssAccQueueCounterConfigMsgSubmit ( + (uint32_t)&(pReadCounters->txTail), + ICP_HSSACC_TDM_IO_UNIT_TX_Q_TAIL_CTR_CFG, + ICP_HSSACC_TDM_IO_UNIT_TX_Q_TAIL_CTR_CFG_RESPONSE, + &(hssAccQueuesCfgStats.txQTailCfg)); + + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1("Failed to submit Tx Tail counter base " + "address. status = %u\n", status); + } + else + { + + /* Configure the address of the TX tail counters */ + status = + HssAccQueueCounterConfigMsgSubmit ( + (uint32_t)&(pWriteCounters->txHead), + ICP_HSSACC_TDM_IO_UNIT_TX_Q_HEAD_CTR_CFG, + ICP_HSSACC_TDM_IO_UNIT_TX_Q_HEAD_CTR_CFG_RESPONSE, + &(hssAccQueuesCfgStats.txQHeadCfg)); + + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1("Failed to submit Tx Head counter base " + "address. status = %u\n", status); + } + } + + if (ICP_STATUS_SUCCESS == status) + { + /* + * Configure the address of the Voice Rx Free head counter and the voice + * Rx tail counter. + */ + status = + HssAccQueueCounterConfigMsgSubmit ( + (uint32_t)&(pWriteCounters->voiceRxCounters), + ICP_HSSACC_TDM_IO_UNIT_VOICE_RX_Q_READER_CFG, + ICP_HSSACC_TDM_IO_UNIT_VOICE_RX_Q_READER_CFG_RESPONSE, + &(hssAccQueuesCfgStats.voiceRxQReaderCfg)); + + + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1("Failed to submit HssAcc Voice Rx Write " + "counters base address. status = %u\n", + status); + } + } + + if (ICP_STATUS_SUCCESS == status) + { + /* + * Configure the address of the Voice Rx Free tail counter and the voice + * Rx head counter. + */ + status = + HssAccQueueCounterConfigMsgSubmit ( + (uint32_t)&(pReadCounters->voiceRxCounters), + ICP_HSSACC_TDM_IO_UNIT_VOICE_RX_Q_WRITER_CFG, + ICP_HSSACC_TDM_IO_UNIT_VOICE_RX_Q_WRITER_CFG_RESPONSE, + &(hssAccQueuesCfgStats.voiceRxQWriterCfg)); + + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1("Failed to submit HssAcc Voice Rx read " + "counters base address. status = %u\n", + status); + } + } + + if (ICP_STATUS_SUCCESS == status) + { + /* + * Configure the address of the HDLC Rx Free head counter and the HDLC + * Rx tail counter. + */ + status = + HssAccQueueCounterConfigMsgSubmit ( + (uint32_t)&(pWriteCounters->hdlcRxCounters), + ICP_HSSACC_TDM_IO_UNIT_HDLC_RX_Q_READER_CFG, + ICP_HSSACC_TDM_IO_UNIT_HDLC_RX_Q_READER_CFG_RESPONSE, + &(hssAccQueuesCfgStats.hdlcRxQReaderCfg)); + + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1("Failed to submit HssAcc HDLC Rx write " + "counters base address. status = %u\n", + status); + } + } + + if (ICP_STATUS_SUCCESS == status) + { + /* + * Configure the address of the HDLC Rx Free tail counter and the HDLC + * Rx head counter. + */ + status = + HssAccQueueCounterConfigMsgSubmit ( + (uint32_t)&(pReadCounters->hdlcRxCounters), + ICP_HSSACC_TDM_IO_UNIT_HDLC_RX_Q_WRITER_CFG, + ICP_HSSACC_TDM_IO_UNIT_HDLC_RX_Q_WRITER_CFG_RESPONSE, + &(hssAccQueuesCfgStats.hdlcRxQWriterCfg)); + + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1("Failed to submit HssAcc HDLC Rx read " + "counters base address. status = %u\n", + status); + } + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTdmIOUnitQueueCountersConfig\n"); + + return status; +} + +/***************************************************************************** + * Abstract: + * Updates the TDM I/O Unit with a new Q depth for a specific Q. + * + *****************************************************************************/ +icp_status_t +HssAccQueueConfigQSizeUpdate(uint32_t channelId, + icp_hssacc_channel_type_t type) +{ + IxQMgrQSize depth = 0; + + if (ICP_HSSACC_CHAN_TYPE_VOICE == type) + { + depth = ICP_HSSACC_VOICE_TX_QUEUE_DEPTH; + } + else + { + depth = ICP_HSSACC_HDLC_TX_QUEUE_DEPTH; + } + return ixQMgrQSizeReconfig (channelId, depth); +} + + +/***************************************************************************** + * Abstract: + * Retrieves the QMgr Q Id for a specific HSS Acc Queue. + * + *****************************************************************************/ +IxQMgrQId +HssAccQueueIdGet (uint32_t qIndexId) +{ + return hssAccQueueIds[qIndexId]; +} + + +/***************************************************************************** + * Abstract: + * Reset the Stats for this module. + * + *****************************************************************************/ +void +HssAccQueuesConfigStatsReset (void) +{ + memset (&hssAccQueuesCfgStats, 0, sizeof(icp_hssacc_queues_config_stats_t)); +} + + + +/***************************************************************************** + * Abstract: + * Displays stats for this module. + * + *****************************************************************************/ +void +HssAccQueuesConfigStatsShow (void) +{ + unsigned channel = 0; + if (TRUE == queuesConfigured) + { + for (channel = 0; channel < ICP_HSSACC_MAX_NUM_CHANNELS; channel++) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Tx Queue %d Base Address Location: 0x%08X\n", + channel, + (uint32_t)txQsAddrArray[channel].virt, + 0, 0, + 0, 0); + } + + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Rx Hdlc Queues Base Address Location: 0x%08X\n" + "Rx Voice Queues Base Address Location: 0x%08X\n" + "Queue Read Counter Address Location: 0x%08X\n" + "Queue Write Counter Address Location: 0x%08X\n", + (uint32_t)rxHdlcQsBlockAddr.virt, + (uint32_t)rxVoiceQsBlockAddr.virt, + (uint32_t)readCountersBaseAddress.virt, + (uint32_t)writeCountersBaseAddress.virt, + 0, 0); + + + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nQueue Configuration Statistics:\n" + "TX Queue Config messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccQueuesCfgStats.txQCfg); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nHDLC RX Queue Config messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccQueuesCfgStats.hdlcRxQCfg); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nVoice RX Queue Config messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccQueuesCfgStats.voiceRxQCfg); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nTX Q Head Counters Config messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccQueuesCfgStats.txQHeadCfg); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nTX Q Tail Counters Config messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccQueuesCfgStats.txQTailCfg); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nVoice Rx Q Reader Config messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccQueuesCfgStats.voiceRxQReaderCfg); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nVoice Rx Q Writer Config messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccQueuesCfgStats.voiceRxQWriterCfg); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nHDLC Rx Q Reader Config messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccQueuesCfgStats.hdlcRxQReaderCfg); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nHDLC Rx Q Writer Config messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccQueuesCfgStats.hdlcRxQWriterCfg); + } + +} diff --git a/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_rx_datapath.c b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_rx_datapath.c new file mode 100644 index 0000000..94bba23 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_rx_datapath.c @@ -0,0 +1,2014 @@ +/****************************************************************************** + * @file icp_hssacc_rx_datapath.c + * + * @description Contents of this file provide the Receive Datapath + * functionality for the HSS Access component + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + *****************************************************************************/ + +#include "IxOsal.h" + +#include "icp.h" +#include "icp_hssacc.h" +#include "icp_hssacc_common.h" +#include "icp_hssacc_queues_config.h" +#include "icp_hssacc_channel_config.h" +#include "icp_hssacc_rings.h" +#include "icp_hssacc_tdm_io_queue_entry.h" +#include "icp_hssacc_address_translate.h" +#include "icp_hssacc_trace.h" +#include "icp_hssacc_rx_datapath.h" + +#include "IxQMgr.h" + + +/* Mutex which controls access to receive datapath service functions */ +TDM_PRIVATE IxOsalMutex hssAccRxServiceMutex[ICP_HSSACC_CHAN_TYPE_DELIMITER]; +TDM_PRIVATE +IxOsalMutex hssAccRxFreeQServiceMutex[ICP_HSSACC_CHAN_TYPE_DELIMITER]; + +/* Data for the descriptor to mbuf mapping queue */ +TDM_PRIVATE uint32_t +HssAccRxDpDescPtrRingData[ICP_HSSACC_MAX_NUM_CHANNELS] +[ICP_HSSACC_RX_DP_CHAN_DESC_PTR_RING_SZ]; + +TDM_PRIVATE icp_hssacc_dataplane_ring_t +HssAccRxDpDescRing[ICP_HSSACC_MAX_NUM_CHANNELS]; + +/* Data for the descriptor to mbuf mapping queue */ +TDM_PRIVATE uint32_t +HssAccRxDpFreeQRingData[ICP_HSSACC_CHAN_TYPE_DELIMITER] +[ICP_HSSACC_HDLC_RX_FREE_QUEUE_DEPTH]; + +TDM_PRIVATE icp_hssacc_dataplane_ring_t +HssAccRxDpFreeQRing[ICP_HSSACC_CHAN_TYPE_DELIMITER]; + +TDM_PRIVATE icp_hssacc_rx_callback_t +HssAccRxChannelCallbacks[ICP_HSSACC_MAX_NUM_CHANNELS]; + +TDM_PRIVATE icp_user_context_t +HssAccRxChannelCallbackUserContexts[ICP_HSSACC_MAX_NUM_CHANNELS]; + +TDM_PRIVATE uint32_t +maxRxDatapathFrameSize[ICP_HSSACC_CHAN_TYPE_DELIMITER]; + +TDM_PRIVATE icp_boolean_t +hssAccRxServiceInitialised = ICP_FALSE; + +TDM_PRIVATE uint32_t +hssAccRxDatapathNumPendPkts[ICP_HSSACC_MAX_NUM_CHANNELS]; + +TDM_PRIVATE icp_boolean_t +hssAccRxDatapathLastReceiveSuccess[ICP_HSSACC_MAX_NUM_CHANNELS]; + +TDM_PRIVATE icp_boolean_t +hssAccRxDatapathWatermarkLevelReached[ICP_HSSACC_MAX_NUM_CHANNELS]; + +TDM_PRIVATE int32_t +hssAccRxDatapathNumUserBuffersInRxSystem[ICP_HSSACC_CHAN_TYPE_DELIMITER]; + +/* Stats */ +#ifndef NDEBUG +TDM_PRIVATE uint32_t hssAccRxNumPktsAged[ICP_HSSACC_MAX_NUM_CHANNELS]; +TDM_PRIVATE uint32_t hssAccRxNumPktsReceived[ICP_HSSACC_MAX_NUM_CHANNELS]; +TDM_PRIVATE uint32_t +hssAccRxNumPktsReplenished[ICP_HSSACC_CHAN_TYPE_DELIMITER]; +TDM_PRIVATE uint32_t hssAccRxNumReceiveFailures[ICP_HSSACC_MAX_NUM_CHANNELS]; +TDM_PRIVATE uint32_t +hssAccRxNumReplenishFailures[ICP_HSSACC_CHAN_TYPE_DELIMITER]; +#endif + + + +/* + * Initialises the service mutex. + */ +#define ICP_HSSACC_RX_DP_SERVICE_MUTEX_INIT(service) \ + (ixOsalMutexInit(&(hssAccRxServiceMutex[service]))) + +/* + * Locks the service mutex. + */ +#define ICP_HSSACC_RX_DP_SERVICE_MUTEX_LOCK(service) \ + (ixOsalMutexLock(&(hssAccRxServiceMutex[service]),ICP_HSSACC_MUTEX_TIMEOUT)) + +/* + * Unlocks the service mutex. + */ +#define ICP_HSSACC_RX_DP_SERVICE_MUTEX_UNLOCK(service) \ + (ixOsalMutexUnlock(&(hssAccRxServiceMutex[service]))) + +/* + * Destroys the service mutex. + */ +#define ICP_HSSACC_RX_DP_SERVICE_MUTEX_DESTROY(service) \ + (ixOsalMutexDestroy(&(hssAccRxServiceMutex[service]))) + +/* + * Initialises the rx free q service mutex. + */ +#define ICP_HSSACC_RX_FREEQ_DP_SERVICE_MUTEX_INIT(service) \ + (ixOsalMutexInit(&(hssAccRxFreeQServiceMutex[service]))) + +/* + * Locks the rx free q service mutex. + */ +#define ICP_HSSACC_RX_FREEQ_DP_SERVICE_MUTEX_LOCK(service) \ + (ixOsalMutexLock(&(hssAccRxFreeQServiceMutex[service]), \ + ICP_HSSACC_MUTEX_TIMEOUT)) + +/* + * Unlocks the rx free q service mutex. + */ +#define ICP_HSSACC_RX_FREEQ_DP_SERVICE_MUTEX_UNLOCK(service) \ + (ixOsalMutexUnlock(&(hssAccRxFreeQServiceMutex[service]))) + +/* + * Destroys the rx free q service mutex. + */ +#define ICP_HSSACC_RX_FREEQ_DP_SERVICE_MUTEX_DESTROY(service) \ + (ixOsalMutexDestroy(&(hssAccRxFreeQServiceMutex[service]))) + + + + +/****************************************************************************** + * Abstract: + * Return type of channel (voice or HDLC) + * + ******************************************************************************/ +TDM_PRIVATE icp_hssacc_channel_type_t +HssAccChanTypeGet (IxQMgrQId qId) +{ + icp_hssacc_channel_type_t chanType = ICP_HSSACC_CHAN_TYPE_DELIMITER; + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChanTypeGet\n"); + + if (qId == HssAccQueueIdGet(ICP_HSSACC_HDLC_RX_Q)) + { + chanType = ICP_HSSACC_CHAN_TYPE_HDLC; + } + else if (qId == HssAccQueueIdGet(ICP_HSSACC_VOICE_RX_Q)) + { + chanType = ICP_HSSACC_CHAN_TYPE_VOICE; + } + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChanTypeGet\n"); + return chanType; +} + +/****************************************************************************** + * Abstract: + * Add hssAcc-supplied buffer to Rx Free Q for use by TDM I/O Unit + * + ******************************************************************************/ +icp_status_t +icp_HssAccRxFreeChecklessReplenish( + icp_hssacc_channel_type_t channelType, + icp_hssacc_osal_mbuf_tdm_io_section_t *pMBufTdmIo + ) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + icp_hssacc_tdm_io_queue_entry_t qEntry; + icp_hssacc_tdm_io_queue_entry_t *pEntry = &qEntry; + IxQMgrQEntryType entry = 0; + IxQMgrQId qId = 0; + IX_OSAL_MBUF *pBuffer = NULL; + uint32_t buffer_len = 0; + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccRxFreeChecklessReplenish\n"); + pBuffer = + (IX_OSAL_MBUF*) ICP_OSAL_MBUF_TDM_SECT_OSAL_MBUF_START(pMBufTdmIo); + + buffer_len = IX_OSAL_MBUF_MLEN(pBuffer); + + /* Set qId based on whether buffer is Voice or HDLC */ + if (channelType == ICP_HSSACC_CHAN_TYPE_HDLC) + { + qId = HssAccQueueIdGet(ICP_HSSACC_HDLC_RX_FREE_Q); + } + else if (channelType == ICP_HSSACC_CHAN_TYPE_VOICE) + { + qId = HssAccQueueIdGet(ICP_HSSACC_VOICE_RX_FREE_Q); + } + else + { + status = ICP_STATUS_INVALID_PARAM; + return status; + } + + /* Fill out Rx Free Q Entry */ + ICP_TDM_IO_Q_ENTRY_CHANNEL_ID(pEntry) = 0; + ICP_TDM_IO_Q_ENTRY_STATUS(pEntry) = 0; + + ICP_TDM_IO_Q_ENTRY_CURR_BUF_LEN_MSB(pEntry) = + ICP_OSAL_MBUF_PKT_LEN_MSB((uint16_t) buffer_len); + + ICP_TDM_IO_Q_ENTRY_CURR_BUF_LEN_LSB(pEntry) = + ICP_OSAL_MBUF_PKT_LEN_LSB((uint16_t) buffer_len); + + ICP_TDM_IO_Q_ENTRY_DATA(pEntry) = + (void *) HssAccVirtToPhysAddressTranslateAndSwap( + (void *) ICP_OSAL_MBUF_TDM_SECT_DATA(pMBufTdmIo)); + + ICP_TDM_IO_Q_ENTRY_PKT_LEN(pEntry) = 0; + + ICP_TDM_IO_Q_ENTRY_OSAL_MBUF(pEntry) = + (IX_OSAL_MBUF *) HssAccVirtToPhysAddressTranslateAndSwap( + (void *) pMBufTdmIo); + + /* Acquire service mutex */ + if (ICP_HSSACC_RX_FREEQ_DP_SERVICE_MUTEX_LOCK(channelType) == IX_SUCCESS) + { + /* Add entry to Rx Free Q */ + status = ixQMgrQWrite(qId, (IxQMgrQEntryType *) pEntry); + /* Check for overflow (only possible error returned by a Q write) */ + if (status == ICP_STATUS_OVERFLOW) + { + ICP_HSSACC_REPORT_ERROR_1("icp_HssAccRxFreeChecklessReplenish - " + "Q overflow writing to Rx Free Q\n", + 0); + } + else + { + if ICP_HSSACC_DATAPLANE_RING_FULL( + HssAccRxDpFreeQRing[channelType]) + { + /* If the internal ring is full, remove the oldest + entry before adding another one */ + ICP_HSSACC_DATAPLANE_RING_ENTRY_REM( + HssAccRxDpFreeQRing[channelType], entry); + } + + entry = (IxQMgrQEntryType) + ICP_OSAL_MBUF_TDM_SECT_OSAL_MBUF_START(pMBufTdmIo); + + /* Add buffer to internal ring also */ + ICP_HSSACC_DATAPLANE_RING_ENTRY_ADD( + HssAccRxDpFreeQRing[channelType], entry); + } + + if (ICP_HSSACC_RX_FREEQ_DP_SERVICE_MUTEX_UNLOCK(channelType) != + IX_SUCCESS) + { + if (channelType == ICP_HSSACC_CHAN_TYPE_VOICE) + { + ICP_HSSACC_REPORT_ERROR_1("icp_HssAccRxFreeChecklessReplenish - " + "Mutex Unlock Error for " + "voice service\n", 0); + } + else + { + ICP_HSSACC_REPORT_ERROR_1("icp_HssAccRxFreeChecklessReplenish - " + "Mutex Unlock Error for " + "HDLC service\n", 0); + } + status = ICP_STATUS_MUTEX; + } + } + else + { + if (channelType == ICP_HSSACC_CHAN_TYPE_VOICE) + { + ICP_HSSACC_REPORT_ERROR_1("icp_HssAccRxFreeChecklessReplenish - " + "Mutex Lock Error for " + "voice service\n", 0); + } + else + { + ICP_HSSACC_REPORT_ERROR_1("icp_HssAccRxFreeChecklessReplenish - " + "Mutex Lock Error for " + "HDLC service\n", 0); + } + + status = ICP_STATUS_MUTEX; + } + +#ifndef NDEBUG + /* Log packet */ + if (status != ICP_STATUS_SUCCESS) + { + hssAccRxNumReplenishFailures[channelType] ++; + } + else + { + hssAccRxNumPktsReplenished[channelType] ++; + } +#endif + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccRxFreeChecklessReplenish\n"); + + return status; +} + + +/****************************************************************************** + * Abstract: + * Register rx callback and user context + * + ******************************************************************************/ +void +HssAccChannelRxCallbackRegister(uint32_t channelId, + icp_hssacc_rx_callback_t rxCallback, + icp_user_context_t userContext) +{ + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelRxCallbackRegister\n"); + + HssAccRxChannelCallbacks[channelId] = rxCallback; + HssAccRxChannelCallbackUserContexts[channelId] = userContext; + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelRxCallbackRegister\n"); +} + +/****************************************************************************** + * Abstract: + * Register rx callback and user context + * + ******************************************************************************/ +void +HssAccChannelRxCallbackDeregister(uint32_t channelId) +{ + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelRxCallbackDeregister\n"); + + HssAccRxChannelCallbacks[channelId] = NULL; + HssAccRxChannelCallbackUserContexts[channelId] = 0; + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelRxCallbackDeregister\n"); +} + +/****************************************************************************** + * Abstract: + * Service Rx Q and call a callback for every entry received + * Process receive Q, calling callbacks for each received buffer. + * Called from the queue processing function. The Q manager callbacks are + * triggered by HssAccRxDatapathService + * + ******************************************************************************/ +void +HssAccRxQServiceCallback (IxQMgrQId qId, + IxQMgrCallbackId cbId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + uint32_t numEntries = 0; + uint32_t k = 0; + uint32_t chId = 0; + IxQMgrQEntryType qEntry = 0; + IxQMgrQEntryType physQEntry = 0; + unsigned callbacksToDo = 0; + icp_hssacc_osal_mbuf_tdm_io_section_t *pMBufTdmIo = NULL; + icp_hssacc_channel_type_t chanType = ICP_HSSACC_CHAN_TYPE_DELIMITER; + unsigned chanCallbackNeeded[ICP_HSSACC_MAX_NUM_CHANNELS]; + + + ICP_HSSACC_DP_TRACE_2 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccRxQServiceCallback for " + "Q %d and CB Id %d\n", + qId, cbId); + + /* Retrieve channel type */ + chanType = HssAccChanTypeGet(qId); + + memset(chanCallbackNeeded,0,ICP_HSSACC_MAX_NUM_CHANNELS*sizeof(unsigned)); + + /* Acquire service mutex */ + if (IX_SUCCESS != ICP_HSSACC_RX_DP_SERVICE_MUTEX_LOCK(chanType)) + { + ICP_HSSACC_REPORT_ERROR_1("HssAccRxQService - " + "Mutex Lock Error for service %d\n", + chanType); + return; + } + + /* Get number of entries in q */ + status = ixQMgrQNumEntriesGetWithChecks ( qId, &numEntries); + + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR("HssAccRxQService - " + "Error Reading Num Entries " + "from the Queue\n"); + + if (ICP_HSSACC_RX_DP_SERVICE_MUTEX_UNLOCK(chanType) != IX_SUCCESS) + { + ICP_HSSACC_REPORT_ERROR_1("HssAccRxQService - " + "Mutex Unlock Error for service %d\n", + chanType); + } + + return; + } + + for (k = 0; k < numEntries; k ++) + { + status = ixQMgrQReadWithChecks (qId, &physQEntry); + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR("HssAccRxQServiceCallback - Error" + " Reading from the Queue\n"); + continue; + } + + /* Convert physical address (that TDM I/O Unit uses) to + virtual address (that Access layer uses) */ + qEntry = (IxQMgrQEntryType) + HssAccPhysToVirtAddressSwapAndTranslate(physQEntry); + + ICP_HSSACC_DP_TRACE_2(ICP_HSSACC_DEBUG, + "HssAccRxQServiceCallback - " + "got Phys Entry 0x%08X to Virt 0x%08X\n", + physQEntry, + qEntry); + + /* Convert q Entry to a pointer to TDM I/O-specific + portion of OSAL MBUF */ + pMBufTdmIo = + (icp_hssacc_osal_mbuf_tdm_io_section_t *) qEntry; + /* Retrieve channel Id */ + chId = ICP_OSAL_MBUF_TDM_SECT_CHANNEL_ID(pMBufTdmIo); + + if (ICP_HSSACC_CHANNEL_ENABLED != + HssAccChannelConfigStateQuery(chId)) + { + /* if channel is not enabled put the buffer on the + rx free q and not on the channel ring */ + if (ICP_STATUS_SUCCESS != + icp_HssAccRxFreeChecklessReplenish(chanType, + pMBufTdmIo)) + { + ICP_HSSACC_REPORT_ERROR_1( + "HssAccRxQServiceCallback - " + " Rx Free Replenish failed for channel type %d\n", + chanType); + } + } + else + { + if (!ICP_HSSACC_DATAPLANE_RING_FULL( + HssAccRxDpDescRing[chId])) + { + /* VOICE PACKET AGING: check the channel type and + queue Level. Reject if above level and + previous buffer was accepted onto ring */ + if (ICP_HSSACC_CHAN_TYPE_VOICE == + HssAccChannelConfigTypeQuery(chId)) + { + if(ICP_HSSACC_RX_Q_WATERMARK_LEVEL <= + hssAccRxDatapathNumPendPkts[chId]) + { + hssAccRxDatapathWatermarkLevelReached[chId] + = ICP_TRUE; + } + else if ((ICP_TRUE == + hssAccRxDatapathWatermarkLevelReached[chId]) && + (0 == hssAccRxDatapathNumPendPkts[chId])) + { + hssAccRxDatapathWatermarkLevelReached[chId] + = ICP_FALSE; + } + } + + if ((ICP_TRUE == + hssAccRxDatapathWatermarkLevelReached[chId]) && + (ICP_TRUE == + hssAccRxDatapathLastReceiveSuccess[chId])) + { + /* can only be true for voice */ + ICP_HSSACC_DP_TRACE_1(ICP_HSSACC_DEBUG, + "HssAccRxQServiceCallback - " + "Regulating Rx Flow for channel %d\n", + chId); + /* put the buffer on the rx free q and not on the + channel ring */ + if (ICP_STATUS_SUCCESS != + icp_HssAccRxFreeChecklessReplenish( + chanType, + pMBufTdmIo)) + { + ICP_HSSACC_REPORT_ERROR_1( + "HssAccRxQServiceCallback - Rx Free" + " Replenish failed for channel type %d\n", + chanType); + } + +#ifndef NDEBUG + hssAccRxNumPktsAged[chId]++; +#endif + hssAccRxDatapathLastReceiveSuccess[chId] + = ICP_FALSE; + } + else + { + /* Put q entry in ring associated with + correct channel */ + ICP_HSSACC_DATAPLANE_RING_ENTRY_ADD( + HssAccRxDpDescRing[chId], + qEntry); + hssAccRxDatapathNumPendPkts[chId] ++; + hssAccRxDatapathLastReceiveSuccess[chId] + = ICP_TRUE; + + /* Log which channel requires a callback and + increment the total num of callbacks to do */ + if (NULL != HssAccRxChannelCallbacks[chId]) + { + chanCallbackNeeded[chId] ++; + callbacksToDo ++; + } + } + } + else + { + ICP_HSSACC_DP_TRACE_1 (ICP_HSSACC_DEBUG, + "HssAccRxQServiceCallback - Internal Ring" + " overflow on channel %d\n", + chId); + + /* put the buffer on the rx free q and not on the + channel ring */ + if (ICP_STATUS_SUCCESS != + icp_HssAccRxFreeChecklessReplenish( + chanType, + pMBufTdmIo)) + { + ICP_HSSACC_REPORT_ERROR_1( + "HssAccRxQServiceCallback - Rx Free" + " Replenish failed for channel type %d\n", + chanType); + } + + hssAccRxDatapathLastReceiveSuccess[chId] = ICP_FALSE; + continue; + } + } + } + + if (ICP_HSSACC_RX_DP_SERVICE_MUTEX_UNLOCK(chanType) != IX_SUCCESS) + { + ICP_HSSACC_REPORT_ERROR_1("HssAccRxQServiceCallback - " + "Mutex Unlock Error for service %d\n", + chanType); + } + else + { + k = 0; + while (callbacksToDo) + { + while (chanCallbackNeeded[k]) + { + ICP_HSSACC_DP_TRACE_2(ICP_HSSACC_DEBUG, + "HssAccRxQServiceCallback - channel %d, " + " %d callbacks left\n", + k, callbacksToDo-1); + + HssAccRxChannelCallbacks[k]( + HssAccRxChannelCallbackUserContexts[k]); + chanCallbackNeeded[k] --; + callbacksToDo --; + } + k ++; + } + } + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccRxQServiceCallback\n"); + +} + + +/****************************************************************************** + * Abstract: + * Process receive Q *without* any calling of callbacks. Called + * from icp_HssAccReceive. If nothing in rx Q, returns ICP_FALSE in + * bufferReceived arg + * + *****************************************************************************/ +icp_status_t +HssAccRxQService (IxQMgrQId qId, + unsigned channelId, + icp_boolean_t *bufferReceived) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + uint32_t numEntries = 0; + uint32_t k = 0; + uint32_t chId = 0; + IxQMgrQEntryType qEntry = 0; + IxQMgrQEntryType physQEntry = 0; + icp_hssacc_osal_mbuf_tdm_io_section_t *pMBufTdmIo = NULL; + icp_hssacc_channel_type_t chanType = ICP_HSSACC_CHAN_TYPE_DELIMITER; + + ICP_HSSACC_DP_TRACE_2 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccRxQService for " + "Q %d and channelId %d\n", + qId, channelId); + + *bufferReceived = ICP_FALSE; + + /* Retrieve channel type */ + chanType = HssAccChanTypeGet(qId); + + if (IX_SUCCESS != ICP_HSSACC_RX_DP_SERVICE_MUTEX_LOCK(chanType)) + { + ICP_HSSACC_REPORT_ERROR_1("HssAccRxQService - " + "Mutex Lock Error for service %d\n", + chanType); + status = ICP_STATUS_MUTEX; + return status; + } + + /* Get number of entries in q */ + status = ixQMgrQNumEntriesGetWithChecks ( qId, &numEntries); + + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR("HssAccRxQService - " + "Error Reading Num Entries " + "from the Queue\n"); + + if (ICP_HSSACC_RX_DP_SERVICE_MUTEX_UNLOCK(chanType) != IX_SUCCESS) + { + ICP_HSSACC_REPORT_ERROR_1("HssAccRxQService - " + "Mutex Unlock Error for service %d\n", + chanType); + } + + return status; + } + + for (k = 0; k < numEntries; k ++) + { + status = ixQMgrQReadWithChecks (qId, &physQEntry); + + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR("HssAccRxQService - Error" + " Reading from the Queue\n"); + continue; + } + + /* Convert physical address (that TDM I/O Unit uses) to + virtual address (that Access layer uses) */ + qEntry = (IxQMgrQEntryType) + HssAccPhysToVirtAddressSwapAndTranslate(physQEntry); + + ICP_HSSACC_DP_TRACE_2(ICP_HSSACC_DEBUG, + "HssAccRxQService - " + "got Phys Entry 0x%08X to Virt 0x%08X\n", + physQEntry, + qEntry); + + /* Convert q Entry to a pointer to TDM I/O-specific + portion of OSAL MBUF */ + pMBufTdmIo = + (icp_hssacc_osal_mbuf_tdm_io_section_t *) qEntry; + /* Retrieve channel Id */ + chId = ICP_OSAL_MBUF_TDM_SECT_CHANNEL_ID(pMBufTdmIo); + + if (ICP_HSSACC_CHANNEL_ENABLED != + HssAccChannelConfigStateQuery(chId)) + { + /* if channel is not enabled put the buffer on the + rx free q and not on the channel ring */ + if (ICP_STATUS_SUCCESS != + icp_HssAccRxFreeChecklessReplenish(chanType, + pMBufTdmIo)) + { + ICP_HSSACC_REPORT_ERROR_1( + "HssAccRxQService - " + " Rx Free Replenish failed for channel type %d\n", + chanType); + } + } + else + { + if (!ICP_HSSACC_DATAPLANE_RING_FULL( + HssAccRxDpDescRing[chId])) + { + /* VOICE PACKET AGING: check the channel type and + queue Level. Reject if above level and + previous buffer was accepted onto ring */ + if (ICP_HSSACC_CHAN_TYPE_VOICE == + HssAccChannelConfigTypeQuery(chId)) + { + if(ICP_HSSACC_RX_Q_WATERMARK_LEVEL <= + hssAccRxDatapathNumPendPkts[chId]) + { + hssAccRxDatapathWatermarkLevelReached[chId] + = ICP_TRUE; + } + else if ((ICP_TRUE == + hssAccRxDatapathWatermarkLevelReached[chId]) && + (0 == hssAccRxDatapathNumPendPkts[chId])) + { + hssAccRxDatapathWatermarkLevelReached[chId] + = ICP_FALSE; + } + } + + if ((ICP_TRUE == + hssAccRxDatapathWatermarkLevelReached[chId]) && + (ICP_TRUE == + hssAccRxDatapathLastReceiveSuccess[chId])) + { + /* can only be true for voice */ + ICP_HSSACC_DP_TRACE_1(ICP_HSSACC_DEBUG, + "HssAccRxQService - " + "Regulating Rx Flow for channel %d\n", + chId); + /* put the buffer on the rx free q and not on the + channel ring */ + if (ICP_STATUS_SUCCESS != + icp_HssAccRxFreeChecklessReplenish( + chanType, + pMBufTdmIo)) + { + ICP_HSSACC_REPORT_ERROR_1( + "HssAccRxQService - Rx Free" + " Replenish failed for channel type %d\n", + chanType); + } +#ifndef NDEBUG + hssAccRxNumPktsAged[chId]++; +#endif + hssAccRxDatapathLastReceiveSuccess[chId] + = ICP_FALSE; + } + else + { + /* Put q entry in ring associated with + correct channel */ + ICP_HSSACC_DATAPLANE_RING_ENTRY_ADD( + HssAccRxDpDescRing[chId], + qEntry); + hssAccRxDatapathNumPendPkts[chId] ++; + hssAccRxDatapathLastReceiveSuccess[chId] + = ICP_TRUE; + if (channelId == chId) + { + ICP_HSSACC_DP_TRACE_1 (ICP_HSSACC_DEBUG, + "HssAccRxQService - A new " + "buffer was pushed into the " + "internal ring on channel %d\n", + chId); + /* flag a buffer has been received */ + *bufferReceived = ICP_TRUE; + } + } + } + else + { + ICP_HSSACC_DP_TRACE_1 (ICP_HSSACC_DEBUG, + "HssAccRxQService - Internal Ring" + " overflow on channel %d\n", + chId); + + /* put the buffer on the rx free q and not on the + channel ring */ + if (ICP_STATUS_SUCCESS != + icp_HssAccRxFreeChecklessReplenish( + chanType, + pMBufTdmIo)) + { + ICP_HSSACC_REPORT_ERROR_1( + "HssAccRxQService - Rx Free" + " Replenish failed for channel type %d\n", + chanType); + } + + hssAccRxDatapathLastReceiveSuccess[chId] = ICP_FALSE; + continue; + } + } + } + + if (ICP_HSSACC_RX_DP_SERVICE_MUTEX_UNLOCK(chanType) != IX_SUCCESS) + { + ICP_HSSACC_REPORT_ERROR_1("HssAccRxQService - " + "Mutex Unlock Error for service %d\n", + chanType); + status = ICP_STATUS_MUTEX; + } + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccRxQService\n"); + + return status; + +} + + + +/****************************************************************************** + * Abstract: + * Function called from icp_HssAccReceive which + * checks to see if there's anything in channel's internal ring. + * If there is, this is returned immediately, otherwise calls + * HssAccRxQService + * + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccRxReceive (IxQMgrQId qId, + uint32_t channelId, + IX_OSAL_MBUF ** buffer) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IxQMgrQEntryType qEntry; + icp_hssacc_osal_mbuf_tdm_io_section_t *pMBufTdmIo; + icp_boolean_t bufferReceived = ICP_TRUE; + icp_hssacc_channel_type_t chanType = HssAccChannelConfigTypeQuery(channelId); + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccRxReceive\n"); + + /* Return NULL buffer by default */ + *buffer = NULL; + + /* If there's anything available for channel, return it, */ + if (ICP_HSSACC_DATAPLANE_RING_EMPTY(HssAccRxDpDescRing[channelId])) + { + /* otherwise, process queue and repeat check */ + status = HssAccRxQService(qId, channelId, &bufferReceived); + } + else + { + bufferReceived = ICP_TRUE; + } + + if ( (status == ICP_STATUS_SUCCESS) && (bufferReceived == ICP_TRUE) ) + { + + /* There is definitely something in channel's ring now */ + + /* Get an entry */ + ICP_HSSACC_DATAPLANE_RING_ENTRY_REM(HssAccRxDpDescRing[channelId], + qEntry); + hssAccRxDatapathNumUserBuffersInRxSystem[chanType] --; + hssAccRxDatapathNumPendPkts[channelId] --; + + /* Entry is a pointer to TDM I/O Unit-specific portion of + an OSAL buffer, */ + pMBufTdmIo = (icp_hssacc_osal_mbuf_tdm_io_section_t *) qEntry; + + /* look up where start of buffer is */ + *buffer = ICP_OSAL_MBUF_TDM_SECT_OSAL_MBUF_START(pMBufTdmIo); + /* Set the length of received buffer in OSAL buffer fields */ + + IX_OSAL_MBUF_MLEN(*buffer) = + ( (ICP_OSAL_MBUF_TDM_SECT_CURR_BUF_LEN_MSB(pMBufTdmIo) << + ICP_OSAL_MBUF_TDM_SECT_LEN_MSB_OFFSET) | + ICP_OSAL_MBUF_TDM_SECT_CURR_BUF_LEN_LSB(pMBufTdmIo) ); + IX_OSAL_MBUF_PKT_LEN(*buffer) = IX_OSAL_MBUF_MLEN(*buffer); + + HssAccDataEndiannessSwap(*buffer); + + }/*if ( (status == ICP_STATUS_SUCCESS) && (bufferReceived == ICP_TRUE) )*/ + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccRxReceive\n"); + + return status; +} + + + +/****************************************************************************** + * Abstract: + * This function receives a buffer. Simply checks channel type + * and calls HssAccRxReceive. Also logs packets. + * + *****************************************************************************/ +icp_status_t +icp_HssAccReceive (uint32_t channelId, IX_OSAL_MBUF ** buffer) +{ + icp_hssacc_channel_type_t chanType = ICP_HSSACC_CHAN_TYPE_DELIMITER; + icp_status_t status = ICP_STATUS_SUCCESS; + IxQMgrQId qId = IX_QMGR_MAX_NUM_QUEUES; + + ICP_HSSACC_DP_TRACE_1 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccReceive for channel %d\n", + channelId); + +#ifndef NDEBUG + if (ICP_HSSACC_MAX_NUM_CHANNELS <= channelId) + { + ICP_HSSACC_REPORT_ERROR("icp_HssAccReceive - channelId " + "out of range\n"); + status = ICP_STATUS_INVALID_PARAM; + } +#endif + if (ICP_STATUS_SUCCESS == status) + { + /* Retrieve qId for channel */ + chanType = HssAccChannelConfigTypeQuery(channelId); + if (chanType == ICP_HSSACC_CHAN_TYPE_HDLC) + { + qId = HssAccQueueIdGet(ICP_HSSACC_HDLC_RX_Q); + } + else if (chanType == ICP_HSSACC_CHAN_TYPE_VOICE) + { + qId = HssAccQueueIdGet(ICP_HSSACC_VOICE_RX_Q); + } + else + { + status = ICP_STATUS_INVALID_PARAM; + } + } + if (status == ICP_STATUS_SUCCESS) + { + status = HssAccRxReceive(qId, channelId, buffer); + } + +#ifndef NDEBUG + /* Log packet */ + if ( (status != ICP_STATUS_SUCCESS) || (*buffer == NULL) ) + { + hssAccRxNumReceiveFailures[channelId] ++; + } + else + { + hssAccRxNumPktsReceived[channelId] ++; + } +#endif + + ICP_HSSACC_DP_TRACE_2 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccReceive for channel %d " + "with buffer 0x%08X\n", + channelId, + (uint32_t)*buffer); + return status; +} + + +/****************************************************************************** + * Abstract: + * Function to run the Q Mgr processing function and call + * associated callbacks + * + ******************************************************************************/ +icp_status_t +HssAccRxDatapathService(icp_hssacc_channel_type_t channelType) +{ + IxQMgrDispatchGroup group; + icp_status_t status = ICP_STATUS_SUCCESS; + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccRxDatapathService\n"); + + /* Just call dispatcher loop for Rx Qs */ + if (channelType == ICP_HSSACC_CHAN_TYPE_VOICE) + { + group = IX_QMGR_DISPATCH_VOICE_RX_HSS; + ixQMgrDispatcherLoopRun(group); + } + else if (channelType == ICP_HSSACC_CHAN_TYPE_HDLC) + { + group = IX_QMGR_DISPATCH_HDLC_RX_HSS; + ixQMgrDispatcherLoopRun(group); + } + else + { + status = ICP_STATUS_INVALID_PARAM; + } + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccRxDatapathService\n"); + return status; +} + + + +/****************************************************************************** + * Abstract: +* Reset the per-channel statistics +* +******************************************************************************/ +void +HssAccRxDatapathChanStatsReset(uint32_t channelId) +{ +#ifndef NDEBUG + hssAccRxNumPktsReceived[channelId] = 0; + hssAccRxNumReceiveFailures[channelId] = 0; + hssAccRxNumPktsAged[channelId] = 0; +#endif +} + + + + +/****************************************************************************** + * Abstract: + * Print out the per-channel statistics + * + ******************************************************************************/ +void +HssAccRxDatapathChanStatsShow(uint32_t channelId) +{ +#ifndef NDEBUG + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nRx Datapath Statistics for Channel %d\n", + channelId, 0, 0, 0, 0, 0); + + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\t\t%d Packets Received\n" + "\t\t%d Packet Receive Failures\n" + "\t\t%d Packets Aged\n", + hssAccRxNumPktsReceived[channelId], + hssAccRxNumReceiveFailures[channelId], + hssAccRxNumPktsAged[channelId], 0, 0, 0); + +#else + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nChannel Rx Datapath Statistics Not Supported in this Build\n", + 0, 0, 0, 0, 0, 0); +#endif +} + + + +/****************************************************************************** + * Abstract: + * Function to print out stats on replenishing + * + ******************************************************************************/ +void +HssAccRxDatapathReplenishStatsShow(icp_hssacc_channel_type_t serviceType) +{ +#ifndef NDEBUG + if (serviceType == ICP_HSSACC_CHAN_TYPE_HDLC) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nRx Datapath Replenish Statistics for HDLC service\n", + 0, 0, 0, 0, 0, 0); + } + else + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nRx Datapath Replenish Statistics for voice service\n", + 0, 0, 0, 0, 0, 0); + } + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\t\t%d Packets Replenished\n" + "\t\t%d Packet Replenish Failures\n", + hssAccRxNumPktsReplenished[serviceType], + hssAccRxNumReplenishFailures[serviceType], 0, 0, 0, 0); +#else + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nRx Datapath Service Statistics Not Supported in this Build\n", + 0, 0, 0, 0, 0, 0); +#endif +} + + + + +/****************************************************************************** + * Abstract: + * Function to reset stats on replenishing + * + *****************************************************************************/ +void +HssAccRxDatapathReplenishStatsReset(icp_hssacc_channel_type_t serviceType) +{ +#ifndef NDEBUG + hssAccRxNumPktsReplenished[serviceType] = 0; + hssAccRxNumReplenishFailures[serviceType] = 0; +#endif +} + + + +/****************************************************************************** + * Abstract: + * Reset all globals + * + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccRxDatapathReset(void) +{ + int k = 0; + icp_status_t status = ICP_STATUS_SUCCESS; + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccRxDatapathReset\n"); + + for (k = 0; k < ICP_HSSACC_MAX_NUM_CHANNELS; k ++) + { + + HssAccRxDpDescRing[k].content = &HssAccRxDpDescPtrRingData[k][0]; + HssAccRxDpDescRing[k].size = + ICP_HSSACC_RX_DP_CHAN_DESC_PTR_RING_SZ; + HssAccRxDpDescRing[k].mask = + ICP_HSSACC_RX_DP_CHAN_DESC_PTR_RING_SZ - 1; + HssAccRxDpDescRing[k].tail = 0; + HssAccRxDpDescRing[k].head = 0; + HssAccRxChannelCallbacks[k] = NULL; + HssAccRxChannelCallbackUserContexts[k] = 0; + HssAccRxDatapathChanStatsReset(k); + hssAccRxDatapathNumPendPkts[k] = 0; + hssAccRxDatapathLastReceiveSuccess[k] = ICP_FALSE; + hssAccRxDatapathWatermarkLevelReached[k] = ICP_FALSE; + } + + for (k = 0; k < ICP_HSSACC_CHAN_TYPE_DELIMITER; k ++) + { + HssAccRxDpFreeQRing[k].content = &HssAccRxDpFreeQRingData[k][0]; + HssAccRxDpFreeQRing[k].size = ICP_HSSACC_HDLC_RX_FREE_QUEUE_DEPTH; + HssAccRxDpFreeQRing[k].mask = ICP_HSSACC_HDLC_RX_FREE_QUEUE_DEPTH-1; + HssAccRxDpFreeQRing[k].tail = 0; + HssAccRxDpFreeQRing[k].head = 0; + maxRxDatapathFrameSize[k] = 0; +#ifndef NDEBUG + hssAccRxNumPktsReplenished[k] = 0; + hssAccRxNumReplenishFailures[k] = 0; +#endif + hssAccRxDatapathNumUserBuffersInRxSystem[k] = 0; + } + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccRxDatapathReset\n"); + + return status; +} + + + + +/****************************************************************************** + * Abstract: + * Initialise Rx datapath global variables + * + ******************************************************************************/ +icp_status_t +HssAccRxDatapathInit(void) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + uint32_t k = 0; + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccRxDatapathInit\n"); + /* Check if component has already been initialised */ + if (ICP_TRUE == hssAccRxServiceInitialised) + { + ICP_HSSACC_REPORT_ERROR ("HssAccRxDatapathInit - " + "component has already been initialised\n"); + + status = ICP_STATUS_FAIL; + } + else /* component has never been initialised */ + { + + /* Initialise service mutexes */ + for (k = 0; k < ICP_HSSACC_CHAN_TYPE_DELIMITER; k ++) + { + if (IX_SUCCESS != ICP_HSSACC_RX_DP_SERVICE_MUTEX_INIT(k)) + { + if (k == ICP_HSSACC_CHAN_TYPE_VOICE) + { + ICP_HSSACC_REPORT_ERROR_1("HssAccRxDatapathInit - " + "Mutex Initialisation Error " + "for voice service\n", 0); + } + else + { + ICP_HSSACC_REPORT_ERROR_1("HssAccRxDatapathInit - " + "Mutex Initialisation " + "Error for HDLC service\n", 0); + } + status = ICP_STATUS_MUTEX; + } + + if (IX_SUCCESS != ICP_HSSACC_RX_FREEQ_DP_SERVICE_MUTEX_INIT(k)) + { + if (k == ICP_HSSACC_CHAN_TYPE_VOICE) + { + ICP_HSSACC_REPORT_ERROR_1("HssAccRxDatapathInit - Rx Free " + "Q Mutex Initialisation Error " + "for voice service\n", 0); + } + else + { + ICP_HSSACC_REPORT_ERROR_1("HssAccRxDatapathInit - Rx Free " + "Q Mutex Initialisation " + "Error for HDLC service\n", 0); + } + status = ICP_STATUS_MUTEX; + } + } + + if (status == ICP_STATUS_SUCCESS) + { + status = HssAccRxDatapathReset(); + if (status == ICP_STATUS_SUCCESS) + { + hssAccRxServiceInitialised = ICP_TRUE; + } + } + } + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccRxDatapathInit\n"); + return status; +} + + + + +/****************************************************************************** + * Abstract: + * Shut down Rx datapath Module. + * + *****************************************************************************/ +icp_status_t +HssAccRxDatapathShutdown(void) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + uint32_t k = 0; + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccRxDatapathShutdown\n"); + + /* Check if component has not been initialised */ + if (ICP_FALSE == hssAccRxServiceInitialised) + { + ICP_HSSACC_REPORT_ERROR ("HssAccRxDatapathShutdown - " + "component has not been initialised\n"); + status = ICP_STATUS_FAIL; + } + else /* component has been initialised */ + { + status = HssAccRxDatapathReset(); + + if (status == ICP_STATUS_SUCCESS) + { + + /* Destroy service mutexes */ + for (k = 0; k < ICP_HSSACC_CHAN_TYPE_DELIMITER; k ++) + { + if (IX_SUCCESS != ICP_HSSACC_RX_DP_SERVICE_MUTEX_DESTROY(k)) + { + ICP_HSSACC_REPORT_ERROR_1("HssAccRxDatapathShutdown - " + "Mutex Destroy Error for " + "service %d\n", + k); + status = ICP_STATUS_MUTEX; + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccRxDatapathShutdown\n"); + return status; + } + + if (IX_SUCCESS != ICP_HSSACC_RX_FREEQ_DP_SERVICE_MUTEX_DESTROY(k)) + { + ICP_HSSACC_REPORT_ERROR_1("HssAccRxDatapathShutdown - Rx " + "Free Q Mutex Destroy Error for " + "service %d\n", + k); + status = ICP_STATUS_MUTEX; + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccRxDatapathShutdown\n"); + return status; + } + } + } + if (ICP_STATUS_SUCCESS == status) + { + hssAccRxServiceInitialised = ICP_FALSE; + } + } + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccRxDatapathShutdown\n"); + return status; +} + + +/****************************************************************************** + * Abstract: + * Add user-supplied buffer to Rx Free Q for use by TDM I/O Unit + * + ******************************************************************************/ +icp_status_t +icp_HssAccRxFreeReplenish ( + icp_hssacc_channel_type_t channelType, + IX_OSAL_MBUF *buffer) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + icp_hssacc_osal_mbuf_tdm_io_section_t *pMBufTdmIo; + uint32_t buffer_len = 0; + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccRxFreeReplenish\n"); + + if (channelType != ICP_HSSACC_CHAN_TYPE_HDLC + && channelType != ICP_HSSACC_CHAN_TYPE_VOICE) + { + status = ICP_STATUS_INVALID_PARAM; + return status; + } + + /* Check that buffer is not NULL */ + if (buffer == NULL) + { + ICP_HSSACC_REPORT_ERROR("icp_HssAccRxFreeReplenish - " + "Buffer pointer is NULL\n"); + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccRxFreeReplenish\n"); + status = ICP_STATUS_INVALID_PARAM; + return status; + } + + /* Check that buffer is not chained. We do not support chaining. */ + if ((IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(buffer) != NULL) || + (IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(buffer) != NULL)) + { + ICP_HSSACC_REPORT_ERROR("icp_HssAccRxFreeReplenish - " + "Buffer or Packet Chaining not supported " + "for reception\n"); + status = ICP_STATUS_INVALID_PARAM; + } + + if (IX_OSAL_MBUF_MDATA(buffer) == NULL) + { + ICP_HSSACC_REPORT_ERROR("icp_HssAccRxFreeReplenish - " + "Buffer's data pointer cannot be NULL\n"); + status = ICP_STATUS_INVALID_PARAM; + } + + /* Check if buffer length supplied is ok. + All buffers supplied need to accomodate the max frame size possible */ + buffer_len = IX_OSAL_MBUF_MLEN(buffer); + if ( buffer_len < maxRxDatapathFrameSize[channelType]) + { + ICP_HSSACC_REPORT_ERROR("icp_HssAccRxFreeReplenish - " + "Buffer is too small. Buffers supplied " + "must all accomodate max frame size\n"); + status = ICP_STATUS_INVALID_PARAM; + } + + if (status == ICP_STATUS_SUCCESS) + { + + /* check chan type and compare num bufs in rx path to size of rx free q */ + if (channelType == ICP_HSSACC_CHAN_TYPE_VOICE) + { + if(ICP_HSSACC_VOICE_RX_QUEUE_DEPTH + <= hssAccRxDatapathNumUserBuffersInRxSystem + [ICP_HSSACC_CHAN_TYPE_VOICE]) + { + ICP_HSSACC_REPORT_ERROR_1("icp_HssAccRxFreeReplenish - " + "Voice Rx Datapath Max Buffer Limit Reached\n", + 0); + status = ICP_STATUS_OVERFLOW; + } + } + else + { + if(ICP_HSSACC_HDLC_RX_QUEUE_DEPTH + <= hssAccRxDatapathNumUserBuffersInRxSystem + [ICP_HSSACC_CHAN_TYPE_HDLC]) + { + ICP_HSSACC_REPORT_ERROR_1("icp_HssAccRxFreeReplenish - " + "HDLC Rx Datapath Max Buffer Limit Reached\n", + 0); + status = ICP_STATUS_OVERFLOW; + } + } + + if (status == ICP_STATUS_SUCCESS) + { + /* Add buffer to relevant Rx free Q */ + + /* First, copy info from OSAL buffer to TDM I/O + Unit-specific portion */ + /* Get address of TDM I/O Unit-specific portion of OSAL buffer */ + pMBufTdmIo = + (icp_hssacc_osal_mbuf_tdm_io_section_t *) &(buffer->ix_ne); + + /* Copy current buffer data location */ + ICP_OSAL_MBUF_TDM_SECT_DATA(pMBufTdmIo) = + (void *) IX_OSAL_MBUF_MDATA(buffer); + + /* Copy current buffer location */ + ICP_OSAL_MBUF_TDM_SECT_OSAL_MBUF_START(pMBufTdmIo) = buffer; + + status = icp_HssAccRxFreeChecklessReplenish (channelType, + pMBufTdmIo); + + if ( ICP_STATUS_SUCCESS == status ) + { + hssAccRxDatapathNumUserBuffersInRxSystem[channelType] ++; + } + + } + + } + + return status; +} + + + +/****************************************************************************** + * Abstract: + * Set max frame size for HDLC, must be done at init + * + *****************************************************************************/ +void +HssAccRxDatapathHdlcInit(uint32_t maxRxFrameSize) +{ + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccRxDatapathHdlcInit\n"); + maxRxDatapathFrameSize[ICP_HSSACC_CHAN_TYPE_HDLC] = maxRxFrameSize; + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccRxDatapathHdlcInit\n"); +} + + + + +/****************************************************************************** + * Abstract: + * Set max frame size for voice, must be done at init + * + *****************************************************************************/ +void +HssAccRxDatapathVoiceInit(uint32_t maxRxFrameSize) +{ + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccRxDatapathVoiceInit\n"); + maxRxDatapathFrameSize[ICP_HSSACC_CHAN_TYPE_VOICE] = maxRxFrameSize; + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccRxDatapathVoiceInit\n"); +} + + +/****************************************************************************** + * Abstract: + * Return the Max Rx Sample/Frame size configured for the specified Service + * + *****************************************************************************/ +uint32_t +HssAccRxDatapathMaxServiceFrameSizeGet(icp_hssacc_channel_type_t servType) +{ + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Called HssAccRxDatapathMaxServiceFrameSizeGet\n"); + return maxRxDatapathFrameSize[servType]; +} + + + + +/****************************************************************************** + * Abstract: + * Checks to see if any channels exist for a specified service other than + * the one being worked on. + * + *****************************************************************************/ +icp_boolean_t +HssAccRxDatapathServAllChansDisabledQuery(icp_hssacc_channel_type_t chanType, + const unsigned channelId) +{ + uint32_t chanId = 0; + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering " + "HssAccRxDatapathServAllChansDisabledQuery\n"); + + for (chanId=0; chanId < ICP_HSSACC_MAX_NUM_CHANNELS; chanId ++) + { + if (chanType == HssAccChannelConfigTypeQuery(chanId) ) + { + if ((HssAccChannelConfigStateQuery(chanId) != + ICP_HSSACC_CHANNEL_UNINITIALISED) && + (chanId != channelId)) + { + ICP_HSSACC_DP_TRACE_1 (ICP_HSSACC_DEBUG, + "HssAccRxDatapathServAllChansDisabledQuery -" + " Found channel %u\n", + chanId); + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting " + "HssAccRxDatapathServAllChans" + "DisabledQuery\n"); + return ICP_FALSE; + } + } + } + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting " + "HssAccRxDatapathServAllChansDisabledQuery\n"); + return ICP_TRUE; +} + + +/****************************************************************************** + * Abstract: + * Retrieve all buffers left in a specific service RxFree queue + * + *****************************************************************************/ +icp_status_t +HssAccRxDatapathServiceSpecificRxFreeEmpty(icp_hssacc_channel_type_t chanType, + IX_OSAL_MBUF * * ppStartChainBuffer, + IX_OSAL_MBUF * * ppEndChainBuffer) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IX_OSAL_MBUF * pCurrentBuffer = NULL; + IxQMgrQId rxfreeqId = IX_QMGR_MAX_NUM_QUEUES; + IxQMgrQId rxqId = IX_QMGR_MAX_NUM_QUEUES; + unsigned numEntries = 0; + IxQMgrQEntryType freeQEntry; + icp_boolean_t bufferReceived = ICP_FALSE; + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccRxDatapathServiceSpecificRxFreeEmpty\n"); + + if (chanType == ICP_HSSACC_CHAN_TYPE_HDLC) + { + rxfreeqId = HssAccQueueIdGet(ICP_HSSACC_HDLC_RX_FREE_Q); + rxqId = HssAccQueueIdGet(ICP_HSSACC_HDLC_RX_Q); + } + else if (chanType == ICP_HSSACC_CHAN_TYPE_VOICE) + { + rxfreeqId = HssAccQueueIdGet(ICP_HSSACC_VOICE_RX_FREE_Q); + rxqId = HssAccQueueIdGet(ICP_HSSACC_VOICE_RX_Q); + } + else + { + status = ICP_STATUS_INVALID_PARAM; + return status; + } + + /* the important part here is to drain the rx queue + into the rx free queue */ + if (ICP_STATUS_SUCCESS != + (status = HssAccRxQService(rxqId, + ICP_HSSACC_MAX_NUM_CHANNELS, + &bufferReceived) )) + { + return status; + } + + /* Acquire service mutex */ + if (IX_SUCCESS != ICP_HSSACC_RX_DP_SERVICE_MUTEX_LOCK(chanType)) + { + if (chanType == ICP_HSSACC_CHAN_TYPE_VOICE) + { + ICP_HSSACC_REPORT_ERROR( + "HssAccRxDatapathServiceSpecificRxFreeEmpty - " + "Mutex Lock Error for " + "voice service\n"); + } + else + { + ICP_HSSACC_REPORT_ERROR( + "HssAccRxDatapathServiceSpecificRxFreeEmpty - " + "Mutex Lock Error for " + "HDLC service\n"); + } + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccRxDatapathServiceSpecificRxFreeEmpty\n"); + return ICP_STATUS_MUTEX; + } + + status = ixQMgrQNumEntriesGet (rxfreeqId, + &numEntries); + + /* Chain all Rx free Q Buffers */ + if (ICP_STATUS_SUCCESS == status) + { + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_DEBUG, + "HssAccRxDatapathServiceSpecificRxFreeEmpty - " + "Create Chain with Rx Free Buffers\n"); + /* First of all read out useless entries in the ring + that mirrors the Rx Free Q */ + while (ICP_HSSACC_DATAPLANE_RING_NUM_ENTRIES_GET( + HssAccRxDpFreeQRing[chanType]) > + numEntries) + { + ICP_HSSACC_DATAPLANE_RING_TAIL_INCR(HssAccRxDpFreeQRing[chanType]); + } + + /* Wind back write pointer to Rx Free Q by number of + entries in Q */ + status = ixQMgrQWriteRollback(rxfreeqId, numEntries); + } + + if (status == ICP_STATUS_SUCCESS) + { + /* add an entry from free Q to start */ + if ((0 != numEntries) && + (!ICP_HSSACC_DATAPLANE_RING_EMPTY(HssAccRxDpFreeQRing[chanType]))) + { + + /* Remove entry from internal ring mirroring + entries in Rx Free Q */ + /* Difference between ring and Q is that ring holds + pointers to buffers, not Rx Free Q entries */ + ICP_HSSACC_DATAPLANE_RING_ENTRY_REM( + HssAccRxDpFreeQRing[chanType], freeQEntry); + + hssAccRxDatapathNumUserBuffersInRxSystem[chanType] --; + numEntries --; + *ppStartChainBuffer = (IX_OSAL_MBUF *) freeQEntry; + pCurrentBuffer = *ppStartChainBuffer; + } + while (!ICP_HSSACC_DATAPLANE_RING_EMPTY(HssAccRxDpFreeQRing[chanType])) + { + /* Remove entry from internal ring mirroring + entries in Rx Free Q */ + ICP_HSSACC_DATAPLANE_RING_ENTRY_REM( + HssAccRxDpFreeQRing[chanType], + freeQEntry); + if (NULL == pCurrentBuffer) + { + ICP_HSSACC_REPORT_ERROR( + "HssAccRxDatapathServiceSpecificRxFreeEmpty - " + "Corrupted Internal Receive Free ring\n"); + status = ICP_STATUS_FATAL; + break; + } + + hssAccRxDatapathNumUserBuffersInRxSystem[chanType] --; + + IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(pCurrentBuffer) = + (IX_OSAL_MBUF *) freeQEntry; + pCurrentBuffer = (IX_OSAL_MBUF *) freeQEntry; + } + } + + + *ppEndChainBuffer = pCurrentBuffer; + + + +if (ICP_HSSACC_RX_DP_SERVICE_MUTEX_UNLOCK(chanType) != + IX_SUCCESS) + { + if (chanType == ICP_HSSACC_CHAN_TYPE_VOICE) + { + ICP_HSSACC_REPORT_ERROR("HssAccRxDatapathServiceSpecificRxFreeEmpty -" + " Mutex Unlock Error for " + "voice service\n"); + } + else + { + ICP_HSSACC_REPORT_ERROR("HssAccRxDatapathServiceSpecificRxFreeEmpty -" + " Mutex Unlock Error for " + "HDLC service\n"); + } + status = ICP_STATUS_MUTEX; + } + + +ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccRxDatapathServiceSpecificRxFreeEmpty\n"); +return status; +} + + + +/****************************************************************************** + * Abstract: + * Retrieve all buffers left in a specific service RxFree queue + * if this is the last channel + * + *****************************************************************************/ +icp_status_t +HssAccRxDatapathRxFreeEmpty(unsigned channelId, + icp_hssacc_channel_type_t chanType, + IX_OSAL_MBUF * * ppStartChainBuffer, + IX_OSAL_MBUF * * ppEndChainBuffer) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccRxDatapathRxFreeEmpty\n"); + + /* Are all channels disabled for this service? + (except for channelId) */ + if (HssAccRxDatapathServAllChansDisabledQuery(chanType, + channelId) == ICP_TRUE) + { + /* Retrieve rxfree and rx qIds for channel */ + if (chanType != ICP_HSSACC_CHAN_TYPE_HDLC && + chanType != ICP_HSSACC_CHAN_TYPE_VOICE) + { + status = ICP_STATUS_INVALID_PARAM; + } + else + { + status = HssAccRxDatapathServiceSpecificRxFreeEmpty( + chanType, + ppStartChainBuffer, + ppEndChainBuffer); + +/*unit test code uses ixQMgrWrite() directly - bypassing the + internal hssAcc counter*/ + if (ICP_STATUS_SUCCESS == status) + { + if (0 != hssAccRxDatapathNumUserBuffersInRxSystem[chanType]) + { + ICP_HSSACC_REPORT_ERROR_1("HssAccRxDatapathRxFreeEmpty - " + "Tracked number of user buffers in rx system " + "(%d) != 0\n", + hssAccRxDatapathNumUserBuffersInRxSystem[chanType]); + } + } + } + } + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccRxDatapathRxFreeEmpty\n"); + + return status; +} + + +/****************************************************************************** + * Abstract: + * Retrieve all buffers in a chain from both Voice and HDLC Rx Free Qs where + * there are no channels enabled for the particular service + * + *****************************************************************************/ +icp_status_t +HssAccRxFreeQsBufsRetrieve(IX_OSAL_MBUF * * ppStartChainBuffer, + IX_OSAL_MBUF * * ppEndChainBuffer) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + icp_boolean_t chainStarted = ICP_FALSE; + IX_OSAL_MBUF * pStartChainRxFreeBuffer = NULL; + IX_OSAL_MBUF * pEndChainRxFreeBuffer = NULL; + int k = 0; + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccRxFreeQsBufsRetrieve "); + + for (k = 0; k < ICP_HSSACC_CHAN_TYPE_DELIMITER; k ++) + { + /* ICP_HSSACC_MAX_NUM_CHANNELS is used so the + internal check is on all channels of type k */ + if (HssAccRxDatapathServAllChansDisabledQuery( + k, + ICP_HSSACC_MAX_NUM_CHANNELS) + == ICP_TRUE) + { + pStartChainRxFreeBuffer = NULL; + pEndChainRxFreeBuffer = NULL; + + status = HssAccRxDatapathServiceSpecificRxFreeEmpty( + k, + &pStartChainRxFreeBuffer, + &pEndChainRxFreeBuffer); + + if (ICP_STATUS_SUCCESS == status) + { + if (NULL != pStartChainRxFreeBuffer) + { + if (ICP_TRUE == chainStarted) + { + IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(*ppEndChainBuffer) + = pStartChainRxFreeBuffer; + } + else + { + *ppStartChainBuffer = pStartChainRxFreeBuffer; + } + *ppEndChainBuffer = pEndChainRxFreeBuffer; + + chainStarted = ICP_TRUE; + } + } + } + } + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccRxFreeQsBufsRetrieve\n"); + return status; +} + + +/****************************************************************************** + * Abstract: + * Retrieve all buffers in a chain from Rx Ring for a specified channel + * + *****************************************************************************/ +icp_status_t +HssAccRxDatapathChanBufsRetrieve(uint32_t channelId, + IX_OSAL_MBUF * * ppStartChainBuffer, + IX_OSAL_MBUF * * ppEndChainBuffer) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + uint32_t numEntries = 0; + uint32_t entry = 0; + icp_hssacc_osal_mbuf_tdm_io_section_t *pMBufTdmIo = NULL; + IX_OSAL_MBUF * pCurrentBuffer = NULL; + icp_boolean_t chainStarted = ICP_FALSE; + icp_hssacc_channel_type_t chanType = ICP_HSSACC_CHAN_TYPE_DELIMITER; + IX_OSAL_MBUF * pStartChainRxFreeBuffer = NULL; + IX_OSAL_MBUF * pEndChainRxFreeBuffer = NULL; + + ICP_HSSACC_DP_TRACE_1 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccRxDatapathChanBufsRetrieve " + "for channel %d\n", + channelId); + + /* Process receive Q */ + chanType = HssAccChannelConfigTypeQuery(channelId); + + if (chanType != ICP_HSSACC_CHAN_TYPE_HDLC && + chanType != ICP_HSSACC_CHAN_TYPE_VOICE) + { + status = ICP_STATUS_INVALID_PARAM; + } + + if (status == ICP_STATUS_SUCCESS) + { + numEntries = + ICP_HSSACC_DATAPLANE_RING_NUM_ENTRIES_GET( + HssAccRxDpDescRing[channelId]); + + /* Special case for starting the Chain */ + if (numEntries != 0) + { + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_DEBUG, + "HssAccRxDatapathChanBufsRetrieve - " + "Start retrieving buffers\n"); + numEntries --; + ICP_HSSACC_DATAPLANE_RING_ENTRY_REM(HssAccRxDpDescRing[channelId], + entry); + hssAccRxDatapathNumPendPkts[channelId] --; + hssAccRxDatapathNumUserBuffersInRxSystem[chanType] --; + + /* Entry is a pointer to TDM I/O Unit-specific + portion of an OSAL buffer, */ + pMBufTdmIo = + (icp_hssacc_osal_mbuf_tdm_io_section_t *) entry; + /* look up where start of buffer is */ + if (NULL == pMBufTdmIo) + { + ICP_HSSACC_REPORT_ERROR("HssAccRxDatapathChanBufsRetrieve - " + "Corrupted Internal Receive ring\n"); + return ICP_STATUS_FATAL; + } + *ppStartChainBuffer = + ICP_OSAL_MBUF_TDM_SECT_OSAL_MBUF_START(pMBufTdmIo); + if (NULL == *ppStartChainBuffer) + { + ICP_HSSACC_REPORT_ERROR("HssAccRxDatapathChanBufsRetrieve - " + "Corrupted Receive Entry\n"); + return ICP_STATUS_FATAL; + } + + pCurrentBuffer = *ppStartChainBuffer; + *ppEndChainBuffer = pCurrentBuffer; + chainStarted = ICP_TRUE; +#ifndef NDEBUG + hssAccRxNumPktsReceived[channelId] ++; +#endif + } + + } + + if (ICP_STATUS_SUCCESS == status) + { + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_DEBUG, + "HssAccRxDatapathChanBufsRetrieve - " + "Create Chain with Rx'ed Buffers\n"); + + while (!ICP_HSSACC_DATAPLANE_RING_EMPTY(HssAccRxDpDescRing[channelId])) + { + ICP_HSSACC_DATAPLANE_RING_ENTRY_REM(HssAccRxDpDescRing[channelId], + entry); + numEntries --; + hssAccRxDatapathNumPendPkts[channelId] --; + hssAccRxDatapathNumUserBuffersInRxSystem[chanType] --; + + /* Entry is a pointer to TDM I/O-specific portion + of an OSAL buffer, */ + pMBufTdmIo = + (icp_hssacc_osal_mbuf_tdm_io_section_t *) entry; + if (NULL == pMBufTdmIo) + { + ICP_HSSACC_REPORT_ERROR("HssAccRxDatapathChanBufsRetrieve" + " - Corrupted Internal Receive " + "ring\n"); + status = ICP_STATUS_FATAL; + break; + } + /* look up where start of buffer is */ + IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(pCurrentBuffer) = + ICP_OSAL_MBUF_TDM_SECT_OSAL_MBUF_START(pMBufTdmIo); + + pCurrentBuffer = + ICP_OSAL_MBUF_TDM_SECT_OSAL_MBUF_START(pMBufTdmIo); +#ifndef NDEBUG + hssAccRxNumPktsReceived[channelId] ++; +#endif + } + *ppEndChainBuffer = pCurrentBuffer; + + } + + + if (ICP_STATUS_SUCCESS == status) + { + + /* Second Stage: If no channel left enabled for this service, + return all buffers in rx Free Q */ + /* Check if we started a chain previously or not */ + status = HssAccRxDatapathRxFreeEmpty(channelId, + chanType, + &pStartChainRxFreeBuffer, + &pEndChainRxFreeBuffer); + if (NULL != pStartChainRxFreeBuffer) + { + if (ICP_TRUE == chainStarted) + { + IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(*ppEndChainBuffer) = + pStartChainRxFreeBuffer; + } + else + { + *ppStartChainBuffer = pStartChainRxFreeBuffer; + } + *ppEndChainBuffer = pEndChainRxFreeBuffer; + } + } + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccRxDatapathChanBufsRetrieve\n"); + + return status; +} diff --git a/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_service.c b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_service.c new file mode 100644 index 0000000..71e0fbd --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_service.c @@ -0,0 +1,2579 @@ +/****************************************************************************** + * @file icp_hssacc_service.c + * + * @description Contents of this file provides the implementation of the + * HSS Service functions + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + *****************************************************************************/ + +/* ---------------------------------------------------------------------------- + * Includes + * ---------------------------------------------------------------------------- + */ +#include "IxOsal.h" + +#include "icp.h" +#include "icp_hssacc.h" +#include "icp_hssacc_common.h" +#include "icp_hssacc_port_config.h" +#include "icp_hssacc_channel_config.h" +#include "icp_hssacc_queues_config.h" +#include "icp_hssacc_channel_list.h" +#include "icp_hssacc_voice_bypass.h" +#include "icp_hssacc_timeslot_allocation.h" +#include "icp_hssacc_tx_datapath.h" +#include "icp_hssacc_trace.h" +#include "icp_hssacc_rx_datapath.h" + + + +/* + * ---------------------------------------------------------------------------- + * Global variables + * ---------------------------------------------------------------------------- + */ +/* Mutex which controls access to control path functions */ +IxOsalMutex hssAccControlPathMutex; + +/* Flag to test whether the HssAcc component has been initialised or not. */ +TDM_PRIVATE icp_boolean_t serviceInitialised = ICP_FALSE; + +/* Stats */ +typedef struct icp_hssacc_service_stats_s +{ +/* Internal stats for Timer configuraton messaging */ + icp_hssacc_msg_with_resp_stats_t timerStat; + icp_hssacc_msg_with_resp_stats_t intStat; + icp_hssacc_msg_with_resp_stats_t abtAlnRead; + icp_hssacc_msg_with_resp_stats_t fcsMaxRead; + icp_hssacc_msg_with_resp_stats_t chanStatRead; + icp_hssacc_msg_with_resp_stats_t swErrRead; + icp_hssacc_msg_with_resp_stats_t swErrReset; +} icp_hssacc_service_stats_t; + +TDM_PRIVATE icp_hssacc_service_stats_t hssAccServStats; + +/* Data structure containing all registered callbacks + for all channels and ports */ +TDM_PRIVATE icp_hssacc_port_error_callback_t +hssAccPortErrorCb[ICP_HSSACC_MAX_NUM_PORTS][ICP_HSSACC_CHAN_TYPE_DELIMITER]; + +TDM_PRIVATE icp_hssacc_error_callback_t +hssAccErrorCb[ICP_HSSACC_CHAN_TYPE_DELIMITER]; + + +TDM_PRIVATE icp_user_context_t +hssAccPortErrorCtxt[ICP_HSSACC_MAX_NUM_PORTS][ICP_HSSACC_CHAN_TYPE_DELIMITER]; + +TDM_PRIVATE icp_user_context_t +hssAccErrorCtxt[ICP_HSSACC_CHAN_TYPE_DELIMITER]; + +TDM_PRIVATE uint32_t +hssAccStaticErrorBitmask = 0; + +TDM_PRIVATE icp_boolean_t voiceIntEnabled = ICP_FALSE; +TDM_PRIVATE icp_boolean_t hdlcIntEnabled = ICP_FALSE; + +/* + * ---------------------------------------------------------------------------- + * Function definitions + * ---------------------------------------------------------------------------- + */ +TDM_PRIVATE icp_status_t +HssAccTdmIOUnitErrorMhCbRegister (IxPiuMhCallback callback); + +void +HssAccTdmIOUnitErrorCallback(IxPiuMhPiuId piuId, IxPiuMhMessage message); + +void +HssAccPortErrorDummyClientCb (icp_user_context_t userContext, + icp_hssacc_port_error_t errorType); + +void +HssAccErrorDummyClientCb (icp_user_context_t userContext, + icp_hssacc_error_t errorType); + +TDM_PRIVATE icp_status_t +HssAccTdmIOErrorStatsShow (void); + +TDM_PRIVATE icp_status_t +HssAccSwErrorStatsShow (void); + +TDM_PRIVATE icp_status_t +HssAccSwErrorStatsReset (void); + +TDM_PRIVATE icp_status_t +HssAccChannelTdmIOErrorStatsShow(unsigned channelId); + +TDM_PRIVATE icp_status_t +HssAccChannelTdmIOErrorStatsReset(unsigned channelId); + +TDM_PRIVATE void +HssAccServiceStatsReset (void); + +TDM_PRIVATE void +HssAccServiceStatsShow (void); + +TDM_PRIVATE icp_status_t +HssAccServiceIntGenUpdate (void); + +/***************************************************************************** + * Abstract: + * Sets up the Dual coprocessor instructions in the TDM I/O Unit + * + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccTdmUnitDualInstSet (void) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + uint32_t appDualId = 0; + IxPiuDlAppDualInstruction appDualInstruction; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTdmUnitDualInstSet\n"); + +#if defined(__ep805xx) + appDualInstruction.copr0 = ICP_HSSACC_TDM_IO_UNIT_CPP_COPROC; + appDualInstruction.inst0 = ICP_HSSACC_TDM_IO_UNIT_CPP_RD_WORD_INST; + appDualInstruction.copr1 = ICP_HSSACC_TDM_IO_UNIT_SDC_COPROC; + appDualInstruction.inst1 = ICP_HSSACC_TDM_IO_UNIT_SDC_WR_HDLC_INST; + status = ixPiuDlAppDualSet ( + IX_PIUDL_PIUID_PIU0, + appDualId, + &appDualInstruction); + if ( ICP_STATUS_SUCCESS != status ) + { + ICP_HSSACC_REPORT_ERROR ("HssAccTdmUnitDualInstSet - " + "Failed to set Application " + "specific dual in TDM I/O Unit\n"); + + return ICP_STATUS_FATAL; + } + + appDualId++; + appDualInstruction.copr0 = ICP_HSSACC_TDM_IO_UNIT_SDC_COPROC; + appDualInstruction.inst0 = ICP_HSSACC_TDM_IO_UNIT_SDC_RD_HDLC_INST; + appDualInstruction.copr1 = ICP_HSSACC_TDM_IO_UNIT_CPP_COPROC; + appDualInstruction.inst1 = ICP_HSSACC_TDM_IO_UNIT_CPP_WR_WORD_INST; + + status = ixPiuDlAppDualSet ( + IX_PIUDL_PIUID_PIU0, + appDualId, + &appDualInstruction); + if ( ICP_STATUS_SUCCESS != status ) + { + ICP_HSSACC_REPORT_ERROR ("HssAccTdmUnitDualInstSet - " + "Failed to set Application " + "specific dual in TDM I/O Unit\n"); + + return ICP_STATUS_FATAL; + } + + + appDualId++; + appDualInstruction.copr0 = ICP_HSSACC_TDM_IO_UNIT_CPP_COPROC; + appDualInstruction.inst0 = ICP_HSSACC_TDM_IO_UNIT_CPP_RD_WORD_INST; + appDualInstruction.copr1 = ICP_HSSACC_TDM_IO_UNIT_SDC_COPROC; + appDualInstruction.inst1 = ICP_HSSACC_TDM_IO_UNIT_SDC_WR_VOICE_INST; + status = ixPiuDlAppDualSet ( + IX_PIUDL_PIUID_PIU0, + appDualId, + &appDualInstruction); + if ( ICP_STATUS_SUCCESS != status ) + { + ICP_HSSACC_REPORT_ERROR ("HssAccTdmUnitDualInstSet - " + "Failed to set Application " + "specific dual in TDM I/O Unit\n"); + + return ICP_STATUS_FATAL; + } + + appDualId++; + appDualInstruction.copr0 = ICP_HSSACC_TDM_IO_UNIT_SDC_COPROC; + appDualInstruction.inst0 = ICP_HSSACC_TDM_IO_UNIT_SDC_RD_VOICE_INST; + appDualInstruction.copr1 = ICP_HSSACC_TDM_IO_UNIT_CPP_COPROC; + appDualInstruction.inst1 = ICP_HSSACC_TDM_IO_UNIT_CPP_WR_WORD_INST; + + status = ixPiuDlAppDualSet ( + IX_PIUDL_PIUID_PIU0, + appDualId, + &appDualInstruction); + if ( ICP_STATUS_SUCCESS != status ) + { + ICP_HSSACC_REPORT_ERROR ("HssAccTdmUnitDualInstSet - " + "Failed to set Application " + "specific dual in TDM I/O Unit\n"); + + return ICP_STATUS_FATAL; + } + + +#endif + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTdmUnitDualInstSet\n"); + return status; +} + + + +/****************************************************************************** + * Abstract: + * Initializes the HSS I/O Access library for the HSS TDM I/O Unit. + * This function is responsible for initialising resources for use by + * this component. It should be called before any other HSS Access + * function is called. Default values for configuration items affecting + * all ports will not be set-up; it is up to the client to call the + * relevant port configuration functions before enabling the port. + * + * + *****************************************************************************/ +icp_status_t +icp_HssAccInit(void) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + unsigned index = 0; + IxPiuMhMessage message; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccInit\n"); + + /* Check if component is already initialised */ + if (ICP_TRUE == serviceInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccInit - " + "component has already been initialised\n"); + + status = ICP_STATUS_FAIL; + } + else /* component has never been initialised */ + { + /* Initialise the Service Mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_INIT()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccInit - " + "failed to initialise HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + } + + if (status == ICP_STATUS_SUCCESS) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_LOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccInit - " + "failed to lock HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + else + { + HssAccServiceStatsReset(); + + if(ICP_STATUS_SUCCESS == status) + { + if( (ICP_STATUS_SUCCESS == HssAccTdmUnitDualInstSet() ) && + (ICP_STATUS_SUCCESS == HssAccPortConfigInit()) && + (ICP_STATUS_SUCCESS == HssAccChannelConfigInit()) && + (ICP_STATUS_SUCCESS == HssAccQueuesInit() ) && + (ICP_STATUS_SUCCESS == HssAccTxDatapathInit()) && + (ICP_STATUS_SUCCESS == HssAccRxDatapathInit()) && + (ICP_STATUS_SUCCESS == HssAccTdmIOUnitErrorMhCbRegister + (HssAccTdmIOUnitErrorCallback) )) + { + HssAccVoiceBypassInit(); + + /* Reset all Error Callbacks for the component, + port Error Callbacks and service Errors callbacks */ + for (index =0; index < ICP_HSSACC_MAX_NUM_PORTS; index ++) + { + hssAccPortErrorCb[index][ICP_HSSACC_CHAN_TYPE_VOICE] = + HssAccPortErrorDummyClientCb; + hssAccPortErrorCtxt[index][ICP_HSSACC_CHAN_TYPE_VOICE] = + (icp_user_context_t)index; + hssAccPortErrorCb[index][ICP_HSSACC_CHAN_TYPE_HDLC] = + HssAccPortErrorDummyClientCb; + hssAccPortErrorCtxt[index][ICP_HSSACC_CHAN_TYPE_HDLC] = + (icp_user_context_t)index; + } + hssAccErrorCb[ICP_HSSACC_CHAN_TYPE_VOICE] = + HssAccErrorDummyClientCb; + hssAccErrorCb[ICP_HSSACC_CHAN_TYPE_HDLC] = + HssAccErrorDummyClientCb; + hssAccErrorCtxt[ICP_HSSACC_CHAN_TYPE_VOICE] = + (icp_user_context_t)ICP_HSSACC_CHAN_TYPE_VOICE; + hssAccErrorCtxt[ICP_HSSACC_CHAN_TYPE_HDLC] = + (icp_user_context_t)ICP_HSSACC_CHAN_TYPE_HDLC; + } + else + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccInit - one or more " + "modules failed to initialise\n"); + + status = HssAccPortConfigShutdown(); + status = HssAccChannelConfigShutdown(); + status = HssAccQueuesShutdown(); + status = HssAccTxDatapathShutdown(); + status = HssAccRxDatapathShutdown(); + /* This will deregister the Callback */ + status = HssAccTdmIOUnitErrorMhCbRegister(NULL); + status = ICP_STATUS_FAIL; + } + } + /* Last Step enable notifications with the QMgr + for the Receive Side */ + if (ICP_STATUS_SUCCESS == status) + { + if (ICP_STATUS_SUCCESS == HssAccRxQueuesNotificationEnable()) + { + ICP_HSSACC_TRACE_0 (ICP_HSSACC_DEBUG, + "HssAccInit - Service has " + "successfully initialised\n"); + hssAccStaticErrorBitmask = 0; + serviceInitialised = ICP_TRUE; + } + else + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccInit - " + "failed notification enable\n"); + status = HssAccVoiceBypassShutdown(); + status = HssAccPortConfigShutdown(); + status = HssAccChannelConfigShutdown(); + status = HssAccQueuesShutdown(); + status = HssAccTxDatapathShutdown(); + status = HssAccRxDatapathShutdown(); + /* This will deregister the Callback */ + status = HssAccTdmIOUnitErrorMhCbRegister(NULL); + status = ICP_STATUS_FAIL; + } + } + /* Set the Timer interval for the TDM I/O Unit to enable the Unit */ + if (ICP_STATUS_SUCCESS == status) + { + /* Construct the message to configure the queue */ + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_HSS_TIMER_CFG, + 0, + 0, + 0, + ICP_HSSACC_TDM_IO_UNIT_HSS_TIMER_INTERVAL, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + if (ICP_STATUS_SUCCESS == + HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HSS_TIMER_CFG_RESPONSE, + &(hssAccServStats.timerStat), + NULL) ) + { + ICP_HSSACC_TRACE_0 (ICP_HSSACC_DEBUG, + "HssAccInit - Timer Interval " + "Set\n"); + } + else + { + + ICP_HSSACC_REPORT_ERROR ("icp_HssAccInit - " + "failed Timer Interval Set\n"); + status = HssAccVoiceBypassShutdown(); + status = HssAccPortConfigShutdown(); + status = HssAccChannelConfigShutdown(); + status = HssAccQueuesShutdown(); + status = HssAccTxDatapathShutdown(); + status = HssAccRxDatapathShutdown(); + /* This will deregister the Callback */ + status = HssAccTdmIOUnitErrorMhCbRegister(NULL); + status = ICP_STATUS_FAIL; + } + } + + /* release the HssAcc Mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccInit - " + "failed to release HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + } + } + + + if (status != ICP_STATUS_SUCCESS) + { + /* report the error */ + ICP_HSSACC_REPORT_ERROR ("icp_HssAccInit - " + "failed to initialise HssAcc\n"); + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccInit\n"); + + return status; +} + + + + +/****************************************************************************** + * Abstract: + * Initialises the HDLC service specific part of the TDM I/O Unit: + * max frame size and whether to generate interrupts for HDLC data or not + * + *****************************************************************************/ +icp_status_t +icp_HssAccHdlcInit(unsigned maxRxFrameSize, + icp_boolean_t intGenerationEnable) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccHdlcInit\n"); + + /* Check if component is initialised */ + if (ICP_TRUE != serviceInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccHdlcInit - " + "component has not been initialised\n"); + status = ICP_STATUS_FAIL; + } + else + { + if (0 == maxRxFrameSize) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccHdlcInit - " + "Max Rx Frame Size cannot be 0\n"); + status = ICP_STATUS_INVALID_PARAM; + } + else + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_LOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccHdlcInit - " + "failed to lock HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + + else + { + if (ICP_TRUE == intGenerationEnable) + { + hdlcIntEnabled = ICP_TRUE; + status = HssAccServiceIntGenUpdate(); + } + HssAccRxDatapathHdlcInit(maxRxFrameSize); + + /* release the HssAcc Mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccHdlcInit - " + "failed to release HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + } + + } + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccHdlcInit\n"); + + return status; +} + + + + +/****************************************************************************** + * Abstract: + * Setup the Voice service on the TDM I/O unit. provides is with the + * max receive frame size and whether to generate interrupts for Voice + * traffic or not. + * + *****************************************************************************/ +icp_status_t +icp_HssAccVoiceInit(unsigned maxRxFrameSize, + icp_boolean_t intGenerationEnable) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccVoiceInit\n"); + + /* Check if component is already been initialised */ + if (ICP_TRUE != serviceInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccVoiceInit - " + "component has not been initialised\n"); + + status = ICP_STATUS_FAIL; + } + else + { + if (0 == maxRxFrameSize) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccVoiceInit - " + "Max Rx Frame Size cannot be 0\n"); + status = ICP_STATUS_INVALID_PARAM; + } + else + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_LOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccVoiceInit - " + "failed to lock HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + else + { + if (ICP_TRUE == intGenerationEnable) + { + voiceIntEnabled = ICP_TRUE; + status = HssAccServiceIntGenUpdate(); + } + HssAccRxDatapathVoiceInit(maxRxFrameSize); + + /* release the HssAcc Mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccVoiceInit - " + "failed to release HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + } + } + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccVoiceInit\n"); + + return status; +} + + + + +/****************************************************************************** + * Abstract: Shutdown the HSS I/O Access Library including all its sub-modules + * + *****************************************************************************/ +icp_status_t +icp_HssAccShutdown (void) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccShutdown\n"); + + /* If the service hasnt already been initialised then + we dont need to do anything */ + if (ICP_FALSE == serviceInitialised ) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccShutdown - " + "the service is not initialised\n"); + status = ICP_STATUS_FAIL; + } + if (ICP_STATUS_SUCCESS == status) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_LOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccShutdown - " + "failed to lock HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + else + { + voiceIntEnabled = ICP_FALSE; + hdlcIntEnabled = ICP_FALSE; + status = HssAccServiceIntGenUpdate(); + /* Shutdown Tx and Rx datapath sub-components + Tx: buffers in the tx queues will be sent before being freed + Rx: buffers in the rx queue will be freed and not sent to the client + */ + if (ICP_STATUS_SUCCESS == status) + { + status = HssAccPortConfigShutdown(); + } + if (ICP_STATUS_SUCCESS == status) + { + status = HssAccChannelConfigShutdown(); + } + if (ICP_STATUS_SUCCESS == status) + { + status = HssAccQueuesShutdown(); + } + if (ICP_STATUS_SUCCESS == status) + { + status = HssAccVoiceBypassShutdown(); + } + if (ICP_STATUS_SUCCESS == status) + { + status = HssAccTxDatapathShutdown (); + } + if (ICP_STATUS_SUCCESS == status) + { + status = HssAccRxDatapathShutdown (); + } + if (ICP_STATUS_SUCCESS == status) + { + /* This will deregister the Callback */ + status = HssAccTdmIOUnitErrorMhCbRegister(NULL); + } + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccShutdown - " + "failed to release HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + } + + /* Destroy HssAcc Mutex */ + if (ICP_STATUS_SUCCESS == status) + { + status = ICP_HSSACC_MUTEX_DESTROY(); + } + serviceInitialised = ICP_FALSE; + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccShutdown\n"); + return status; +} + + + +/****************************************************************************** + * Abstract: register data callbacks for a channel + * + *****************************************************************************/ +icp_status_t +icp_HssAccChannelCallbacksRegister ( + unsigned channelId, + icp_user_context_t userContext, + icp_hssacc_rx_callback_t rxCallback, + icp_hssacc_tx_done_callback_t txDoneCallback) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccChannelCallbacksRegister\n"); + + /* If the service hasnt been initialised, report an error */ + if (ICP_FALSE == serviceInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelCallbacksRegister - " + "Service has not been initialised\n"); + status = ICP_STATUS_FAIL; + } + if (ICP_STATUS_SUCCESS == status) + { + if (ICP_HSSACC_MAX_NUM_CHANNELS <= channelId) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelCallbacksRegister - " + "Channel Id is not valid\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } + if (ICP_STATUS_SUCCESS == status) + { + if ((NULL == rxCallback) || + (NULL == txDoneCallback)) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelCallbacksRegister - " + "Callback function pointers invalid\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } + + /* save the callbacks to an internal structure so that + the datapath can use them */ + if (ICP_STATUS_SUCCESS == status) + { + HssAccChannelRxCallbackRegister(channelId, rxCallback, userContext); + HssAccTxDatapathChanTxDoneCallbackRegister(channelId, + txDoneCallback, + userContext); + } + return status; + +} + + + + +/****************************************************************************** + * Abstract: register Error callbacks for a channel + *****************************************************************************/ +icp_status_t +icp_HssAccErrorCallbackRegister (icp_hssacc_channel_type_t channelType, + icp_user_context_t userContext, + icp_hssacc_error_callback_t errorCallback) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccErrorCallbackRegister\n"); + + /* If the service hasnt already been initialised then + we dont need to do anything */ + if (ICP_FALSE == serviceInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccErrorCallbackRegister - " + "Service has not been initialised\n"); + status = ICP_STATUS_FAIL; + } + if (ICP_STATUS_SUCCESS == status) + { + if ((NULL == errorCallback) || + (ICP_HSSACC_ENUM_INVALID (channelType, + ICP_HSSACC_CHAN_TYPE_DELIMITER))) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccErrorCallbackRegister - " + "one or more parameters invalid\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } + if (ICP_STATUS_SUCCESS == status) + { + hssAccErrorCb[channelType] = errorCallback; + hssAccErrorCtxt[channelType] = userContext; + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccErrorCallbackRegister\n"); + return status; +} + + + + + +/****************************************************************************** + * Abstract: + * Service the datapath, Rx and Tx + * + *****************************************************************************/ +icp_status_t +icp_HssAccDataPathService (icp_hssacc_channel_type_t channelType) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccDataPathService\n"); +#ifndef NDEBUG + if (ICP_FALSE == serviceInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccDataPathService - " + "service is not initialised\n"); + status = ICP_STATUS_FAIL; + } + + if (ICP_STATUS_SUCCESS == status) + { + if (ICP_HSSACC_ENUM_INVALID(channelType, ICP_HSSACC_CHAN_TYPE_DELIMITER)) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccDataPathService - " + "invalid Type to service\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } +#endif + if (ICP_STATUS_SUCCESS == status) + { + /* Service Tx Direction */ + status = HssAccTxDatapathService(channelType); + } + if (ICP_STATUS_SUCCESS == status) + { + /* Service Rx Direction */ + status = HssAccRxDatapathService(channelType); + } + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccDataPathService\n"); + return status; +} + + + + +/****************************************************************************** + * Abstract: + * Retrive all the buffers in the TDM I/O unit associated with the + * specified channel. will call Rx and Tx sub-modules. If channelId is + * equal to ICP_HSSACC_MAX_NUM_CHANNELS then retrieve buffers from the + * rx free queues for any service which has all unitialized channels. + * + *****************************************************************************/ +icp_status_t +icp_HssAccAllBuffersRetrieve (unsigned channelId, + IX_OSAL_MBUF * * buffer) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + icp_boolean_t mutexLocked = ICP_FALSE; + IX_OSAL_MBUF * pEndChainBuffer = NULL; + IX_OSAL_MBUF * pTmpBuffer = NULL; + IX_OSAL_MBUF * pTmpEndChainBuffer = NULL; + icp_hssacc_channel_state_t channelState = ICP_HSSACC_CHANNEL_UNINITIALISED; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccAllBuffersRetrieve\n"); + + if (ICP_TRUE != serviceInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccAllBuffersRetrieve - " + "service is not initialised\n"); + status = ICP_STATUS_FAIL; + } + if (ICP_STATUS_SUCCESS == status) + { + /* channelId == ICP_HSSACC_MAX_NUM_CHANNELS is allowed */ + if (ICP_HSSACC_MAX_NUM_CHANNELS < channelId) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccAllBuffersRetrieve - " + "Channel Id Invalid\n"); + status = ICP_STATUS_INVALID_PARAM; + } + if (NULL == buffer) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccAllBuffersRetrieve - " + "Buffer Pointer Invalid\n"); + status = ICP_STATUS_INVALID_PARAM; + } + + } + if (ICP_STATUS_SUCCESS == status) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_LOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccAllBuffersRetrieve - " + "failed to lock HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + else + { + mutexLocked = ICP_TRUE; + + if (ICP_HSSACC_MAX_NUM_CHANNELS != channelId) + { + /* Check that the channel is not enabled first */ + channelState = HssAccChannelConfigStateQuery(channelId); + + if (ICP_HSSACC_CHANNEL_ENABLED == channelState + || ICP_HSSACC_CHANNEL_DOWN_TRANSITION == channelState) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccAllBuffersRetrieve - " + "Channel is enabled\n"); + status = ICP_STATUS_RESOURCE; + } + } + } + } + + + if (status == ICP_STATUS_SUCCESS) + { + + *buffer = NULL; + + if (ICP_HSSACC_MAX_NUM_CHANNELS > channelId) + { + if (ICP_STATUS_SUCCESS == status) + { + /* Retrieve Tx Datapath Buffers Chain containing all leftover + TxDones and submitted Tx buffers that werent transmitted */ + status = HssAccTxDatapathChannelBuffersRetrieve( + channelId, + buffer, + &pTmpEndChainBuffer); + } + + if (status == ICP_STATUS_SUCCESS) + { + /* Retrieve Rx Datapath Buffer Chain */ + status = HssAccRxDatapathChanBufsRetrieve(channelId, + &pTmpBuffer, + &pEndChainBuffer); + } + } + else + { + /* Retrieve Rx Free Q Buffer Chain(s) */ + status = HssAccRxFreeQsBufsRetrieve(&pTmpBuffer, + &pEndChainBuffer); + } + } + + + if (status == ICP_STATUS_SUCCESS) + { + if (*buffer != NULL) + { + if (pTmpBuffer != NULL) + { + /* Link two chains together */ + IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(pTmpEndChainBuffer) = + pTmpBuffer; + } + } + else if (pTmpBuffer != NULL) + { + /* Rx datapath or free queue buffers were retrieved so + operation succeeded */ + *buffer = pTmpBuffer; + } + + /* Notify Channel Config of success */ + if (ICP_HSSACC_MAX_NUM_CHANNELS > channelId) + { + HssAccChannelConfigBuffersClearedNotify(channelId); + } + } + + + if (ICP_TRUE == mutexLocked) + { + /* release the HssAcc Mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccAllBuffersRetrieve - " + "failed to release HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + } + + + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccAllBuffersRetrieve\n"); + return status; +} + + + + +/****************************************************************************** + * Abstract: + * saves the provided callback for the specified port and service. + * + *****************************************************************************/ +icp_status_t +icp_HssAccPortErrorCallbackRegister ( + unsigned portId, + icp_hssacc_channel_type_t channelType, + icp_user_context_t userContext, + icp_hssacc_port_error_callback_t portErrorCallback) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccPortErrorCallbackRegister\n"); + + if (ICP_TRUE != serviceInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortErrorCallbackRegister - " + "service is not initialised\n"); + status = ICP_STATUS_FAIL; + } + if (ICP_STATUS_SUCCESS == status) + { + if ((ICP_HSSACC_MAX_NUM_PORTS <= portId) || + ICP_HSSACC_ENUM_INVALID (channelType, + ICP_HSSACC_CHAN_TYPE_DELIMITER)) + { + ICP_HSSACC_REPORT_ERROR_2 ("icp_HssAccPortErrorCallbackRegister - " + "Invalid parameter portId %u for " + "service %u\n", + portId, + channelType); + status = ICP_STATUS_INVALID_PARAM; + } + + if (NULL == portErrorCallback) + { + ICP_HSSACC_REPORT_ERROR_1 ("icp_HssAccPortErrorCallbackRegister - " + "Invalid callback provided 0x%08X\n", + (uint32_t)portErrorCallback); + status = ICP_STATUS_INVALID_PARAM; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + hssAccPortErrorCb[portId][channelType] = portErrorCallback; + hssAccPortErrorCtxt[portId][channelType] = userContext; + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccPortErrorCallbackRegister\n"); + return status; +} + + + +/***************************************************************************** + * Abstract: + * display all stats within this Access module and the TDM I/O unit. + * + *****************************************************************************/ +void +icp_HssAccStatsShow (void) +{ + unsigned channelId = 0; + icp_status_t status = ICP_STATUS_SUCCESS; + icp_hssacc_channel_type_t channelType = 0; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccStatsShow\n"); + + /* If the service hasnt already been initialised then we dont + need to do anything */ + if (ICP_TRUE == serviceInitialised) + { + HssAccPortConfigStatsShow(); + HssAccQueuesConfigStatsShow(); + HssAccChannelConfigStatsShow(); + HssAccTsAllocStatsShow(); + HssAccBypassStatsShow(); + + while ((ICP_STATUS_SUCCESS == status ) && + (channelId < ICP_HSSACC_MAX_NUM_CHANNELS)) + { + status = icp_HssAccChannelStatsShow(channelId); + channelId ++; + } + while ((ICP_STATUS_SUCCESS == status ) && + (channelType < ICP_HSSACC_CHAN_TYPE_DELIMITER)) + { + HssAccRxDatapathReplenishStatsShow(channelType); + channelType ++; + } + HssAccServiceStatsShow(); + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccStatsShow\n"); + +} + + + +/***************************************************************************** + * Abstract: + * Reset all internal stats. + * + *****************************************************************************/ +void +icp_HssAccStatsReset (void) +{ + unsigned channelId = 0; + icp_status_t status = ICP_STATUS_SUCCESS; + icp_hssacc_channel_type_t channelType = 0; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccStatsReset\n"); + + /* If the service hasnt already been initialised then we dont + need to do anything */ + if (ICP_TRUE == serviceInitialised) + { + HssAccPortConfigStatsReset(); + HssAccQueuesConfigStatsReset(); + HssAccChannelConfigStatsReset(); + HssAccTsAllocStatsReset(); + HssAccBypassStatsReset(); + + while ((ICP_STATUS_SUCCESS == status ) && + (channelId < ICP_HSSACC_MAX_NUM_CHANNELS)) + { + status = icp_HssAccChannelStatsReset(channelId); + channelId ++; + } + while ((ICP_STATUS_SUCCESS == status ) && + (channelType < ICP_HSSACC_CHAN_TYPE_DELIMITER)) + { + HssAccRxDatapathReplenishStatsReset(channelType); + channelType ++; + } + if (ICP_STATUS_SUCCESS == status) + { + /* Also reset here the Sw Error Stats from the TDM IO Unit */ + status = HssAccSwErrorStatsReset (); + } + HssAccServiceStatsReset(); + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccStatsReset\n"); + +} + + + +/***************************************************************************** + * Abstract: + * display all stats relating to the specified channel + * + *****************************************************************************/ +icp_status_t +icp_HssAccChannelStatsShow (unsigned channelId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccChannelStatsShow\n"); + + /* If the service hasnt already been initialised then we dont + need to do anything */ + if (ICP_FALSE == serviceInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelStatsShow - " + "Service has not been initialised\n"); + status = ICP_STATUS_FAIL; + } + if (ICP_STATUS_SUCCESS == status) + { + if (ICP_HSSACC_MAX_NUM_CHANNELS <= channelId) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelStatsShow - " + "channel number is invalid\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + HssAccChannelConfigStateShow (channelId); + HssAccTxDatapathChanStatsShow(channelId); + HssAccRxDatapathChanStatsShow(channelId); + + + if (ICP_STATUS_SUCCESS != HssAccChannelTdmIOErrorStatsShow(channelId)) + { + ICP_HSSACC_REPORT_ERROR("icp_HssAccChannelStatsShow - Error " + "retrieving Stats from TDM I/O Unit\n"); + status = ICP_STATUS_RESOURCE; + } + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccChannelStatsShow\n"); + return status; +} + + + +/***************************************************************************** + * Abstract: + * reset all the stats relating to the specified channel. + * + *****************************************************************************/ +icp_status_t +icp_HssAccChannelStatsReset (unsigned channelId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + icp_boolean_t mutexLocked = ICP_FALSE; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccChannelStatsReset\n"); + + /* If the service hasnt already been initialised then we + dont need to do anything */ + if (ICP_FALSE == serviceInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelStatsReset - " + "Service has not been initialised\n"); + status = ICP_STATUS_FAIL; + } + if (ICP_STATUS_SUCCESS == status) + { + if (ICP_HSSACC_MAX_NUM_CHANNELS <= channelId) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelStatsReset - " + "channel number is invalid\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } + if (ICP_STATUS_SUCCESS == status) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_LOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelStatsReset - " + "failed to lock HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + else + { + mutexLocked = ICP_TRUE; + } + } + if (ICP_STATUS_SUCCESS == status) + { + /* Reset the Datapath Stats for this channel */ + HssAccTxDatapathChanStatsReset(channelId); + HssAccRxDatapathChanStatsReset(channelId); + + if (ICP_STATUS_SUCCESS != HssAccChannelTdmIOErrorStatsReset(channelId)) + { + ICP_HSSACC_REPORT_ERROR("icp_HssAccChannelStatsShow - Error " + "retrieving Stats from TDM I/O Unit\n"); + status = ICP_STATUS_RESOURCE; + } + + } + if (mutexLocked == ICP_TRUE) + { + /* release the HssAcc Mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelStatsReset - " + "failed to release HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccChannelStatsReset\n"); + return status; +} + + + +/***************************************************************************** + * Abstract: + * show all the stats relating to the specified port, this includes + * all the channels associated to timeslots on this port. + * + *****************************************************************************/ +icp_status_t +icp_HssAccPortStatsShow (unsigned portId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + unsigned channelId = ICP_HSSACC_MAX_NUM_CHANNELS; + icp_hssacc_tdm_io_unit_channel_list_t listId = + ICP_HSSACC_TDM_IO_UNIT_LIST_TX_PRIMARY; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccPortStatsShow\n"); + + /* If the service hasnt already been initialised then we dont + need to do anything */ + if (ICP_FALSE == serviceInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortStatsShow - " + "Service has not been initialised\n"); + status = ICP_STATUS_FAIL; + } + /* Check Port Number */ + if (portId >= ICP_HSSACC_MAX_NUM_PORTS) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortStatsShow - " + "port number is invalid\n"); + status = ICP_STATUS_INVALID_PARAM; + } + if (ICP_STATUS_SUCCESS == status) + { + /* For each port, the channels to be processed are split + into 3 lists for the TDM I/O Unit. + Show the channels in each list */ + channelId = HssAccChannelListLastPortChannelGet (portId, + listId); + + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Channels on the Primary List for port %u:\n", + portId, + 0, 0, 0, 0, 0); + while (ICP_HSSACC_MAX_NUM_CHANNELS > channelId) + { + icp_HssAccChannelStatsShow(channelId); + channelId = HssAccChannelListPrevChannelOnListGet(channelId); + } + + } + /* Repeat for the Secondary 0 list */ + if (ICP_STATUS_SUCCESS == status) + { + listId = ICP_HSSACC_TDM_IO_UNIT_LIST_TX_SECONDARY_0; + channelId = HssAccChannelListLastPortChannelGet (portId, + listId); + + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Channels on the Secondary 0 List for port %u:\n", + portId, + 0, 0, 0, 0, 0); + while (ICP_HSSACC_MAX_NUM_CHANNELS > channelId) + { + icp_HssAccChannelStatsShow(channelId); + channelId = HssAccChannelListPrevChannelOnListGet(channelId); + } + + } + + /* Repeat for the Secondary 1 list */ + if (ICP_STATUS_SUCCESS == status) + { + listId = ICP_HSSACC_TDM_IO_UNIT_LIST_TX_SECONDARY_1; + channelId = HssAccChannelListLastPortChannelGet (portId, + listId); + + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Channels on the Secondary 1 List for port %u:\n", + portId, + 0, 0, 0, 0, 0); + while (ICP_HSSACC_MAX_NUM_CHANNELS > channelId) + { + icp_HssAccChannelStatsShow(channelId); + channelId = HssAccChannelListPrevChannelOnListGet(channelId); + } + + + /* Also print out here the Sw Error Stats from the TDM IO Unit */ + status = HssAccSwErrorStatsShow (); + } + + if (ICP_STATUS_SUCCESS == status) + { + + /* And overall stats for Abt, Aln, FCS and Max pkt size errors */ + status = HssAccTdmIOErrorStatsShow (); + } + + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccPortStatsShow\n"); + return status; + +} + + + + +/***************************************************************************** + * Abstract: + * reset all the stats relating to the specified port, this includes + * resting all the stats for channels on this port. + * + *****************************************************************************/ +icp_status_t +icp_HssAccPortStatsReset (unsigned portId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + unsigned channelId = ICP_HSSACC_MAX_NUM_CHANNELS; + icp_hssacc_tdm_io_unit_channel_list_t listId = + ICP_HSSACC_TDM_IO_UNIT_LIST_TX_PRIMARY; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccPortStatsReset\n"); + + + /* If the service hasnt already been initialised then we dont + need to do anything */ + if (ICP_FALSE == serviceInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortStatsReset - " + "Service has not been initialised\n"); + status = ICP_STATUS_FAIL; + } + + /* Check Port Number */ + if (portId >= ICP_HSSACC_MAX_NUM_PORTS) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortStatsReset - " + "port number is invalid\n"); + status = ICP_STATUS_INVALID_PARAM; + } + + + if (ICP_STATUS_SUCCESS == status) + { + /* For each port, the channels to be processed are split + into 3 lists for the TDM I/O Unit. + Show the channels in each list */ + channelId = HssAccChannelListLastPortChannelGet (portId, + listId); + + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Channels on the Primary List for port %u:\n", + portId, + 0, 0, 0, 0, 0); + while (ICP_HSSACC_MAX_NUM_CHANNELS > channelId) + { + icp_HssAccChannelStatsReset(channelId); + channelId = HssAccChannelListPrevChannelOnListGet(channelId); + } + + } + /* Repeat for the Secondary 0 list */ + if (ICP_STATUS_SUCCESS == status) + { + listId = ICP_HSSACC_TDM_IO_UNIT_LIST_TX_SECONDARY_0; + channelId = HssAccChannelListLastPortChannelGet (portId, + listId); + + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Channels on the Secondary 0 List for port %u:\n", + portId, + 0, 0, 0, 0, 0); + while (ICP_HSSACC_MAX_NUM_CHANNELS > channelId) + { + icp_HssAccChannelStatsReset(channelId); + channelId = HssAccChannelListPrevChannelOnListGet(channelId); + } + + } + + /* Repeat for the Secondary 1 list */ + if (ICP_STATUS_SUCCESS == status) + { + listId = ICP_HSSACC_TDM_IO_UNIT_LIST_TX_SECONDARY_1; + channelId = HssAccChannelListLastPortChannelGet (portId, + listId); + + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Channels on the Secondary 1 List for port %u:\n", + portId, + 0, 0, 0, 0, 0); + while (ICP_HSSACC_MAX_NUM_CHANNELS > channelId) + { + icp_HssAccChannelStatsReset(channelId); + channelId = HssAccChannelListPrevChannelOnListGet(channelId); + } + } + + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccPortStatsReset\n"); + return status; + +} + + + +/***************************************************************************** + * Abstract: + * return the number of channels supported by the TDM I/O unit. + * + *****************************************************************************/ +unsigned +icp_HssAccNumSupportedChannelsGet ( void ) +{ + return ICP_HSSACC_MAX_NUM_CHANNELS; +} + + + + +/***************************************************************************** + * Abstract: + * register the HSS I/O Access callback with the Message Handler. + * + *****************************************************************************/ +icp_status_t +HssAccTdmIOUnitErrorMhCbRegister (IxPiuMhCallback callback) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTdmIOUnitErrorMhCbRegister\n"); + if (ICP_STATUS_SUCCESS != + ixPiuMhUnsolicitedCallbackRegister ( + IX_PIUMH_PIUID_PIU0, + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_STATUS, + callback)) + { + + ICP_HSSACC_REPORT_ERROR ("HssAccTdmIOUnitErrorMhCbRegister - " + "Could not register callback\n"); + status = ICP_STATUS_FAIL; + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTdmIOUnitErrorMhCbRegister\n"); + + return status; +} + + +/***************************************************************************** + * Abstract: + * this is the callback that the Message Handler will call when it + * receives an error message from the TDM I/O unit. + * + *****************************************************************************/ +void +HssAccTdmIOUnitErrorCallback(IxPiuMhPiuId piuId, IxPiuMhMessage message) +{ + uint32_t localBitmask = 0; + uint32_t portBitmask = 0; + unsigned portId = ICP_HSSACC_MAX_NUM_PORTS; + icp_hssacc_port_error_t portError = ICP_HSSACC_PORT_ERROR_TX_LOS; + uint32_t errorOffset = 0; + icp_hssacc_error_t errorType = ICP_HSSACC_ERROR_DELIMITER; + icp_boolean_t bothServices = ICP_FALSE; + icp_hssacc_channel_type_t service = ICP_HSSACC_CHAN_TYPE_DELIMITER; + icp_status_t status = ICP_STATUS_SUCCESS; + ICP_HSSACC_TRACE_2 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTdmIOUnitErrorCallback 0x%08X 0x%08X\n", + message.data[0], + message.data[1]); + + + if ((IX_PIUMH_PIUID_PIU0 != piuId) || + ((message.data[0] >> ICP_HSSACC_TDM_IO_UNIT_BYTE0_OFFSET) != + (ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_STATUS))) + { + ICP_HSSACC_REPORT_ERROR ("HssAccTdmIOUnitErrorCallback - " + "Invalid parameters\n"); + } + else + { + /* First check if we have any port errors */ + localBitmask = + message.data[0] & ICP_HSSACC_TDM_IO_UNIT_ERR_ALL_PORT_MASK; + if (0 != localBitmask) + { + /* determine which port error triggered this message */ + portId = 0; + while (0 != localBitmask) + { + portBitmask = localBitmask & + ICP_HSSACC_TDM_IO_UNIT_ERR_SGLE_PORT_MASK; + if (0 != portBitmask) + { + while ((portBitmask & 1) != 1) + { + portBitmask >>= 1; + portError ++; + } + ICP_HSSACC_TRACE_1 (ICP_HSSACC_DEBUG, + "HssAccTdmIOUnitErrorCallback - " + "Error Reported on port %u\n", + portId); + /* use the client callbacks */ + hssAccPortErrorCb[portId][ICP_HSSACC_CHAN_TYPE_HDLC]( + hssAccPortErrorCtxt[portId][ICP_HSSACC_CHAN_TYPE_HDLC], + portError); + + hssAccPortErrorCb[portId][ICP_HSSACC_CHAN_TYPE_VOICE]( + hssAccPortErrorCtxt[portId][ICP_HSSACC_CHAN_TYPE_VOICE], + portError); + } + localBitmask >>= ICP_HSSACC_TDM_IO_UNIT_NEXT_PORT_SHIFT; + portId ++; + } + } + + + /* now check for a software error triggering this message; + compare the bitmask sent with our static one */ + localBitmask = message.data[1]; + if ((0 != localBitmask) && + (hssAccStaticErrorBitmask != localBitmask)) + { + while ((localBitmask & 1) == (hssAccStaticErrorBitmask & 1)) + { + localBitmask >>= 1; + hssAccStaticErrorBitmask >>= 1; + errorOffset ++; + } + switch (errorOffset) + { + case ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_MSG_OUT_FIFO_H: + case ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_MSG_OUT_FIFO_L: + errorType = ICP_HSSACC_ERROR_MESSAGE_FIFO_OVERFLOW; + bothServices = ICP_TRUE; + break; + case ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_RX_V_FREE_UNDERF: + errorType = ICP_HSSACC_ERROR_RX_FREE_UNDERFLOW; + service = ICP_HSSACC_CHAN_TYPE_VOICE; + break; + case ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_RX_H_FREE_UNDERF: + errorType = ICP_HSSACC_ERROR_RX_FREE_UNDERFLOW; + service = ICP_HSSACC_CHAN_TYPE_HDLC; + break; + case ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_RX_V_INT_FIFO_OVERF: + case ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_RX_V_Q_OVERF: + errorType = ICP_HSSACC_ERROR_RX_OVERFLOW; + service = ICP_HSSACC_CHAN_TYPE_VOICE; + break; + case ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_RX_H_INT_FIFO_OVERF: + case ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_RX_H_Q_OVERF: + errorType = ICP_HSSACC_ERROR_RX_OVERFLOW; + service = ICP_HSSACC_CHAN_TYPE_HDLC; + break; + default: + ICP_HSSACC_REPORT_ERROR ("HssAccTdmIOUnitErrorCallback - " + "Unknown Software Error " + "from TDM I/O Unit\n"); + status = ICP_STATUS_FAIL; + break; + + } + if (ICP_STATUS_SUCCESS == status) + { + ICP_HSSACC_TRACE_0 (ICP_HSSACC_DEBUG, + "HssAccTdmIOUnitErrorCallback - " + "Firmware Error Reported\n"); + if (ICP_TRUE == bothServices) + { + hssAccErrorCb[ICP_HSSACC_CHAN_TYPE_HDLC]( + hssAccErrorCtxt[ICP_HSSACC_CHAN_TYPE_HDLC], + errorType); + hssAccErrorCb[ICP_HSSACC_CHAN_TYPE_VOICE]( + hssAccErrorCtxt[ICP_HSSACC_CHAN_TYPE_VOICE], + errorType); + } + else + { + hssAccErrorCb[service](hssAccErrorCtxt[service], + errorType); + } + hssAccStaticErrorBitmask = message.data[1]; + } + } + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTdmIOUnitErrorCallback\n"); +} + + + +/***************************************************************************** + * Abstract: + * this is a dummy callback used in the event of the client never + * registering its own for a port error + * + *****************************************************************************/ +void HssAccPortErrorDummyClientCb (icp_user_context_t userContext, + icp_hssacc_port_error_t errorType) +{ + ICP_HSSACC_TRACE_2 (ICP_HSSACC_DEBUG, + "HssAccPortErrorDummyClientCb - received " + "notification of Port error %u for service %u\n", + errorType, + (unsigned)userContext); +} + + + +/***************************************************************************** + * Abstract: + * this is a dummy callback used in the event of the client never + * registering its own for a TDM I/O Unit firmware error. + * + *****************************************************************************/ +void HssAccErrorDummyClientCb (icp_user_context_t userContext, + icp_hssacc_error_t errorType) +{ + ICP_HSSACC_TRACE_2 (ICP_HSSACC_DEBUG, + "HssAccErrorDummyClientCb - " + "received notification of error %u for service %u\n", + errorType, + (unsigned)userContext); +} + + + + + + + +/***************************************************************************** + * Abstract: + * display all stats provided by the TDM I/O unit relating to detected + * firmware errors. + * + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccSwErrorStatsShow (void) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IxPiuMhMessage message; + unsigned statValue = 0; + icp_boolean_t mutexLocked = ICP_FALSE; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccSwErrorStatsShow\n"); + + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_LOCK()) + { + ICP_HSSACC_REPORT_ERROR ("HssAccSwErrorStatsShow - " + "failed to lock HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + else + { + mutexLocked = ICP_TRUE; + } + + if (ICP_STATUS_SUCCESS == status) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "TDM IO Unit Firmware Error Stats:\n", + 0, 0, 0, 0, 0, 0); + + /* Retrieve each Sw Error Count and print it */ + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ, + ICP_HSSACC_TDM_IO_UNIT_RX_VOICE_Q_OVERFLOW, 0, 0, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ_RESPONSE, + &(hssAccServStats.swErrRead), + &statValue); + } + + if ( ICP_STATUS_SUCCESS == status) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Receive Voice Q Overflows: %u\n", + statValue, + 0, 0, 0, 0, 0); + + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ, + ICP_HSSACC_TDM_IO_UNIT_RX_HDLC_Q_OVERFLOW, 0, 0, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ_RESPONSE, + &(hssAccServStats.swErrRead), + &statValue); + } + + if ( ICP_STATUS_SUCCESS == status) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Receive HDLC Q Overflows: %u\n", + statValue, + 0, 0, 0, 0, 0); + + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ, + ICP_HSSACC_TDM_IO_UNIT_RX_VOICE_FIFO_OVERFLOW, 0, 0, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ_RESPONSE, + &(hssAccServStats.swErrRead), + &statValue); + } + + if ( ICP_STATUS_SUCCESS == status) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Receive Voice FIFO Overflows: %u\n", + statValue, + 0, 0, 0, 0, 0); + + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ, + ICP_HSSACC_TDM_IO_UNIT_RX_HDLC_FIFO_OVERFLOW, 0, 0, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ_RESPONSE, + &(hssAccServStats.swErrRead), + &statValue); + } + + if ( ICP_STATUS_SUCCESS == status) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Receive HDLC FIFO Overflows: %u\n", + statValue, + 0, 0, 0, 0, 0); + + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ, + ICP_HSSACC_TDM_IO_UNIT_RX_VOICE_FREE_Q_UNDERFLOW, 0, 0, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ_RESPONSE, + &(hssAccServStats.swErrRead), + &statValue); + } + + if ( ICP_STATUS_SUCCESS == status) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Receive Voice Free Q Underflows: %u\n", + statValue, + 0, 0, 0, 0, 0); + + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ, + ICP_HSSACC_TDM_IO_UNIT_RX_HDLC_FREE_Q_UNDERFLOW, 0, 0, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ_RESPONSE, + &(hssAccServStats.swErrRead), + &statValue); + } + + if ( ICP_STATUS_SUCCESS == status) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Receive Voice HDLC Free Underflows: %u\n", + statValue, + 0, 0, 0, 0, 0); + + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ, + ICP_HSSACC_TDM_IO_UNIT_MSG_OUT_FIFO_LP_OVERFLOW, 0, 0, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ_RESPONSE, + &(hssAccServStats.swErrRead), + &statValue); + } + + if ( ICP_STATUS_SUCCESS == status) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Msg Out FIFO Low Priority Overflows: %u\n", + statValue, + 0, 0, 0, 0, 0); + + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ, + ICP_HSSACC_TDM_IO_UNIT_MSG_OUT_FIFO_HP_OVERFLOW, 0, 0, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ_RESPONSE, + &(hssAccServStats.swErrRead), + &statValue); + } + + if ( ICP_STATUS_SUCCESS == status) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Msg Out FIFO High Priority Overflows: %u\n", + statValue, + 0, 0, 0, 0, 0); + + } + + if (ICP_TRUE == mutexLocked) + { + /* release the HssAcc Mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("HssAccSwErrorStatsShow - " + "failed to release HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccSwErrorStatsShow\n"); + return status; +} + + +/***************************************************************************** + * Abstract: + * reset the firmware error stats in the TDM I/O Unit. + * + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccSwErrorStatsReset (void) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IxPiuMhMessage message; + uint8_t resetFlag = 1; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccSwErrorStatsReset\n"); + + /* Retrieve each Sw Error Count and print it */ + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ, + ICP_HSSACC_TDM_IO_UNIT_RX_VOICE_Q_OVERFLOW, + resetFlag, 0, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ_RESPONSE, + &(hssAccServStats.swErrReset), + NULL); + + if ( ICP_STATUS_SUCCESS == status) + { + + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ, + ICP_HSSACC_TDM_IO_UNIT_RX_HDLC_Q_OVERFLOW, + resetFlag, 0, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ_RESPONSE, + &(hssAccServStats.swErrReset), + NULL); + } + + if ( ICP_STATUS_SUCCESS == status) + { + + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ, + ICP_HSSACC_TDM_IO_UNIT_RX_VOICE_FIFO_OVERFLOW, + resetFlag, 0, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ_RESPONSE, + &(hssAccServStats.swErrReset), + NULL); + } + + if ( ICP_STATUS_SUCCESS == status) + { + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ, + ICP_HSSACC_TDM_IO_UNIT_RX_HDLC_FIFO_OVERFLOW, + resetFlag, 0, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ_RESPONSE, + &(hssAccServStats.swErrReset), + NULL); + } + + if ( ICP_STATUS_SUCCESS == status) + { + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ, + ICP_HSSACC_TDM_IO_UNIT_RX_VOICE_FREE_Q_UNDERFLOW, + resetFlag, 0, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ_RESPONSE, + &(hssAccServStats.swErrReset), + NULL); + } + + if ( ICP_STATUS_SUCCESS == status) + { + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ, + ICP_HSSACC_TDM_IO_UNIT_RX_HDLC_FREE_Q_UNDERFLOW, + resetFlag, 0, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ_RESPONSE, + &(hssAccServStats.swErrReset), + NULL); + } + + if ( ICP_STATUS_SUCCESS == status) + { + + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ, + ICP_HSSACC_TDM_IO_UNIT_MSG_OUT_FIFO_LP_OVERFLOW, + resetFlag, 0, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ_RESPONSE, + &(hssAccServStats.swErrReset), + NULL); + } + + if ( ICP_STATUS_SUCCESS == status) + { + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ, + ICP_HSSACC_TDM_IO_UNIT_MSG_OUT_FIFO_HP_OVERFLOW, + resetFlag, 0, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ_RESPONSE, + &(hssAccServStats.swErrReset), + NULL); + } + + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccSwErrorStatsReset\n"); + return status; +} + +/***************************************************************************** + * Abstract: + * display all error stats collected by the TDM I/O unit. + * + *****************************************************************************/ +icp_status_t +HssAccTdmIOErrorStatsShow (void) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IxPiuMhMessage message; + unsigned statValue = 0; + icp_boolean_t mutexLocked = ICP_FALSE; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTdmIOErrorStatsShow\n"); + + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_LOCK()) + { + ICP_HSSACC_REPORT_ERROR ("HssAccTdmIOErrorStatsShow - " + "failed to lock HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + else + { + mutexLocked = ICP_TRUE; + } + + + if ( ICP_STATUS_SUCCESS == status) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "TDM IO Unit Global Error Stats:\n", + 0, 0, 0, 0, 0, 0); + + /* Retrieve each hardware error Count and print it */ + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_ABT_ALN_ERR_READ, + 0, 0, 0, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_ABT_ALN_ERR_READ_RESPONSE, + &(hssAccServStats.abtAlnRead), + &statValue); + } + + if ( ICP_STATUS_SUCCESS == status) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Alignment Errors %u, Abort Errors %u\n", + statValue & ICP_HSSACC_TDM_IO_UNIT_SHORT1_MASK, + (statValue & ICP_HSSACC_TDM_IO_UNIT_SHORT0_MASK) >> + ICP_HSSACC_TDM_IO_UNIT_SHORT0_OFFSET, + 0, 0, 0, 0); + + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_FCS_MAX_ERR_READ, + 0, 0, 0, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = + HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_FCS_MAX_ERR_READ_RESPONSE, + &(hssAccServStats.fcsMaxRead), + &statValue); + } + + if ( ICP_STATUS_SUCCESS == status) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "FCS Errors %u, Max Frame Size Errors %u\n", + statValue & ICP_HSSACC_TDM_IO_UNIT_SHORT1_MASK, + (statValue & ICP_HSSACC_TDM_IO_UNIT_SHORT0_MASK) >> + ICP_HSSACC_TDM_IO_UNIT_SHORT0_OFFSET, + 0, 0, 0, 0); + } + + if (ICP_TRUE == mutexLocked) + { + /* release the HssAcc Mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("HssAccTdmIOErrorStatsShow - " + "failed to release HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTdmIOErrorStatsShow\n"); + return status; +} + + + + + +/***************************************************************************** + * Abstract: + * display all error stats collected by the TDM I/O Unit for the specified + * channel. + * + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccChannelTdmIOErrorStatsShow(unsigned channelId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IxPiuMhMessage message; + unsigned statValue = 0; + icp_boolean_t mutexLocked = ICP_FALSE; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelTdmIOErrorStatsShow\n"); + + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_LOCK()) + { + ICP_HSSACC_REPORT_ERROR ("HssAccChannelTdmIOErrorStatsShow - " + "failed to lock HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + else + { + mutexLocked = ICP_TRUE; + } + + if ( ICP_STATUS_SUCCESS == status) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "TDM IO Unit channel Error Stats for channel %u:\n", + channelId, 0, 0, 0, 0, 0); + + + /* Retrieve Stats from the TDM I/O Unit */ + + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_STATS_READ, + channelId, 0, + ICP_HSSACC_TDM_IO_UNIT_CHAN_STAT_ABT_ALN, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_STATS_READ_RESPONSE, + &(hssAccServStats.chanStatRead), + &statValue); + } + + if ( ICP_STATUS_SUCCESS == status) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Abort or Alignment: %u\n", + statValue, + 0, 0, 0, 0, 0); + + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_STATS_READ, + channelId, 0, + ICP_HSSACC_TDM_IO_UNIT_CHAN_STAT_FCS, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_STATS_READ_RESPONSE, + &(hssAccServStats.chanStatRead), + &statValue); + } + + if ( ICP_STATUS_SUCCESS == status) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "FCS: %u\n", + statValue, + 0, 0, 0, 0, 0); + + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_STATS_READ, + channelId, 0, + ICP_HSSACC_TDM_IO_UNIT_CHAN_STAT_MAX_SIZE, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_STATS_READ_RESPONSE, + &(hssAccServStats.chanStatRead), + &statValue); + + } + + if ( ICP_STATUS_SUCCESS == status) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Max Size: %u\n", + statValue, + 0, 0, 0, 0, 0); + + +#ifndef NDEBUG + /* Retrieve Packet Rx and Tx stats */ + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_STATS_READ, + channelId, 0, + ICP_HSSACC_TDM_IO_UNIT_CHAN_STAT_TX_PKTS, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_STATS_READ_RESPONSE, + &(hssAccServStats.chanStatRead), + &statValue); + } + + if ( ICP_STATUS_SUCCESS == status) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Transmitted Packets: %u\n", + statValue, + 0, 0, 0, 0, 0); + + + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_STATS_READ, + channelId, 0, + ICP_HSSACC_TDM_IO_UNIT_CHAN_STAT_RX_PKTS, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_STATS_READ_RESPONSE, + &(hssAccServStats.chanStatRead), + &statValue); + } + if ( ICP_STATUS_SUCCESS == status) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Received Packets: %u\n", + statValue, + 0, 0, 0, 0, 0); + + +#endif + } + + if (ICP_TRUE == mutexLocked) + { + /* release the HssAcc Mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("HssAccChannelTdmIOErrorStatsShow - " + "failed to release HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelTdmIOErrorStatsShow\n"); + return status; +} + +/***************************************************************************** + * Abstract: + * get the TDM I/O unit to reset all error stats for the specified channel. + * + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccChannelTdmIOErrorStatsReset(unsigned channelId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IxPiuMhMessage message; + uint8_t resetFlag = 1; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelTdmIOErrorStatsReset\n"); + + + + /* Retrieve Stats from the TDM I/O Unit */ + + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_STATS_READ, + channelId, resetFlag, + ICP_HSSACC_TDM_IO_UNIT_CHAN_STAT_ABT_ALN, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_STATS_READ_RESPONSE, + &(hssAccServStats.chanStatRead), + NULL); + + if ( ICP_STATUS_SUCCESS == status) + { + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_STATS_READ, + channelId, resetFlag, + ICP_HSSACC_TDM_IO_UNIT_CHAN_STAT_FCS, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_STATS_READ_RESPONSE, + &(hssAccServStats.chanStatRead), + NULL); + } + + if ( ICP_STATUS_SUCCESS == status) + { + + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_STATS_READ, + channelId, resetFlag, + ICP_HSSACC_TDM_IO_UNIT_CHAN_STAT_MAX_SIZE, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_STATS_READ_RESPONSE, + &(hssAccServStats.chanStatRead), + NULL); + + } + + if ( ICP_STATUS_SUCCESS == status) + { + +#ifndef NDEBUG + /* Retrieve Packet Rx and Tx stats */ + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_STATS_READ, + channelId, resetFlag, + ICP_HSSACC_TDM_IO_UNIT_CHAN_STAT_TX_PKTS, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_STATS_READ_RESPONSE, + &(hssAccServStats.chanStatRead), + NULL); + } + + if ( ICP_STATUS_SUCCESS == status) + { + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_STATS_READ, + channelId, resetFlag, + ICP_HSSACC_TDM_IO_UNIT_CHAN_STAT_RX_PKTS, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_STATS_READ_RESPONSE, + &(hssAccServStats.chanStatRead), + NULL); + +#endif + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelTdmIOErrorStatsReset\n"); + return status; +} + + + +/***************************************************************************** + * Abstract: + * reset all internal stats for this sub-module only. + * + *****************************************************************************/ +TDM_PRIVATE void +HssAccServiceStatsReset (void) +{ + memset (&hssAccServStats, 0, sizeof(icp_hssacc_service_stats_t)); +} + + + + +/***************************************************************************** + * Abstract: + * display all internal stats for this sub-module. + * + *****************************************************************************/ +TDM_PRIVATE void +HssAccServiceStatsShow (void) +{ + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccServiceStatsShow\n"); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nTDM Service Statistics:\n" + "Service Timer Config Messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccServStats.timerStat); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nInterrupt Generation Configuration Messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccServStats.intStat); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nAbort and Alignment Error Stats Read Messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccServStats.abtAlnRead); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nFCS and Max Size Error Stats Read Messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccServStats.fcsMaxRead); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nChannel Stats Read Messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccServStats.chanStatRead); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nTDM IO Unit Firmware Error Stats Read Messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccServStats.swErrRead); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nTDM IO Unit Firmware Error Stats Reset Messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccServStats.swErrReset); + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccServiceStatsShow\n"); + +} + + + +/***************************************************************************** + * Abstract: + * Updates the configuration of the int generation on the TDM I/O Unit + * + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccServiceIntGenUpdate (void) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + uint8_t voiceTxEnabled = ICP_HSSACC_TDM_IO_UNIT_HSS_INT_DISABLED; + uint8_t voiceRxEnabled = ICP_HSSACC_TDM_IO_UNIT_HSS_INT_DISABLED; + uint8_t hdlcTxEnabled = ICP_HSSACC_TDM_IO_UNIT_HSS_INT_DISABLED; + uint8_t hdlcRxEnabled = ICP_HSSACC_TDM_IO_UNIT_HSS_INT_DISABLED; + IxPiuMhMessage message; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccServiceIntGenUpdate\n"); + + if (ICP_TRUE == voiceIntEnabled) + { + voiceTxEnabled = ICP_HSSACC_TDM_IO_UNIT_HSS_INT_ENABLED; + voiceRxEnabled = ICP_HSSACC_TDM_IO_UNIT_HSS_INT_ENABLED; + } + + if (ICP_TRUE == hdlcIntEnabled) + { + hdlcTxEnabled = ICP_HSSACC_TDM_IO_UNIT_HSS_INT_ENABLED; + hdlcRxEnabled = ICP_HSSACC_TDM_IO_UNIT_HSS_INT_ENABLED; + } + + /* Construct the message to configure the interrupt generation */ + HssAccComTdmIOUnitCmd8byteMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_HSS_INT_CFG, + 0, 0, 0, + hdlcTxEnabled, hdlcRxEnabled, + voiceTxEnabled, voiceRxEnabled, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HSS_INT_CFG_RESPONSE, + &(hssAccServStats.intStat), + NULL); + + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR ("HssAccServiceIntGenUpdate - " + "Failed to update Interrupt Gen " + "Config in TDM I/O Unit\n"); + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccServiceIntGenUpdate\n"); + return status; +} diff --git a/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_symbols.c b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_symbols.c new file mode 100644 index 0000000..53e7855 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_symbols.c @@ -0,0 +1,121 @@ +/****************************************************************************** + * @file icp_hssacc_symbols.c + * + * @description Contents of this file provide the list of symbols to be + * exported by this module + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + *****************************************************************************/ + + +#ifdef __linux + + +#include <linux/module.h> +#include "icp_hssacc.h" + +EXPORT_SYMBOL(icp_HssAccInit); +EXPORT_SYMBOL(icp_HssAccHdlcInit); +EXPORT_SYMBOL(icp_HssAccVoiceInit); +EXPORT_SYMBOL(icp_HssAccShutdown); +EXPORT_SYMBOL(icp_HssAccNumSupportedPortsGet); +EXPORT_SYMBOL(icp_HssAccPortConfig); +EXPORT_SYMBOL(icp_HssAccPortUp); +EXPORT_SYMBOL(icp_HssAccPortDown); +EXPORT_SYMBOL(icp_HssAccNumSupportedChannelsGet); +EXPORT_SYMBOL(icp_HssAccChannelAllocate); +EXPORT_SYMBOL(icp_HssAccChannelConfigure); +EXPORT_SYMBOL(icp_HssAccChannelHdlcServiceConfigure); +EXPORT_SYMBOL(icp_HssAccChannelVoiceServiceConfigure); +EXPORT_SYMBOL(icp_HssAccChannelCallbacksRegister); +EXPORT_SYMBOL(icp_HssAccErrorCallbackRegister); +EXPORT_SYMBOL(icp_HssAccPortErrorCallbackRegister); +EXPORT_SYMBOL(icp_HssAccNumSupportedGCTsGet); +EXPORT_SYMBOL(icp_HssAccNumSupportedVoiceBypassesGet); +EXPORT_SYMBOL(icp_HssAccVoiceBypassGctDownload); +EXPORT_SYMBOL(icp_HssAccVoiceBypassEnable); +EXPORT_SYMBOL(icp_HssAccVoiceBypassDisable); +EXPORT_SYMBOL(icp_HssAccChannelUp); +EXPORT_SYMBOL(icp_HssAccChannelDown); +EXPORT_SYMBOL(icp_HssAccChannelDelete); +EXPORT_SYMBOL(icp_HssAccTransmit); +EXPORT_SYMBOL(icp_HssAccReceive); +EXPORT_SYMBOL(icp_HssAccRxFreeReplenish); +EXPORT_SYMBOL(icp_HssAccTxDoneRetrieve); +EXPORT_SYMBOL(icp_HssAccAllBuffersRetrieve); +EXPORT_SYMBOL(icp_HssAccDataPathService); +EXPORT_SYMBOL(icp_HssAccChannelStatsShow); +EXPORT_SYMBOL(icp_HssAccChannelStatsReset); +EXPORT_SYMBOL(icp_HssAccPortStatsShow); +EXPORT_SYMBOL(icp_HssAccPortStatsReset); +EXPORT_SYMBOL(icp_HssAccStatsShow); +EXPORT_SYMBOL(icp_HssAccStatsReset); + +#include "icp_hssacc_queues_config.h" + +// hacky +EXPORT_SYMBOL(HssAccQueueIdGet); + +#endif diff --git a/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_timeslot_allocation.c b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_timeslot_allocation.c new file mode 100644 index 0000000..80a9d72 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_timeslot_allocation.c @@ -0,0 +1,665 @@ +/****************************************************************************** + * + * @file icp_hssacc_timeslot_allocation.c + * + * @description Content of this file is the implementation of the Timeslot + * allocation and de-allocation functionality used for channel Allocation + * and deletion. This platform specific implementation compliments the + * file icp_hssacc_common_timeslot_allocation.c containing the common + * sections of this module. + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + *****************************************************************************/ +#include "IxOsal.h" + +#include "icp_hssacc.h" +#include "icp_hssacc_common.h" +#include "icp_hssacc_trace.h" +#include "icp_hssacc_timeslot_allocation.h" +#include "icp_hssacc_port_config.h" +#include "icp_hssacc_channel_config.h" +#include "icp_hssacc_address_translate.h" + + + +#define ICP_HSSACC_OFFSET_HALF_WD_PER_LINE (16) +#define ICP_HSSACC_CHAN_OFFS_PER_WD (2) + +/* This Macro operates an endianness swap on half-words for + addressing purposes within the TDM I/O Unit channel offset + table */ +#define ICP_HSSACC_CHAN_OFFS_LOC_IN_TBL(chan) ((chan)^1) + +/* Stats */ +typedef struct icp_hssacc_ts_alloc_stats_s +{ + icp_hssacc_msg_with_resp_stats_t hssPortProvTableLoad; + icp_hssacc_msg_with_resp_stats_t chanOffsetTableLoad; + icp_hssacc_msg_with_resp_stats_t chanOffsetTableRead; + icp_hssacc_msg_with_resp_stats_t hssPortProvTableSwap; +} icp_hssacc_ts_alloc_stats_t; + + +TDM_PRIVATE icp_hssacc_ts_alloc_stats_t hssAccTsAllocStats; + +TDM_PRIVATE icp_boolean_t hssAccTsAllocated [ICP_HSSACC_MAX_NUM_PORTS]; + + +/** + * Function Definition: HssAccTsAllocSwapStatsGet + */ +icp_hssacc_msg_with_resp_stats_t * HssAccTsAllocSwapStatsGet(void) +{ + return &(hssAccTsAllocStats.hssPortProvTableSwap); +} + +/** + * Function Definition: HssAccTsAllocOffsetTableReadStatsGet + */ +icp_hssacc_msg_with_resp_stats_t * HssAccTsAllocOffsetTableReadStatsGet(void) +{ + return &(hssAccTsAllocStats.chanOffsetTableRead); +} + +/** + * Function Definition: HssAccTsAllocPlatformInit + */ +icp_status_t HssAccTsAllocPlatformInit (void) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + unsigned portIndex = 0; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTsAllocPlatformInit\n"); + + for (portIndex = 0; portIndex < ICP_HSSACC_MAX_NUM_PORTS; portIndex ++) + { + hssAccTsAllocated[portIndex] = ICP_FALSE; + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTsAllocPlatformInit\n"); + return status; +} + + + +/** + * Function definition: HssAccTsAllocStatsReset + */ +void HssAccTsAllocStatsReset (void) +{ + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTsAllocStatsReset\n"); + memset (&hssAccTsAllocStats, + 0, + sizeof(icp_hssacc_ts_alloc_stats_t)); + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTsAllocStatsReset\n"); +} + + + +#ifdef SW_SWAPPING +/** + * Function definition: HssAccTsAllocTableWordsSwap + * This function assumes that the size provided is a multiple + * of a word size. + */ +TDM_PRIVATE +void HssAccTsAllocTableWordsSwap (uint32_t * tableAddr, + uint32_t sizeInBytes) +{ + unsigned index = 0; + for (;index < (sizeInBytes/ICP_HSSACC_WORD_SIZE); index ++) + { + tableAddr[index] = IX_OSAL_SWAP_BE_SHARED_LONG(tableAddr[index]); + } +} +#endif + + + +/** + * Function definition: HssAccTsAllocOffsetTableLoad + */ + +TDM_PRIVATE icp_status_t +HssAccTsAllocOffsetTableLoad (unsigned portId, + uint32_t offsetTablePhysAddr, + uint8_t messageId, + uint8_t messageRespId, + icp_hssacc_msg_with_resp_stats_t * stats, + icp_boolean_t activeTableLoad) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IxPiuMhMessage message; + uint8_t activeShadow = 0; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTsAllocOffsetTableLoad\n"); + + /* Translate Active/Shadow, only used for certain types of message + of no impact on others */ + if ( ICP_TRUE == activeTableLoad ) + { + activeShadow = 1; + } + + /* Create Message for TDM I/O Unit */ + HssAccComTdmIOUnitCmd4byte1wordMsgCreate (messageId, + 0, + portId, + activeShadow, + offsetTablePhysAddr, + &message); + /* Send the message */ + status = HssAccComTdmIOUnitMsgSendAndRecv(message, + messageRespId, + stats, + NULL); + + + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR("HssAccTsAllocOffsetTableLoad - " + "Failed communication with TDM I/O Unit " + "for Timeslot Allocation\n"); + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTsAllocOffsetTableLoad\n"); + + return status; +} + + + + +/** + * Function definition: HssAccTsAllocDummyProvTableCreate + * This will create a table with a single channel enabled + * with all timeslots assigned + */ +void +HssAccTsAllocDummyProvTableCreate (uint32_t * provTable) +{ + unsigned index = 0; + for (index = 0; index < ICP_HSSACC_MAX_TIMESLOTS_PER_PORT; index++) + { + provTable[index] = + (ICP_HSSACC_TDM_IO_UNIT_TS_ENABLE << + ICP_HSSACC_TDM_IO_UNIT_TS_EN_BIT_OFFSET); + } +} + + +/***************************************************************************** + * Abstract: + * Builds a new channel offset table for the TDM I/O unit. Only the offsets + * of channels on the specified HSS port will be affected. + * Also constructs a new Timeslot provisioning table for the specified port. + * When both tables have been built, they are loaded into the TDM I/O unit. + * + *****************************************************************************/ +icp_status_t +HssAccTsAllocUpdate(unsigned portId, + const icp_hssacc_channel_config_t * hssChannelData) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + unsigned chanId = 0, hdmaChannelId = 0; + unsigned tableProvOffset[ICP_HSSACC_MAX_NUM_PORTS]; + uint32_t tableOffset = 0; + uint16_t *pTdmIoUnitOffsetTable = NULL; + uint32_t *pHdmaProvTable = NULL; + uint8_t tsIndex, indexOffset = 0; + icp_boolean_t noTsUsed = ICP_TRUE; + uint32_t hdmaProvTablePhysOffset = 0; + uint32_t tdmIoUnitOffsetTablePhysOffset = 0; + + ICP_HSSACC_TRACE_1 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTsAllocUpdate - " + "Configuring timeslots on port %u\n", + portId); + + /* Get the base address of the channel offset tables */ + pTdmIoUnitOffsetTable = + (uint16_t *)HssAccTsAllocTdmIoUnitOffsetTableVirtAddrGet(); + + pHdmaProvTable = + (uint32_t *)HssAccTsAllocHdmaProvTableVirtAddrGet(); + + /* Clear the contents of the TDM I/O Unit channe offset table + and timeslot provisioning table */ + memset (pHdmaProvTable, 0, ICP_HSSACC_TDM_IO_UNIT_PROV_TABLE_SZ); + memset (pTdmIoUnitOffsetTable, 0, ICP_HSSACC_TDM_IO_UNIT_OFFSET_TABLE_SZ); + memset (tableProvOffset, 0, ICP_HSSACC_MAX_NUM_PORTS*sizeof(unsigned)); + /* + * The objective here is to pack the internal TDM I/O Unit memory channel + * usage such that the TDM I/O unit's internal memory doesn't become + * fragmented from adding/removing channels. This allows us to make maximum + * use of the total available memory. + * + * Two tables need to be updated: + * 1) the TDM I/O unit's offset table, which has a 1-to-1 mapping between + * MAX_NUM channels and their location in internal memory. Only + * channels on the specified port will be updated. The offset of each + * channel is relative to the port base address. + * 2) the TDM I/O Unit's timeslot proviosining table, which tracks the + * offsets of all channels active on that port. The channel ID(s) on a + * port differ from that of the TDM I/O unit (since we can't + * have MAX_NUM channels per port). For example, + * channel 5 (from the perspective of the access layer/TDM I/O unit) + * could have a channel ID of 0 on the port where it is active. + * + * Timeslot aggregation is also performed for all channels on the port. + */ + + /* The TDM I/O unit offset table has an entry for MAX_NUM channels */ + for (chanId = 0; chanId < ICP_HSSACC_MAX_NUM_CHANNELS; chanId++) + { + /* + * Only need to update the channels on the specified port, so skip any + * that are active on other ports, or inactive. + * This preserves the offsets for channels on other HSS ports. + */ + if (hssChannelData[chanId].size > 0) + { + /* Update the TDM I/O unit offset table for the active + channel (byte offset required)*/ + pTdmIoUnitOffsetTable[ICP_HSSACC_CHAN_OFFS_LOC_IN_TBL(chanId)] = + tableProvOffset[hssChannelData[chanId].portId]; + + if (hssChannelData[chanId].portId == portId) + { + noTsUsed = ICP_FALSE; + hssAccTsAllocated[portId] = ICP_TRUE; + + /* Calculate the HDMA timeslot index offset */ + indexOffset = hssChannelData[chanId].lineId * + ICP_HSSACC_MAX_TIMESLOTS_PER_TDM_LINE; + + + /* Enable the timeslots used by this channel */ + for (tsIndex = 0; + tsIndex < ICP_HSSACC_MAX_TIMESLOTS_PER_TDM_LINE; + tsIndex ++) + { + if (hssChannelData[chanId].timeslotMap & BIT_SET(tsIndex)) + { + ICP_HSSACC_TRACE_3 (ICP_HSSACC_DEBUG, + "HssAccTsAllocUpdate - Timeslot" + " %u is used by chan %u " + "on port %u\n", + tsIndex, + chanId, + hssChannelData[chanId].portId); + pHdmaProvTable[indexOffset + tsIndex] = + (ICP_HSSACC_TDM_IO_UNIT_TS_ENABLE << + ICP_HSSACC_TDM_IO_UNIT_TS_EN_BIT_OFFSET) | + (hdmaChannelId << ICP_HSSACC_TDM_IO_UNIT_CHAN_OFFSET); + } + } + + /* + * Must offset by 128 words in order to get to the first channel + * configuration word. + */ + indexOffset = ICP_HSSACC_MAX_TIMESLOTS_PER_PORT; + + /* Update the HDMA offset table */ + pHdmaProvTable[indexOffset + hdmaChannelId] = + tableOffset << ICP_HSSACC_TDM_IO_UNIT_CHAN_OFFSET; + + hdmaChannelId ++; + + /* Update the word offset by the size of the channel */ + tableOffset += hssChannelData[chanId].size; + } + tableProvOffset[hssChannelData[chanId].portId] += + hssChannelData[chanId].size*ICP_HSSACC_WORD_SIZE; + + } + } + + /* if no TS are used for this port, we need to allocate a dummy single + channel with all timeslots assigned to keep the TDM I/O Unit from + generating errors */ + if (noTsUsed) + { + HssAccTsAllocDummyProvTableCreate(pHdmaProvTable); + } +#ifdef SW_SWAPPING + HssAccTsAllocTableWordsSwap(pHdmaProvTable, + ICP_HSSACC_TDM_IO_UNIT_PROV_TABLE_SZ); + + HssAccTsAllocTableWordsSwap((uint32_t*)pTdmIoUnitOffsetTable, + ICP_HSSACC_TDM_IO_UNIT_OFFSET_TABLE_SZ); +#endif + + /* Flush the new tables to memory */ + IX_OSAL_CACHE_FLUSH (pHdmaProvTable, ICP_HSSACC_TDM_IO_UNIT_PROV_TABLE_SZ); + IX_OSAL_CACHE_FLUSH (pTdmIoUnitOffsetTable, + ICP_HSSACC_TDM_IO_UNIT_OFFSET_TABLE_SZ); + + /* Convert virtual addresses to Physical Offsets */ + hdmaProvTablePhysOffset = + HssAccVirtToPhysAddressTranslate(pHdmaProvTable); + tdmIoUnitOffsetTablePhysOffset = + HssAccVirtToPhysAddressTranslate((uint32_t*)pTdmIoUnitOffsetTable); + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_DEBUG, + "HssAccTsAllocUpdate - Update HDMA" + " provision table\n"); + + + /* Load the new HDMA offset table for this port */ + status = HssAccTsAllocOffsetTableLoad ( + portId, + hdmaProvTablePhysOffset, + ICP_HSSACC_TDM_IO_UNIT_PORT_PROV_TABLE_LOAD, + ICP_HSSACC_TDM_IO_UNIT_PORT_PROV_TABLE_LOAD_RESPONSE, + &(hssAccTsAllocStats.hssPortProvTableLoad), + ICP_FALSE); + + if (ICP_STATUS_SUCCESS == status) + { + ICP_HSSACC_TRACE_0 (ICP_HSSACC_DEBUG, + "HssAccTsAllocUpdate - Update offset" + " table\n"); + + /* Load the new TDM I/O unit offset table */ + status = HssAccTsAllocOffsetTableLoad( + 0, + tdmIoUnitOffsetTablePhysOffset, + ICP_HSSACC_TDM_IO_UNIT_OFFS_TABLE_LOAD, + ICP_HSSACC_TDM_IO_UNIT_OFFS_TABLE_LOAD_RESPONSE, + &(hssAccTsAllocStats.chanOffsetTableLoad), + ICP_FALSE); + } + + + + if (ICP_STATUS_SUCCESS == status) + { + status = HssAccTsAllocTableSwap (portId); + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTsAllocUpdate\n"); + + return status; +} + + + +/** + * Function definition: HssAccTsAllocInitialAllocationUpdate + */ +icp_status_t +HssAccTsAllocInitialAllocationUpdate(unsigned portId) + +{ + icp_status_t status = ICP_STATUS_SUCCESS; + uint32_t *pHdmaProvTable = NULL; + uint32_t hdmaProvTablePhysOffset = 0; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTsAllocInitialAllocationUpdate\n"); + if (ICP_TRUE != hssAccTsAllocated[portId]) + { + + /* Get the base address of the channel offset tables */ + pHdmaProvTable = + (uint32_t *)HssAccTsAllocHdmaProvTableVirtAddrGet(); + + /* Clear the contents of the HDMA offset table */ + memset (pHdmaProvTable, 0, ICP_HSSACC_TDM_IO_UNIT_PROV_TABLE_SZ); + + + HssAccTsAllocDummyProvTableCreate(pHdmaProvTable); + +#ifdef SW_SWAPPING + HssAccTsAllocTableWordsSwap(pHdmaProvTable, + ICP_HSSACC_TDM_IO_UNIT_PROV_TABLE_SZ); + +#endif + /* Flush the new tables to memory */ + IX_OSAL_CACHE_FLUSH (pHdmaProvTable, + ICP_HSSACC_TDM_IO_UNIT_PROV_TABLE_SZ); + + + /* Convert virtual addresses to Physical Offsets */ + hdmaProvTablePhysOffset = + HssAccVirtToPhysAddressTranslate(pHdmaProvTable); + + ICP_HSSACC_TRACE_0(ICP_HSSACC_DEBUG, + "HssAccTsAllocInitialAllocationUpdate - " + "Update Timeslot provisioning table\n"); + + + /* Load the new timeslot Provisioning table for this port */ + status = + HssAccTsAllocOffsetTableLoad ( + portId, + hdmaProvTablePhysOffset, + ICP_HSSACC_TDM_IO_UNIT_PORT_PROV_TABLE_LOAD, + ICP_HSSACC_TDM_IO_UNIT_PORT_PROV_TABLE_LOAD_RESPONSE, + &(hssAccTsAllocStats.hssPortProvTableLoad), + ICP_TRUE); + + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTsAllocInitialAllocationUpdate\n"); + return status; +} + + + + + + + +/** + * Function definition: HssAccTsAllocOffsetTableShow + */ +TDM_PRIVATE void +HssAccTsAllocOffsetTableShow (icp_boolean_t readShadowTable) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + uint32_t offsetTableWord = 0; + uint16_t offsetTableOffset = 0; + unsigned channelCount = 0; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTsAllocOffsetTableShow\n"); + + for (offsetTableOffset = 0; + offsetTableOffset < ICP_HSSACC_TDM_IO_UNIT_OFFSET_TABLE_SZ; + offsetTableOffset += ICP_HSSACC_WORD_SIZE) + { + status = HssAccTsAllocOffsetTableWordRead (readShadowTable, + offsetTableOffset, + &offsetTableWord); + if (ICP_STATUS_SUCCESS == status) + { + if (0 == (offsetTableOffset % ICP_HSSACC_OFFSET_HALF_WD_PER_LINE)) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "%u: ", + channelCount, + 0, 0, 0, 0, 0); + } + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "0x%04X 0x%04X ", + (uint16_t)((offsetTableWord & + ICP_HSSACC_TDM_IO_UNIT_SHORT0_MASK) >> + ICP_HSSACC_TDM_IO_UNIT_SHORT0_OFFSET), + (uint16_t)(offsetTableWord & + ICP_HSSACC_TDM_IO_UNIT_SHORT1_MASK), + 0, 0, 0, 0); + if ((ICP_HSSACC_OFFSET_HALF_WD_PER_LINE - ICP_HSSACC_WORD_SIZE) == + (offsetTableOffset % ICP_HSSACC_OFFSET_HALF_WD_PER_LINE)) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\n", 0, 0, 0, 0, 0, 0); + } + } + else + { + ICP_HSSACC_REPORT_ERROR ("HssAccTsAllocOffsetTableShow - " + "Failed to read " + "Channel Offset Table from TDM I/O Unit\n"); + break; + } + channelCount += ICP_HSSACC_CHAN_OFFS_PER_WD; + } + + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\n", 0, 0, 0, 0, 0, 0); + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTsAllocOffsetTableShow\n"); +} + + +/** + * Function definition: HssAccTsAllocChanOffsetActiveTableShow + */ +void HssAccTsAllocChanOffsetActiveTableShow (void) +{ + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTsAllocChanOffsetActiveTableShow\n"); + + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nTDM I/O Unit Channel Offset ACTIVE Table:\n", + 0, 0, 0, 0, 0, 0); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\n----------------------------------------------\n", + 0, 0, 0, 0, 0, 0); + HssAccTsAllocOffsetTableShow (ICP_FALSE); + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTsAllocChanOffsetActiveTableShow\n"); +} + + +/** + * Function definition: HssAccTsAllocChanOffsetShadowTableShow + */ +void HssAccTsAllocChanOffsetShadowTableShow (void) +{ + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTsAllocChanOffsetShadowTableShow\n"); + + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nTDM I/O Unit Channel Offset SHADOW Table:\n", + 0, 0, 0, 0, 0, 0); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\n----------------------------------------\n", + 0, 0, 0, 0, 0, 0); + HssAccTsAllocOffsetTableShow (ICP_TRUE); + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTsAllocChanOffsetShadowTableShow\n"); +} + + + +/** + * Function definition: HssAccTsAllocStatsShow + */ +void HssAccTsAllocStatsShow (void) +{ + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTsAllocStatsShow\n"); + + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nTimeslot Allocation Stats:\n", + 0, 0, 0, 0, 0, 0); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Stats for TDM I/O Unit channel Offset Table Load messages:\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow(hssAccTsAllocStats.chanOffsetTableLoad); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Stats for Timeslot Provisioning Table Load messages:\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow(hssAccTsAllocStats.hssPortProvTableLoad); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Stats for Timeslot Provisioning Table Swap messages:\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow(hssAccTsAllocStats.hssPortProvTableSwap); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Stats for TDM I/O Unit channel Offset Table Read messages:\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow(hssAccTsAllocStats.chanOffsetTableRead); + + HssAccTsAllocChanOffsetActiveTableShow(); + HssAccTsAllocChanOffsetShadowTableShow(); + + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTsAllocStatsShow\n"); +} diff --git a/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_tx_datapath.c b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_tx_datapath.c new file mode 100644 index 0000000..3f02636 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_tx_datapath.c @@ -0,0 +1,1023 @@ +/***************************************************************************** + * @file icp_hssacc_tx_datapath.c + * + * @description Contents of this file provide the implementation of the + * transmit functionality for the HSS I/O Access component + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + ******************************************************************************/ + +#include "IxOsal.h" + + +#include "icp.h" +#include "icp_hssacc.h" +#include "icp_hssacc_trace.h" +#include "icp_hssacc_channel_config.h" +#include "icp_hssacc_address_translate.h" + +#include "icp_hssacc_rings.h" +#include "icp_hssacc_queues_config.h" +#include "icp_hssacc_tx_datapath.h" +#include "icp_hssacc_tdm_io_queue_entry.h" +#include "IxQMgr.h" + + +/* Mutex which controls access to transmit datapath path functions */ +TDM_PRIVATE IxOsalMutex hssAccTxMutex[ICP_HSSACC_MAX_NUM_CHANNELS]; + +TDM_PRIVATE icp_hssacc_tx_done_callback_t +hssAccTxDoneChannelCallbacks[ICP_HSSACC_MAX_NUM_CHANNELS]; + +TDM_PRIVATE icp_user_context_t +hssAccTxDoneUserContext[ICP_HSSACC_MAX_NUM_CHANNELS]; + +TDM_PRIVATE uint32_t +hssAccTxDatapathNumPendPkts[ICP_HSSACC_MAX_NUM_CHANNELS]; + +TDM_PRIVATE icp_boolean_t +hssAccTxDatapathLastSubmitSuccess[ICP_HSSACC_MAX_NUM_CHANNELS]; + +TDM_PRIVATE icp_boolean_t hssAccTxServiceInitialised = ICP_FALSE; + + +/* Stats */ +#ifndef NDEBUG +TDM_PRIVATE uint32_t hssAccTxNumPktsSubmissions[ICP_HSSACC_MAX_NUM_CHANNELS]; +TDM_PRIVATE uint32_t +hssAccTxNumPktsSuccessSubmissions[ICP_HSSACC_MAX_NUM_CHANNELS]; +TDM_PRIVATE uint32_t hssAccTxNumPktsDone[ICP_HSSACC_MAX_NUM_CHANNELS]; +#endif + + +/* + * Initialises the service mutex. + */ +#define ICP_HSSACC_TX_DP_MUTEX_INIT(channelId) \ + (ixOsalMutexInit(&hssAccTxMutex[channelId])) + +/* + * Locks the service mutex. + */ +#define ICP_HSSACC_TX_DP_MUTEX_LOCK(channelId) \ + (ixOsalMutexLock(&hssAccTxMutex[channelId],ICP_HSSACC_MUTEX_TIMEOUT)) + +/* + * Unlocks the service mutex. + */ +#define ICP_HSSACC_TX_DP_MUTEX_UNLOCK(channelId) \ + (ixOsalMutexUnlock(&hssAccTxMutex[channelId])) + +/* + * Destroys the service mutex. + */ +#define ICP_HSSACC_TX_DP_MUTEX_DESTROY(channelId) \ + (ixOsalMutexDestroy(&hssAccTxMutex[channelId])) + +/* + * Reset the stats for a channel + */ +#ifndef NDEBUG +#define ICP_HSSACC_TX_DP_CHAN_STATS_RESET(channelId) do { \ + hssAccTxNumPktsSuccessSubmissions[channelId] = 0; \ + hssAccTxNumPktsSubmissions[channelId] = 0; \ + hssAccTxNumPktsDone[channelId] =0; \ + } while(0); +#else +#define ICP_HSSACC_TX_DP_CHAN_STATS_RESET(channelId) do { \ + } while (0); +#endif + + +/* Data for the descriptor to mbuf mapping queue */ +TDM_PRIVATE uint32_t +hssAccDataPlaneTxDescRingData +[ICP_HSSACC_MAX_NUM_CHANNELS][ICP_HSSACC_TX_QUEUE_DEPTH]; + + +TDM_PRIVATE icp_hssacc_dataplane_ring_t +hssAccDataPlaneTxDescRing[ICP_HSSACC_MAX_NUM_CHANNELS]; + +TDM_PRIVATE icp_boolean_t hssAccDataPlaneTxBypass[ICP_HSSACC_MAX_NUM_CHANNELS]; + + +/***************************************************************************** + * Abstract: + * Resets the Tx Datapath internal data. + * + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccTxDatapathReset(void); + + + + +icp_status_t +HssAccTxDatapathInit(void) +{ + uint32_t index = 0; + icp_status_t status = ICP_STATUS_SUCCESS; + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTxDatapathInit\n"); + if (ICP_TRUE == hssAccTxServiceInitialised) + { + ICP_HSSACC_REPORT_ERROR("HssAccTxDatapathInit - Tx Datapath sub-component" + " already initialised\n"); + status = ICP_STATUS_RESOURCE; + } + + if (ICP_STATUS_SUCCESS == status) + { + /* We support 1 client only per channel, to protect against corruption + we need 1 mutex per channel */ + for (index = 0; + index < ICP_HSSACC_MAX_NUM_CHANNELS; + index ++) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_TX_DP_MUTEX_INIT(index)) + { + ICP_HSSACC_REPORT_ERROR_1("HssAccTxDatapathInit - Mutex " + "Init Error for channel %d\n", + index); + status = ICP_STATUS_MUTEX; + break; + } + } + status = HssAccTxDatapathReset(); + } + if (ICP_STATUS_SUCCESS == status) + { + hssAccTxServiceInitialised = ICP_TRUE; + } + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTxDatapathInit\n"); + return status; +} + + +void +HssAccTxDatapathChanStatsReset(uint32_t channelId) +{ + if (ICP_STATUS_SUCCESS == ICP_HSSACC_TX_DP_MUTEX_LOCK(channelId)) + { + ICP_HSSACC_TX_DP_CHAN_STATS_RESET(channelId); + + if (ICP_STATUS_SUCCESS != ICP_HSSACC_TX_DP_MUTEX_UNLOCK(channelId)) + { + ICP_HSSACC_REPORT_ERROR_1("HssAccTxDatapathChanStatsReset - " + "Mutex Unlock Error for channel %d\n", + channelId); + } + } + else + { + ICP_HSSACC_REPORT_ERROR_1("HssAccTxDatapathChanStatsReset - " + "Mutex Lock Error for channel %d\n", + channelId); + } +} + + +void +HssAccTxDatapathChanStatsShow(uint32_t channelId) +{ +#ifndef NDEBUG + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nChannel Tx Datapath Statistics\n", + 0, 0, 0, 0, 0, 0); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\t\t%d Packets Submitted\n" + "\t\t%d Packets Successfully Submitted\n" + "\t\t%d Packets Done and Recycled to Client\n", + hssAccTxNumPktsSubmissions[channelId], + hssAccTxNumPktsSuccessSubmissions[channelId], + hssAccTxNumPktsDone[channelId], 0, 0, 0); +#else + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nChannel Tx Datapath Statistics Not Supported in this Build\n", + 0, 0, 0, 0, 0, 0); +#endif +} + + +icp_status_t +HssAccTxDatapathShutdown(void) +{ + uint32_t index = 0; + icp_status_t status = ICP_STATUS_SUCCESS; + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTxDatapathShutdown\n"); + if (ICP_TRUE == hssAccTxServiceInitialised) + { + status = HssAccTxDatapathReset(); + if (ICP_STATUS_SUCCESS == status) + { + for (index = 0; index < ICP_HSSACC_MAX_NUM_CHANNELS; index ++) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_TX_DP_MUTEX_DESTROY(index)) + { + ICP_HSSACC_REPORT_ERROR_1("HssAccTxDatapathShutdown - Mutex " + "Destroy Error for channel %d\n", + index); + status = ICP_STATUS_MUTEX; + break; + } + } + } + if (ICP_STATUS_SUCCESS == status) + { + hssAccTxServiceInitialised = ICP_FALSE; + } + } + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTxDatapathShutdown\n"); + return status; +} + + +TDM_PRIVATE icp_status_t +HssAccTxDatapathReset(void) +{ + uint32_t index = 0; + icp_status_t status = ICP_STATUS_SUCCESS; + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTxDatapathReset\n"); + for (index = 0; index < ICP_HSSACC_MAX_NUM_CHANNELS; index ++) + { + if (ICP_STATUS_SUCCESS == ICP_HSSACC_TX_DP_MUTEX_LOCK(index)) + { + hssAccDataPlaneTxDescRing[index].content = + hssAccDataPlaneTxDescRingData[index]; + hssAccDataPlaneTxDescRing[index].size = ICP_HSSACC_TX_QUEUE_DEPTH; + hssAccDataPlaneTxDescRing[index].mask = + ICP_HSSACC_TX_QUEUE_DEPTH - 1; + + hssAccDataPlaneTxDescRing[index].tail = 0; + hssAccDataPlaneTxDescRing[index].head = 0; + hssAccDataPlaneTxBypass[index] = ICP_FALSE; + hssAccTxDatapathNumPendPkts[index] = 0; + hssAccTxDatapathLastSubmitSuccess[index] = ICP_FALSE; + ICP_HSSACC_TX_DP_CHAN_STATS_RESET(index); + if (ICP_STATUS_SUCCESS != ICP_HSSACC_TX_DP_MUTEX_UNLOCK(index)) + { + ICP_HSSACC_REPORT_ERROR_1("HssAccTxDatapathReset - " + "Mutex Unlock Error for channel %d\n", + index); + status = ICP_STATUS_MUTEX; + break; + } + } + else + { + ICP_HSSACC_REPORT_ERROR_1("HssAccTxDatapathReset - " + "Mutex Lock Error for channel %d\n", + index); + status = ICP_STATUS_MUTEX; + break; + } + } + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTxDatapathReset\n"); + return status; +} + + +icp_status_t +HssAccTxDatapathChanTypeUpdate (uint32_t channelId, + icp_hssacc_channel_type_t chanType) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTxDatapathChanTypeUpdate\n"); + if (ICP_STATUS_SUCCESS == ICP_HSSACC_TX_DP_MUTEX_LOCK(channelId)) + { + if (ICP_HSSACC_CHAN_TYPE_HDLC == chanType) + { + hssAccDataPlaneTxDescRing[channelId].size = + ICP_HSSACC_HDLC_TX_QUEUE_DEPTH; + hssAccDataPlaneTxDescRing[channelId].mask = + ICP_HSSACC_HDLC_TX_QUEUE_DEPTH - 1; + } + else + { + hssAccDataPlaneTxDescRing[channelId].size = + ICP_HSSACC_VOICE_TX_QUEUE_DEPTH; + hssAccDataPlaneTxDescRing[channelId].mask = + ICP_HSSACC_VOICE_TX_QUEUE_DEPTH - 1; + } + if (ICP_STATUS_SUCCESS != ICP_HSSACC_TX_DP_MUTEX_UNLOCK(channelId)) + { + ICP_HSSACC_REPORT_ERROR_1("HssAccTxDatapathChanTypeUpdate - " + "Mutex Unlock Error for channel %d\n", + channelId); + status = ICP_STATUS_MUTEX; + } + } + else + { + ICP_HSSACC_REPORT_ERROR_1("HssAccTxDatapathChanTypeUpdate - " + "Mutex Lock Error for channel %d\n", + channelId); + status = ICP_STATUS_MUTEX; + } + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTxDatapathChanTypeUpdate\n"); + return status; +} + +TDM_PRIVATE icp_status_t +HssAccTxDatapathBufferValidityCheck(const IX_OSAL_MBUF * buffer, + icp_hssacc_channel_type_t channelType) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTxDatapathBufferValidityCheck\n"); + + if ((NULL != IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(buffer)) || + (NULL != IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(buffer))) + { + ICP_HSSACC_REPORT_ERROR("HssAccTxDatapathBufferValidityCheck - " + "Buffer and Packet Chaining not supported " + "for Transmission\n"); + status = ICP_STATUS_INVALID_PARAM; + } + if ( IX_OSAL_MBUF_PKT_LEN(buffer) != IX_OSAL_MBUF_MLEN(buffer)) + { + ICP_HSSACC_REPORT_ERROR("HssAccTxDatapathBufferValidityCheck - " + "Buffer length and Packet Length in OS " + "Abstraction Layer Buffer must be equal\n"); + status = ICP_STATUS_INVALID_PARAM; + } + if (0 == IX_OSAL_MBUF_PKT_LEN(buffer)) + { + ICP_HSSACC_REPORT_ERROR("HssAccTxDatapathBufferValidityCheck - " + "Buffer length cannot be 0\n"); + status = ICP_STATUS_INVALID_PARAM; + } + if (NULL == IX_OSAL_MBUF_MDATA(buffer)) + { + ICP_HSSACC_REPORT_ERROR("HssAccTxDatapathBufferValidityCheck - " + "Pointer to data cannot be NULL\n"); + status = ICP_STATUS_INVALID_PARAM; + } + if (ICP_HSSACC_CHAN_TYPE_VOICE == channelType) + { + /* voice buffers - check if length is not + modulo 4 (using bit comparison) */ + if (0 != (IX_OSAL_MBUF_PKT_LEN(buffer) & + (uint32_t) ICP_HSSACC_TX_VOICE_PACKET_LENGTH_CHECK_MASK)) + { + ICP_HSSACC_REPORT_ERROR_1("HssAccTxDatapathBufferValidityCheck - " + "Voice buffer length must be divisible " + "by 4 - buffer provided has " + "length %d\n", + IX_OSAL_MBUF_PKT_LEN(buffer)); + status = ICP_STATUS_INVALID_PARAM; + } + } + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTxDatapathBufferValidityCheck\n"); + return status; +} + + +TDM_PRIVATE void +HssAccTxDatapathBufferTdmSectionUpdate(uint32_t channelId, + IX_OSAL_MBUF * buffer) +{ + icp_hssacc_osal_mbuf_tdm_io_section_t * pBufferTdmSection = + (icp_hssacc_osal_mbuf_tdm_io_section_t*)&(buffer->ix_ne); + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTxDatapathBufferTdmSectionUpdate\n"); + + /* Using the data in the normal section of the OSAL Buffer, + we fill the TDM I/O private section of the buffer */ + ICP_OSAL_MBUF_TDM_SECT_CHANNEL_ID(pBufferTdmSection) = channelId; + ICP_OSAL_MBUF_TDM_SECT_STATUS(pBufferTdmSection) = 0; + + ICP_OSAL_MBUF_TDM_SECT_CURR_BUF_LEN_MSB(pBufferTdmSection) = + ICP_OSAL_MBUF_PKT_LEN_MSB(IX_OSAL_MBUF_PKT_LEN(buffer)); + + ICP_OSAL_MBUF_TDM_SECT_CURR_BUF_LEN_LSB(pBufferTdmSection) = + ICP_OSAL_MBUF_PKT_LEN_LSB(IX_OSAL_MBUF_PKT_LEN(buffer)); + + ICP_OSAL_MBUF_TDM_SECT_DATA(pBufferTdmSection) = IX_OSAL_MBUF_MDATA(buffer); + ICP_OSAL_MBUF_TDM_SECT_PKT_LEN(pBufferTdmSection) = 0; + + ICP_OSAL_MBUF_TDM_SECT_NEXT_BUF(pBufferTdmSection) = NULL; + ICP_OSAL_MBUF_TDM_SECT_OSAL_MBUF_START(pBufferTdmSection) = buffer; + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTxDatapathBufferTdmSectionUpdate\n"); +} + + + +/* This function requires the OSAL buffer to have been filled + with the correct data in the TDM I/O specific section */ +TDM_PRIVATE void +HssAccTxDatapathQueueEntryCreate(IX_OSAL_MBUF * buffer, + icp_hssacc_tdm_io_queue_entry_t * qEntry) +{ + /* initialise this pointer to the start of the TDM I/O Private section + of the OSAL buffer passed as a parameter */ + icp_hssacc_osal_mbuf_tdm_io_section_t * pBufferTdmSection = + (icp_hssacc_osal_mbuf_tdm_io_section_t*)&(buffer->ix_ne); + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTxDatapathQueueEntryCreate\n"); + /* Create the first word of the Q Entry using the first word of the TDM I/O + Section of the buffer passed */ + qEntry->descriptor.word = + pBufferTdmSection->tdm_io_entry.descriptor.word; + + /* Endianness Swap done by translation function */ + ICP_TDM_IO_Q_ENTRY_DATA(qEntry) = + (void*)HssAccVirtToPhysAddressTranslateAndSwap( + ICP_OSAL_MBUF_TDM_SECT_DATA(pBufferTdmSection)); + + /* This field is not used for Tx */ + ICP_TDM_IO_Q_ENTRY_PKT_LEN(qEntry) = 0; + + ICP_TDM_IO_Q_ENTRY_OSAL_MBUF(qEntry) = + (IX_OSAL_MBUF*)HssAccVirtToPhysAddressTranslateAndSwap(buffer); + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTxDatapathQueueEntryCreate\n"); +} + +icp_status_t +icp_HssAccTransmit (uint32_t channelId, + IX_OSAL_MBUF *buffer) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + icp_hssacc_tdm_io_queue_entry_t qEntry; + icp_boolean_t mutexLocked = ICP_FALSE; + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccTransmit\n"); + +#ifndef NDEBUG + if (ICP_TRUE != hssAccTxServiceInitialised) + { + ICP_HSSACC_REPORT_ERROR("icp_HssAccTransmit - Service not initialised\n"); + status = ICP_STATUS_FAIL; + } + + if (ICP_STATUS_SUCCESS == status) + { + if (ICP_HSSACC_MAX_NUM_CHANNELS <= channelId) + { + ICP_HSSACC_REPORT_ERROR("icp_HssAccTransmit - invalid ChannelId\n"); + status = ICP_STATUS_INVALID_PARAM; + } + else + { + hssAccTxNumPktsSubmissions[channelId] ++; + } + if (NULL == buffer) + { + ICP_HSSACC_REPORT_ERROR("icp_HssAccTransmit - Invalid Buffer\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } + +#endif + + + if (ICP_STATUS_SUCCESS == status) + { + /* Check the Buffer validity */ + status = + HssAccTxDatapathBufferValidityCheck(buffer, + HssAccChannelConfigTypeQuery( + channelId)); + } + if (ICP_STATUS_SUCCESS == status) + { + /* Lock the Datapath on Transmit */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_TX_DP_MUTEX_LOCK(channelId)) + { + ICP_HSSACC_REPORT_ERROR_1("icp_HssAccTransmit - " + "Mutex Lock Error for channel %d\n", + channelId); + status = ICP_STATUS_MUTEX; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + mutexLocked = ICP_TRUE; + if (ICP_TRUE == hssAccDataPlaneTxBypass[channelId]) + { + ICP_HSSACC_REPORT_ERROR_1("icp_HssAccTransmit - " + "Tx not allowed, Channel %d is bypassed\n", + channelId); + status = ICP_STATUS_RESOURCE; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Check the Channel Type and Queue Level. reject if above level and + previous submission was accepted */ + if ((ICP_HSSACC_CHAN_TYPE_VOICE == + HssAccChannelConfigTypeQuery(channelId)) && + (ICP_HSSACC_TX_Q_WATERMARK_LEVEL <= + hssAccTxDatapathNumPendPkts[channelId]) && + (ICP_TRUE == hssAccTxDatapathLastSubmitSuccess[channelId])) + { + ICP_HSSACC_DP_TRACE_1 (ICP_HSSACC_DEBUG, + "icp_HssAccTransmit - " + "Regulating Tx Flow for channel %d\n", + channelId); + status = ICP_STATUS_OVERFLOW; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + HssAccDataEndiannessSwap(buffer); + HssAccTxDatapathBufferTdmSectionUpdate(channelId, + buffer); + /* Create the Queue Entry for the Q */ + HssAccTxDatapathQueueEntryCreate(buffer, + &qEntry); + /* Submit the Entry to the Queue */ + status = ixQMgrQWrite (HssAccQueueIdGet(channelId), + (IxQMgrQEntryType *)&qEntry); + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Push the Buffer Ptr onto the Ring */ + ICP_HSSACC_DATAPLANE_RING_ENTRY_ADD(hssAccDataPlaneTxDescRing[channelId], + buffer); + hssAccTxDatapathNumPendPkts[channelId] ++; + hssAccTxDatapathLastSubmitSuccess[channelId] = ICP_TRUE; +#ifndef NDEBUG + hssAccTxNumPktsSuccessSubmissions[channelId] ++; +#endif + } + else + { + hssAccTxDatapathLastSubmitSuccess[channelId] = ICP_FALSE; + } + + /* Unlock the datapath */ + if (ICP_TRUE == mutexLocked) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_TX_DP_MUTEX_UNLOCK(channelId)) + { + ICP_HSSACC_REPORT_ERROR_1("icp_HssAccTransmit - " + "Mutex Unlock Error for channel %d\n", + channelId); + status = ICP_STATUS_MUTEX; + } + } + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccTransmit\n"); + return status; +} + + + +icp_status_t +icp_HssAccTxDoneRetrieve (uint32_t channelId, + IX_OSAL_MBUF **buffer) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + uint32_t entry = 0; + icp_boolean_t mutexLocked = ICP_FALSE; + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccTxDoneRetrieve\n"); +#ifndef NDEBUG + if (ICP_TRUE != hssAccTxServiceInitialised) + { + ICP_HSSACC_REPORT_ERROR("icp_HssAccTxDoneRetrieve - " + "Service not initialised\n"); + status = ICP_STATUS_FAIL; + } + + if (ICP_STATUS_SUCCESS == status) + { + if (ICP_HSSACC_MAX_NUM_CHANNELS <= channelId) + { + ICP_HSSACC_REPORT_ERROR("icp_HssAccTxDoneRetrieve - " + "invalid ChannelId\n"); + status = ICP_STATUS_INVALID_PARAM; + } + if (NULL == buffer) + { + ICP_HSSACC_REPORT_ERROR("icp_HssAccTxDoneRetrieve - " + "Invalid Buffer\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } +#endif + + if (ICP_STATUS_SUCCESS == status) + { + /* Lock the datapath for this Q */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_TX_DP_MUTEX_LOCK(channelId)) + { + ICP_HSSACC_REPORT_ERROR_1("icp_HssAccTxDoneRetrieve - " + "Mutex Lock Error for channel %d\n", + channelId); + status = ICP_STATUS_MUTEX; + } + } + if (ICP_STATUS_SUCCESS == status) + { + mutexLocked = ICP_TRUE; + /* The Shadow counter allows us to keep track of the number of + transmissions completed by the TDM I/O Unit: real Tail - shadow Tail = + number of transmits completed by unit since last servicing. here we are + retrieving the oldest completed transmission so increment the shadow + counter by 1 */ + status = ixQMgrShadowAdvance(HssAccQueueIdGet(channelId), + IX_QMGR_Q_SHADOW_TAIL_ONLY, + 1); + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Get the Buffer Ptr from the Ring */ + ICP_HSSACC_DATAPLANE_RING_ENTRY_REM(hssAccDataPlaneTxDescRing[channelId], + entry); + *buffer = (IX_OSAL_MBUF*)entry; + hssAccTxDatapathNumPendPkts[channelId] --; +#ifndef NDEBUG + hssAccTxNumPktsDone[channelId] ++; +#endif + } + + /* Unlock datapath */ + if (ICP_TRUE == mutexLocked) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_TX_DP_MUTEX_UNLOCK(channelId)) + { + ICP_HSSACC_REPORT_ERROR_1("icp_HssAccTxDoneRetrieve - " + "Mutex Unlock Error for channel %d\n", + channelId); + status = ICP_STATUS_MUTEX; + } + } + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccTxDoneRetrieve\n"); + return status; +} + + + +icp_status_t +HssAccTxDatapathChanBypassStateSet(uint32_t channelId, + icp_boolean_t bypassed) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTxDatapathChanBypassedSet\n"); + /* Lock the Tx Datapath Mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_TX_DP_MUTEX_LOCK(channelId)) + { + ICP_HSSACC_REPORT_ERROR_1("HssAccTxDatapathChanBypassSet - " + "Mutex Lock Error for channel %d\n", + channelId); + status = ICP_STATUS_MUTEX; + } + else + { + hssAccDataPlaneTxBypass[channelId] = bypassed; + + /* Unlock the mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_TX_DP_MUTEX_UNLOCK(channelId)) + { + ICP_HSSACC_REPORT_ERROR_1("HssAccTxDapapathChanBypassedSet - " + "Mutex Unlock Error for channel %d\n", + channelId); + status = ICP_STATUS_MUTEX; + } + } + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTxDatapathChanBypassedSet\n"); + return status; +} + + +void +HssAccTxDatapathChanTxDoneCallbackRegister( + uint32_t channelId, + icp_hssacc_tx_done_callback_t txDoneCallback, + icp_user_context_t userContext) +{ + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTxDatapathChanTxDoneCallbackRegister\n"); + hssAccTxDoneChannelCallbacks[channelId] = txDoneCallback; + hssAccTxDoneUserContext[channelId] = userContext; + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTxDatapathChanTxDoneCallbackRegister\n"); +} + +/****************************************************************************** + * Abstract: + * Register rx callback and user context + * + ******************************************************************************/ +void +HssAccTxDatapathChanTxDoneCallbackDeregister(uint32_t channelId) +{ + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelRxCallbackDeregister\n"); + + hssAccTxDoneChannelCallbacks[channelId] = NULL; + hssAccTxDoneUserContext[channelId] = 0; + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelRxCallbackDeregister\n"); +} + + + +/* Service all channels of the specified channel Type: find any completed + transmissions by the TDM I/O Unit and report them to the client */ +icp_status_t +HssAccTxDatapathService(icp_hssacc_channel_type_t channelType) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + uint32_t index = 0; + uint32_t numEntries = 0; + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTxDatapathService\n"); + + /* cycle through the channels for this service */ + for (; index < ICP_HSSACC_MAX_NUM_CHANNELS; index ++) + { + numEntries = 0; + /* check if servicing is required on TxDone and use the callback + if this is the case */ + if (channelType == HssAccChannelConfigTypeQuery(index)) + { + if (ICP_HSSACC_CHANNEL_ENABLED != + HssAccChannelConfigStateQuery(index)) + { + /* This channel has been configured for this service but it is + not enabled, Datapath functionality is not enabled yet */ + continue; + } + status = ixQMgrShadowDeltaGet(HssAccQueueIdGet(index), + IX_QMGR_Q_SHADOW_TAIL_ONLY, + &numEntries); + } + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1 ("HssAccTxDatapathService - " + "Couldnt determine Queue level for " + "channel %d\n", + index); + break; + } + if (0 < numEntries) + { + if (NULL != hssAccTxDoneChannelCallbacks[index]) + { + hssAccTxDoneChannelCallbacks[index]( + hssAccTxDoneUserContext[index]); + } + else + { + ICP_HSSACC_DP_TRACE_1 (ICP_HSSACC_DEBUG, + "HssAccTxDatapathService - " + "Channel %d has no TxDone callback\n", + index); + } + ICP_HSSACC_DP_TRACE_1 (ICP_HSSACC_DEBUG, + "HssAccTxDatapathService - Channel %d Serviced\n", + index); + } + } + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTxDatapathService\n"); + + return status; +} + + + +/* Retrieve all buffers left over on the specified channel, + channel must be disabled */ +icp_status_t +HssAccTxDatapathChannelBuffersRetrieve(uint32_t channelId, + IX_OSAL_MBUF * * startChainBuffer, + IX_OSAL_MBUF * * endChainBuffer) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + uint32_t numEntries = 0; + uint32_t entry = 0; + IX_OSAL_MBUF * pCurrentBuffer = NULL; + icp_boolean_t mutexLocked = ICP_FALSE; + icp_boolean_t chainStarted = ICP_FALSE; + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTxDatapathChannelBuffersRetrieve\n"); + + /* Lock the datapath for this Q */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_TX_DP_MUTEX_LOCK(channelId)) + { + ICP_HSSACC_REPORT_ERROR_1("HssAccTxDatapathChannelBuffersRetrieve - " + "Mutex Lock Error for channel %d\n", + channelId); + status = ICP_STATUS_MUTEX; + } + + if (ICP_STATUS_SUCCESS == status) + { + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_DEBUG, + "HssAccTxDatapathChannelBuffersRetrieve - " + "Recycle Tx Done Buffers\n"); + + mutexLocked = ICP_TRUE; + status = ixQMgrShadowDeltaGet(HssAccQueueIdGet(channelId), + IX_QMGR_Q_SHADOW_TAIL_ONLY, + &numEntries); + + if ((ICP_STATUS_SUCCESS == status) && + (0 != numEntries)) + { + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_DEBUG, + "HssAccTxDatapathChannelBuffersRetrieve - " + "Update the QMgr for TxDone\n"); + status = ixQMgrShadowAdvance(HssAccQueueIdGet(channelId), + IX_QMGR_Q_SHADOW_TAIL_ONLY, + numEntries); + + if (ICP_STATUS_SUCCESS == status) + { + numEntries --; + ICP_HSSACC_DATAPLANE_RING_ENTRY_REM( + hssAccDataPlaneTxDescRing[channelId], + entry); + + *startChainBuffer = (IX_OSAL_MBUF*)entry; + pCurrentBuffer = (IX_OSAL_MBUF*)entry; + chainStarted = ICP_TRUE; +#ifndef NDEBUG + hssAccTxNumPktsDone[channelId] ++; +#endif + } + } + } + + if (ICP_STATUS_SUCCESS == status) + { + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_DEBUG, + "HssAccTxDatapathChannelBuffersRetrieve - " + "Create Chain with Tx Done Buffers\n"); + + for (; numEntries > 0; numEntries --) + { + ICP_HSSACC_DATAPLANE_RING_ENTRY_REM( + hssAccDataPlaneTxDescRing[channelId], + entry); + + IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(pCurrentBuffer) = + (IX_OSAL_MBUF*)entry; + pCurrentBuffer = (IX_OSAL_MBUF*)entry; +#ifndef NDEBUG + hssAccTxNumPktsDone[channelId] ++; +#endif + } + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_DEBUG, + "HssAccTxDatapathChannelBuffersRetrieve - " + "Recycle Tx Pending Buffers\n"); + + status = ixQMgrQNumEntriesGet(HssAccQueueIdGet(channelId), + &numEntries); + } + if ((ICP_STATUS_SUCCESS == status) && + (0 != numEntries)) + { + /* Update Queue Head counter */ + status = ixQMgrQWriteRollback(HssAccQueueIdGet(channelId), + numEntries); + + } + if (ICP_STATUS_SUCCESS == status) + { + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_DEBUG, + "HssAccTxDatapathChannelBuffersRetrieve - " + "Append Chain with Tx Buffers\n"); + if ((ICP_FALSE == chainStarted) && + (0 != numEntries)) + { + numEntries --; + ICP_HSSACC_DATAPLANE_RING_ENTRY_REM( + hssAccDataPlaneTxDescRing[channelId], + entry); + + *startChainBuffer = (IX_OSAL_MBUF*)entry; + pCurrentBuffer = (IX_OSAL_MBUF*)entry; +#ifndef NDEBUG + hssAccTxNumPktsDone[channelId] ++; +#endif + } + for (; numEntries > 0; numEntries --) + { + ICP_HSSACC_DATAPLANE_RING_ENTRY_REM( + hssAccDataPlaneTxDescRing[channelId], + entry); + + IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(pCurrentBuffer) = + (IX_OSAL_MBUF*)entry; + pCurrentBuffer = (IX_OSAL_MBUF*)entry; +#ifndef NDEBUG + hssAccTxNumPktsDone[channelId] ++; +#endif + } + + *endChainBuffer = pCurrentBuffer; + hssAccTxDatapathNumPendPkts[channelId] = 0; + } + + /* Unlock datapath */ + if (ICP_TRUE == mutexLocked) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_TX_DP_MUTEX_UNLOCK(channelId)) + { + ICP_HSSACC_REPORT_ERROR_1("HssAccTxDatapathChannelBuffersRetrieve - " + "Mutex Unlock Error for channel %d\n", + channelId); + status = ICP_STATUS_MUTEX; + } + } + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTxDatapathChannelBuffersRetrieve\n"); + return status; +} + + diff --git a/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_voice_bypass.c b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_voice_bypass.c new file mode 100644 index 0000000..591b00b --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_voice_bypass.c @@ -0,0 +1,776 @@ +/****************************************************************************** + * @file icp_hssacc_timeslot_switching.c + * + * @description Contents of this file provide the implementation of all + * Timeslot switching functionality as described the icp_hssacc.h header file + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + *****************************************************************************/ + +#include "IxOsal.h" + +#include "icp.h" +#include "icp_hssacc.h" +#include "icp_hssacc_trace.h" +#include "icp_hssacc_common.h" +#include "icp_hssacc_channel_config.h" +#include "icp_hssacc_voice_bypass.h" +#include "icp_hssacc_address_translate.h" +#include "icp_hssacc_tx_datapath.h" + + + +/* Stats */ +typedef struct icp_hssacc_bypass_stats_s +{ + icp_hssacc_msg_with_resp_stats_t gctLoad; + icp_hssacc_msg_with_resp_stats_t gainCfg; + icp_hssacc_msg_with_resp_stats_t bypassEnable; + icp_hssacc_msg_with_resp_stats_t bypassDisable; +} icp_hssacc_bypass_stats_t; + + + +/* Internal GCT info */ +typedef struct icp_hssacc_gct_internal_data_s +{ + icp_boolean_t configured; + unsigned numBypassUsing; +} icp_hssacc_gct_internal_data_t; + + + +/* Internal Timeslot switch info */ +typedef struct icp_hssacc_bypass_internal_data_s +{ + icp_boolean_t enabled; + unsigned srcChannelId; + unsigned destChannelId; + unsigned portId; + unsigned gctId; +} icp_hssacc_bypass_internal_data_t; + +TDM_PRIVATE icp_hssacc_gct_internal_data_t +hssAccGctData[ICP_HSSACC_MAX_NUM_VOICE_BYPASS_GCTS]; + +TDM_PRIVATE icp_hssacc_bypass_internal_data_t +hssAccBypassData[ICP_HSSACC_MAX_NUM_VOICE_BYPASSES]; + +TDM_PRIVATE icp_boolean_t channelSwitchModuleInitialised = ICP_FALSE; + +TDM_PRIVATE icp_hssacc_bypass_stats_t hssAccBypassStats; + + + +/****************************************************************************** + * Abstract: + * Initialise the Voice bypass module + * + *****************************************************************************/ +void +HssAccVoiceBypassInit(void) +{ + unsigned index = 0; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccVoiceBypassInit\n"); + if (ICP_TRUE == channelSwitchModuleInitialised) + { + ICP_HSSACC_REPORT_ERROR("HssAccVoiceBypassInit - module already " + "initialised\n"); + } + else + { + + for (;index < ICP_HSSACC_MAX_NUM_VOICE_BYPASS_GCTS; index ++) + { + hssAccGctData[index].configured = ICP_FALSE; + hssAccGctData[index].numBypassUsing = 0; + } + + for (index = 0; index < ICP_HSSACC_MAX_NUM_VOICE_BYPASSES; index ++) + { + hssAccBypassData[index].enabled = ICP_FALSE; + hssAccBypassData[index].srcChannelId = ICP_HSSACC_MAX_NUM_CHANNELS; + hssAccBypassData[index].destChannelId = ICP_HSSACC_MAX_NUM_CHANNELS; + hssAccBypassData[index].portId = ICP_HSSACC_MAX_NUM_PORTS; + hssAccBypassData[index].gctId = ICP_HSSACC_MAX_NUM_VOICE_BYPASS_GCTS; + } + + HssAccBypassStatsReset(); + + channelSwitchModuleInitialised = ICP_TRUE; + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccVoiceBypassInit\n"); + +} + + +/****************************************************************************** + * Abstract: + * Shutdown the Voice Bypass module. + * + *****************************************************************************/ +icp_status_t +HssAccVoiceBypassShutdown(void) +{ + unsigned index = 0; + icp_status_t status = ICP_STATUS_SUCCESS; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccVoiceBypassShutdown\n"); + if (ICP_TRUE != channelSwitchModuleInitialised) + { + ICP_HSSACC_REPORT_ERROR("HssAccVoiceBypassShutdown - module has not " + "already been initialised\n"); + status = ICP_STATUS_FAIL; + } + + for (index = 0; index < ICP_HSSACC_MAX_NUM_VOICE_BYPASSES; index ++) + { + if (ICP_TRUE == hssAccBypassData[index].enabled) + { + ICP_HSSACC_REPORT_ERROR_1 ("HssAccVoiceBypassShutdown - " + "Bypass %u is still enabled, can't" + " shutdown\n", + index); + status = ICP_STATUS_RESOURCE; + } + } + if (ICP_STATUS_SUCCESS == status) + { + for (index = 0;index < ICP_HSSACC_MAX_NUM_VOICE_BYPASS_GCTS; index ++) + { + hssAccGctData[index].configured = ICP_FALSE; + hssAccGctData[index].numBypassUsing = 0; + } + channelSwitchModuleInitialised = ICP_FALSE; + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccVoiceBypassShutdown\n"); + return status; +} + + + +/****************************************************************************** + * Abstract: + * Returns the number of supported Gain Control Tables. + * + *****************************************************************************/ +unsigned +icp_HssAccNumSupportedGCTsGet ( void ) +{ + return ICP_HSSACC_MAX_NUM_VOICE_BYPASS_GCTS; +} + + +/****************************************************************************** + * Abstract: + * returns the number of Voice bypasses supported + * + *****************************************************************************/ +unsigned +icp_HssAccNumSupportedVoiceBypassesGet ( void ) +{ + return ICP_HSSACC_MAX_NUM_VOICE_BYPASSES; +} + +/****************************************************************************** + * Abstract: + * Download the provided Gain Control Table to the TDM I/O Unit. + * + *****************************************************************************/ +icp_status_t +icp_HssAccVoiceBypassGctDownload (unsigned voiceBypassGct, + uint8_t *gainCtrlTable) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + uint32_t physAddr = 0; + IxPiuMhMessage message; + icp_boolean_t mutexLocked = ICP_FALSE; + ICP_HSSACC_TRACE_1 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccVoiceBypassGctDownload " + "for Table %u\n", + voiceBypassGct); + + if (ICP_FALSE == channelSwitchModuleInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccVoiceBypassGctDownload - " + "Service is not Initialised\n"); + status = ICP_STATUS_FAIL; + } + + if (ICP_STATUS_SUCCESS == status) + { + if ((voiceBypassGct >= ICP_HSSACC_MAX_NUM_VOICE_BYPASS_GCTS)|| + (NULL == gainCtrlTable)) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccVoiceBypassGctDownload - " + "invalid parameter\n"); + status = ICP_STATUS_INVALID_PARAM; + } + else if (0 != + ((uint32_t)gainCtrlTable & ICP_HSSACC_DBLE_WD_ALIGN_MASK)) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccVoiceBypassGctDownload - " + "invalid alignment for GCT memory " + "location\n"); + status = ICP_STATUS_INVALID_PARAM; + } + + } + + + if (ICP_STATUS_SUCCESS == status) + { + /* Grab the HssAcc mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_LOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccVoiceBypassGctDownload - " + "failed to lock HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + else + { + mutexLocked = ICP_TRUE; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Check if this Gain Control table has already been configured + and if it is already in use for a bypass, we only allow configuration + of the GCT if it is not in use by any bypass */ + if (0 != hssAccGctData[voiceBypassGct].numBypassUsing) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccVoiceBypassGctDownload - " + "GCT is currently in use by 1 " + "or more bypasses\n"); + status = ICP_STATUS_RESOURCE; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Send Configuration to TDM I/O Unit and save it in + Access for Stats purposes */ + + + /* Convert the table base address to a physical address */ + physAddr = + HssAccVirtToPhysAddressTranslate(gainCtrlTable); + + /* Construct the message to load the table */ + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_GCT_LOAD, + 0, + 0, + voiceBypassGct, + physAddr, + &message); + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = + HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_GCT_LOAD_RESPONSE, + &(hssAccBypassStats.gctLoad), + NULL); + + if (ICP_STATUS_SUCCESS == status) + { + hssAccGctData[voiceBypassGct].configured = ICP_TRUE; + } + else + { + ICP_HSSACC_REPORT_ERROR("icp_HssAccVoiceBypassGctDownload - " + "failed to set Table in TDM I/O Unit\n"); + } + + } + /* Free the HssAcc mutex */ + if (ICP_TRUE == mutexLocked) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccVoiceBypassGctDownload - " + "failed to release HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + } + + + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccVoiceBypassGctDownload\n"); + return status; +} + + + + + +/****************************************************************************** + * Abstract: + * Enable the specified Voice bypass between the specified source and + * destination channels. + * + *****************************************************************************/ +icp_status_t +icp_HssAccVoiceBypassEnable (unsigned portId, + unsigned voiceBypassId, + unsigned voiceBypassGct, + unsigned srcChannelId, + unsigned destChannelId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IxPiuMhMessage message; + icp_boolean_t mutexLocked = ICP_FALSE; + unsigned index = 0; + ICP_HSSACC_TRACE_2 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccVoiceBypassEnable for Table %u " + "on bypass %u\n", + voiceBypassGct, + voiceBypassId); + + if (ICP_FALSE == channelSwitchModuleInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccVoiceBypassEnable - " + "Service is not Initialised\n"); + status = ICP_STATUS_FAIL; + } + + if (ICP_STATUS_SUCCESS == status) + { + if ((portId >= ICP_HSSACC_MAX_NUM_PORTS) || + (voiceBypassId >= ICP_HSSACC_MAX_NUM_VOICE_BYPASSES) || + (voiceBypassGct >= ICP_HSSACC_MAX_NUM_VOICE_BYPASS_GCTS)) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccVoiceBypassEnable - invalid " + "Bypass configuration parameter\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } + + + if (ICP_STATUS_SUCCESS == status) + { + if ((ICP_HSSACC_MAX_NUM_CHANNELS <= srcChannelId) || + (ICP_HSSACC_MAX_NUM_CHANNELS <= destChannelId)) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccVoiceBypassEnable - Channels " + "selected for bypass are invalid\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Grab the HssAcc mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_LOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccVoiceBypassEnable - " + "failed to lock HssAcc Mutex\n"); + + status = ICP_STATUS_MUTEX; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + mutexLocked = ICP_TRUE; + + if (ICP_TRUE == hssAccBypassData[voiceBypassId].enabled) + { + ICP_HSSACC_REPORT_ERROR_1 ("icp_HssAccVoiceBypassEnable - Selected " + "bypass (%u) is already enabled; it must " + "be disabled first before " + "reconfiguring\n", + voiceBypassId); + status = ICP_STATUS_RESOURCE; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + if (ICP_TRUE != hssAccGctData[voiceBypassGct].configured) + { + ICP_HSSACC_REPORT_ERROR_1 ("icp_HssAccVoiceBypassEnable - Selected " + "Gain Control Table (%u) is not " + "configured, need to configure it first\n", + voiceBypassGct); + status = ICP_STATUS_RESOURCE; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + for (index = 0; index < ICP_HSSACC_MAX_NUM_VOICE_BYPASSES; index ++) + { + if ((hssAccBypassData[index].srcChannelId == srcChannelId) || + (hssAccBypassData[index].destChannelId == destChannelId)) + { + ICP_HSSACC_REPORT_ERROR_1("icp_HssAccVoiceBypassEnable - " + "One of the channels selected is " + "already used in a identical role " + "for bypass %u\n", + index); + status = ICP_STATUS_RESOURCE; + break; + } + } + } + + if (ICP_STATUS_SUCCESS == status) + { + if ( (ICP_FALSE == HssAccChannelConfigValidBypass(srcChannelId,portId)) || + (ICP_FALSE == HssAccChannelConfigValidBypass(destChannelId,portId))) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccVoiceBypassEnable - Channel(s) " + "selected for bypass is(are) not " + "appropriate (Narrowband Enabled Channels " + "only on same port)\n"); + status = ICP_STATUS_RESOURCE; + } + } + + + if (ICP_STATUS_SUCCESS == status) + { + /* Link the Bypass to the Gain Control Table */ + + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_BYPASS_GAIN_CFG, + portId, + voiceBypassId, + voiceBypassGct, + 0, + &message); + + + status = + HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_BYPASS_GAIN_CFG_RESPONSE, + &(hssAccBypassStats.gainCfg), + NULL); + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_2("icp_HssAccVoiceBypassEnable - " + "Failed to link GCT %u with Voice " + "Bypass %u on the TDM I/O Unit\n", + voiceBypassGct, + voiceBypassId); + } + + + + if (ICP_STATUS_SUCCESS == status) + { + /* Configure the Bypass*/ + + HssAccComTdmIOUnitCmd8byteMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_BYPASS_ENABLE, + portId, + voiceBypassId, + srcChannelId, + destChannelId, + 0, 0, 0, + &message); + + + status = + HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_BYPASS_ENABLE_RESPONSE, + &(hssAccBypassStats.bypassEnable), + NULL); + + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1("icp_HssAccVoiceBypassEnable - " + "Failed to enable Voice " + "Bypass %u on the TDM I/O Unit\n", + voiceBypassId); + } + + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Save bypass config and send new channel state to tx */ + hssAccBypassData[voiceBypassId].enabled = ICP_TRUE; + hssAccBypassData[voiceBypassId].portId = portId; + hssAccBypassData[voiceBypassId].srcChannelId = srcChannelId; + hssAccBypassData[voiceBypassId].destChannelId = destChannelId; + hssAccBypassData[voiceBypassId].gctId = voiceBypassGct; + hssAccGctData[voiceBypassGct].numBypassUsing ++; + + /* Notify the Tx Datapath and config modules that this channel is + bypassed */ + HssAccTxDatapathChanBypassStateSet(destChannelId, + ICP_TRUE); + HssAccChannelBypassPairSet(srcChannelId, destChannelId); + } + } + + + + /* Free the HssAcc mutex */ + if (ICP_TRUE == mutexLocked) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccVoiceBypassEnable - " + "failed to release HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccVoiceBypassEnable\n"); + return status; +} + + + + +/****************************************************************************** + * Abstract: + * disable the specified Voice bypass. + * + *****************************************************************************/ +icp_status_t +icp_HssAccVoiceBypassDisable (unsigned voiceBypassId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IxPiuMhMessage message; + icp_boolean_t mutexLocked = ICP_FALSE; + unsigned gctId = ICP_HSSACC_MAX_NUM_VOICE_BYPASS_GCTS; + ICP_HSSACC_TRACE_1 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccVoiceBypassDisable for Bypass %u\n", + voiceBypassId); + + if (ICP_FALSE == channelSwitchModuleInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccVoiceBypassDisable - " + "Service is not Initialised\n"); + status = ICP_STATUS_FAIL; + } + + if (ICP_STATUS_SUCCESS == status) + { + if (voiceBypassId >= ICP_HSSACC_MAX_NUM_VOICE_BYPASSES) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccVoiceBypassDisable - invalid " + "Bypass ID\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Grab the HssAcc mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_LOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccVoiceBypassDisable - " + "failed to lock HssAcc Mutex\n"); + + status = ICP_STATUS_MUTEX; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + mutexLocked = ICP_TRUE; + + if (ICP_TRUE != hssAccBypassData[voiceBypassId].enabled) + { + ICP_HSSACC_REPORT_ERROR_1 ("icp_HssAccVoiceBypassDisable - Selected " + "bypass (%u) is not enabled\n", + voiceBypassId); + status = ICP_STATUS_RESOURCE; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Configure the Bypass*/ + + HssAccComTdmIOUnitCmd8byteMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_BYPASS_DISABLE, + hssAccBypassData[voiceBypassId].portId, + voiceBypassId, + 0, + 0, 0, 0, 0, + &message); + + + status = + HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_BYPASS_DISABLE_RESPONSE, + &(hssAccBypassStats.bypassDisable), + NULL); + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1("icp_HssAccVoiceBypassDisable - " + "Failed to disable Voice " + "Bypass %u on the TDM I/O Unit\n", + voiceBypassId); + } + + + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Save bypass config and send new channel state to tx */ + hssAccBypassData[voiceBypassId].enabled = ICP_FALSE; + gctId = hssAccBypassData[voiceBypassId].gctId; + hssAccBypassData[voiceBypassId].portId = ICP_HSSACC_MAX_NUM_PORTS; + hssAccBypassData[voiceBypassId].gctId = + ICP_HSSACC_MAX_NUM_VOICE_BYPASS_GCTS; + hssAccGctData[gctId].numBypassUsing --; + + /* Notify the Tx Datapath module that this channel is + no longer bypassed */ + HssAccTxDatapathChanBypassStateSet( + hssAccBypassData[voiceBypassId].destChannelId, + ICP_FALSE); + + HssAccChannelBypassPairClear( + hssAccBypassData[voiceBypassId].srcChannelId, + hssAccBypassData[voiceBypassId].destChannelId); + + hssAccBypassData[voiceBypassId].srcChannelId = + ICP_HSSACC_MAX_NUM_CHANNELS; + hssAccBypassData[voiceBypassId].destChannelId = + ICP_HSSACC_MAX_NUM_CHANNELS; + } + + /* Free the HssAcc mutex */ + if (ICP_TRUE == mutexLocked) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccVoiceBypassDisable - " + "failed to release HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + } + + + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccVoiceBypassDisable\n"); + return status; +} + + + +/****************************************************************************** + * Abstract: + * Display the stats collected by this sub-module. + * + * + *****************************************************************************/ +void +HssAccBypassStatsShow (void) +{ + + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nVoice Channel Bypass Configuration:\n" + "Gain Control Table Loading\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccBypassStats.gctLoad); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nBypass Gain Control Config messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccBypassStats.gainCfg); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nBypass Enable messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccBypassStats.bypassEnable); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nBypass Disable messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccBypassStats.bypassDisable); + +} + +/****************************************************************************** + * Abstract: + * Reset the stats collected by this sub-module. + * + *****************************************************************************/ +void +HssAccBypassStatsReset (void) +{ + memset (&hssAccBypassStats, + 0, + sizeof(icp_hssacc_bypass_stats_t)); +} diff --git a/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_address_translate.h b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_address_translate.h new file mode 100644 index 0000000..df0475d --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_address_translate.h @@ -0,0 +1,142 @@ +/****************************************************************************** + * @file icp_hssacc_address_translate.h + * + * @description Content of this file provides the prototypes for address + * translation functionality + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + *****************************************************************************/ +#ifndef ICP_HSSACC_ADDRESS_TRANSLATE_H +#define ICP_HSSACC_ADDRESS_TRANSLATE_H + +#include "icp.h" + + +/***************************************************************************** + * Abstract: + * Translate a Virtual address to a physical offset, includes Endianness + * Swapping if necessary. + * + *****************************************************************************/ +uint32_t +HssAccVirtToPhysAddressTranslateAndSwap(void* virtAddr); + + + +/***************************************************************************** + * Abstract: + * Translate a physical offset to a virtual address includes endianness + * swapping and platform specific bit manipulation where required. + * + *****************************************************************************/ +void * +HssAccPhysToVirtAddressSwapAndTranslate(uint32_t physAddr); + + +/***************************************************************************** + * Abstract: + * Translate a Virtual address to a physical offset. + * + *****************************************************************************/ +uint32_t +HssAccVirtToPhysAddressTranslate(void * const virtAddr); + + + +/***************************************************************************** + * Abstract: + * Translate a physical offset to a virtual address. + * + *****************************************************************************/ +void * +HssAccPhysToVirtAddressTranslate(const uint32_t physAddr); + + + +/***************************************************************************** + * Abstract: + * Allocate a chunk of memory for DMA communication with the TDM I/O Unit. + * returns the virtual address and the physical offset as an out parameter. + * virtual Address will be NULL if allocation failed and physAddr will be + * left un-touched. + * + *****************************************************************************/ +void * +HssAccDmaMemAllocate(uint32_t sizeBytes, + uint32_t * physAddr); + + + + +/***************************************************************************** + * Abstract: + * Swap Endianness on the data of an OSAL Buffer + * + *****************************************************************************/ +void +HssAccDataEndiannessSwap(IX_OSAL_MBUF * const buffer); + +#endif /* ICP_HSSACC_ADDRESS_TRANSLATE_H */ diff --git a/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_channel_config.h b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_channel_config.h new file mode 100644 index 0000000..c355b94 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_channel_config.h @@ -0,0 +1,269 @@ +/******************************************************************************* + * + * @file icp_hssacc_channel_config.h + * + * @description Content of this file is the Prototype definition of the API for + * the Channel Configuration module and all related Data structures shared + * by this module. + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + ******************************************************************************/ + + +#ifndef ICP_HSSACCCHANNELCONFIG_H +#define ICP_HSSACCCHANNELCONFIG_H + +#include "icp.h" +#include "icp_hssacc.h" +#include "icp_hssacc_port_config.h" + + +#define BIT_SET(index) (1 << index) + + +/* + * ---------------------------------------------------------------------------- + * Enumerated types + * ---------------------------------------------------------------------------- + */ + +/* Enum for the various states a channel can be in */ +typedef enum +{ + ICP_HSSACC_CHANNEL_UNINITIALISED = 0, + ICP_HSSACC_CHANNEL_ALLOCATED, + ICP_HSSACC_CHANNEL_CONFIGURED, + ICP_HSSACC_CHANNEL_SERVICE_CONFIGURED, + ICP_HSSACC_CHANNEL_DOWN, + ICP_HSSACC_CHANNEL_ENABLED, + ICP_HSSACC_CHANNEL_DOWN_TRANSITION +} icp_hssacc_channel_state_t; + + + +/* + Definition of the structure containing all Channel + configuration Data +*/ +typedef struct icp_hssacc_channel_config_s +{ + icp_hssacc_channel_state_t state; /* Current state of the channel */ + icp_hssacc_channel_type_t type; /* Voice or data */ + unsigned size; /* Size of the channel in timeslots */ + unsigned portId; /* HSS port number for the channel */ + icp_hssacc_line_t lineId; /* TDM line number for the channel */ + uint32_t timeslotMap; /* Timeslots reserved for the channel */ + uint32_t sdcCtrlReg; /* Common channel settings */ + uint32_t rxCfg; /* HDLC Rx settings */ + uint32_t txCfg; /* HDLC Tx settings */ + icp_boolean_t dataPolarity; /* polarity of the data */ + icp_hssacc_bit_endian_t bitEndian; /* specifies endianness of the chan */ + icp_boolean_t byteSwap; /* byteSwapping on/off */ + icp_hssacc_robbed_bit_value_t rBitValue; /* value 0/1 of robbed bit */ + icp_hssacc_robbed_bit_location_t rBitLocation; + /* location of the robbed bit in the byte */ + icp_hssacc_bit_robbing_t bitRobbing; /* bit robbing used or not */ + + /* HDLC specific */ + icp_hssacc_hdlc_sof_flag_type_t sofFlagType; /* start of frame */ + icp_hssacc_hdlc_idle_pattern_t hdlcTxIdlePattern; /* idle pattern to Tx */ + icp_hssacc_hdlc_idle_pattern_t hdlcRxIdlePattern; /* expected idle on rx */ + icp_hssacc_hdlc_crc_bit_width_t hdlcCrcBitWidth; /* CRC size */ + uint32_t hdlcMaxFrSize; /* maximum frame size on rx */ + + /* VOICE specific */ + uint32_t voiceSampleSize; /* size of voice samples */ + uint8_t voiceIdlePattern; /* voice silence pattern */ + icp_hssacc_channel_voice_tx_idle_action_t txIdleAction; + /* tx silence or repeat last frame */ + + unsigned numBypasses; /* channel can be involved in up to 2 bypasses, + one as source, one as destination */ +} icp_hssacc_channel_config_t; + +/* ---------------------------------------------------------------------------- + * Function declarations + * ---------------------------------------------------------------------------- + */ +/***************************************************************************** + * Abstract: + * Initialise the Channel Configuration module + * + *****************************************************************************/ +icp_status_t +HssAccChannelConfigInit(void); + + +/***************************************************************************** + * Abstract: + * shutdown the Channel Configuration module + * + *****************************************************************************/ +icp_status_t +HssAccChannelConfigShutdown(void); + + + +/***************************************************************************** + * Abstract: + * Reset the internal stats gathered by this module + * + *****************************************************************************/ +void +HssAccChannelConfigStatsReset (void); + + + +/***************************************************************************** + * Abstract: + * display all stats gathered by this module. + * + *****************************************************************************/ +void +HssAccChannelConfigStatsShow (void); + + + +/***************************************************************************** + * Abstract: + * display the state of the specified channel + * + *****************************************************************************/ +void +HssAccChannelConfigStateShow (unsigned channelId); + + +/***************************************************************************** + * Abstract: + * check whether it is valid to configure a bypass on the specified + * channel. + * + *****************************************************************************/ +icp_boolean_t +HssAccChannelConfigValidBypass(const unsigned channelId, + const unsigned portId); + + +/***************************************************************************** + * Abstract: + * set the 2 specified channels as part of a bypass + * + *****************************************************************************/ +void +HssAccChannelBypassPairSet(unsigned srcChannelId, + unsigned destChannelId); + + +/***************************************************************************** + * Abstract: + * clear the 2 specified channels from any bypass connection + * + *****************************************************************************/ +void +HssAccChannelBypassPairClear(unsigned srcChannelId, + unsigned destChannelId); + + +/***************************************************************************** + * Abstract: + * query the service to which the specified channel is associated, Voice + * or HDLC. + * + *****************************************************************************/ +icp_hssacc_channel_type_t +HssAccChannelConfigTypeQuery (unsigned channelId); + + + +/***************************************************************************** + * Abstract: + * query the current state of the specified channel. + * + *****************************************************************************/ +icp_hssacc_channel_state_t +HssAccChannelConfigStateQuery (unsigned channelId); + + + +/***************************************************************************** + * Abstract: + * notify the Channel Configuration module that all buffers associated + * with this channel have been retrieved. + * + *****************************************************************************/ +void +HssAccChannelConfigBuffersClearedNotify (unsigned channelId); + + + +/***************************************************************************** + * Abstract: + * query whether there are any channels allocated on the specified port. + * + *****************************************************************************/ +icp_boolean_t +HssAccChannelConfigUsedChansOnPortFind (const unsigned portId); +#endif /* ICP_HSSACCCHANNELCONFIG_H */ diff --git a/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_channel_list.h b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_channel_list.h new file mode 100644 index 0000000..df939fc --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_channel_list.h @@ -0,0 +1,137 @@ +/****************************************************************************** + * @file icp_hssacc_channel_list.h + * + * @description Content of this file includes the prototypes for channel + * list manipulations + * + * @ingroup icp_HssAcc + * + * @revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + *****************************************************************************/ +#ifndef ICP_HSSACC_CHANNEL_LIST_H +#define ICP_HSSACC_CHANNEL_LIST_H + + +#include "icp.h" + +/***************************************************************************** + * Abstract + * Reset All the channels lists + * + *****************************************************************************/ +void HssAccChannelListsReset (void); + + +/***************************************************************************** + * Abstract + * Add a channel to one of the lists for processing. + * + *****************************************************************************/ +icp_status_t HssAccChannelListAdd (unsigned hssPortId, + unsigned chanId, + unsigned chanSize); + + + + +/***************************************************************************** + * Abstract + * Remove the specified channel from processing lists. + * + *****************************************************************************/ +icp_status_t HssAccChannelListRemove (unsigned hssPortId, + unsigned chanId, + unsigned chanSize); + + +/***************************************************************************** + * Abstract + * Retrieve the ID of the last channel being processed on a specific port + * and a specific list + * + *****************************************************************************/ +unsigned +HssAccChannelListLastPortChannelGet (unsigned portId, + icp_hssacc_channel_list_t listId); + +/***************************************************************************** + * Abstract + * Retrieve the prev channel to processed in the list this channel + * belongs to. + * + *****************************************************************************/ +unsigned +HssAccChannelListPrevChannelOnListGet(unsigned channelId); + + +/***************************************************************************** + * Abstract + * Reset the messaging stats for Channel List management. + * + *****************************************************************************/ +void +HssAccChannelListsStatsReset (void); + + +#endif diff --git a/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_common.h b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_common.h new file mode 100644 index 0000000..c839e53 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_common.h @@ -0,0 +1,978 @@ +/****************************************************************************** + * @file icp_hssacc_common.h + * + * @description this file contains value definitions and function prototypes + * that are common accross all the HSS Access component + * + * @revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + *****************************************************************************/ + + +#ifndef ICP_HSSACCCOMMON_H +#define ICP_HSSACCCOMMON_H + +#include "IxOsal.h" +#include "icp.h" +#include "IxPiuMh.h" +#include "IxPiuDl.h" +#include "icp_hssacc.h" + + +#if !defined(TDM_PRIVATE) +#define TDM_PRIVATE static +#else +#define TDM_PRIVATE +#endif +#ifdef IXP23XX +#define ICP_HSSACC_MAX_NUM_CHANNELS (128) +#endif +#ifdef TOLAPAI +#define ICP_HSSACC_MAX_NUM_CHANNELS (128) +#endif + + +/* + * This macro represents an invalid Channel + */ +#define ICP_HSSACC_INVALID_CHAN ICP_HSSACC_MAX_NUM_CHANNELS + + + +#ifdef TOLAPAI +#define ICP_HSSACC_MAX_NUM_PORTS 3 +#else +#ifdef IXP23XX +#define ICP_HSSACC_MAX_NUM_PORTS 4 +#endif +#endif + +#define ICP_HSSACC_MAX_NUM_VOICE_BYPASS_GCTS 4 + +#define ICP_HSSACC_MAX_NUM_VOICE_BYPASSES 4 + +/* ---------------------------------------------------------------------------- + * Externs + * ---------------------------------------------------------------------------- + */ +/* Mutex which controls access to control path functions */ +extern IxOsalMutex hssAccControlPathMutex; + + +/* ---------------------------------------------------------------------------- + * Defines and Macros. + * ---------------------------------------------------------------------------- + */ +/* + * Timeout value in ms + */ +#define ICP_HSSACC_MUTEX_TIMEOUT 10 + +/* + * Initialises the service mutex. + */ +#define ICP_HSSACC_MUTEX_INIT() (ixOsalMutexInit(&hssAccControlPathMutex)) + +/* + * Locks the service mutex. + */ +#define ICP_HSSACC_MUTEX_LOCK() (ixOsalMutexLock( \ + &hssAccControlPathMutex,\ + ICP_HSSACC_MUTEX_TIMEOUT)) + +/* + * Unlocks the service mutex. + */ +#define ICP_HSSACC_MUTEX_UNLOCK() (ixOsalMutexUnlock(&hssAccControlPathMutex)) + +/* + * Destroys the service mutex. + */ +#define ICP_HSSACC_MUTEX_DESTROY() (\ + ixOsalMutexDestroy(&hssAccControlPathMutex)) + +/* + * The bit offset for byte 0 in a TDM I/O Unit message + */ +#define ICP_HSSACC_TDM_IO_UNIT_BYTE0_OFFSET (24) + +/* + * The byte mask for byte 0 in a TDM I/O Unit message + */ +#define ICP_HSSACC_TDM_IO_UNIT_BYTE0_MASK (0xFF << \ + ICP_HSSACC_TDM_IO_UNIT_BYTE0_OFFSET) + +/* + * The bit offset for byte 1 in a TDM I/O Unit message + */ +#define ICP_HSSACC_TDM_IO_UNIT_BYTE1_OFFSET (16) + +/* + * The byte mask for byte 1 in a TDM I/O Unit message + */ +#define ICP_HSSACC_TDM_IO_UNIT_BYTE1_MASK (0xFF << \ + ICP_HSSACC_TDM_IO_UNIT_BYTE1_OFFSET) + +/* + * The bit offset for byte 2 in a TDM I/O Unit message + */ +#define ICP_HSSACC_TDM_IO_UNIT_BYTE2_OFFSET (8) + +/* + * The byte mask for byte 2 in a TDM I/O Unit message + */ +#define ICP_HSSACC_TDM_IO_UNIT_BYTE2_MASK (0xFF << \ + ICP_HSSACC_TDM_IO_UNIT_BYTE2_OFFSET) + +/* + * The bit offset for byte 3 in a TDM I/O Unit message + */ +#define ICP_HSSACC_TDM_IO_UNIT_BYTE3_OFFSET (0) + +/* + * The byte mask for byte 3 in a TDM I/O Unit message + */ +#define ICP_HSSACC_TDM_IO_UNIT_BYTE3_MASK (0xFF << \ + ICP_HSSACC_TDM_IO_UNIT_BYTE3_OFFSET) + + + +/* + * The byte offset for Short 0 in a TDM I/O Unit message + */ +#define ICP_HSSACC_TDM_IO_UNIT_SHORT0_OFFSET (16) + +/* + * The byte mask for short 0 in a TDM I/O Unit message + */ +#define ICP_HSSACC_TDM_IO_UNIT_SHORT0_MASK (0xFFFF << \ + ICP_HSSACC_TDM_IO_UNIT_SHORT0_OFFSET) + +/* + * The byte offset for Short 1 in a TDM I/O Unit message + */ +#define ICP_HSSACC_TDM_IO_UNIT_SHORT1_OFFSET 0 + +/* + * The byte mask for Short 1 in a TDM I/O Unit message + */ +#define ICP_HSSACC_TDM_IO_UNIT_SHORT1_MASK (0xFFFF << \ + ICP_HSSACC_TDM_IO_UNIT_SHORT1_OFFSET) + + +/* + * The size of a word in bytes + */ +#define ICP_HSSACC_WORD_SIZE 4 + + +/* Mask to determine whether an address is aligned on a double + word boundary or not */ +#define ICP_HSSACC_DBLE_WD_ALIGN_MASK 0x7 + + +/* + * Mechanism to validate the upper (MAX) and lower (0) bounds + * of a positive enumeration + * + * param int [in] VALUE - the integer value to test + * param int [in] MAX - the maximum value to test against + * + * This macro returns TRUE if the bounds are invalid and FALSE if + * they are okay. NOTE: MAX will be an invalid value, so check >= + * + */ +#define ICP_HSSACC_ENUM_INVALID(VALUE, MAX) ((((VALUE) < 0) || \ + ((VALUE) >= (MAX))) ? \ + TRUE : FALSE) + + +/* + * TDM I/O Unit message commands + */ +/* + * HDMA configuration commands + */ + +/* + * Port configuration commands + */ +#define ICP_HSSACC_TDM_IO_UNIT_PORT_CFG_TABLE_LOAD (0x20) +#define ICP_HSSACC_TDM_IO_UNIT_PORT_CFG_TABLE_LOAD_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_PORT_CFG_TABLE_LOAD +#define ICP_HSSACC_TDM_IO_UNIT_PORT_ENABLE (0x21) +#define ICP_HSSACC_TDM_IO_UNIT_PORT_ENABLE_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_PORT_ENABLE +#define ICP_HSSACC_TDM_IO_UNIT_PORT_DISABLE (0x22) +#define ICP_HSSACC_TDM_IO_UNIT_PORT_DISABLE_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_PORT_DISABLE +#define ICP_HSSACC_TDM_IO_UNIT_PORT_PROV_TABLE_LOAD (0x23) +#define ICP_HSSACC_TDM_IO_UNIT_PORT_PROV_TABLE_LOAD_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_PORT_PROV_TABLE_LOAD +#define ICP_HSSACC_TDM_IO_UNIT_PORT_PROV_TABLE_SWAP (0x24) +#define ICP_HSSACC_TDM_IO_UNIT_PORT_PROV_TABLE_SWAP_DONE \ + ICP_HSSACC_TDM_IO_UNIT_PORT_PROV_TABLE_SWAP +#define ICP_HSSACC_TDM_IO_UNIT_PORT_ERROR_READ (0x25) +#define ICP_HSSACC_TDM_IO_UNIT_PORT_ERROR_READ_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_PORT_ERROR_READ +#define ICP_HSSACC_TDM_IO_UNIT_PORT_CFG_TABLE_READ (0x26) +#define ICP_HSSACC_TDM_IO_UNIT_PORT_CFG_TABLE_READ_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_PORT_CFG_TABLE_READ +#ifdef IXP23XX +#define ICP_HSSACC_TDM_IO_UNIT_PORT_TS_REMAP_TABLE_LOAD (0x27) +#define ICP_HSSACC_TDM_IO_UNIT_PORT_TS_REMAP_TABLE_LOAD_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_PORT_TS_REMAP_TABLE_LOAD +#define ICP_HSSACC_TDM_IO_UNIT_PORT_TS_REMAP_TABLE_READ (0x28) +#define ICP_HSSACC_TDM_IO_UNIT_PORT_TS_REMAP_TABLE_READ_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_PORT_TS_REMAP_TABLE_READ +#endif + +/* + * Queue configuration commands + */ +#define ICP_HSSACC_TDM_IO_UNIT_HSS_PORT_CFG (0x40) +#define ICP_HSSACC_TDM_IO_UNIT_HSS_PORT_CFG_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_HSS_PORT_CFG +#define ICP_HSSACC_TDM_IO_UNIT_HSS_CHAN_CFG (0x41) +#define ICP_HSSACC_TDM_IO_UNIT_HSS_CHAN_CFG_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_HSS_CHAN_CFG +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_CHAN_CFG (0x42) +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_CHAN_CFG_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_HDLC_CHAN_CFG +#define ICP_HSSACC_TDM_IO_UNIT_VOICE_CHAN_CFG (0x43) +#define ICP_HSSACC_TDM_IO_UNIT_VOICE_CHAN_CFG_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_VOICE_CHAN_CFG +#define ICP_HSSACC_TDM_IO_UNIT_NEXT_CHAN_WRITE (0x44) +#define ICP_HSSACC_TDM_IO_UNIT_NEXT_CHAN_WRITE_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_NEXT_CHAN_WRITE +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_CHAN_RX_MAX_SIZE_WR (0x45) +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_CHAN_RX_MAX_SIZE_WR_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_HDLC_CHAN_RX_MAX_SIZE_WR +#define ICP_HSSACC_TDM_IO_UNIT_CHAN_FLOW_ENABLE (0x46) +#define ICP_HSSACC_TDM_IO_UNIT_CHAN_FLOW_ENABLE_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_CHAN_FLOW_ENABLE +#define ICP_HSSACC_TDM_IO_UNIT_CHAN_FLOW_DISABLE (0x47) +#define ICP_HSSACC_TDM_IO_UNIT_CHAN_FLOW_DISABLE_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_CHAN_FLOW_DISABLE +#define ICP_HSSACC_TDM_IO_UNIT_ABT_ALN_ERR_READ (0x48) +#define ICP_HSSACC_TDM_IO_UNIT_ABT_ALN_ERR_READ_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_ABT_ALN_ERR_READ +#define ICP_HSSACC_TDM_IO_UNIT_FCS_MAX_ERR_READ (0x49) +#define ICP_HSSACC_TDM_IO_UNIT_FCS_MAX_ERR_READ_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_FCS_MAX_ERR_READ +#define ICP_HSSACC_TDM_IO_UNIT_STATS_READ (0x4A) +#define ICP_HSSACC_TDM_IO_UNIT_STATS_READ_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_STATS_READ +#define ICP_HSSACC_TDM_IO_UNIT_BYPASS_ENABLE (0x4B) +#define ICP_HSSACC_TDM_IO_UNIT_BYPASS_ENABLE_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_BYPASS_ENABLE +#define ICP_HSSACC_TDM_IO_UNIT_BYPASS_DISABLE (0x4C) +#define ICP_HSSACC_TDM_IO_UNIT_BYPASS_DISABLE_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_BYPASS_DISABLE +#define ICP_HSSACC_TDM_IO_UNIT_GCT_LOAD (0x4D) +#define ICP_HSSACC_TDM_IO_UNIT_GCT_LOAD_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_GCT_LOAD +#define ICP_HSSACC_TDM_IO_UNIT_BYPASS_GAIN_CFG (0x4E) +#define ICP_HSSACC_TDM_IO_UNIT_BYPASS_GAIN_CFG_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_BYPASS_GAIN_CFG +#define ICP_HSSACC_TDM_IO_UNIT_TX_CHAN_Q_ADDR_CFG (0x4F) +#define ICP_HSSACC_TDM_IO_UNIT_TX_CHAN_Q_ADDR_CFG_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_TX_CHAN_Q_ADDR_CFG + + +#define ICP_HSSACC_TDM_IO_UNIT_TX_Q_CFG (0xA0) +#define ICP_HSSACC_TDM_IO_UNIT_TX_Q_CFG_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_TX_Q_CFG +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_RX_Q_CFG (0xA1) +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_RX_Q_CFG_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_HDLC_RX_Q_CFG +#define ICP_HSSACC_TDM_IO_UNIT_VOICE_RX_Q_CFG (0xA2) +#define ICP_HSSACC_TDM_IO_UNIT_VOICE_RX_Q_CFG_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_VOICE_RX_Q_CFG +#define ICP_HSSACC_TDM_IO_UNIT_TX_Q_HEAD_CTR_CFG (0xA3) +#define ICP_HSSACC_TDM_IO_UNIT_TX_Q_HEAD_CTR_CFG_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_TX_Q_HEAD_CTR_CFG +#define ICP_HSSACC_TDM_IO_UNIT_TX_Q_TAIL_CTR_CFG (0xA4) +#define ICP_HSSACC_TDM_IO_UNIT_TX_Q_TAIL_CTR_CFG_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_TX_Q_TAIL_CTR_CFG +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_RX_Q_READER_CFG (0xA5) +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_RX_Q_READER_CFG_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_HDLC_RX_Q_READER_CFG +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_RX_Q_WRITER_CFG (0xA6) +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_RX_Q_WRITER_CFG_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_HDLC_RX_Q_WRITER_CFG +#define ICP_HSSACC_TDM_IO_UNIT_VOICE_RX_Q_READER_CFG (0xA7) +#define ICP_HSSACC_TDM_IO_UNIT_VOICE_RX_Q_READER_CFG_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_VOICE_RX_Q_READER_CFG +#define ICP_HSSACC_TDM_IO_UNIT_VOICE_RX_Q_WRITER_CFG (0xA8) +#define ICP_HSSACC_TDM_IO_UNIT_VOICE_RX_Q_WRITER_CFG_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_VOICE_RX_Q_WRITER_CFG +#define ICP_HSSACC_TDM_IO_UNIT_HSS_INT_CFG (0xA9) +#define ICP_HSSACC_TDM_IO_UNIT_HSS_INT_CFG_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_HSS_INT_CFG +#define ICP_HSSACC_TDM_IO_UNIT_HSS_TIMER_CFG (0xAA) +#define ICP_HSSACC_TDM_IO_UNIT_HSS_TIMER_CFG_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_HSS_TIMER_CFG +#define ICP_HSSACC_TDM_IO_UNIT_OFFS_TABLE_LOAD (0xAB) +#define ICP_HSSACC_TDM_IO_UNIT_OFFS_TABLE_LOAD_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_OFFS_TABLE_LOAD +#define ICP_HSSACC_TDM_IO_UNIT_OFFS_TABLE_READ (0xAC) +#define ICP_HSSACC_TDM_IO_UNIT_OFFS_TABLE_READ_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_OFFS_TABLE_READ + + +#define ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_STATUS (0x80) +#define ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ (0x81) +#define ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ + + +/* interval in TDM I/O Unit cycles at which the TDM I/O Unit is to + service the Software Queues */ +#ifdef TOLAPAI +#define ICP_HSSACC_TDM_IO_UNIT_HSS_TIMER_INTERVAL (133000) +#else +#ifdef IXP23XX +#define ICP_HSSACC_TDM_IO_UNIT_HSS_TIMER_INTERVAL (100000) +#endif +#endif + +#ifdef TOLAPAI +#define ICP_HSSACC_TDM_IO_UNIT_MAX_TRANSACTION_SIZE_WRDS (14) +#else +#ifdef IXP23XX +#define ICP_HSSACC_TDM_IO_UNIT_MAX_TRANSACTION_SIZE_WRDS (9) +#endif +#endif + +#define ICP_HSSACC_TDM_IO_UNIT_HSS_INT_DISABLED (0) +#define ICP_HSSACC_TDM_IO_UNIT_HSS_INT_ENABLED (1) + +/* Channel Stats codes for Stat Read TDM I/O Unit message */ + +#define ICP_HSSACC_TDM_IO_UNIT_CHAN_STAT_ABT_ALN (0) +#define ICP_HSSACC_TDM_IO_UNIT_CHAN_STAT_MAX_SIZE (1) +#define ICP_HSSACC_TDM_IO_UNIT_CHAN_STAT_FCS (2) +#ifndef NDEBUG +#define ICP_HSSACC_TDM_IO_UNIT_CHAN_STAT_RX_PKTS (3) +#define ICP_HSSACC_TDM_IO_UNIT_CHAN_STAT_TX_PKTS (4) +#endif + +#ifdef IXP23XX +/* LUT defines used in the creation of the timeslot allocation + tables to be sent to the TDM I/O Unit */ +#define ICP_HSSACC_TDM_IO_UNIT_WORDS_PER_LUT (8) +#define ICP_HSSACC_TDM_IO_UNIT_LUT_WORD_FULL_ASSIGNMENT (0x55555555) +#define ICP_HSSACC_TDM_IO_UNIT_LUT_WORD_T1_ASSIGNMENT (0x5555) +#define ICP_HSSACC_TDM_IO_UNIT_LUT_E1_SIZE_WRDS (2) +#define ICP_HSSACC_TDM_IO_UNIT_LUT_DMVIP_SIZE_WRDS (4) +#define ICP_HSSACC_TDM_IO_UNIT_LUT_QMVIP_SIZE_WRDS (8) +#endif + + +/* Provision Table defines */ +#define ICP_HSSACC_TDM_IO_UNIT_PROV_TABLE_SZ (0x400) +#define ICP_HSSACC_TDM_IO_UNIT_TS_ENABLE (1) +#define ICP_HSSACC_TDM_IO_UNIT_CHAN_OFFSET (16) +#define ICP_HSSACC_TDM_IO_UNIT_TS_EN_BIT_OFFSET (23) +#define ICP_HSSACC_TDM_IO_UNIT_OFFSET_TABLE_SZ (0x200) + +/* Queue List configuration */ +#define ICP_HSSACC_TDM_IO_UNIT_CHAN_ADD_FLAG (0) +#define ICP_HSSACC_TDM_IO_UNIT_CHAN_DEL_FLAG (1) + +/* When adding/removing channels on a linked list for + * a port, these values are used to indicate whether the list is + * a Tx list or an Rx list + */ +#define IX_HSSACC_TDM_IO_UNIT_LIST_INDICATOR_TX (0) +#define IX_HSSACC_TDM_IO_UNIT_LIST_INDICATOR_RX (1) + +/* Defines for specifying the data flow direction which we are + enabling/disabling for this channel */ +#define ICP_HSSACC_TDM_IO_UNIT_FLOW_DIR_NEITHER (0) +#define ICP_HSSACC_TDM_IO_UNIT_FLOW_DIR_TX_ONLY (1) +#define ICP_HSSACC_TDM_IO_UNIT_FLOW_DIR_RX_ONLY (2) +#define ICP_HSSACC_TDM_IO_UNIT_FLOW_DIR_BOTH (3) + + +/* Queue Configuration parameters for QMgr component */ +#define ICP_HSSACC_VOICE_RX_WATERMARK (1) +#define ICP_HSSACC_HDLC_RX_WATERMARK (1) +#define ICP_HSSACC_TX_WATERMARK (1) + + +/* SDC Control Register Offset and Masks */ +#define ICP_HSSACC_TDM_IO_UNIT_SDC_CHAN_TYPE_VOICE (2) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_CHAN_TYPE_HDLC (0) + +#define ICP_HSSACC_TDM_IO_UNIT_SDC_BIT_ROBBING_OFFSET (14) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_RBIT_LOC_OFFSET (12) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_RBIT_VAL_OFFSET (9) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_INVERT_OFFSET (8) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_CHAN_TYPE_OFFSET (6) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_BIT_REVERSE_OFFSET (5) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_BYTE_SWAP_OFFSET (4) + +#define ICP_HSSACC_TDM_IO_UNIT_SDC_BIT_NO_REVERSE (0) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_BIT_REVERSE (1) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_BYTE_NO_SWAP (0) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_BYTE_SWAP (1) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_BIT_INVERT_ON (1) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_BIT_INVERT_OFF (0) + +#define ICP_HSSACC_TDM_IO_UNIT_SDC_RBIT_ONE_BIT_ON (1) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_RBIT_OFF (0) + +#define ICP_HSSACC_TDM_IO_UNIT_SDC_RBIT_VALUE_ZERO (0) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_RBIT_VALUE_ONE (1) + +#define ICP_HSSACC_TDM_IO_UNIT_SDC_RBIT_LOC_ZERO (1) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_RBIT_LOC_SEVEN (0) + +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_IDLE_FLAG (0) +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_IDLE_ONES (1) + +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_32_BIT_CRC (1) +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_16_BIT_CRC (0) + +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_SOF_SHARED (0) +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_SOF_ONE (1) +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_SOF_TWO (2) + + + + +#define ICP_HSSACC_TDM_IO_UNIT_SDC_CTRL_MSB_MASK (0xFF00) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_CTRL_MSB_OFFSET (8) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_CTRL_LSB_MASK (0xFF) + + +/* HDLC TX & RX CFG Registers Offsets */ +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_TX_CFG_IM_OFFSET (0) +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_TX_CFG_FCS_OFFSET (1) +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_TX_CFG_SF_OFFSET (3) +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_TX_CFG_POSTBF_OFFSET (5) + +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_RX_CFG_IM_OFFSET (0) +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_RX_CFG_FCS_OFFSET (1) +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_RX_CFG_PREBF_OFFSET (3) + +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_CFG_BIT_FLIP (1) +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_CFG_NO_BIT_FLIP (0) + + + + +/* HDMA Register Offset Definitions */ +/* Port Configuration Register Common Section */ +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_FT_OFFSET (30) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_FS_OFFSET (28) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_FE_OFFSET (27) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_DE_OFFSET (26) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_CLKDIR_OFFSET (25) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_FR_OFFSET (24) +#ifdef TOLAPAI +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_CS_OFFSET (23) +#endif +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_RATE_OFFSET (21) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_DP_OFFSET (20) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_BITEND_OFFSET (19) +#ifdef TOLAPAI +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_REFF_OFFSET (17) +#endif + +/* Port Configuration Register Tx Section */ +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_OD_OFFSET (18) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_EN_OFFSET (16) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_TX_PCR_LB_OFFSET (15) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_56KTYPE_OFFSET (13) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_UTYPE_OFFSET (11) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_FB_OFFSET (10) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_56KEND_OFFSET (9) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_56KSEL_OFFSET (8) + + +/* Port Configuration Register Rx Section */ +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_RX_PCR_LB_OFFSET (16) + + +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_LB_ON (1) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_LB_OFF (0) + +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_CLKDIR_INPUT (0) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_CLKDIR_OUTPUT (1) +#ifdef TOLAPAI +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_CS_INT (0) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_CS_EXT_REF (1) +#endif + + +/* Frame Configuration Register */ +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_FBIT_OFFSET (31) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_OFFSET_OFFSET (16) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_MVIP_SWITCH_OFFSET (7) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_MVIP_SETTING_OFFSET (6) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_INT_OFFSET (5) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_FRAME_SIZE_OFFSET (0) + +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_FRAME_SIZE_T1_IN_TS (23) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_FRAME_SIZE_E1_IN_TS (31) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_FRAME_SIZE_T1_IN_BITS (193) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_FRAME_SIZE_E1_IN_BITS (256) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_FRAME_SIZE_DUAL_MVIP_IN_BITS \ + (ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_FRAME_SIZE_E1_IN_BITS * 2) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_FRAME_SIZE_QUAD_MVIP_IN_BITS \ + (ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_FRAME_SIZE_E1_IN_BITS * 4) + +/* The HSS co-processor register values to be added to OFFSET in the + * case of TX and data in the HSSFCR */ +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_OFFSET_TX_ADD_CLK_RATE (0x13) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_OFFSET_TX_ADD_HALF_CLK_RATE (0x11) + +/* value to be added to OFFSET in the case of FBIT being set in the FCR */ +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_OFFSET_FBIT_ADDITION (7) + + +/* Image Configuration Register */ +#ifdef IXP23XX +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_ICR_VOICE_CHANNELISATION_OFFSET (20) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_ICR_PINGPONG_OFFSET (19) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_ICR_PHO_OFFSET (8) +/* Ping Pong */ +#define ICP_HSSACC_TDM_IO_UNIT_HSS_PING_PONG_ENABLED (1) +/* Voice channelisation. */ +#define ICP_HSSACC_TDM_IO_UNIT_HSS_VCH_ENABLED (0) +#endif +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_ICR_PID_OFFSET (16) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_ICR_PBA_OFFSET (0) + +#define ICP_HSSACC_TDM_IO_UNIT_HSS_HDMA_RX_PBA_0 (1) +#define ICP_HSSACC_TDM_IO_UNIT_HSS_HDMA_RX_PBA_1 (3) +#define ICP_HSSACC_TDM_IO_UNIT_HSS_HDMA_RX_PBA_2 (5) +#ifdef IXP23XX +#define ICP_HSSACC_TDM_IO_UNIT_HSS_HDMA_RX_PBA_3 (7) +#endif +#define ICP_HSSACC_TDM_IO_UNIT_HSS_HDMA_TX_PBA_0 (0) +#define ICP_HSSACC_TDM_IO_UNIT_HSS_HDMA_TX_PBA_1 (2) +#define ICP_HSSACC_TDM_IO_UNIT_HSS_HDMA_TX_PBA_2 (4) +#ifdef IXP23XX +#define ICP_HSSACC_TDM_IO_UNIT_HSS_HDMA_TX_PBA_3 (6) +#endif + +/*The port image depth as a power of 2. + The port image depth is always 32*4 = 128 no matter + how many timeslots are assigned*/ +#define ICP_HSSACC_TDM_IO_UNIT_HSS_HDMA_PID_SHIFT (7) + +/* CLK CR */ +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_CLKCR_MAIN_OFFSET (22) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_CLKCR_DENOM_OFFSET (0) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_CLKCR_NUM_OFFSET (12) + +#ifdef IXP23XX +/* HCR */ +#define ICP_HSSACC_TDM_IO_UNIT_HSS_SUB_FRAME_DELTA_OFFSET (32) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_HCR_FRAME_BASE_OFFSET (8) + +/* VCR */ +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_VCR_FRAME_BASE_OFFSET (8) +#endif + +/* CWR */ +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_CWR_TX_CW2_ENABLE_OFFSET (31) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_CWR_TX_CW2_ADDRESS_OFFSET (24) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_CWR_TX_CW1_ENABLE_OFFSET (23) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_CWR_TX_CW1_ADDRESS_OFFSET (16) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_CWR_RX_CW2_ENABLE_OFFSET (15) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_CWR_RX_CW2_ADDRESS_OFFSET (8) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_CWR_RX_CW1_ENABLE_OFFSET (7) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_CWR_RX_CW1_ADDRESS_OFFSET (0) + +/* + Context wakeup Enabling. +*/ +/* 1 means on. 0 means off */ +#define ICP_HSSACC_TDM_IO_UNIT_HSS_TX_CW1_ENABLED (1) +#define ICP_HSSACC_TDM_IO_UNIT_HSS_RX_CW1_ENABLED (1) +#define ICP_HSSACC_TDM_IO_UNIT_HSS_TX_CW1_DISABLED (0) +#define ICP_HSSACC_TDM_IO_UNIT_HSS_RX_CW1_DISABLED (0) +#define ICP_HSSACC_TDM_IO_UNIT_HSS_TX_CW2_ENABLED (1) +#define ICP_HSSACC_TDM_IO_UNIT_HSS_RX_CW2_ENABLED (1) +#define ICP_HSSACC_TDM_IO_UNIT_HSS_TX_CW2_DISABLED (0) +#define ICP_HSSACC_TDM_IO_UNIT_HSS_RX_CW2_DISABLED (0) + + + +/* TDM IO UNIT Software Error codes and Bitmask offsets */ +#define ICP_HSSACC_TDM_IO_UNIT_RX_VOICE_Q_OVERFLOW (0x2) +#define ICP_HSSACC_TDM_IO_UNIT_RX_HDLC_Q_OVERFLOW (0x3) +#define ICP_HSSACC_TDM_IO_UNIT_RX_VOICE_FIFO_OVERFLOW (0x4) +#define ICP_HSSACC_TDM_IO_UNIT_RX_HDLC_FIFO_OVERFLOW (0x5) +#define ICP_HSSACC_TDM_IO_UNIT_RX_VOICE_FREE_Q_UNDERFLOW (0x6) +#define ICP_HSSACC_TDM_IO_UNIT_RX_HDLC_FREE_Q_UNDERFLOW (0x7) +#define ICP_HSSACC_TDM_IO_UNIT_MSG_OUT_FIFO_LP_OVERFLOW (0xa) +#define ICP_HSSACC_TDM_IO_UNIT_MSG_OUT_FIFO_HP_OVERFLOW (0xb) + +/* + * Error Bitmask offset definitions + */ +#ifdef TOLAPAI +#define ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_PORT_RX_PARITY (5) +#define ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_PORT_TX_PARITY (4) +#endif +#define ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_PORT_RX_FLOW (3) +#define ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_PORT_TX_FLOW (2) +#define ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_PORT_RX_LOSS (1) +#define ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_PORT_TX_LOSS (0) + + +#ifdef IXP23XX +#define ICP_HSSACC_TDM_IO_UNIT_ERR_ALL_PORT_MASK (0xFFFFFF) +#else +#define ICP_HSSACC_TDM_IO_UNIT_ERR_ALL_PORT_MASK (0x3FFFF) +#endif +#define ICP_HSSACC_TDM_IO_UNIT_ERR_SGLE_PORT_MASK (0x3F) +#define ICP_HSSACC_TDM_IO_UNIT_NEXT_PORT_SHIFT (6) + +#define ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_MSG_OUT_FIFO_H (23) +#define ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_RX_V_FREE_UNDERF (19) +#define ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_RX_H_FREE_UNDERF (18) +#define ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_RX_V_INT_FIFO_OVERF (17) +#define ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_RX_H_INT_FIFO_OVERF (16) +#define ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_MSG_OUT_FIFO_L (3) +#define ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_RX_H_Q_OVERF (2) +#define ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_RX_V_Q_OVERF (1) + + +/* + * The maximum number of timeslots available on a TDM trunk. + */ +#define ICP_HSSACC_MAX_TIMESLOTS_PER_TDM_LINE (32) +#define ICP_HSSACC_TIMESLOTS_PER_T1_LINE (24) + + +/* + * The number of TDM trunks per HSS port. + */ +#define ICP_HSSACC_MAX_TDM_LINES_PER_PORT (4) + +/* + * The maximum number of timeslots available on a HSS port. + */ +#define ICP_HSSACC_MAX_TIMESLOTS_PER_PORT (\ + ICP_HSSACC_MAX_TIMESLOTS_PER_TDM_LINE * \ + ICP_HSSACC_MAX_TDM_LINES_PER_PORT) + + + +/* System Clock divider definitions for the TDM I/O Unit HDMA coprocessor */ +#ifdef IXP23XX +#define ICP_HSSACC_HDMA_SYSCLK_1544KHZ { 64,147,197 } +#define ICP_HSSACC_HDMA_SYSCLK_2048KHZ { 48, 52, 63 } +#define ICP_HSSACC_HDMA_SYSCLK_8192KHZ { 12, 52,255 } +#else +#ifdef TOLAPAI +#define ICP_HSSACC_HDMA_SYSCLK_1544KHZ { 43,28,192 } +#define ICP_HSSACC_HDMA_SYSCLK_2048KHZ { 32, 135, 255 } +#define ICP_HSSACC_HDMA_SYSCLK_8192KHZ { 8, 135,1023 } +#endif +#endif + + + +/* ---------------------------------------------------------------------------- + * Application Specific Duals + * ---------------------------------------------------------------------------- + */ +#define ICP_HSSACC_TDM_IO_UNIT_CPP_COPROC (0x09) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_COPROC (0x02) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_RD_HDLC_INST (0x09) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_WR_HDLC_INST (0x0C) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_RD_VOICE_INST (0x12) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_WR_VOICE_INST (0x02) +#define ICP_HSSACC_TDM_IO_UNIT_CPP_RD_WORD_INST (0x0C) +#define ICP_HSSACC_TDM_IO_UNIT_CPP_WR_WORD_INST (0x08) + +/* ---------------------------------------------------------------------------- + * Structure definitions + * ---------------------------------------------------------------------------- + */ +/* + * structure of stats for TDM I/O Unit messages with responses + */ +typedef struct icp_hssacc_msg_with_resp_stats_s +{ + uint32_t numTdmIOUnitMessagesSent; + uint32_t numTdmIOUnitRespReceived; + uint32_t numTdmIOUnitTimeoutErrs; + uint32_t numTdmIOUnitInvalidResp; +} icp_hssacc_msg_with_resp_stats_t; + + +/* This is a set of identifiers for the + * channel linked lists + */ +typedef enum icp_hssacc_channel_list_s +{ + ICP_HSSACC_CHANNEL_LIST_PRIMARY = 0, + ICP_HSSACC_CHANNEL_LIST_SECONDARY_0, + ICP_HSSACC_CHANNEL_LIST_SECONDARY_1, + ICP_HSSACC_CHANNEL_LIST_DELIMITER +} icp_hssacc_channel_list_t; + + +/* + This is the list of all the channel lists used by the + HSS I/O Access library +*/ +typedef enum icp_hssacc_tdm_io_unit_channel_list_s +{ + ICP_HSSACC_TDM_IO_UNIT_LIST_TX_PRIMARY = 0, + ICP_HSSACC_TDM_IO_UNIT_LIST_TX_SECONDARY_0, + ICP_HSSACC_TDM_IO_UNIT_LIST_TX_SECONDARY_1, + ICP_HSSACC_TDM_IO_UNIT_LIST_RX_PRIMARY, + ICP_HSSACC_TDM_IO_UNIT_LIST_RX_SECONDARY_0, + ICP_HSSACC_TDM_IO_UNIT_LIST_RX_SECONDARY_1, + ICP_HSSACC_TDM_IO_UNIT_LIST_DELIMITER +} icp_hssacc_tdm_io_unit_channel_list_t; + + +/***************************************************************************** + * Abstract + * HssAcc Receive queue reader counters. + * Used by the HssAcc component to access + * counters written solely by the TDM I/O unit. + * + * + *****************************************************************************/ +typedef struct icp_hssacc_rx_q_read_counters_s +{ + uint32_t rxFreeTail; + uint32_t rxHead; +} __attribute__((packed)) icp_hssacc_rx_q_read_counters_t; + + +/***************************************************************************** + * Abstract + * HssAcc queue reader counters. Used by the HssAcc component to access + * counters written solely by the TDM I/O unit. + * + * Purpose + * Should be used by the access layer to read the counters written by the + * TDM I/O unit. + * + * Fields + * txTail - an array of 1-byte counters for each Tx queue. + * voiceRxCounters.rxFreeTail - a 4-byte counter for the voice Rx free + * tail counter. Only the lower 2 bytes + * are used. + * voiceRxCounters.rxHead - a 4-byte counter for the voice Rx head + * counter. Only the lower 2 bytes are used. + * hdlcRxCounters.rxFreeTail - a 4-byte counter for the HDLC Rx free + * tail counter. Only the lower 2 bytes + * are used. + * hdlcRxCounters.rxHead - a 4-byte counter for the HDLC Rx head + * counter. Only the lower 2 bytes are used. + * + *****************************************************************************/ +typedef struct icp_hssacc_queue_reader_counters_s +{ + /* The tail counters for each of the Tx queues */ + uint8_t txTail[ICP_HSSACC_MAX_NUM_CHANNELS]; + + /* The voice Rx free tail and rx head counters */ + icp_hssacc_rx_q_read_counters_t voiceRxCounters; + + /* The HDLC Rx free tail and rx head counters */ + icp_hssacc_rx_q_read_counters_t hdlcRxCounters; +} __attribute__((packed,aligned(4))) icp_hssacc_queue_reader_counters_t; + + + +/***************************************************************************** + * Abstract + * HssAcc Receive queue writer counters. + * These counters are read by the TDM I/O unit + * and written by HssAcc. + * + *****************************************************************************/ +typedef struct icp_hssacc_rx_q_write_counters_s +{ + uint32_t rxFreeHead; + uint32_t rxTail; +} __attribute__((packed)) icp_hssacc_rx_q_write_counters_t; + + + +/***************************************************************************** + * Abstract + * HssAcc queue writer counters. These counters are read by the TDM I/O unit + * and written by HssAcc. + * + * Purpose + * Should be used by the access layer to update the counters read by the + * TDM I/O unit. + * + * Fields + * txHeadCounters - an array of 1-byte counters for each Tx queue. + * voiceRxCounters.rxFreeHead - a 4-byte counter for the voice Rx free + * head counter. Only the lower 2 bytes + * are used. + * voiceRxCounters.rxTail - a 4-byte counter for the voice Rx tail + * counter. Only the lower 2 bytes are used. + * hdlcRxCounters.rxFreeHead - a 4-byte counter for the HDLC Rx free + * head counter. Only the lower 2 bytes + * are used. + * hdlcRxCounters.rxTail - a 4-byte counter for the HDLC Rx tail + * counter. Only the lower 2 bytes are used. + * + *****************************************************************************/ +typedef struct icp_hssacc_queue_write_counters_s +{ + /* The head counters for all the Tx queues */ + uint8_t txHead[ICP_HSSACC_MAX_NUM_CHANNELS]; + + /* The voice Rx free head and rx tail counters */ + icp_hssacc_rx_q_write_counters_t voiceRxCounters; + + /* The HDLC Rx free head and rx tail counters */ + icp_hssacc_rx_q_write_counters_t hdlcRxCounters; +} __attribute__((packed,aligned(4))) icp_hssacc_queue_write_counters_t; + + + +/* ---------------------------------------------------------------------------- + * Function declarations + * ---------------------------------------------------------------------------- + */ + +/***************************************************************************** + * Abstract: + * Constructs a 2 word TDM I/O Unit message out of 4 individual bytes + * values and a full word value. + * + * + * Side Effects: + * The message will be written into pMessage->data[0] & pMessage->data[1]. + * + * Assumptions: + * None. + * + *****************************************************************************/ +void +HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + uint32_t byte0, + uint32_t byte1, + uint32_t byte2, + uint32_t byte3, + uint32_t word, + IxPiuMhMessage *pMessage); + + +/***************************************************************************** + * Abstract: + * Constructs a 2 word TDM I/O Unit message out of 8 individual byte values. + * + * Side Effects: + * The message will be written into pMessage->data[0] & pMessage->data[1]. + * + * Assumptions: + * None. + * + *****************************************************************************/ +void +HssAccComTdmIOUnitCmd8byteMsgCreate ( + uint32_t byte0, + uint32_t byte1, + uint32_t byte2, + uint32_t byte3, + uint32_t byte4, + uint32_t byte5, + uint32_t byte6, + uint32_t byte7, + IxPiuMhMessage *pMessage); + + +/***************************************************************************** + * Abstract: + * Submits a message to the TDM I/O Unit, waits for a response and verifies + * that the correct response was received. if responseWord is NULL then + * we are not expecting anything more than an ACK. + * + * + *****************************************************************************/ +icp_status_t +HssAccComTdmIOUnitMsgSendAndRecv( + IxPiuMhMessage message, + uint8_t response, + icp_hssacc_msg_with_resp_stats_t * stats, + uint32_t * responseWord); + +/***************************************************************************** + * Abstract: + * Displays Communication Stats relating to a single TDM I/O message + * + * + *****************************************************************************/ +void HssAccSingleMessageStatsShow (icp_hssacc_msg_with_resp_stats_t stat); + +#endif /* ICP_HSSACCCOMMON_H */ diff --git a/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_port_config.h b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_port_config.h new file mode 100644 index 0000000..407ccae --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_port_config.h @@ -0,0 +1,297 @@ +/****************************************************************************** + * @file icp_hssacc_port_config.h + * + * @description this contains the data structure definitions and function + * prototypes necessary for port configuration + * + * @ingroup icp_HssAcc + * + * @revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + *****************************************************************************/ + +#ifndef ICP_HSSACCPORTCONFIG_H +#define ICP_HSSACCPORTCONFIG_H + +#include "icp_hssacc.h" +#include "icp_hssacc_common.h" + + +/* Default Frame Pulse Widths for the TDM ports + Valid Range for Frame Pulse Width is 1 to 8 */ +#define ICP_HSSACC_RX_DFLT_FRM_PULSE_WIDTH 1 +#define ICP_HSSACC_TX_DFLT_FRM_PULSE_WIDTH 1 + +/* Enum for the enabled state of a port */ +typedef enum +{ + ICP_HSSACC_PORT_UNCONFIGURED = 0 , + ICP_HSSACC_PORT_CONFIGURED, + /* config written to memory but not to TDM I/O Unit */ + ICP_HSSACC_PORT_ENABLED + /* config written to TDM I/O Unit, port enabled */ +} icp_hssacc_port_state_t; + +/* + * Enum for each of the TDM lines on a HSS port + */ +typedef enum +{ + ICP_HSSACC_LINE_0 = 0, + ICP_HSSACC_LINE_1, + ICP_HSSACC_LINE_2, + ICP_HSSACC_LINE_3, + ICP_HSSACC_LINE_DELIMITER +} icp_hssacc_line_t; + + +/* + icp_hssacc_data_rate_t is used to specify the GCI setting of either + full line rate or half line rate +*/ +typedef enum + { + ICP_HSSACC_DATA_RATE_EQUALS_CLK_RATE = 0, + ICP_HSSACC_DATA_RATE_HALF_CLK_RATE, + ICP_HSSACC_DATA_RATE_TYPE_DELIMITER + } icp_hssacc_data_rate_t; + + +/* list of settings for the Frame Config Register MVIP ON/OFF bit */ +typedef enum +{ + ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_MVIP_SWITCH_OFF = 0, + ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_MVIP_SWITCH_ON, + ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_MVIP_SWITCH_DELIMITER +} icp_hssacc_hdma_mvip_switch_t; + + +/* list of settings for the Frame Config Register MVIP mode bit */ +typedef enum +{ + ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_MVIP_SETTING_DUAL = 0, + ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_MVIP_SETTING_QUAD, + ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_MVIP_SETTING_DELIMITER +} icp_hssacc_hdma_mvip_setting_t; + +/* + icp_hssacc_port_additional_internal_config_t is used to specify the + additional port configuration information that is not provided through + the HSS I/O Access API + */ +typedef struct icp_hssacc_port_additional_internal_config_s +{ + icp_hssacc_data_rate_t dataRate; + uint32_t frmPulseWidth; +} icp_hssacc_port_additional_internal_config_t; + +/* + combines the API provided port configuration data and the + internal only configuration +*/ +typedef struct icp_hssacc_port_full_config_s +{ + icp_hssacc_port_config_t cfg; /* Port config from API */ + icp_hssacc_port_additional_internal_config_t addCfg; + /* addtional config params needed internally */ +} icp_hssacc_port_full_config_t; + + + +/* + data structure containing all port registers + in the format required by the TDM I/O Unit +*/ +typedef struct icp_hssacc_hdma_port_config_s +{ +#ifdef IXP23XX + uint32_t tx_LUT[ICP_HSSACC_TDM_IO_UNIT_WORDS_PER_LUT]; + /* tx LUT for TDM slot assignments */ + uint32_t rx_LUT[ICP_HSSACC_TDM_IO_UNIT_WORDS_PER_LUT]; + /* rx LUT for TDM slot assignments */ +#endif + uint32_t tx_pcr; + uint32_t rx_pcr; + uint32_t tx_fcr; + uint32_t rx_fcr; + uint32_t tx_icr; +#ifdef IXP23XX + uint32_t tx_vcr; + uint32_t tx_hcr; +#endif + uint32_t rx_icr; +#ifdef IXP23XX + uint32_t rx_vcr; + uint32_t rx_hcr; +#endif + uint32_t clkcr; + uint32_t cwr; +} icp_hssacc_hdma_port_config_t; + + + +/* + internal data structure containing all information + related to port configuration +*/ +typedef struct icp_hssacc_port_internal_config_s +{ + icp_hssacc_port_state_t state; + icp_hssacc_port_full_config_t rx; + icp_hssacc_port_full_config_t tx; + icp_hssacc_hdma_port_config_t * hdmaPortCfgTableVirtAddr; + /* Virtual address of HDMA port cfg table*/ + icp_hssacc_clk_speed_t clkSpeed; +} icp_hssacc_port_internal_config_t; + + + +/* ---------------------------------------------------------------------------- + * Function declarations + * ---------------------------------------------------------------------------- + */ + +/***************************************************************************** + * Abstract: + * sub-module initialisation function + * + *****************************************************************************/ +icp_status_t +HssAccPortConfigInit(void); + + +/***************************************************************************** + * Abstract: + * sub-module shutdown function. + * + *****************************************************************************/ +icp_status_t +HssAccPortConfigShutdown(void); + + +/***************************************************************************** + * Abstract: + * Check the line, first and last TS position are compatible with the + * current port config. + * + *****************************************************************************/ +icp_status_t +HssAccPortLineValidCheck (unsigned portId, + icp_hssacc_line_t lineId, + unsigned firstTsPos, + unsigned lastTsPos); + + + +/***************************************************************************** + * Abstract: + * Retrieve the current state of the port (configgured/disabled/enabled). + * + *****************************************************************************/ +icp_hssacc_port_state_t +HssAccPortStateGet (unsigned portId); + + + + +/***************************************************************************** + * Abstract: + * reset the internal stats of this sub-module + * + *****************************************************************************/ +void +HssAccPortConfigStatsReset (void); + + + +/***************************************************************************** + * Abstract: + * print out the stats of this sub-module + * + *****************************************************************************/ +void +HssAccPortConfigStatsShow (void); + + + +/***************************************************************************** + * Abstract: + * check the validity of the specified Tx clk mode depending on + * the platform + * + *****************************************************************************/ +icp_boolean_t +HssAccPortConfigTxClkModeInvalid(icp_hssacc_clk_mode_t clkMode); + + + +/***************************************************************************** + * Abstract: + * check the validity of the specified Rx clk mode depending on + * the platform + * + *****************************************************************************/ +icp_boolean_t +HssAccPortConfigRxClkModeInvalid(icp_hssacc_clk_mode_t clkMode); + +#endif /* ICP_HSSACCPORTCONFIG_H */ diff --git a/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_port_hdma_reg_mgr.h b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_port_hdma_reg_mgr.h new file mode 100644 index 0000000..0d77dbe --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_port_hdma_reg_mgr.h @@ -0,0 +1,160 @@ +/******************************************************************************* + * + * @file icp_hssacc_port_hdma_reg_mgr.h + * + * @description Content of this file is the prototype definitions for the Port + * HDMA Register creation module + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + ******************************************************************************/ + +#ifndef ICP_HSSACC_PORT_HDMA_REG_MGR_H +#define ICP_HSSACC_PORT_HDMA_REG_MGR_H + + +#include "icp_hssacc.h" + + +/* icp_hssacc_hdma_reg_trans_t is used to specify register types of Tx or Rx */ +typedef enum +{ + ICP_HSSACC_HDMA_RX_REG_TYPE = 0, + /* Rx type register for the HSS Port Config registers */ + ICP_HSSACC_HDMA_TX_REG_TYPE, + /* Tx type register for the HSS Port Config registers */ + ICP_HSSACC_HDMA_REG_TYPE_DELIMITER + /* Delimiter for array sizes */ +} icp_hssacc_hdma_reg_trans_t; + + + +/***************************************************************************** + * Abstract: + * Create the Port Config Register Value for the TDM I/O Unit. + * + *****************************************************************************/ +void +HssAccHdmaMgrPCRCreate (icp_hssacc_hdma_reg_trans_t type, + const icp_hssacc_port_full_config_t *portConfig, + uint32_t *pcr); + + + +/***************************************************************************** + * Abstract: + * Create the Frame Config Register value for the TDM I/O Unit + * + *****************************************************************************/ +icp_status_t +HssAccHdmaMgrFCRCreate (icp_hssacc_hdma_reg_trans_t type, + icp_hssacc_clk_speed_t clkSpeed, + const icp_hssacc_port_full_config_t *portConfig, + uint32_t *fcr); + +/***************************************************************************** + * Abstract: + * Create the Image Config Register Value for the TDM I/O Unit. + * + *****************************************************************************/ +void +HssAccHdmaMgrICRCreate (icp_hssacc_hdma_reg_trans_t type, + unsigned hssPortId, + uint32_t *icr); + + + +/***************************************************************************** + * Abstract: + * Create the Clock Config Register Value for the TDM I/O Unit. + * + *****************************************************************************/ +void +HssAccHdmaMgrClkCRCreate (icp_hssacc_clk_speed_t clkSpeed, + uint32_t *clkCR); + + +/***************************************************************************** + * Abstract: + * Create the Context Wakeup Register for the TDM I/O Unit. + * + *****************************************************************************/ +void +HssAccHdmaMgrCWRCreate (icp_hssacc_clk_speed_t clkSpeed, + uint32_t *cwr); + + +#ifdef IXP23XX +/***************************************************************************** + * Abstract: + * create the Voice Config Regsiter Values for the TDM I/O Unit. + * + *****************************************************************************/ +void +HssAccHdmaMgrVCRCreate (uint32_t *vcr); +#endif + + +#endif /* ICP_HSSACC_PORT_HDMA_REG_MGR_H */ diff --git a/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_queues_config.h b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_queues_config.h new file mode 100644 index 0000000..936b091 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_queues_config.h @@ -0,0 +1,275 @@ +/******************************************************************************* + * + * @file icp_hssacc_queues_config.h + * + * @description Content of this file is the prototype defintions and data + * structure definitions for the Queue configuration module + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + ******************************************************************************/ +#ifndef ICP_HSSACCQUEUESCONFIG_H +#define ICP_HSSACCQUEUESCONFIG_H + +#include "IxQMgr.h" +#include "icp_hssacc_common.h" +#define ICP_HSSACC_RX_QUEUE_ENTRY_SIZE_IN_WORDS (1) +#define ICP_HSSACC_RX_QUEUE_ENTRY_SIZE_IN_BYTES \ + (ICP_HSSACC_RX_QUEUE_ENTRY_SIZE_IN_WORDS * \ + ICP_HSSACC_WORD_SIZE) + +/* The size of the queue descriptor. This is common to all queues */ +#define ICP_HSSACC_QUEUE_DESC_SIZE_IN_WORDS (4) +#define ICP_HSSACC_QUEUE_DESC_SIZE_IN_BYTES \ + (ICP_HSSACC_QUEUE_DESC_SIZE_IN_WORDS * \ + ICP_HSSACC_WORD_SIZE) + +/* + * HssAcc transmit queue settings + */ + +#define ICP_HSSACC_TX_QUEUE_DEPTH_POW_2 (7) +#define ICP_HSSACC_TX_QUEUE_DEPTH (1 << ICP_HSSACC_TX_QUEUE_DEPTH_POW_2) + +#define ICP_HSSACC_HDLC_TX_QUEUE_DEPTH_POW_2 (ICP_HSSACC_TX_QUEUE_DEPTH_POW_2) +#define ICP_HSSACC_HDLC_TX_QUEUE_DEPTH (ICP_HSSACC_TX_QUEUE_DEPTH) + +#define ICP_HSSACC_VOICE_TX_QUEUE_DEPTH_POW_2 (4) +#define ICP_HSSACC_VOICE_TX_QUEUE_DEPTH \ + (1 << ICP_HSSACC_VOICE_TX_QUEUE_DEPTH_POW_2) + +/* The maximum number of bytes required to accomodate one TX queue */ +#define ICP_HSSACC_TX_QUEUE_SIZE_IN_BYTES \ + ((ICP_HSSACC_TX_QUEUE_DEPTH) * \ + ICP_HSSACC_QUEUE_DESC_SIZE_IN_BYTES ) + + +/* + * HssAcc HDLC receive queue settings + */ +/* The depth of the HDLC RX queue */ +#define ICP_HSSACC_HDLC_RX_QUEUE_DEPTH_POW_2 (11) +#define ICP_HSSACC_HDLC_RX_QUEUE_DEPTH \ + (1 << ICP_HSSACC_HDLC_RX_QUEUE_DEPTH_POW_2) + +/* The total number of bytes required to accomodate the HDLC RX queue */ +#define ICP_HSSACC_HDLC_RX_QUEUE_SIZE_IN_BYTES \ + ((ICP_HSSACC_HDLC_RX_QUEUE_DEPTH) * \ + ICP_HSSACC_RX_QUEUE_ENTRY_SIZE_IN_BYTES ) + + +/* + * HssAcc HDLC receive free queue settings + */ +/* The depth of the HDLC RX free queue 2048*/ +#define ICP_HSSACC_HDLC_RX_FREE_QUEUE_DEPTH_POW_2 \ + (ICP_HSSACC_HDLC_RX_QUEUE_DEPTH_POW_2) + +#define ICP_HSSACC_HDLC_RX_FREE_QUEUE_DEPTH \ + (1 << ICP_HSSACC_HDLC_RX_FREE_QUEUE_DEPTH_POW_2) + +/* The total number of bytes required to accomodate the HDLC RX free queue */ +#define ICP_HSSACC_HDLC_RX_FREE_QUEUE_SIZE_IN_BYTES \ + ((ICP_HSSACC_HDLC_RX_FREE_QUEUE_DEPTH) * \ + ICP_HSSACC_QUEUE_DESC_SIZE_IN_BYTES ) + + +/* + * HssAcc Voice receive queue settings + */ +/* The depth of the voice RX queue */ +#define ICP_HSSACC_VOICE_RX_QUEUE_DEPTH_POW_2 (11) +#define ICP_HSSACC_VOICE_RX_QUEUE_DEPTH \ + (1 << ICP_HSSACC_VOICE_RX_QUEUE_DEPTH_POW_2) + +/* The total number of bytes required to accomodate the voice RX queue */ +#define ICP_HSSACC_VOICE_RX_QUEUE_SIZE_IN_BYTES \ + ((ICP_HSSACC_VOICE_RX_QUEUE_DEPTH) * \ + ICP_HSSACC_RX_QUEUE_ENTRY_SIZE_IN_BYTES ) + + +/* + * HssAcc Voice receive free queue settings + */ +/* The depth of the voice RX free queue, as a power of 2 */ +#define ICP_HSSACC_VOICE_RX_FREE_QUEUE_DEPTH_POW_2 \ + (ICP_HSSACC_VOICE_RX_QUEUE_DEPTH_POW_2) + +#define ICP_HSSACC_VOICE_RX_FREE_QUEUE_DEPTH \ + (1 << ICP_HSSACC_VOICE_RX_FREE_QUEUE_DEPTH_POW_2) + +/* The total number of bytes required to accomodate the voice RX free queue */ +#define ICP_HSSACC_VOICE_RX_FREE_QUEUE_SIZE_IN_BYTES \ + ((ICP_HSSACC_VOICE_RX_FREE_QUEUE_DEPTH) * \ + ICP_HSSACC_QUEUE_DESC_SIZE_IN_BYTES ) + + +/* + List of IDs for Receive Queues used with the TDM I/O Unit +*/ + +typedef enum icp_hssacc_receive_queues_e + { + ICP_HSSACC_VOICE_RX_Q = ICP_HSSACC_MAX_NUM_CHANNELS, + ICP_HSSACC_VOICE_RX_FREE_Q, + ICP_HSSACC_HDLC_RX_Q, + ICP_HSSACC_HDLC_RX_FREE_Q + } icp_hssacc_receive_queues_t; + + +#define ICP_HSSACC_NUM_RECEIVE_QS (4) + + + +/* Stats */ +typedef struct icp_hssacc_queues_config_stats_s +{ + icp_hssacc_msg_with_resp_stats_t txQCfg; + icp_hssacc_msg_with_resp_stats_t txChanQAddrCfg; + icp_hssacc_msg_with_resp_stats_t hdlcRxQCfg; + icp_hssacc_msg_with_resp_stats_t voiceRxQCfg; + icp_hssacc_msg_with_resp_stats_t txQHeadCfg; + icp_hssacc_msg_with_resp_stats_t txQTailCfg; + icp_hssacc_msg_with_resp_stats_t voiceRxQReaderCfg; + icp_hssacc_msg_with_resp_stats_t voiceRxQWriterCfg; + icp_hssacc_msg_with_resp_stats_t hdlcRxQReaderCfg; + icp_hssacc_msg_with_resp_stats_t hdlcRxQWriterCfg; +} icp_hssacc_queues_config_stats_t; + + + +/* ---------------------------------------------------------------------------- + * Function declarations + * ---------------------------------------------------------------------------- + */ +/***************************************************************************** + * Abstract: + * Initialise all the queues used between the access layer and the + * TDM I/O Unit + * + *****************************************************************************/ +icp_status_t +HssAccQueuesInit(void); + + +/***************************************************************************** + * Abstract: + * shutdown all the queues used between the access layer and the + * TDM I/O Unit + * + *****************************************************************************/ +icp_status_t +HssAccQueuesShutdown(void); + + +/***************************************************************************** + * Abstract: + * Voice and HDLC channels use queues of different sizes so when a + * channel gets allocated for a specific service we need to make sure + * the size is correct and up to date. + * + *****************************************************************************/ +icp_status_t +HssAccQueueConfigQSizeUpdate(uint32_t channelId, + icp_hssacc_channel_type_t type); + + +/***************************************************************************** + * Abstract: + * Reset this modules stats. + * + *****************************************************************************/ +void +HssAccQueuesConfigStatsReset (void); + + +/***************************************************************************** + * Abstract: + * Display all the stats inherent to this module. + * + *****************************************************************************/ +void +HssAccQueuesConfigStatsShow (void); + + +/***************************************************************************** + * Abstract: + * Retrieve the QMgr queue Id using the internal ID (channel number for + * Tx or rx queue ID) + * + *****************************************************************************/ +IxQMgrQId +HssAccQueueIdGet (uint32_t qIndexId); + +/***************************************************************************** + * Abstract: + * enables the callbacks within the QMgr component. + * + *****************************************************************************/ +icp_status_t +HssAccRxQueuesNotificationEnable(void); + + +#endif /* ICP_HSSACCQUEUESCONFIG_H */ diff --git a/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_rings.h b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_rings.h new file mode 100644 index 0000000..c272757 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_rings.h @@ -0,0 +1,170 @@ +/****************************************************************************** + * @file icp_hssacc_rings.h + * + * @description Content of the file provides Ring creation and manipulation + * functionality + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + *****************************************************************************/ + +#ifndef ICP_HSSACC_RINGS_H +#define ICP_HSSACC_RINGS_H + +/* Tx & Rx s/w ring routines */ +typedef struct icp_hssacc_dataplane_ring_s +{ + volatile uint32_t *content; + uint32_t size; + uint32_t mask; + volatile uint32_t tail; + volatile uint32_t head; +} icp_hssacc_dataplane_ring_t; + +/** + * @def IX_HSSACC_DATAPLANE_RING_ENTRY_ADD + * @brief puts an entry at the head of the sw ring and increments head + * counter + */ +#define ICP_HSSACC_DATAPLANE_RING_ENTRY_ADD(ring,entry) do { \ + icp_hssacc_dataplane_ring_t *pRing = &(ring); \ + pRing->content[pRing->head & pRing->mask] = ((uint32_t)(entry)); \ + pRing->head++; \ + } while (0) + +/** + * @def ICP_HSSACC_DATAPLANE_RING_ENTRY_REM + * @brief gets an entry from the tail of the sw ring and decrements tail + * counter + */ +#define ICP_HSSACC_DATAPLANE_RING_ENTRY_REM(ring,entry) do { \ + icp_hssacc_dataplane_ring_t *pRing = &(ring); \ + entry = pRing->content[pRing->tail & pRing->mask]; \ + pRing->tail++; \ + } while (0) + +/** + * @def ICP_HSSACC_DATAPLANE_RING_TAIL_ENTRY_GET + * @brief Get the entry at the tail of a sw Ring + */ +#define ICP_HSSACC_DATAPLANE_RING_TAIL_ENTRY_GET(ring) \ + (ring).content[ICP_HSSACC_DATAPLANE_RING_TAIL(ring)] + +/** + * @def ICP_HSSACC_DATAPLANE_RING_TAIL + * @brief Get the Tail pointer of a ring + */ +#define ICP_HSSACC_DATAPLANE_RING_TAIL(ring) \ + ((ring).tail & (ring).mask) + +/** + * @def ICP_HSSACC_DATAPLANE_RING_TAIL_INCR + * @brief Increment the Tail pointer of a ring + */ +#define ICP_HSSACC_DATAPLANE_RING_TAIL_INCR(ring) (ring).tail++ + +/** + * @def ICP_HSSACC_DATAPLANE_RING_HEAD_ENTRY_GET + * @brief Get the entry at the head of a sw ring + */ +#define ICP_HSSACC_DATAPLANE_RING_HEAD_ENTRY_GET(ring) \ + (ring).content[ICP_HSSACC_DATAPLANE_RING_HEAD(ring)] + +/** + * @def ICP_HSSACC_DATAPLANE_RING_HEAD + * @brief Get the Head pointer of a sw ring + */ +#define ICP_HSSACC_DATAPLANE_RING_HEAD(ring) \ + ((ring).head & (ring).mask) + +/** + * @def ICP_HSSACC_DATAPLANE_RING_HEAD_INCR + * @brief Increment the Head pointer of a sw ring + */ +#define ICP_HSSACC_DATAPLANE_RING_HEAD_INCR(ring) do { \ + (ring).head++; } while(0) + +/** + * @def ICP_HSSACC_DATAPLANE_RING_NUM_ENTRIES_GET + * @brief gets the number of entries currently in the sw ring + */ +#define ICP_HSSACC_DATAPLANE_RING_NUM_ENTRIES_GET(ring) \ + ((ring).head - (ring).tail) + +/** + * @def ICP_HSSACC_DATAPLANE_RING_FULL + * @brief tests whether the sw ring is full + */ +#define ICP_HSSACC_DATAPLANE_RING_FULL(ring) \ + (((ring).head - (ring).tail) == (ring).size) + +/** + * @def ICP_HSSACC_DATAPLANE_RING_EMPTY + * @brief tests whether the sw ring is empty + */ +#define ICP_HSSACC_DATAPLANE_RING_EMPTY(ring) \ + ((ring).head == (ring).tail) + + +#endif diff --git a/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_rx_datapath.h b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_rx_datapath.h new file mode 100644 index 0000000..62d18d3 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_rx_datapath.h @@ -0,0 +1,216 @@ +/****************************************************************************** + * @file icp_hssacc_rx_datapath.h + * + * @description Content of this file provides the function prototypes for the + * HSS I/O Access receive functionality + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + *****************************************************************************/ + +#ifndef ICP_HSSACC_RX_DP_H +#define ICP_HSSACC_RX_DP_H + +#include "IxOsal.h" +#include "icp.h" +#include "icp_hssacc.h" +#include "IxQMgr.h" + +#define ICP_HSSACC_RX_DP_CHAN_DESC_PTR_RING_SZ (256) + +/* Definition of watermark level for pre-emptive Voice traffic flow regulation, + this watermark is tuned following performance testing, at this point +it is assumed that flow regulation should begin early to prevent Speech latency +build-up. */ +#define ICP_HSSACC_RX_Q_WATERMARK_LEVEL (2) + + +void +HssAccRxQServiceCallback(IxQMgrQId qId, + IxQMgrCallbackId cbId); + +/****************************************************************************** + * Abstract: + * Initialise Rx datapath global variables + * + ******************************************************************************/ +icp_status_t +HssAccRxDatapathInit(void); + +/****************************************************************************** + * Abstract: + * Shut down Rx datapath Module. + * + *****************************************************************************/ +icp_status_t +HssAccRxDatapathShutdown(void); + + +/****************************************************************************** + * Abstract: + * Register rx callback and user context + * + ******************************************************************************/ +void +HssAccChannelRxCallbackRegister(uint32_t channelId, + icp_hssacc_rx_callback_t rxCallback, + icp_user_context_t userContext); + +/****************************************************************************** + * Abstract: + * Deregister rx callback and user context + * + ******************************************************************************/ +void +HssAccChannelRxCallbackDeregister(uint32_t channelId); + +/****************************************************************************** + * Abstract: + * Set max frame size for HDLC, must be done at init + * + *****************************************************************************/ +void +HssAccRxDatapathHdlcInit(uint32_t maxRxFrameSize); + +/****************************************************************************** + * Abstract: + * Set max frame size for voice, must be done at init + * + *****************************************************************************/ +void +HssAccRxDatapathVoiceInit(uint32_t maxRxFrameSize); + +/****************************************************************************** + * Abstract: + * Function to run the Q Mgr processing function and call + * associated callbacks + * + ******************************************************************************/ +icp_status_t +HssAccRxDatapathService(icp_hssacc_channel_type_t channelType); + + + +/****************************************************************************** + * Abstract: + * Retrieve all buffers in an Rx Free Queue if there are no initialized + * channels for the corresponding service + * + *****************************************************************************/ +icp_status_t +HssAccRxFreeQsBufsRetrieve(IX_OSAL_MBUF * * ppStartChainBuffer, + IX_OSAL_MBUF * * ppEndChainBuffer); + +/****************************************************************************** + * Abstract: + * Retrieve all buffers in a chain from Rx Ring for a specified channel + * + *****************************************************************************/ +icp_status_t +HssAccRxDatapathChanBufsRetrieve(uint32_t channelId, + IX_OSAL_MBUF * * startChainBuffer, + IX_OSAL_MBUF * * endChainBuffer); + +/****************************************************************************** + * Abstract: + * Print out the per-channel statistics + * + ******************************************************************************/ +void +HssAccRxDatapathChanStatsShow(uint32_t channelId); + + +/****************************************************************************** + * Abstract: + * Function to print out stats on replenishing + * + ******************************************************************************/ +void +HssAccRxDatapathReplenishStatsShow(icp_hssacc_channel_type_t serviceType); + +/****************************************************************************** + * Abstract: + * Reset the per-channel statistics + ******************************************************************************/ +void +HssAccRxDatapathChanStatsReset(uint32_t channelId); + + +/****************************************************************************** + * Abstract: + * Function to reset stats on replenishing + * + *****************************************************************************/ +void +HssAccRxDatapathReplenishStatsReset(icp_hssacc_channel_type_t serviceType); + + +/****************************************************************************** + * Abstract: + * Return the Max Rx Sample/Frame size configured for the specified Service + * + *****************************************************************************/ +uint32_t +HssAccRxDatapathMaxServiceFrameSizeGet(icp_hssacc_channel_type_t servType); +#endif diff --git a/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_tdm_io_queue_entry.h b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_tdm_io_queue_entry.h new file mode 100644 index 0000000..a6a286a --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_tdm_io_queue_entry.h @@ -0,0 +1,193 @@ +/****************************************************************************** + * @file icp_hssacc_tdm_io_queue_entry.h + * + * @description Content of this file contains the definition and access + * macros for the TDM I/O Queue Entry format + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + *****************************************************************************/ + +#ifndef ICP_HSSACC_TDM_IO_QUEUE_ENTRY_H +#define ICP_HSSACC_TDM_IO_QUEUE_ENTRY_H + + +/***************************************************************************** + * Definition of the Channel descriptor format + * + *****************************************************************************/ +typedef struct icp_hssacc_chan_desc_s +{ + /* In order to handle both Little and Big Endianness correctly, + this data struct contains the Length split into MSB and LSB fields. */ + uint8_t currBufLength_LSB; + uint8_t currBufLength_MSB; + uint8_t status; + uint8_t channelId; +} icp_hssacc_chan_desc_t; + +/***************************************************************************** + * Definition of the Queue Entry format for Tx and RxFree Queues + * + *****************************************************************************/ +typedef struct icp_hssacc_tdm_io_queue_entry_s +{ + /* this union allows us to manipulate and move around the entire data + struct as a single word,thus saving instructions for copies */ + union { + icp_hssacc_chan_desc_t strct; + uint32_t word; + } descriptor; + void * currBufData; + uint32_t packetLengthBytes; + IX_OSAL_MBUF * currBuf; +} icp_hssacc_tdm_io_queue_entry_t; + + + + +/***************************************************************************** + * Definition of the TDM I/O private section of the OSAL Buffer + * + *****************************************************************************/ +typedef struct icp_hssacc_osal_mbuf_tdm_io_section_s +{ + icp_hssacc_tdm_io_queue_entry_t tdm_io_entry; + IX_OSAL_MBUF * pNextBuf; + uint32_t reserved[3]; +} icp_hssacc_osal_mbuf_tdm_io_section_t; + + + +/***************************************************************************** + * Macros for accessing the different fields of a Queue Entry + * + *****************************************************************************/ + +#define ICP_TDM_IO_Q_ENTRY_CHANNEL_ID(entryPtr) \ + ((entryPtr)->descriptor.strct.channelId) + +#define ICP_TDM_IO_Q_ENTRY_STATUS(entryPtr) (entryPtr->descriptor.strct.status) + +#define ICP_TDM_IO_Q_ENTRY_CURR_BUF_LEN_MSB(entryPtr) \ + ((entryPtr)->descriptor.strct.currBufLength_MSB) + +#define ICP_TDM_IO_Q_ENTRY_CURR_BUF_LEN_LSB(entryPtr) \ + ((entryPtr)->descriptor.strct.currBufLength_LSB) + +#define ICP_TDM_IO_Q_ENTRY_DATA(entryPtr) ((entryPtr)->currBufData) + +#define ICP_TDM_IO_Q_ENTRY_PKT_LEN(entryPtr) ((entryPtr)->packetLengthBytes) + +#define ICP_TDM_IO_Q_ENTRY_OSAL_MBUF(entryPtr) ((entryPtr)->currBuf) + + + +/***************************************************************************** + * Macros for accessing the different fields of the TDM I/O Unit private section + * of the OSAL Buffer + * + *****************************************************************************/ + +#define ICP_OSAL_MBUF_TDM_SECT_CHANNEL_ID(mbufPtr) \ + (ICP_TDM_IO_Q_ENTRY_CHANNEL_ID((&((mbufPtr)->tdm_io_entry)))) + +#define ICP_OSAL_MBUF_TDM_SECT_STATUS(mbufPtr) \ + (ICP_TDM_IO_Q_ENTRY_STATUS((&((mbufPtr)->tdm_io_entry)))) + +#define ICP_OSAL_MBUF_TDM_SECT_CURR_BUF_LEN_MSB(mbufPtr) \ + (ICP_TDM_IO_Q_ENTRY_CURR_BUF_LEN_MSB((&((mbufPtr)->tdm_io_entry)))) + +#define ICP_OSAL_MBUF_TDM_SECT_CURR_BUF_LEN_LSB(mbufPtr) \ + (ICP_TDM_IO_Q_ENTRY_CURR_BUF_LEN_LSB((&((mbufPtr)->tdm_io_entry)))) + +#define ICP_OSAL_MBUF_TDM_SECT_DATA(mbufPtr) \ + (ICP_TDM_IO_Q_ENTRY_DATA((&((mbufPtr)->tdm_io_entry)))) + +#define ICP_OSAL_MBUF_TDM_SECT_PKT_LEN(mbufPtr) \ + (ICP_TDM_IO_Q_ENTRY_PKT_LEN((&((mbufPtr)->tdm_io_entry)))) + +#define ICP_OSAL_MBUF_TDM_SECT_NEXT_BUF(mbufPtr) \ + ((mbufPtr)->pNextBuf) + +#define ICP_OSAL_MBUF_TDM_SECT_OSAL_MBUF_START(mbufPtr) \ + (ICP_TDM_IO_Q_ENTRY_OSAL_MBUF((&((mbufPtr)->tdm_io_entry)))) + + +/***************************************************************************** + * Macros for handling the Packet Length field. these are used to manipulate + * the endianness of the field. + * + *****************************************************************************/ +#define ICP_OSAL_MBUF_TDM_SECT_LEN_MASK 0xFF +#define ICP_OSAL_MBUF_TDM_SECT_LEN_MSB_OFFSET 8 + +/* These macros will return as a byte number the MSB and LSB + respectively of a 2 byte packet length field */ +#define ICP_OSAL_MBUF_PKT_LEN_MSB(len) ((len >> ICP_OSAL_MBUF_TDM_SECT_LEN_MSB_OFFSET) & ICP_OSAL_MBUF_TDM_SECT_LEN_MASK) + +#define ICP_OSAL_MBUF_PKT_LEN_LSB(len) (len & ICP_OSAL_MBUF_TDM_SECT_LEN_MASK) + +#endif diff --git a/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_timeslot_allocation.h b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_timeslot_allocation.h new file mode 100644 index 0000000..815e289 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_timeslot_allocation.h @@ -0,0 +1,260 @@ +/******************************************************************************* + * + * @file icp_hssacc_timeslot_allocation.h + * + * @description Content of this file provides the main internal API for the + * timeslot allocation module used as part of channel Allocation and Deletion + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + ******************************************************************************/ + +#ifndef ICP_HSSACC_TIMESLOT_ALLOCATION_H +#define ICP_HSSACC_TIMESLOT_ALLOCATION_H + + + +#include "icp_hssacc_channel_config.h" + + +/***************************************************************************** + * Abstract + * Platform specific initialisation for this sub-module. + * + *****************************************************************************/ +icp_status_t HssAccTsAllocPlatformInit (void); + + + +/***************************************************************************** + * Abstract + * Initialisation of the sub-module. + * + *****************************************************************************/ +icp_status_t HssAccTsAllocInit (void); + + +/***************************************************************************** + * Abstract + * Shutdown this sub-module. + * + *****************************************************************************/ +void HssAccTsAllocShutdown (void); + +/***************************************************************************** + * Abstract + * Remove the allocation of timeslots associated with the specified + * channel. + * + *****************************************************************************/ +icp_status_t +HssAccTsAllocDelete (unsigned channelId, + icp_hssacc_channel_config_t * hssChannelData); + + +/***************************************************************************** + * Abstract + * Update the Timeslot provisioning table for the specified port. will + * also update the offset table for all ports. + * + *****************************************************************************/ +icp_status_t +HssAccTsAllocUpdate(unsigned portId, + const icp_hssacc_channel_config_t * hssChannelData); + + +/***************************************************************************** + * Abstract + * Setup an initial Timeslot allocation for correct behaviour of the + * specified port with no channels configured on it. + * + *****************************************************************************/ +icp_status_t +HssAccTsAllocInitialAllocationUpdate(unsigned portId); + + + + +#ifdef IXP23XX +/***************************************************************************** + * Abstract + * Create the Timeslot Look-up Table for the TDM I/O unit. + * + *****************************************************************************/ +icp_status_t +HssAccTxAllocLUTCreate (icp_hssacc_clk_speed_t clkSpeed, + uint32_t *pHssLUT); +#endif + +/***************************************************************************** + * Abstract + * Swap the Timeslot provisioning tables within the TDM I/O Unit. + * + *****************************************************************************/ +icp_status_t HssAccTsAllocTableSwap (unsigned hssPortId); + + + + +/***************************************************************************** + * Abstract + * returns the address of the Memory block allocated for the + * Timeslot provisioning Table. + * + *****************************************************************************/ +void * HssAccTsAllocHdmaProvTableVirtAddrGet (void); + + +/***************************************************************************** + * Abstract + * Returns the address of the memory block allocated for the timeslot + * offset table. + * + *****************************************************************************/ +void * HssAccTsAllocTdmIoUnitOffsetTableVirtAddrGet (void); + + +/***************************************************************************** + * Abstract + * Return a pointer to the stats for Swap message. + * + *****************************************************************************/ +icp_hssacc_msg_with_resp_stats_t * HssAccTsAllocSwapStatsGet(void); + + +/***************************************************************************** + * Abstract + * return a pointer to the stats for the Offset Table read message. + * + *****************************************************************************/ +icp_hssacc_msg_with_resp_stats_t * HssAccTsAllocOffsetTableReadStatsGet(void); + + + +/***************************************************************************** + * Abstract + * Read one word of the specified table. + * + *****************************************************************************/ +icp_status_t +HssAccTsAllocOffsetTableWordRead (icp_boolean_t readShadowTable, + uint16_t tableOffset, + uint32_t *tableWord); + + + + +/***************************************************************************** + * Abstract: + * Verify that all of the timeslots requested are not already in use. + * + *****************************************************************************/ +icp_boolean_t +HssAccTsAvailableVerify(unsigned portId, icp_hssacc_line_t lineId, + uint32_t tsMap); + + + +/***************************************************************************** + * Abstract: + * Register the timeslots specified for the specified channel. + * + *****************************************************************************/ +void +HssAccTsRegister(unsigned channelId, + unsigned portId, + icp_hssacc_line_t lineId, + uint32_t tsMap); + + +/***************************************************************************** + * Abstract: + * Unregister any timeslots associated with the specified channel. + * + *****************************************************************************/ +void +HssAccTsUnregister(unsigned portId, + icp_hssacc_line_t lineId, + uint32_t tsMap); + +/***************************************************************************** + * Abstract + * Display all the stats collecting within this module. + * + *****************************************************************************/ +void HssAccTsAllocStatsShow (void); + + +/***************************************************************************** + * Abstract + * Reset The stats for the Timeslot allocation module. + * + *****************************************************************************/ +void HssAccTsAllocStatsReset (void); + + + + +#endif /* #ifndef ICP_HSSACC_TIMESLOT_ALLOCATION_H */ diff --git a/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_trace.h b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_trace.h new file mode 100644 index 0000000..703f6e2 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_trace.h @@ -0,0 +1,339 @@ +/******************************************************************************* + * + * @file icp_hssacc_trace.h + * + * @description Content of this file provides Trace functionality for the + * component + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + ******************************************************************************/ + + +#ifndef ICP_HSSACC_TRACE_H +#define ICP_HSSACC_TRACE_H + + +/* ---------------------------------------------------------------------------- + * Includes + * ---------------------------------------------------------------------------- + */ +#include "IxOsal.h" + + +/* + * ---------------------------------------------------------------------------- + * Enumerated types + * ---------------------------------------------------------------------------- + */ + +/***************************************************************************** + * Enumeration defining HssAcc trace levels. + *****************************************************************************/ +typedef enum icp_hssacc_trace_level_e +{ + ICP_HSSACC_TRACE_OFF = 0, /**< NO TRACE */ + ICP_HSSACC_DEBUG = 1, /**< Select traces of interest */ + ICP_HSSACC_FN_ENTRY_EXIT = 2 /**< ALL function entry/exit traces + and all traces of interest */ +} icp_hssacc_trace_level_t; + + +/* ---------------------------------------------------------------------------- + * Defines and Macros. + * ---------------------------------------------------------------------------- + */ + +/***************************************************************************** + * The trace level for the HSS Acc Control path and Datapath blocks + * + * Description: + * This macro turns the debug trace on or off, depending on whether the + * code is compiled for debug or release. + * There are 3 levels allowed in the current compilation setup: + * if NDEBUG is not defined and DEBUG is not defined, then selected tracing + * will be done for the control path and the datapath tracing will be off. + * if NDEBUG is not defined and DEBUG is defined then all function + * entry/exits are on as well selected tracing for control and data paths. + * if NDEBUG is defined ALL tracing is off. + * + *****************************************************************************/ + +#ifdef DEBUG +#define ICP_HSSACC_TRACE_LEVEL ICP_HSSACC_FN_ENTRY_EXIT +#define ICP_HSSACC_DP_TRACE_LEVEL ICP_HSSACC_FN_ENTRY_EXIT +#else +#define ICP_HSSACC_TRACE_LEVEL ICP_HSSACC_TRACE_OFF +#define ICP_HSSACC_DP_TRACE_LEVEL ICP_HSSACC_TRACE_OFF +#endif + + + + + +/***************************************************************************** + * Mechanism for reporting HssAcc software errors + * + *****************************************************************************/ +#define ICP_HSSACC_REPORT_ERROR(STR) \ + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, \ + IX_OSAL_LOG_DEV_STDERR, \ + STR, 0, 0, 0, 0, 0, 0); + +/***************************************************************************** + * Mechanism for reporting HssAcc software errors with 1 argument + * + *****************************************************************************/ +#define ICP_HSSACC_REPORT_ERROR_1(STR,ARG1) \ + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, \ + IX_OSAL_LOG_DEV_STDERR, \ + STR, ARG1, 0, 0, 0, 0, 0); + +/***************************************************************************** + * Mechanism for reporting HssAcc software errors with 2 arguments + * + *****************************************************************************/ +#define ICP_HSSACC_REPORT_ERROR_2(STR,ARG1,ARG2) \ + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, \ + IX_OSAL_LOG_DEV_STDERR, \ + STR, ARG1, ARG2, 0, 0, 0, 0); + + +/***************************************************************************** + * Mechanism for tracing debug for the HssAcc component, with no arguments + * + * Note: + * This macro executes only in debug versions of the code. It does nothing + * in release code. + *****************************************************************************/ +#ifndef NDEBUG + #define ICP_HSSACC_TRACE_0(LEVEL, STR) \ + { \ + if (LEVEL <= ICP_HSSACC_TRACE_LEVEL) \ + { \ + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, \ + IX_OSAL_LOG_DEV_STDOUT, \ + STR, 0, 0, 0, 0, 0, 0); \ + } \ + } +#else + #define ICP_HSSACC_TRACE_0(LEVEL, STR) do { /* nothing */ } while(0) +#endif + +/***************************************************************************** + * Mechanism for tracing debug for the HssAcc component, with one argument + * + * Note: + * This macro executes only in debug versions of the code. It does nothing + * in release code. + *****************************************************************************/ +#ifndef NDEBUG + #define ICP_HSSACC_TRACE_1(LEVEL, STR, ARG1) \ + { \ + if (LEVEL <= ICP_HSSACC_TRACE_LEVEL) \ + { \ + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, \ + IX_OSAL_LOG_DEV_STDOUT, \ + STR, ARG1, 0, 0, 0, 0, 0); \ + } \ + } +#else + #define ICP_HSSACC_TRACE_1(LEVEL, STR, ARG1) do { /* nothing */ } while(0) +#endif + +/***************************************************************************** + * Mechanism for tracing debug for the HssAcc component, with two arguments + * + * Note: + * This macro executes only in debug versions of the code. It does nothing + * in release code. + *****************************************************************************/ +#ifndef NDEBUG + #define ICP_HSSACC_TRACE_2(LEVEL, STR, ARG1, ARG2) \ + { \ + if (LEVEL <= ICP_HSSACC_TRACE_LEVEL) \ + { \ + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, \ + IX_OSAL_LOG_DEV_STDOUT, \ + STR, ARG1, ARG2, 0, 0, 0, 0); \ + } \ + } +#else + #define ICP_HSSACC_TRACE_2(LEVEL, STR, ARG1, ARG2) do { } while(0) +#endif + +/***************************************************************************** + * Mechanism for tracing debug for the HssAcc component, with three arguments + * + * Note: + * This macro executes only in debug versions of the code. It does nothing + * in release code. + * + *****************************************************************************/ +#ifndef NDEBUG + #define ICP_HSSACC_TRACE_3(LEVEL, STR, ARG1, ARG2, ARG3) \ + { \ + if (LEVEL <= ICP_HSSACC_TRACE_LEVEL) \ + { \ + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, \ + IX_OSAL_LOG_DEV_STDOUT, \ + STR, ARG1, ARG2, ARG3, 0, 0, 0); \ + } \ + } +#else + #define ICP_HSSACC_TRACE_3(LEVEL, STR, ARG1, ARG2, ARG3) do { } while(0) +#endif + +/***************************************************************************** + * Mechanism for tracing debug for the HssAcc component, with four arguments + * + * Note: + * This macro executes only in debug versions of the code. It does nothing + * in release code. + * + *****************************************************************************/ +#ifndef NDEBUG + #define ICP_HSSACC_TRACE_4(LEVEL, STR, ARG1, ARG2, ARG3, ARG4) \ + { \ + if (LEVEL <= ICP_HSSACC_TRACE_LEVEL) \ + { \ + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, \ + IX_OSAL_LOG_DEV_STDOUT, \ + STR, ARG1, ARG2, ARG3, ARG4, 0, 0); \ + } \ + } +#else + #define ICP_HSSACC_TRACE_4(LEVEL, STR, ARG1, ARG2, ARG3, ARG4) do { } while(0) +#endif + + +/***************************************************************************** + * Mechanism for tracing debug for the HSS Acc Datapath block component, + * with no arguments + * + * Note: + * This macro executes only in debug versions of the code. It does nothing + * in release code. + *****************************************************************************/ +#ifndef NDEBUG + #define ICP_HSSACC_DP_TRACE_0(LEVEL, STR) \ + { \ + if (LEVEL <= ICP_HSSACC_DP_TRACE_LEVEL) \ + { \ + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, \ + IX_OSAL_LOG_DEV_STDOUT, \ + STR, 0, 0, 0, 0, 0, 0); \ + } \ + } +#else + #define ICP_HSSACC_DP_TRACE_0(LEVEL, STR) do { /* nothing */ } while(0) +#endif + +/***************************************************************************** + * Mechanism for tracing debug for the HssAcc Datapath component, + * with one argument + * + * Note: + * This macro executes only in debug versions of the code. It does nothing + * in release code. + *****************************************************************************/ +#ifndef NDEBUG + #define ICP_HSSACC_DP_TRACE_1(LEVEL, STR, ARG1) \ + { \ + if (LEVEL <= ICP_HSSACC_DP_TRACE_LEVEL) \ + { \ + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, \ + IX_OSAL_LOG_DEV_STDOUT, \ + STR, ARG1, 0, 0, 0, 0, 0); \ + } \ + } +#else + #define ICP_HSSACC_DP_TRACE_1(LEVEL, STR, ARG1) do { /* nothing */ } while(0) +#endif + +/***************************************************************************** + * Mechanism for tracing debug for the HssAcc Datapath component, + * with two arguments + * + * Note: + * This macro executes only in debug versions of the code. It does nothing + * in release code. + *****************************************************************************/ +#ifndef NDEBUG + #define ICP_HSSACC_DP_TRACE_2(LEVEL, STR, ARG1, ARG2) \ + { \ + if (LEVEL <= ICP_HSSACC_DP_TRACE_LEVEL) \ + { \ + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, \ + IX_OSAL_LOG_DEV_STDOUT, \ + STR, ARG1, ARG2, 0, 0, 0, 0); \ + } \ + } +#else + #define ICP_HSSACC_DP_TRACE_2(LEVEL, STR, ARG1, ARG2) do { } while(0) +#endif + + +#endif /* ICP_HSSACC_TRACE_H */ diff --git a/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_tx_datapath.h b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_tx_datapath.h new file mode 100644 index 0000000..4c6c722 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_tx_datapath.h @@ -0,0 +1,191 @@ +/******************************************************************************* + * + * @file icp_hssacc_tx_datapath.h + * + * @description Content of this file provides the internal API for the Transmit + * datapath module. + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + ******************************************************************************/ + +#ifndef ICP_HSSACC_TX_DATAPATH_H +#define ICP_HSSACC_TX_DATAPATH_H + +#include "icp_hssacc.h" + +/* Definition of watermark level for pre-emptive Voice traffic flow regulation, + this watermark is tuned following performance testing, at this point +it is assumed that flow regulation should begin early to prevent Speech latency +build-up. */ +#define ICP_HSSACC_TX_Q_WATERMARK_LEVEL (4) + +/* Voice packet length should be modulo 4. A pre-transmit voice buffer check +will bitwise AND the voice packet length with this value. */ +#define ICP_HSSACC_TX_VOICE_PACKET_LENGTH_CHECK_MASK (0x00000003) + + +/***************************************************************************** + * Abstract: + * Initialises this subcomponent (mutex...) and Resets the Tx Datapath + * internal data. + * + *****************************************************************************/ +icp_status_t +HssAccTxDatapathInit(void); + + +/***************************************************************************** + * Abstract: + * Destroys all allocated memory and mutexes for this component. + * + *****************************************************************************/ +icp_status_t +HssAccTxDatapathShutdown(void); + +/***************************************************************************** + * Abstract: + * updates the Type for specified channel, + * will potentially trigger a resizing of the Queue associated with this + * channel. + * + *****************************************************************************/ +icp_status_t +HssAccTxDatapathChanTypeUpdate (uint32_t channelId, + icp_hssacc_channel_type_t chanType); + + +/***************************************************************************** + * Abstract: + * Set or unset the channel as bypassed, will allow the component to prevent + * or allow Tx. + * + *****************************************************************************/ +icp_status_t +HssAccTxDatapathChanBypassStateSet(uint32_t channelId, + icp_boolean_t bypassed); + + +/***************************************************************************** + * Abstract: + * Register the Tx Done callback + * + *****************************************************************************/ +void +HssAccTxDatapathChanTxDoneCallbackRegister( + uint32_t channelId, + icp_hssacc_tx_done_callback_t txDoneCallback, + icp_user_context_t userContext); + +/***************************************************************************** + * Abstract: + * Deregister the Tx Done callback + * + *****************************************************************************/ +void +HssAccTxDatapathChanTxDoneCallbackDeregister(uint32_t channelId); + + +/***************************************************************************** + * Abstract: + * Triggers the servicing of all the Tx Queues, this will trigger TxDone + * callbacks when appropriate for each queue of type channelType. + * + *****************************************************************************/ +icp_status_t +HssAccTxDatapathService(icp_hssacc_channel_type_t channelType); + + + +/***************************************************************************** + * Abstract: + * Retrieve all buffers in the transmit path for specified channel + * + *****************************************************************************/ +icp_status_t +HssAccTxDatapathChannelBuffersRetrieve(uint32_t channelId, + IX_OSAL_MBUF * * startChainBuffer, + IX_OSAL_MBUF * * endChainBuffer); + + +/***************************************************************************** + * Abstract: + * Reset the stats for specified channel + * + *****************************************************************************/ +void +HssAccTxDatapathChanStatsReset(uint32_t channelId); + + + +/***************************************************************************** + * Abstract: + * Print out the stats for the specified channel + * + *****************************************************************************/ +void +HssAccTxDatapathChanStatsShow(uint32_t channelId); + +#endif diff --git a/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_voice_bypass.h b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_voice_bypass.h new file mode 100644 index 0000000..e59fec7 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_voice_bypass.h @@ -0,0 +1,115 @@ +/******************************************************************************* + * + * @file icp_hssacc_voice_bypass.h + * + * @description Content of this file provides the internal API for the Voice + * bypass module + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + ******************************************************************************/ + +#ifndef ICP_HSSACC_VOICE_BYPASS_H +#define ICP_HSSACC_VOICE_BYPASS_H + +#include "icp.h" + +/***************************************************************************** + * Abstract + * This function initialises the internals of the Voice Bypass + * sub-module. it can only be called once. + * + *****************************************************************************/ +void +HssAccVoiceBypassInit(void); + + +/***************************************************************************** + * Abstract + * This function shuts down the Voice Bypass submodule. the module + * must have been initialised beforehand. + * + *****************************************************************************/ +icp_status_t +HssAccVoiceBypassShutdown(void); + +/***************************************************************************** + * Abstract + * This function displays the internal gathered by this sub-module. + * + *****************************************************************************/ +void +HssAccBypassStatsShow (void); + + +/***************************************************************************** + * Abstract + * This function resets all the internal stats relating to this sub-module. + * + *****************************************************************************/ +void +HssAccBypassStatsReset (void); + +#endif diff --git a/Acceleration/library/icp_telephony/tdm_io_access/linux_2.6_kernel_space.mk b/Acceleration/library/icp_telephony/tdm_io_access/linux_2.6_kernel_space.mk new file mode 100644 index 0000000..325733d --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/linux_2.6_kernel_space.mk @@ -0,0 +1,76 @@ +################### +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# Contact Information: +# Intel Corporation +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# +################### + +#specific include directories in kernel space +INCLUDES+= -I $(ICP_OSAL_DIR)/platforms/EP805XX/include \ + -I $(ICP_OSAL_DIR)/platforms/EP805XX/os/linux/include \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/core \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules/ddk \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules/ioMem \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules/bufferMgt + + +#Extra Flags Specific in kernel space e.g. include path or debug flags etc. e.g to add an include path EXTRA_CFLAGS += -I$(src)/../include +EXTRA_CFLAGS += $(INCLUDES) -DTOLAPAI -D__tolapai -DEP805XX -D__ep805xx -DIX_HW_COHERENT_MEMORY=1 +EXTRA_LDFLAGS+=-whole-archive + diff --git a/Acceleration/library/icp_utils/OSAL/Makefile b/Acceleration/library/icp_utils/OSAL/Makefile new file mode 100644 index 0000000..47aa507 --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/Makefile @@ -0,0 +1,796 @@ +# +# Top level OSAL Makefile +# +# +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# + + +################################################################ +# Determine the target OS and Endian mode + +## IX_TARGET needs to be set as one of linuxbe/linuxle, vxle/vxbe. +## wince has its own build system. +# Added for NBCM config + +## Reuse IX_TARGET for TARGET_ENDIAN. +IX_OSAL_MK_TARGET_ENDIAN := $(IX_TARGET) + +# NOTE - this is case-sensitive +ifneq (,$(filter $(IX_TARGET), linuxbe linuxle)) +ifeq ($(IX_OSAL_OS_LEVEL), user_space) +IX_OSAL_MK_TARGET_OS := linux_user +else +IX_OSAL_MK_TARGET_OS := linux +endif + +else +IX_OSAL_MK_TARGET_OS := vxworks +endif + + +ifeq ($(IX_OSAL_MK_TARGET_OS), linux) +ifeq ($(IX_LINUXVER), 2.6.18) +IX_OSAL_OS_LINUX_VERSION := GT_2_6_18 +else +ifeq ($(IX_LINUXVER), 2.6.20) +IX_OSAL_OS_LINUX_VERSION := GT_2_6_18 +endif #2.6.20 +endif #2.6.18 +endif # IX_OSAL_MK_TARGET_OS = linux + +ICP_ROOT?=/vobs + +################################################################ +# assign the target platform +# + +IX_OSAL_MK_TGT_DEVICE := $(IX_DEVICE) + + +include platforms/$(IX_OSAL_MK_TGT_DEVICE)/os/$(IX_OSAL_MK_TARGET_OS)/make/OsalConfig.mk +################################################################ +# Determine the OSAL Optional Modules to build + +# NOTE - this is case-sensitive + +#OPTIONAL_MODULES := ioMem bufferMgt + +OPTIONAL_MODULES := + +ifdef ENABLE_IOMEM +OPTIONAL_MODULES := ioMem +endif + +ifdef ENABLE_BUFFERMGT +OPTIONAL_MODULES := $(OPTIONAL_MODULES) bufferMgt +endif + +ifeq ($(IX_OSAL_OS_LEVEL), user_space) +MODULES := $(OPTIONAL_MODULES) +else +# In kernel space ddk is an important module and cannot +# be made optional. +MODULES := ddk $(OPTIONAL_MODULES) +endif + + +################################################################ +# OSAL sub-directories (this layout is replicated in many places) +# + +OSAL_DIRS = . \ + core \ + $(MODULES:%=modules/%) + +################################################################ +# Output directories +# + +MAIN_SRC_PREFIX := common/src +OS_SRC_PREFIX := common/os/$(IX_OSAL_MK_TARGET_OS)/src + +MAIN_INC_PREFIX := common/include +OS_INC_PREFIX := common/os/$(IX_OSAL_MK_TARGET_OS)/include + +OBJ_BASE_DIR := lib/$(IX_OSAL_MK_TGT_DEVICE)/$(IX_OSAL_MK_TARGET_OS)/$(IX_OSAL_MK_TARGET_ENDIAN) + +SRC_DIRS := $(OSAL_DIRS:%=$(MAIN_SRC_PREFIX)/%) $(OSAL_DIRS:%=$(OS_SRC_PREFIX)/%) +SRC_DIRS += platforms/$(IX_OSAL_MK_TGT_DEVICE)/os/$(IX_OSAL_MK_TARGET_OS)/src + +ifeq ($(IX_OSAL_OS_LEVEL), user_space) +SRC_DIRS += common/POSIX/src +endif + +# Due to limitations of 'mkdir' on Windows, we need to make each +# subdirectory level in turn, so we build the list here + + +# We replicate the directory structure of the 'src' directory +# This makes it easier to relate dependencies between build objects, source files +# and the respective 'component.mk' files. +OUTPUT_DIRS := lib \ + lib/$(IX_OSAL_MK_TGT_DEVICE) \ + lib/$(IX_OSAL_MK_TGT_DEVICE)/$(IX_OSAL_MK_TARGET_OS) \ + lib/$(IX_OSAL_MK_TGT_DEVICE)/$(IX_OSAL_MK_TARGET_OS)/$(IX_OSAL_MK_TARGET_ENDIAN) \ + $(OBJ_BASE_DIR) \ + $(OBJ_BASE_DIR)/common \ + $(OBJ_BASE_DIR)/$(MAIN_SRC_PREFIX) \ + $(OBJ_BASE_DIR)/$(MAIN_SRC_PREFIX)/core \ + $(OBJ_BASE_DIR)/$(MAIN_SRC_PREFIX)/modules \ + $(MODULES:%=$(OBJ_BASE_DIR)/$(MAIN_SRC_PREFIX)/modules/%) \ + $(OBJ_BASE_DIR)/common/os \ + $(OBJ_BASE_DIR)/common/os/$(IX_OSAL_MK_TARGET_OS) \ + $(OBJ_BASE_DIR)/$(OS_SRC_PREFIX) \ + $(OBJ_BASE_DIR)/$(OS_SRC_PREFIX)/core \ + $(OBJ_BASE_DIR)/$(OS_SRC_PREFIX)/modules \ + $(MODULES:%=$(OBJ_BASE_DIR)/$(OS_SRC_PREFIX)/modules/%) + + +OUTPUT_DIRS += $(OBJ_BASE_DIR)/platforms \ + $(OBJ_BASE_DIR)/platforms/$(IX_OSAL_MK_TGT_DEVICE) \ + $(OBJ_BASE_DIR)/platforms/$(IX_OSAL_MK_TGT_DEVICE)/os \ + $(OBJ_BASE_DIR)/platforms/$(IX_OSAL_MK_TGT_DEVICE)/os/$(IX_OSAL_MK_TARGET_OS) \ + $(OBJ_BASE_DIR)/platforms/$(IX_OSAL_MK_TGT_DEVICE)/os/$(IX_OSAL_MK_TARGET_OS)/src + + +# POSIX directory structure for output +ifeq ($(IX_OSAL_OS_LEVEL), user_space) + + +OUTPUT_DIRS += $(OBJ_BASE_DIR)/common/POSIX \ + $(OBJ_BASE_DIR)/common/POSIX/src + +endif + +ifdef IX_OSAL_INTEG_TEST +OUTPUT_DIRS += $(OBJ_BASE_DIR)/common/test +endif + + +################################################################ +# Compiler & Linker commands and options +# + +# These macros are defined for the Target OS in the following file +# - IX_OSAL_MK_HOST_OS +# - CC +# - LD +# - AR +# - CFLAGS +# - LDFLAGS + +# Always have -Wall option ON for production build +CFLAGS += -Wall +#CFLAGS += -Wstrict-prototypes -Wmissing-prototypes -Wmissing-declarations + +include platforms/$(IX_OSAL_MK_TGT_DEVICE)/os/$(IX_OSAL_MK_TARGET_OS)/make/OemMake.mk +include common/os/${IX_OSAL_MK_TARGET_OS}/make/macros.mk + +# include any additional flags set by the user +CFLAGS += $(IX_OSAL_MK_CFLAGS) +LDFLAGS += $(IX_OSAL_MK_LDFLAGS) + +ifdef IX_EXTRA_WARNINGS +# Optional "aggressive" warning flags. These will produce a lot of warning +# messages about OS header files, but there should still be +# no warnings in Intel production code. +ifeq ($(TOOL_FAMILY),diab) +CFLAGS += -Wsign-compare -Wformat -Wstrict-prototypes -Wshadow -Wmissing-prototypes \ + -Wmissing-declarations -Wnested-externs -Winline \ + -fstrict-aliasing -fno-builtin -fsigned-char +else +CFLAGS += -Wsign-compare -Wformat -Wstrict-prototypes -Wshadow -Wmissing-prototypes \ + -Wmissing-declarations -Wnested-externs -Winline -Waggregate-return \ + -fstrict-aliasing -fno-builtin -fsigned-char +endif # ifeq ($(TOOL_FAMILY),diab) +endif + + +################################################################ +# Include directories +# + +INCLUDE_DIRS += common/include $(OSAL_DIRS:%=$(MAIN_INC_PREFIX)/%) $(OSAL_DIRS:%=$(OS_INC_PREFIX)/%) + +INCLUDE_DIRS += platforms/$(IX_OSAL_MK_TGT_DEVICE)/include +INCLUDE_DIRS += platforms/$(IX_OSAL_MK_TGT_DEVICE)/os/$(IX_OSAL_MK_TARGET_OS)/include + +### Include OSAL POSIX directories in user space. +ifeq ($(IX_OSAL_OS_LEVEL), user_space) +INCLUDE_DIRS += common/POSIX/include + +endif + +CFLAGS += $(INCLUDE_DIRS:%=-I%) -DIX_COMPONENT=1 + +ifdef IX_HW_COHERENT_MEMORY +CFLAGS += -DIX_HW_COHERENT_MEMORY +endif + +ifdef IX_OSAL_MEM_ASSERT_ON +CFLAGS += -DIX_OSAL_MEM_ASSERT_ON +endif + +ifdef IX_OSAL_INTEG_TEST +CFLAGS += -DIX_OSAL_INTEG_TEST +endif + + +# Enable appropriate flags in the code depending +# on the modules selected for the build. + +ifneq (,$(findstring ioMem,$(MODULES))) +CFLAGS += -DENABLE_IOMEM +endif + +ifneq (,$(findstring bufferMgt,$(MODULES))) +CFLAGS += -DENABLE_BUFFERMGT +endif + +ifneq (,$(findstring ddk,$(MODULES))) +CFLAGS += -DENABLE_DDK +endif + +################################################################ +# Other commands +# + +# A sed command to process the output of $(CC) -M. It prepends a +# directory name to the object filename and adds the .d file to the +# rule as a rule target, and then appends the name of this makefile +# and the component makefile corresponding to the particular object as +# a dependency. +# +# Note the use of '=' rather than ':=' so that the value of $* will +# be evaluated later, when we use the command within a template rule. +# +# Note where '$$' is used in the sed commands, 'make' interprets it as +# a single '$'. + +ifeq ($(TOOL_FAMILY),diab) +FILTER_DEPS = sed -e $(SAFE_QUOTE)s,$(notdir $*)\.o:,$(OBJ_BASE_DIR)$*.d $(OBJ_BASE_DIR)/$*.o: $(dir $*)component.mk Makefile,g$(SAFE_QUOTE) +else +ifneq ($(VX_VERSION),vx55) +FILTER_DEPS = sed -e $(SAFE_QUOTE)s,$(notdir $*)\.o,$(OBJ_BASE_DIR)$*.d $(OBJ_BASE_DIR)/$*.o,g$(SAFE_QUOTE) \ + -e '$$s,$$, $(dir $*)component.mk Makefile,' +else +FILTER_DEPS = sed -e $(SAFE_QUOTE)s,$(notdir $*)\.o,$(OBJ_BASE_DIR)$*.d $(OBJ_BASE_DIR)/$*.o,g$(SAFE_QUOTE) \ + -e $(SAFE_QUOTE)$$s,$$, $(dir $*)component.mk Makefile,$(SAFE_QUOTE) +endif #VX_VERSION +endif + +################################################################ +# Build platform specific macros +# +# These are : CMD_SEP : the string we use to seperate multiple +# commands on a single line. +# ECHO_QUOTE : to print leading whitespace with the unix +# shells' echo command, we need quotes. +# SAFE_QUOTE : the qoute character needed to enclose a +# 'sed' command. +# ECHO_BLANKLINE : The command to print an empty line. +# RM : unconditionally delete file(s) + +ifeq ($(IX_OSAL_MK_HOST_OS),windows) +ifeq ($(VXSHELL),ZSH) +# windows zsh settings +CMD_SEP := && +ECHO_QUOTE := "# " this comment is here to fix emacs syntax highlighting +ECHO_BACKSLASH := \# comment needed to keep \ away from end of line +SAFE_QUOTE := "# " this comment is here to fix emacs syntax highlighting +ECHO_BLANKLINE := echo " " +RM := vxrm +TOUCH_EMPTY_FILE := touch +else +# Windows settings +CMD_SEP := && +ECHO_QUOTE := # cmd.exe's echo command doesn't need quotes +ECHO_BACKSLASH := \# comment needed to keep \ away from end of line +SAFE_QUOTE := "# " this comment is here to fix emacs syntax highlighting +ECHO_BLANKLINE := @cmd.exe /c echo. +RM := vxrm +# Windows doesn't have a 'touch' command. Warning! Unlike Unix touch, +# this will overwrite the existing file! +TOUCH_EMPTY_FILE := echo. > +endif +else +# Unix settings +CMD_SEP := ; +ECHO_QUOTE := "# " this comment is here to fix emacs syntax highlighting +ECHO_BACKSLASH := \\ +SAFE_QUOTE := '# ' this comment is here to fix emacs syntax highlighting +ECHO_BLANKLINE := @echo +RM := rm -f +TOUCH_EMPTY_FILE := touch +endif + +# A command for printing trace messages in the makefile. +MAKEFILE_TRACE := @echo $(ECHO_QUOTE)--- Makefile: $(ECHO_QUOTE) # Use this setting to enable messages +#MAKEFILE_TRACE = @\# # Use this setting to disable messages + + +################################################################ +# Component makefiles +# + +# Each source directory should contain a component.mk file which contains +# a list of objects to be built and extra CFLAGS specific to the code in that directory + +# include component,mk files from all source directories +include $(SRC_DIRS:%=%/component.mk) + +# include test directory if want integration test suite +ifdef IX_OSAL_INTEG_TEST +include common/test/component.mk +endif + + + +################################################################ +# Platform makefiles +# + + +PLATFORM_MAIN_DIR := platforms/$(IX_OSAL_MK_TGT_DEVICE)/src +PLATFORM_OBJ := $(platform_OBJ:%=$(OBJ_BASE_DIR)/platforms/$(IX_OSAL_MK_TGT_DEVICE)/os/$(IX_OSAL_MK_TARGET_OS)/src/%) +PLATFORM_SRC :=$(subst .o,.c,$(platform_OBJ:%=platforms/$(IX_OSAL_MK_TGT_DEVICE)/os/$(IX_OSAL_MK_TARGET_OS)/src/%)) + +# Required for Parasoft +SOURCES := $(platform_OBJ:%.o=platforms/$(IX_OSAL_MK_TGT_DEVICE)/os/$(IX_OSAL_MK_TARGET_OS)/src/%.c) + +################################################################ +# Test makefiles +# +ifdef IX_OSAL_INTEG_TEST +TEST_MAIN_DIR := common/test +TEST_OBJ := $(test_OBJ:%=$(OBJ_BASE_DIR)/common/test/%) +endif + + + +################################################################ +# Core makefiles +# + +CORE_MAIN_DIR := $(MAIN_SRC_PREFIX)/core +CORE_OS_DIR := $(OS_SRC_PREFIX)/core + +# CORE_OBJ lists all of the object files in the OSAL Core directories, with path info +CORE_OBJ := $(core_OBJ:%=$(OBJ_BASE_DIR)/$(CORE_MAIN_DIR)/%) \ + $(core_os_OBJ:%=$(OBJ_BASE_DIR)/$(CORE_OS_DIR)/%) +CORE_SRC :=$(subst .o,.c,$(core_OBJ:%=$(CORE_MAIN_DIR)/%) $(core_os_OBJ:%=$(CORE_OS_DIR)/%)) + +# Required for Parasoft +SOURCES += $(core_OBJ:%.o=$(CORE_MAIN_DIR)/%.c) +SOURCES += $(core_os_OBJ:%.o=$(CORE_OS_DIR)/%.c) + +################################################################ +# POSIX makefiles +# + +ifeq ($(IX_OSAL_OS_LEVEL), user_space) +POSIX_MAIN_DIR := common/POSIX/src +POSIX_OBJ := $(POSIX_OBJS:%=$(OBJ_BASE_DIR)/common/POSIX/src/%) +POSIX_SRC :=$(subst .o,.c,$(POSIX_OBJS:%=common/POSIX/src/%)) + +# Required for Parasoft +SOURCES += $(POSIX_OBJS:%.o=common/POSIX/src/%.c) +endif + +################################################################ +# Optional module makefiles +# + +ifneq (0,$(words $(MODULES))) + +MODULE_MAIN_BASE_DIR := $(MAIN_SRC_PREFIX)/modules +MODULE_OS_BASE_DIR := $(OS_SRC_PREFIX)/modules + +# MODULE_OBJ lists all of the object files in the OSAL module directories, with path info +MODULE_OBJ := $(foreach m, $(MODULES), $($(m)_OBJ:%=$(OBJ_BASE_DIR)/$(MODULE_MAIN_BASE_DIR)/$(m)/%)) \ + $(foreach m, $(MODULES), $($(m)_os_OBJ:%=$(OBJ_BASE_DIR)/$(MODULE_OS_BASE_DIR)/$(m)/%)) +MODULE_SRC :=$(subst .o,.c,\ +$(foreach m,$(MODULES),$($(m)_OBJ:%=$(MODULE_MAIN_BASE_DIR)/$(m)/%)) \ +$(foreach m,$(MODULES),$($(m)_os_OBJ:%=$(MODULE_OS_BASE_DIR)/$(m)/%))) + +# Required for Parasoft +SOURCES += $(foreach m, $(MODULES), $($(m)_OBJ:%.o=$(MODULE_MAIN_BASE_DIR)/$(m)/%.c)) +SOURCES += $(foreach m, $(MODULES), $($(m)_os_OBJ:%.o=$(MODULE_OS_BASE_DIR)/$(m)/%.c)) + +endif + + +################################################################ +# Combined object list macros +# + +ALL_OBJ := $(PLATFORM_OBJ) $(CORE_OBJ) $(MODULE_OBJ) + +# Include POSIX directory when building for user space. +ifeq ($(IX_OSAL_OS_LEVEL),user_space) +ALL_OBJ += $(POSIX_OBJ) +endif + +ifdef COMP +ALL_RT_OBJ := $($(COMP)_OBJ) +ALL_RT_SRC := $($(COMP)_SRC) +else +ALL_RT_OBJ := $(ALL_OBJ) +#ALL_RT_OBJ := $(filter-out $(OBJ_BASE_DIR)/$(CORE_OS_DIR)/IxOsalOsThread.o,$(ALL_RT_OBJ)) +#ALL_RT_SRC :=$(PLATFORM_SRC) $(CORE_SRC) +ALL_RT_SRC :=$(MODULE_SRC) $(PLATFORM_SRC) $(CORE_SRC) + +ifeq ($(IX_OSAL_OS_LEVEL),user_space) +ALL_RT_SRC +=$(POSIX_SRC) +endif +endif + +# Add test suite if needed +ifdef IX_OSAL_INTEG_TEST +ALL_OBJ += $(TEST_OBJ) +endif + +################################################################ +# Rules +# + +# Default target +usage: + $(ECHO_BLANKLINE) + @echo $(ECHO_QUOTE)-------------------------------------------- $(ECHO_QUOTE) + @echo $(ECHO_QUOTE)osal/Makefile usage (for linux) $(ECHO_QUOTE) + @echo $(ECHO_QUOTE)-------------------------------------------- $(ECHO_QUOTE) + @echo $(ECHO_QUOTE)Requirements: $(ECHO_QUOTE) + @echo $(ECHO_QUOTE) - IX_TARGET : [linuxle | linuxbe] $(ECHO_QUOTE) + @echo $(ECHO_QUOTE) - IX_LINUXVER : 2.6 $(ECHO_QUOTE) + @echo $(ECHO_QUOTE) - LINUX_SRC : <Path of Linux kernel src> $(ECHO_QUOTE) + @echo $(ECHO_QUOTE) - IX_OSAL_OS_LEVEL: [kernel_space | user_space] $(ECHO_QUOTE) + @echo $(ECHO_QUOTE) - IX_TARGET : linuxle $(ECHO_QUOTE) + @echo $(ECHO_QUOTE) - IX_OSAL_PLATFORM: platform_name $(ECHO_QUOTE) + @echo $(ECHO_QUOTE) - IX_HW_COHERENT_MEMORY: 1 $(ECHO_QUOTE) + @echo $(ECHO_QUOTE) - IX_OSAL_INTEG_TEST: [1 | 0] $(ECHO_QUOTE) + @echo $(ECHO_QUOTE) - source the same environment.tcsh + @echo $(ECHO_QUOTE)-------------------------------------------- $(ECHO_QUOTE) + @echo $(ECHO_QUOTE)osal/Makefile usage (for vxworks) $(ECHO_QUOTE) + @echo $(ECHO_QUOTE)-------------------------------------------- $(ECHO_QUOTE) + @echo $(ECHO_QUOTE)Requirements: $(ECHO_QUOTE) + @echo $(ECHO_QUOTE) - IX_TARGET: [vxle | vxbe] $(ECHO_QUOTE) + @echo $(ECHO_QUOTE) - Source env_scripts/env_vxworksXY_xscale.bat $(ECHO_QUOTE) + @echo $(ECHO_QUOTE)-------------------------------------------- $(ECHO_QUOTE) + @echo $(ECHO_QUOTE)Build commands: $(ECHO_QUOTE) + @echo $(ECHO_QUOTE)make lkm: to build osal as a loadable module$(ECHO_QUOTE) + @echo $(ECHO_QUOTE)make libosal: to build osal library$(ECHO_QUOTE) + @echo $(ECHO_QUOTE)make clean: to remove library and dependency files $(ECHO_QUOTE) + $(ECHO_BLANKLINE) + + + +################################################################ +# Output directories + +# +# Other rules should depend on OUTPUT_DIR_FLAGS, never OUTPUT_DIRS. +# Depending on OUTPUT_DIRS would cause a rule to fire whenever +# any files in the output directories are modified. +# +# Because the automatic dependency rules and 'Makefile:' depend on +# OUTPUT_DIR_FLAGS, no other rules need to depend on them, as the +# dependencies are always built first. + +OUTPUT_DIR_FLAGS := $(sort $(OUTPUT_DIRS:%=%/.dirCreationFlag)) + +$(OUTPUT_DIR_FLAGS): + $(MAKEFILE_TRACE) Creating output directory +ifeq ($(IX_OSAL_MK_HOST_OS),windows) +# The MSDOS 'mkdir' command must use '\' as path seperator and will +# fail if the dir already exists, so we need a '-' + -mkdir $(subst /,\,$(patsubst %/.dirCreationFlag,%,$@)) +else + mkdir -p $(patsubst %/.dirCreationFlag,%,$@) +endif + $(TOUCH_EMPTY_FILE) $@ + +# If the makefile depends on something, it will always be built. Note +# that unless IX_BYPASS_DEPS is defined, the output directories are +# made anyway, because they depend on the %.d rule, which is processed +# before this one. +Makefile: $(OUTPUT_DIR_FLAGS) + + +################################################################ +# Template rules to compile C and assembler +# + +# Place per-directory CFLAGS here if needed here. + +# Place the use per file CFLAGS instead of per-directory CFLAGS, probably easier to implement here. + +# Place CFLAGS to pass the target os name to the C code +CFLAGS += -DIX_OSAL_TARGET_OS_EXT=_$(IX_OSAL_MK_TARGET_OS) +CFLAGS += -DIX_OSAL_PLATFORM_EXT=_$(IX_OSAL_MK_TGT_DEVICE) + + +CFLAGS += -DIX_COMPONENT_NAME=ix_osal + +# Rule to build .d dependency files for C files (the object filename contains the path info to match the .c file) +$(OBJ_BASE_DIR)/%.d: %.c $(OUTPUT_DIR_FLAGS) + $(MAKEFILE_TRACE) Building dependency info for $@ from C + $(CC) $(MAKE_DEP_FLAG) $(CFLAGS) $(ASM_C_RULES_CFLAGS_FOR_FILE) -DIX_GENERATING_DEPENDENCIES $< > $@.tmp + $(FILTER_DEPS) < $@.tmp > $@ + $(RM) $@.tmp + +# Rule to build dependency info for assembler (the object filename contains the path info to match the .s file) +$(OBJ_BASE_DIR)/%.d: %.s $(OUTPUT_DIR_FLAGS) + $(MAKEFILE_TRACE) Building dependency info for $@ from asm +ifeq ($(TOOL_FAMILY),diab) + $(CC) $(MAKE_DEP_FLAG) $(CFLAGS) -Xpreprocess-assembly -W:as:,-Xlabel-colon,-Xsemi-is-newline \ + $(ASM_C_RULES_CFLAGS_FOR_FILE) $< > $@.tmp +else + $(CC) $(MAKE_DEP_FLAG) $(CFLAGS) -x assembler-with-cpp $(ASM_C_RULES_CFLAGS_FOR_FILE) $< > $@.tmp +endif + $(FILTER_DEPS) < $@.tmp > $@ + $(RM) $@.tmp + + +# Rule to build object file from c code (the object filename contains the path info to match the .c file) +$(OBJ_BASE_DIR)/%.o: %.c + $(MAKEFILE_TRACE) Building object file $@ from C + $(CC) $(CFLAGS) $< -c -o $@ + +# Rule to build object file from assembler (the object filename contains the path info to match the .s file) +$(OBJ_BASE_DIR)/%.o: %.s + $(MAKEFILE_TRACE) Building object file $@ from asm +ifeq ($(TOOL_FAMILY),diab) + $(CC) $(CFLAGS) -Xpreprocess-assembly -W:as:,-Xlabel-colon,-Xsemi-is-newline \ + $< -c -o $@ +else + $(CC) $(CFLAGS) -P -x assembler-with-cpp $< -c -o $@ +endif + +DEPS := $(ALL_OBJ:.o=.d) +-include $(DEPS) + + +# Rule to build loadable osal module + +lkm : CFLAGS += -DIX_OSAL_MODULE -DOSAL_EXPORT_SYMBOLS +lkm : $(OBJ_BASE_DIR)/libosal.a +ifneq ($(IX_OSAL_MK_TARGET_OS), vxworks) + + + +ifndef IX_OSAL_INTEG_TEST +ifeq ($(IX_OSAL_MK_TARGET_OS), linux) +ifeq ($(IX_LINUXVER), 2.6) + @echo 'LINUX_SRC := $(LINUX_SRC)' > $(IX_OSAL_KERN26_MAKEFILE) + @echo 'EXTRA_LDFLAGS := --whole-archive' > $(IX_OSAL_KERN26_MAKEFILE) + @echo ' ' >> $(IX_OSAL_KERN26_MAKEFILE) + @echo 'obj-m := osalModule.o' >> $(IX_OSAL_KERN26_MAKEFILE) + @echo ' ' >> $(IX_OSAL_KERN26_MAKEFILE) + @echo 'osalModule-objs := libosal.a' >> $(IX_OSAL_KERN26_MAKEFILE) + @echo ' ' >> $(IX_OSAL_KERN26_MAKEFILE) + @echo 'default:' >> $(IX_OSAL_KERN26_MAKEFILE) + @echo -ne "\t" >> $(IX_OSAL_KERN26_MAKEFILE) + @echo 'make $(IX_KBUILD_CROSSCOMPILE) -C $(LINUX_SRC) M=$(shell pwd)/$(OBJ_BASE_DIR) V=1 modules' >> $(IX_OSAL_KERN26_MAKEFILE) + make -C $(OBJ_BASE_DIR) +endif # ifeq IX_LINUXVER + +ifeq ($(IX_OSAL_OS_LINUX_VERSION), GT_2_6_18) + @echo 'LINUX_SRC := $(LINUX_SRC)' > $(IX_OSAL_KERN26_MAKEFILE) + @echo 'EXTRA_LDFLAGS := --whole-archive' > $(IX_OSAL_KERN26_MAKEFILE) + @echo ' ' >> $(IX_OSAL_KERN26_MAKEFILE) + @echo 'obj-m := osalModule.o' >> $(IX_OSAL_KERN26_MAKEFILE) + @echo ' ' >> $(IX_OSAL_KERN26_MAKEFILE) + @echo 'osalModule-objs := libosal.a' >> $(IX_OSAL_KERN26_MAKEFILE) + @echo ' ' >> $(IX_OSAL_KERN26_MAKEFILE) + @echo 'default:' >> $(IX_OSAL_KERN26_MAKEFILE) + @echo -ne "\t" >> $(IX_OSAL_KERN26_MAKEFILE) + @echo 'make $(IX_KBUILD_CROSSCOMPILE) -C $(LINUX_SRC) M=$(shell pwd)/$(OBJ_BASE_DIR) modules' >> $(IX_OSAL_KERN26_MAKEFILE) + make -C $(OBJ_BASE_DIR) +endif # IX_OSAL_OS_LINUX_VERSION > GT_2_6_18 + +endif # ifeq IX_OSAL_MK_TARGET_OS +else + @echo "Error: Unset IX_OSAL_INTEG_TEST to build osal as loadable module" + @exit 1 +endif # IX_OSAL_INTEG_TEST +endif # ifeq IX_OSAL_MK_TARGET_OS, vxworks + + +ifneq ($(IX_OSAL_OS_LINUX_VERSION), GT_2_6_18) + $(ECHO_BLANKLINE) + @echo $(ECHO_QUOTE) CFLAGS = $(CFLAGS) $(ECHO_QUOTE) + $(ECHO_BLANKLINE) +endif + +IX_OSAL_KERN26_MAKEFILE := $(OBJ_BASE_DIR)/Makefile + +# Rule to build OSAL library +libosal : $(OBJ_BASE_DIR)/libosal.a +# ifdef IX_INTEL +# Use "make libosal IX_OSAL_INTEG_TEST=1" to build the integration code for kernel +# 2.6. The kernel object is ix_osal_test.ko. + +ifdef IX_OSAL_INTEG_TEST +ifeq ($(IX_OSAL_MK_TARGET_OS), linux) +ifeq ($(IX_LINUXVER), 2.6) + @echo 'LINUX_SRC := $(LINUX_SRC)' > $(IX_OSAL_KERN26_MAKEFILE) + @echo 'EXTRA_LDFLAGS := --whole-archive' > $(IX_OSAL_KERN26_MAKEFILE) + @echo ' ' >> $(IX_OSAL_KERN26_MAKEFILE) + @echo 'obj-m := osal_test.o' >> $(IX_OSAL_KERN26_MAKEFILE) + @echo ' ' >> $(IX_OSAL_KERN26_MAKEFILE) + @echo 'osal_test-objs := libosal.a' >> $(IX_OSAL_KERN26_MAKEFILE) + @echo ' ' >> $(IX_OSAL_KERN26_MAKEFILE) + @echo 'default:' >> $(IX_OSAL_KERN26_MAKEFILE) + @echo -ne "\t" >> $(IX_OSAL_KERN26_MAKEFILE) + @echo 'make $(IX_KBUILD_CROSSCOMPILE) -C $(LINUX_SRC) M=$(shell pwd)/$(OBJ_BASE_DIR) V=1 modules' >> $(IX_OSAL_KERN26_MAKEFILE) + make -C $(OBJ_BASE_DIR) +endif # ifeq IX_LINUXVER + +ifeq ($(IX_OSAL_OS_LINUX_VERSION), GT_2_6_18) + @echo 'LINUX_SRC := $(LINUX_SRC)' > $(IX_OSAL_KERN26_MAKEFILE) + @echo 'EXTRA_LDFLAGS := --whole-archive' > $(IX_OSAL_KERN26_MAKEFILE) + @echo ' ' >> $(IX_OSAL_KERN26_MAKEFILE) + @echo 'obj-m := osal_test.o' >> $(IX_OSAL_KERN26_MAKEFILE) + @echo ' ' >> $(IX_OSAL_KERN26_MAKEFILE) + @echo 'osal_test-objs := libosal.a' >> $(IX_OSAL_KERN26_MAKEFILE) + @echo ' ' >> $(IX_OSAL_KERN26_MAKEFILE) + @echo 'default:' >> $(IX_OSAL_KERN26_MAKEFILE) + @echo -ne "\t" >> $(IX_OSAL_KERN26_MAKEFILE) + @echo 'make $(IX_KBUILD_CROSSCOMPILE) -C $(LINUX_SRC) M=$(shell pwd)/$(OBJ_BASE_DIR) modules' >> $(IX_OSAL_KERN26_MAKEFILE) + make -C $(OBJ_BASE_DIR) + +endif # IX_OSAL_OS_LINUX_VERSION > GT_2_6_18 + + +endif # ifeq IX_OSAL_MK_TARGET_OS +endif # ifdef IX_OSAL_INTEG_TEST +# endif IX_INTEL + + +ifneq ($(IX_OSAL_OS_LINUX_VERSION), GT_2_6_18) + $(ECHO_BLANKLINE) + @echo $(ECHO_QUOTE) CFLAGS = $(CFLAGS) $(ECHO_QUOTE) + $(ECHO_BLANKLINE) +endif +$(OBJ_BASE_DIR)/libosal.a : $(ALL_OBJ) + $(MAKEFILE_TRACE) Building OSAL library containing components $(COMPONENTS:%=\"%\") + $(AR) rvs $(OBJ_BASE_DIR)/libosal.a $^ + + $(MAKEFILE_TRACE) Copy the static library file to a fixed location - OSAL source root. +#ifneq ($(IX_OSAL_OS_LEVEL),user_space) + cp $(OBJ_BASE_DIR)/libosal.a libosal.a +#else +# cp $(OBJ_BASE_DIR)/libosal.a libosal_user.a +#endif + +# Simple rule to build everything +.PHONY: all +all: libosal + +# To build loadable +ALL_LOADABLES := $(OBJ_BASE_DIR)/osalTest.out + +OSAL_MODULES := $(OBJ_BASE_DIR)/osalModule.o +module : $(OSAL_MODULES) + +.phony: loadable +loadable: $(ALL_LOADABLES) + +.phony: loadable-test +loadable-test: $(OBJ_BASE_DIR)/osalTest.out + $(MAKEFILE_TRACE) Copy the testframe work file to the fixed location. + cp $(OBJ_BASE_DIR)/osalTest.out . + +################################################ +# Full paths to the component and test objects going into the image +LOADABLE_RULE_OBJ = $(ALL_OBJ) +# The names of the libraries that will be linked to a loadable +LOADABLE_RULE_LIB_FILES = $(OBJ_BASE_DIR)/libosal.a + + +# Rule to build a loadable object +$(ALL_LOADABLES) : $(OBJ_BASE_DIR)/%.out : + $(MAKEFILE_TRACE) Building relocatable object for component $* +ifeq ($(IX_OSAL_MK_TARGET_OS),vxworks) + $(NM) $(LOADABLE_RULE_OBJ) | $(MUNCH) > $(OBJ_BASE_DIR)/ctdt.c + $(COMPILE_TRADITIONAL) $(CFLAGS) $(OBJ_BASE_DIR)/ctdt.c \ + -o $(OBJ_BASE_DIR)/ctdt.o + $(LD) $(LDFLAGS) $(LOADABLE_RULE_OBJ) $(OBJ_BASE_DIR)/ctdt.o\ + -L$(OBJ_BASE_DIR) -o $@ +else +ifeq ($(IX_OSAL_MK_TARGET_OS),linux) + $(LD) $(LDFLAGS) $(LOADABLE_RULE_OBJ) \ + -L$(OBJ_BASE_DIR) -o $@ +else + # Link with the realtime and pthread user space libraries. + $(CC) $(LOADABLE_RULE_LIB_FILES) -lrt -pthread -o $@ +endif +endif # IX_OSAL_MK_TARGET_OS == vxworks + +$(OBJ_BASE_DIR)/osalModule.o : $(filter-out $(TEST_OBJ), $(ALL_OBJ)) + $(LD) $(LDFLAGS) $(LOADABLE_RULE_OBJ) -L$(OBJ_BASE_DIR) -o $@ + +################################################################ +# Rule to clean the build output directory +# + +.PHONY: clean +clean: + $(MAKEFILE_TRACE) Deleting all build products +ifeq ($(IX_OSAL_MK_HOST_OS),windows) + rm -rf lib/$(IX_OSAL_MK_TGT_DEVICE)/$(IX_OSAL_MK_TARGET_OS)/ +else + $(RM) -r lib/$(IX_OSAL_MK_TGT_DEVICE)/$(IX_OSAL_MK_TARGET_OS)/$(IX_OSAL_MK_TARGET_ENDIAN) + @find lib -name .dirCreationFlag | xargs rm -r + $(RM) *.ko *.o *.a *.out +endif + +################################################################ +# Rule specific to Platfrom specific release build rule +# +-include platforms/$(IX_OSAL_MK_TGT_DEVICE)/os/$(IX_OSAL_MK_TARGET_OS)/make/RelMake.mk + +################################################################ +# showmacro - prints the value of a variable. For makefile debugging. +.PHONY: showmacro +showmacro: + @echo $($(MACRO)) + diff --git a/Acceleration/library/icp_utils/OSAL/common/include/IxOsal.h b/Acceleration/library/icp_utils/OSAL/common/include/IxOsal.h new file mode 100644 index 0000000..427e082 --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/include/IxOsal.h @@ -0,0 +1,3079 @@ +/** + * @file IxOsal.h + * + * @brief Top include file for OSAL + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +#ifndef IxOsal_H +#define IxOsal_H +#ifdef __cplusplus +extern "C"{ +#endif + +/* Basic types */ +#include "IxOsalTypes.h" + +/* Include assert */ +#include "IxOsalAssert.h" + +/* + * Config header gives users option to choose IO MEM + * and buffer management modules + */ + +#include "IxOsalConfig.h" + + +/* + * Symbol file needed by some OS. + */ +#include "IxOsalUtilitySymbols.h" + +/* OS-specific header */ +#include "IxOsalOs.h" + + +/** + * @defgroup IxOsal Operating System Abstraction Layer (OSAL) API + * + * @brief This service provides a thin layer of OS dependency services. + * + * This file contains the API to the functions which are some what OS dependant and would + * require porting to a particular OS. + * A primary focus of the component development is to make them as OS independent as possible. + * All other components should abstract their OS dependency to this module. + * Services overview + * -# Data types, constants, defines + * -# Interrupts + * - bind interrupts to handlers + * - unbind interrupts from handlers + * - disables all interrupts + * - enables all interrupts + * - selectively disables interrupts + * - enables an interrupt level + * - disables an interrupt level + * - atomic memory allocation + * -# Memory + * - allocates aligned memory + * - frees aligned memory + * - allocates memory + * - frees memory + * - copies memory zones + * - fills a memory zone + * - allocates cache-safe memory + * - frees cache-safe memory + * - physical to virtual address translation + * - virtual to physical address translation + * - cache to memory flush + * - cache line invalidate + * -# Threads + * - creates a new thread + * - starts a newly created thread + * - kills an existing thread + * - exits a running thread + * - sets the priority of an existing thread + * - suspends thread execution + * - resumes thread execution + * -# IPC + * - creates a message queue + * - deletes a message queue + * - sends a message to a message queue + * - receives a message from a message queue + * -# Thread Synchronisation + * - initializes a mutex + * - locks a mutex + * - unlocks a mutex + * - non-blocking attempt to lock a mutex + * - destroys a mutex object + * - initializes a fast mutex + * - non-blocking attempt to lock a fast mutex + * - unlocks a fast mutex + * - destroys a fast mutex object + * - initializes a semaphore + * - posts to (increments) a semaphore + * - waits on (decrements) a semaphore + * - non-blocking wait on semaphore + * - gets semaphore value + * - destroys a semaphore object + * - yields execution of current thread + * -# Time functions + * - yielding sleep for a number of milliseconds + * - busy sleep for a number of microseconds + * - value of the timestamp counter + * - resolution of the timestamp counter + * - system clock rate, in ticks + * - current system time + * - converts ixOsalTimeVal into ticks + * - converts ticks into ixOsalTimeVal + * - converts ixOsalTimeVal to milliseconds + * - converts milliseconds to IxOsalTimeval + * - "equal" comparison for IxOsalTimeval + * - "less than" comparison for IxOsalTimeval + * - "greater than" comparison for IxOsalTimeval + * - "add" operator for IxOsalTimeval + * - "subtract" operator for IxOsalTimeval + * -# Logging + * - sets the current logging verbosity level + * - interrupt-safe logging function + * -# Timer services + * - schedules a repeating timer + * - schedules a single-shot timer + * - cancels a running timer + * - displays all the running timers + * -# PCI Support + * - Find PCI device. + * - Read 8 bits from the configuration space + * - Read 16 bits from the configuration space + * - Read 32 bits from the configuration space + * - Write 8 bits to the configuration space + * - Write 16 bits to the configuration space + * - Write 32 bits to the configuration space + * - Free PCI device + * -# SpinLock Support + * - Initializes the SpinLock object + * - Acquires a spin lock + * - Releases the spin lock + * - Tries to acquire the spin lock + * - Destroy the spin lock object + * -# Atomic Support + * The following API's used for IA atomic only not for + * IA to AE Atomics. + * - read the value of atomic variable + * - set the value of atomic variable + * - add the value to atomic variable + * - subtract the value from atomic variable + * - subtract the value from atomic variable and test result + * - increment the value of atomic variable + * - decrement the value of atomic variable + * - decrement the value of atomic variable and test result + * - increment the value of atomic variable and test result + * -# Memory Barrier Support + * - read memory barrier which orders only memory reads + * - write memory barrier which orders only memory writes + * -# Optional Modules + * - Device drivers kernel + * - Buffer management module + * - I/O memory and endianess support module + */ + + +/* + * Prototypes + */ + +#if !defined(__linux_user) && !defined(__freebsd_user) +/* ========================== Interrupts ================================ + * + */ + +/** + * @ingroup IxOsal + * + * @brief Binds an interrupt handler to an interrupt level + * + * @param irqLevel (in) - interrupt level + * @param irqHandler (in) - interrupt handler + * @param parameter (in) - custom parameter to be passed to the + * interrupt handler + * + * Binds an interrupt handler to an interrupt level. The operation will + * fail if the wrong level is selected, if the handler is NULL, or if the + * interrupt is already bound. This functions binds the specified C + * routine to an interrupt level. When called, the "parameter" value will + * be passed to the routine. + * + * Reentrant: yes + * IRQ safe: yes + * + * @return IX_SUCCESS if the operation succeeded or IX_FAIL otherwise + */ +PUBLIC IX_STATUS ixOsalIrqBind (UINT32 irqLevel, + IxOsalVoidFnVoidPtr irqHandler, + void *parameter); + +/** + * @ingroup IxOsal + * + * @brief Unbinds an interrupt handler from an interrupt level + * + * @param irqLevel (in) - interrupt level + * + * Unbinds the selected interrupt level from any previously registered + * handler + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return IX_SUCCESS if the operation succeeded or IX_FAIL otherwise + */ +PUBLIC IX_STATUS ixOsalIrqUnbind (UINT32 irqLevel); + + +/** + * @ingroup IxOsal + * + * @brief Disables all interrupts + * + * @param - none + * + * Disables all the interrupts and prevents tasks scheduling + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return interrupt enable status prior to locking + */ +PUBLIC UINT32 ixOsalIrqLock (void); + +/** + * @ingroup IxOsal + * + * @brief Enables all interrupts + * + * @param irqEnable (in) - interrupt enable status, prior to interrupt + * locking + * + * Enables the interrupts and task scheduling, cancelling the effect + * of ixOsalIrqLock() + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return None + */ +PUBLIC void ixOsalIrqUnlock (UINT32 irqEnable); + +/** + * @ingroup IxOsal + * + * @brief Selectively disables interrupts + * + * @param irqLevel � new interrupt level + * + * Disables the interrupts below the specified interrupt level + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @note Depending on the implementation this function can disable all + * the interrupts + * + * @return previous interrupt level + */ +PUBLIC UINT32 ixOsalIrqLevelSet (UINT32 irqLevel); + +/** + * @ingroup IxOsal + * + * @brief Enables an interrupt level + * + * @param irqLevel � interrupt level to enable + * + * Enables the specified interrupt level + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - none + */ +PUBLIC void ixOsalIrqEnable (UINT32 irqLevel); + +/** + * @ingroup IxOsal + * + * @brief Disables an interrupt level + * + * @param irqLevel � interrupt level to disable + * + * Disables the specified interrupt level + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - none + */ +PUBLIC void ixOsalIrqDisable (UINT32 irqLevel); + +#endif /* __linux_user || __freebsd_user */ +/* ============================= Memory ================================= + * + */ + +/** + * @ingroup IxOsal + * + * @brief Allocates aligned memory + * + * @param space - (Unused right now ) kernel_space or user_space + * @param size - malloc memory size required to be allocated + * @param alignment - alignment required in bytes + * + * Allocate an aligned memory zone + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - void pointer to malloced memory + */ +PUBLIC VOID * ixOsalMemAllocAligned(UINT32 space, UINT32 size, UINT32 alignment); + +/** + * @ingroup IxOsal + * + * @brief Frees memory allocated by ixOsalMemAllocAligned + * + * @param ptr - pointer to contiguous aligned memory zone + * @param size - memory size allocated which needs to be freed. + * + * Frees a previously allocated Aligned memory zone + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - none + */ +PUBLIC void ixOsalMemAlignedFree(void *ptr, UINT32 size); + +/** + * @ingroup IxOsal + * + * @brief Allocates memory + * + * @param size - memory size to allocate, in bytes + * + * Allocates a memory zone of a given size + * The returned memory is garaunteed to be physically contiguos if the + * given size is less than 128Kb. + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return Pointer to the allocated zone or NULL if the allocation failed + */ +PUBLIC void *ixOsalMemAlloc (UINT32 size); + +/** + * @ingroup IxOsal + * + * @brief Frees memory allocated by ixOsalMemAlloc + * + * @param ptr - pointer to the memory zone + * + * Frees a previously allocated memory zone + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - none + */ +PUBLIC VOID ixOsalMemFree (VOID *ptr); + +/** + * @ingroup IxOsal + * + * @brief Copies data bytes from src memory zone to dest memory zone + * + * @param dest - destination memory zone + * @param src - source memory zone + * @param count - number of bytes to copy + * + * Copies count bytes from the source memory zone pointed by src into the + * memory zone pointed by dest. + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return Pointer to the destination memory zone + */ +PUBLIC void *ixOsalMemCopy (void *dest, const void *src, UINT32 count); + +/** + * @ingroup IxOsal + * + * @brief Fills a memory zone + * + * @param ptr - pointer to the memory zone + * @param filler - byte to fill the memory zone with + * @param count - number of bytes to fill + * + * Fills a memory zone with a given constant byte + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return Pointer to the memory zone + */ +PUBLIC void *ixOsalMemSet (void *ptr, UINT8 filler, UINT32 count); + +/** + * @ingroup IxOsal + * + * @brief Compares memory zones + * + * @param dest - destination memory zone + * @param src - source memory zone + * @param count - number of bytes to compare + * + * Compares count bytes from the source memory zone pointed by src with the + * memory zone pointed by dest. + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return IX_SUCCESS/IX_FAIL + */ +PUBLIC IX_STATUS ixOsalMemCmp (void *dest, void *src, UINT32 count); + +#if !defined(__linux_user) && !defined(__freebsd_user) + +/** + * @ingroup IxOsal + * + * @brief Allocates memory in IRQ safe context + * + * @param size - memory size to allocate, in bytes + * + * Allocates a memory zone of a given size without sleeping. + * If the required resourse is not immediatly available NULL pointer is returned + * This is suitable for IRQ context or mutex/spinlock context when sleeping + * is not allowed + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return Pointer to the allocated zone or NULL if the allocation failed + */ +PUBLIC void *ixOsalMemAllocAtomic (UINT32 size); + +#if (!defined(__freebsd)) +/** + * @ingroup IxOsal + * + * @brief physical to virtual address translation + * + * @param physAddr - physical address + * + * Converts a physical address into its equivalent MMU-mapped virtual address + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return Corresponding virtual address, as UINT32 + */ +#define IX_OSAL_MMU_PHYS_TO_VIRT(physAddr) \ + IX_OSAL_OS_MMU_PHYS_TO_VIRT(physAddr) + +#endif /*!defined(__freebsd)*/ +/** + * @ingroup IxOsal + * + * @brief virtual to physical address translation + * + * @param virtAddr - virtual address + * + * Converts a virtual address into its equivalent MMU-mapped physical address + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return Corresponding physical address, as UINT32 + */ +#define IX_OSAL_MMU_VIRT_TO_PHYS(virtAddr) \ + IX_OSAL_OS_MMU_VIRT_TO_PHYS(virtAddr) + +/** + * @ingroup IxOsal + * + * @brief Allocates cache-safe memory + * + * @param size - size, in bytes, of the allocated zone + * + * Allocates a cache-safe memory zone of at least "size" bytes and returns + * the pointer to the memory zone. This memory zone, depending on the + * platform, is either uncached or aligned on a cache line boundary to make + * the CACHE_FLUSH and CACHE_INVALIDATE macros safe to use. The memory + * allocated with this function MUST be freed with ixOsalCacheDmaFree(), + * otherwise memory corruption can occur. This function allocates 32byte aligned + * physical contigeous memory. The minimum size memory it can allocate is + * 32byte and maximum size depends on the availability in OS. + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return Pointer to the memory zone or NULL if allocation failed + * + * @note It is important to note that cache coherence is maintained in + * software by using the IX_OSAL_CACHE_FLUSH and IX_OSAL_CACHE_INVALIDATE + * macros to maintain consistency between cache and external memory. + */ +PUBLIC void *ixOsalCacheDmaMalloc (UINT32 size); + +/** + * @ingroup IxOsal + * + * @brief Allocates cache-safe memory + * + * @param size - size, in bytes, of the allocated zone + * + * Allocates a cache-safe memory zone of at least "size" bytes and returns + * the pointer to the memory zone. This memory zone, depending on the + * platform, is either uncached or aligned on a cache line boundary to make + * the CACHE_FLUSH and CACHE_INVALIDATE macros safe to use. The memory + * allocated with this function MUST be freed with ixOsalCacheDmaFree(), + * otherwise memory corruption can occur. This function allocates 32byte aligned + * physical contigeous memory. The minimum size memory it can allocate is + * 32byte and maximum size depends on the availability in OS. + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return Pointer to the memory zone or NULL if allocation failed + * + * @note It is important to note that cache coherence is maintained in + * software by using the IX_OSAL_CACHE_FLUSH and IX_OSAL_CACHE_INVALIDATE + * macros to maintain consistency between cache and external memory. + */ +#define IX_OSAL_CACHE_DMA_MALLOC(size) ixOsalCacheDmaMalloc(size) + +/** + * @ingroup IxOsal + * + * @brief Frees cache-safe memory + * + * @param ptr - pointer to the memory zone + * + * Frees a memory zone previously allocated with ixOsalCacheDmaMalloc() + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - none + */ +PUBLIC void ixOsalCacheDmaFree (void *ptr); + +/** + * @ingroup IxOsal + * + * @brief Frees cache-safe memory + * + * @param ptr - pointer to the memory zone + * + * Frees a memory zone previously allocated with ixOsalCacheDmaMalloc() + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - none + */ +#define IX_OSAL_CACHE_DMA_FREE(ptr) ixOsalCacheDmaFree(ptr) + + + +/** + * @ingroup IxOsal + * + * @brief cache to memory flush + * + * @param addr - memory address to flush from cache + * @param size - number of bytes to flush (rounded up to a cache line) + * + * Flushes the cached value of the memory zone pointed by "addr" into memory, + * rounding up to a cache line. Use before the zone is to be read by a + * processing unit which is not cache coherent with the main CPU. + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - none + */ +#define IX_OSAL_CACHE_FLUSH(addr, size) IX_OSAL_OS_CACHE_FLUSH(addr, size) + + + +/** + * @ingroup IxOsal + * + * @brief cache line invalidate + * + * @param addr - memory address to invalidate in cache + * @param size - number of bytes to invalidate (rounded up to a cache line) + * + * Invalidates the cached value of the memory zone pointed by "addr", + * rounding up to a cache line. Use before reading the zone from the main + * CPU, if the zone has been updated by a processing unit which is not cache + * coherent with the main CPU. + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - none + */ +#define IX_OSAL_CACHE_INVALIDATE(addr, size) IX_OSAL_OS_CACHE_INVALIDATE(addr, size) + +/** + * @ingroup IxOsal + * + * @brief cache line preload + * + * @param addr - memory address to cache + * @param size - number of bytes to cache (rounded up to a cache line) + * + * + * Preloads a section of memory to the cache memory in multiples of cache line size. + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - none + */ +#define IX_OSAL_CACHE_PRELOAD(addr, size) IX_OSAL_OS_CACHE_PRELOAD(addr, size) + +#endif /* __linux_user || __freebsd_user */ + + +/* ============================= Threads ================================= + * + */ + +/** + * @ingroup IxOsal + * + * @brief Creates a new thread + * + * @param thread - handle of the thread to be created + * @param threadAttr - pointer to a thread attribute object + * @param startRoutine - thread entry point + * @param arg - argument to be passed to the startRoutine + * + * Creates a thread given a thread handle and a thread attribute object. The + * same thread attribute object can be used to create separate threads. "NULL" + * can be specified as the attribute, in which case the default values will + * be used. The thread needs to be explicitly started using ixOsalThreadStart(). + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - IX_SUCCESS/IX_FAIL + */ +PUBLIC IX_STATUS ixOsalThreadCreate (IxOsalThread * thread, + IxOsalThreadAttr * threadAttr, + IxOsalVoidFnVoidPtr startRoutine, + void *arg); + +/** + * @ingroup IxOsal + * + * @brief Starts a newly created thread + * + * @param thread - handle of the thread to be started + * + * Starts a thread given its thread handle. This function is to be called + * only once, following the thread initialization. + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - IX_SUCCESS/IX_FAIL + */ +PUBLIC IX_STATUS ixOsalThreadStart (IxOsalThread * thread); + +/** + * @ingroup IxOsal + * + * @brief Terminates a thread execution + * + * @param thread - handle of the thread to be terminated + * + * Kills a thread given its thread handle. + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @note This function does not guarentee to kill the thread immediately. The + * thread must use ixOsalThreadStopCheck() to check if it should perform + * cleanup and suicide. + * + * @return - IX_SUCCESS/IX_FAIL + */ +PUBLIC IX_STATUS ixOsalThreadKill (IxOsalThread * thread); + +/** + * @ingroup IxOsal + * + * @brief Exits a running thread + * + * Terminates the calling thread + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - This function never returns + */ +PUBLIC void ixOsalThreadExit (void); + +/** + * @ingroup IxOsal + * + * @brief Sets the priority of a thread + * + * @param thread - handle of the thread + * @param priority - new priority, between 0 and 255 (0 being the highest) + * + * Sets the thread priority + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - IX_SUCCESS/IX_FAIL + */ +PUBLIC IX_STATUS ixOsalThreadPrioritySet (IxOsalThread * thread, + UINT32 priority); + +/** + * @ingroup IxOsal + * + * @brief Suspends thread execution + * + * @param thread - handle of the thread + * + * Suspends the thread execution. The suspended thread can be resumed + * by ixOsalThreadResume call + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - IX_SUCCESS/IX_FAIL + */ +PUBLIC IX_STATUS ixOsalThreadSuspend (IxOsalThread * thread); + +/** + * @ingroup IxOsal + * + * @brief Resumes thread execution + * + * @param thread - handle of the thread + * + * Resumes the thread execution + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - IX_SUCCESS/IX_FAIL + */ +PUBLIC IX_STATUS ixOsalThreadResume (IxOsalThread * thread); + +/** + * @ingroup IxOsal + * + * @brief Check if thread should stop execution + * + * Check if ixOsalThreadKill has been called. When this API return TRUE, the + * thread should perform cleanup and exit. + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - TRUE/FALSE + */ + +PUBLIC BOOL ixOsalThreadStopCheck(void); + + +/* ======================= Message Queues (IPC) ========================== + * + */ + +/** + * @ingroup IxOsal + * + * @brief Creates a message queue + * + * @param queue - queue handle + * @param msgCount - maximum number of messages to hold in the queue + * @param msgLen - maximum length of each message, in bytes + * + * Creates a message queue of msgCount messages, each containing msgLen bytes + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - IX_SUCCESS/IX_FAIL + */ +PUBLIC IX_STATUS ixOsalMessageQueueCreate (IxOsalMessageQueue * queue, + UINT32 msgCount, UINT32 msgLen); + +/** + * @ingroup IxOsal + * + * @brief Creates a message queue + * + * @param queue - queue handle + * @param msgCount - maximum number of messages to hold in the queue + * @param msgLen - maximum length of each message, in bytes + * + * Creates a blocking message queue of msgCount messages, each containing + * msgLen bytes + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - IX_SUCCESS/IX_FAIL + */ +PUBLIC IX_STATUS ixOsalSyncMessageQueueCreate (IxOsalMessageQueue * queue, + UINT32 msgCount, UINT32 msgLen); + +/** + * @ingroup IxOsal + * + * @brief Deletes a message queue + * + * @param queue - message queue handle + * + * Deletes a message queue + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - IX_SUCCESS/IX_FAIL + */ + +PUBLIC IX_STATUS ixOsalMessageQueueDelete (IxOsalMessageQueue * queue); + +/** + * @ingroup IxOsal + * + * @brief Sends a message to a message queue + * + * @param queue - message queue handle + * @param message - message to send + * + * Sends a message to the message queue. The message will be copied (at the + * configured size of the message) into the queue. + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - IX_SUCCESS/IX_FAIL + */ +PUBLIC IX_STATUS ixOsalMessageQueueSend (IxOsalMessageQueue * queue, + UINT8 * message); + +/** + * @ingroup IxOsal + * + * @brief Receives a message from a message queue + * + * @param queue - queue handle + * @param message - pointer to where the message should be copied to + * + * Retrieves the first message from the message queue + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - IX_SUCCESS/IX_FAIL + * IX_EAGAIN - specified message queue is empty + * IX_EBADF - invalid message queue descriptor + * IX_EMSGSIZE - insufficient message buffer size + * IX_EINTR - operation interrupted + * IX_EINVAL - invalid + * IX_ETIMEDOUT - timeout before any message arrived + * IX_EBADMSG - corrupt message + */ +PUBLIC IX_STATUS ixOsalMessageQueueReceive (IxOsalMessageQueue * queue, + UINT8 * message); + +/** + * @ingroup IxOsal + * + * @brief Receives a message from a message queue + * + * @param queue - queue handle + * @param message - pointer to where the message should be copied to + * @param timeout - timeout time in millisec + * + * Retrieves the first message from the message queue within specified time + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - IX_SUCCESS - success + * IX_EAGAIN - specified message queue is empty + * IX_ETIMEDOUT - timeout before any message arrived + * + */ +PUBLIC IX_STATUS ixOsalSyncMessageQueueReceive(IxOsalMessageQueue * queue, + UINT8 * message, INT32 timeout); + +/* ======================= Thread Synchronisation ======================== + * + */ + +/** + * @ingroup IxOsal + * + * @brief initializes a mutex + * + * @param mutex - mutex handle + * + * Initializes a mutex object + * Note: Mutex initialization ixOsalMutexInit API must be called + * first before using any OSAL Mutex APIs + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - IX_SUCCESS/IX_FAIL + */ +PUBLIC IX_STATUS ixOsalMutexInit (IxOsalMutex * mutex); + +/** + * @ingroup IxOsal + * + * @brief locks a mutex + * + * @param mutex - mutex handle + * @param timeout - timeout in ms; IX_OSAL_WAIT_FOREVER (-1) to wait forever + * or IX_OSAL_WAIT_NONE to return immediately + * + * Locks a mutex object + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - IX_SUCCESS/IX_FAIL + */ +PUBLIC IX_STATUS ixOsalMutexLock (IxOsalMutex * mutex, INT32 timeout); + +/** + * @ingroup IxOsal + * + * @brief Unlocks a mutex + * + * @param mutex - mutex handle + * + * Unlocks a mutex object + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - IX_SUCCESS/IX_FAIL + */ +PUBLIC IX_STATUS ixOsalMutexUnlock (IxOsalMutex * mutex); + +/** + * @ingroup IxOsal + * + * @brief Non-blocking attempt to lock a mutex + * + * @param mutex - mutex handle + * + * Attempts to lock a mutex object, returning immediately with IX_SUCCESS if + * the lock was successful or IX_FAIL if the lock failed + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - IX_SUCCESS/IX_FAIL + */ +PUBLIC IX_STATUS ixOsalMutexTryLock (IxOsalMutex * mutex); + +/** + * @ingroup IxOsal + * + * @brief Destroys a mutex object + * + * @param mutex - mutex handle + * + * Destroys a mutex object; the caller should ensure that no thread is + * blocked on this mutex. If call made when thread blocked on mutex the + * behaviour is unpredictable + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - IX_SUCCESS/IX_FAIL + */ +PUBLIC IX_STATUS ixOsalMutexDestroy (IxOsalMutex * mutex); + +/** + * @ingroup IxOsal + * + * @brief Initializes a fast mutex + * + * @param mutex - fast mutex handle + * + * Initializes a fast mutex object + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - IX_SUCCESS/IX_FAIL + */ +PUBLIC IX_STATUS ixOsalFastMutexInit (IxOsalFastMutex * mutex); + +/** + * @ingroup IxOsal + * + * @brief Non-blocking attempt to lock a fast mutex + * + * @param mutex - fast mutex handle + * + * Attempts to lock a fast mutex object, returning immediately with + * IX_SUCCESS if the lock was successful or IX_FAIL if the lock failed + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - IX_SUCCESS/IX_FAIL + */ +PUBLIC IX_STATUS ixOsalFastMutexTryLock (IxOsalFastMutex * mutex); + +/** + * @ingroup IxOsal + * + * @brief Unlocks a fast mutex + * + * @param mutex - fast mutex handle + * + * Unlocks a fast mutex object + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - IX_SUCCESS/IX_FAIL + */ +PUBLIC IX_STATUS ixOsalFastMutexUnlock (IxOsalFastMutex * mutex); + +/** + * @ingroup IxOsal + * + * @brief Destroys a fast mutex object + * + * @param mutex - fast mutex handle + * + * Destroys a fast mutex object + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - IX_SUCCESS/IX_FAIL + */ +PUBLIC IX_STATUS ixOsalFastMutexDestroy (IxOsalFastMutex * mutex); + +/** + * @ingroup IxOsal + * + * @brief Initializes a semaphore + * + * @param semaphore - semaphore handle + * @param value - initial semaphore value + * + * Initializes a semaphore object + * Note: Semaphore initialization ixOsalSemaphoreInit API must be called + * first before using any OSAL Semaphore APIs + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - IX_SUCCESS/IX_FAIL + */ +PUBLIC IX_STATUS ixOsalSemaphoreInit (IxOsalSemaphore * semaphore, + UINT32 value); + +/** + * @ingroup IxOsal + * + * @brief Posts to (increments) a semaphore + * + * @param semaphore - semaphore handle + * + * Increments a semaphore object + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - IX_SUCCESS/IX_FAIL + */ +PUBLIC IX_STATUS ixOsalSemaphorePost (IxOsalSemaphore * semaphore); + +/** + * @ingroup IxOsal + * + * @brief Waits on (decrements) a semaphore + * + * @param semaphore - semaphore handle + * @param timeout - timeout, in ms; IX_OSAL_WAIT_FOREVER (-1) if the thread + * is to block indefinitely or IX_OSAL_WAIT_NONE (0) if the thread is to + * return immediately even if the call fails + * + * Decrements a semaphore, blocking if the semaphore is + * unavailable (value is 0). + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - IX_SUCCESS/IX_FAIL + */ +PUBLIC IX_STATUS ixOsalSemaphoreWait (IxOsalSemaphore * semaphore, + INT32 timeout); + +/** + * @ingroup IxOsal + * + * @brief Non-blocking wait on semaphore + * + * @param semaphore - semaphore handle + * + * Decrements a semaphore, not blocking the calling thread if the semaphore + * is unavailable + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - IX_SUCCESS/IX_FAIL + */ +PUBLIC IX_STATUS ixOsalSemaphoreTryWait (IxOsalSemaphore * semaphore); + +/** + * @ingroup IxOsal + * + * @brief Gets semaphore value + * + * @param semaphore - semaphore handle + * @param value - location to store the semaphore value + * + * Retrieves the current value of a semaphore object + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - IX_SUCCESS/IX_FAIL + */ +PUBLIC IX_STATUS ixOsalSemaphoreGetValue (IxOsalSemaphore * semaphore, + UINT32 * value); + +/** + * @ingroup IxOsal + * + * @brief Destroys a semaphore object + * + * @param semaphore - semaphore handle + * + * Destroys a semaphore object; the caller should ensure that no thread is + * blocked on this semaphore. If call made when thread blocked on semaphore the + * behaviour is unpredictable + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - IX_SUCCESS/IX_FAIL + */ +PUBLIC IX_STATUS ixOsalSemaphoreDestroy (IxOsalSemaphore * semaphore); + + +/* ======================== SpinLock functions ========================= + * + */ +#ifdef ENABLE_SPINLOCK + +/** + * @ingroup IxOsal + * + * @brief Initializes the SpinLock object + * + * @param slock - Spinlock handle + * @param slockType - Spinlock type + * + * Initializes the SpinLock object and its type. + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - IX_SUCCESS/IX_FAIL + */ +PUBLIC IX_STATUS ixOsalSpinLockInit(IxOsalSpinLock *slock, IxOsalSpinLockType slockType); + + +/** + * @ingroup IxOsal + * + * @brief Acquires a spin lock + * + * @param slock - Spinlock handle + * + * This routine acquires a spin lock so the + * caller can synchronize access to shared data in a + * multiprocessor-safe way by raising IRQL. + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - Returns IX_SUCCESS if the spinlock is acquired. Returns IX_FAIL if + * spinlock handle is NULL. If spinlock is already acquired by any + * other thread of execution then it tries in busy loop/spins till it + * gets spinlock. + */ +PUBLIC IX_STATUS ixOsalSpinLockLock(IxOsalSpinLock *slock); + +/** + * @ingroup IxOsal + * + * @brief Releases the spin lock + * + * @param slock - Spinlock handle + * + * This routine releases the spin lock which the thread had acquired + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - return IX_SUCCESS if the spinlock is released. Returns IX_FAIL if + * spinlockhandle passed is NULL. + */ +PUBLIC IX_STATUS ixOsalSpinLockUnlock(IxOsalSpinLock *slock); + +/** + * @ingroup IxOsal + * + * @brief Tries to acquire the spin lock + * + * @param slock - Spinlock handle + * + * This routine attempts to acquire a spin lock but doesn't block the thread + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - return IX_SUCCESS if the spinlock is acquired. Return IX_FAIL if + * spinlock is already acquired other thread of execution or if the + * spinlock handle is NULL + */ +PUBLIC IX_STATUS ixOsalSpinLockTry(IxOsalSpinLock *slock); + +/** + * @ingroup IxOsal + * + * @brief Destroy the spin lock object + * + * @param slock - Spinlock handle + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - IX_SUCCESS/IX_FAIL + */ +PUBLIC IX_STATUS ixOsalSpinLockDestroy(IxOsalSpinLock *slock); +/** + * @ingroup IxOsal + * + * @brief checks whether spinlock can be acquired + * + * @param slock - Spinlock handle + * + * This routine checks whether spinlock available for lock + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - IX_SUCCESS if spinlock is locked. Returns IX_FAIL if spinlock + * is not locked. + */ + +PUBLIC IX_STATUS ixOsalSpinLockIsLocked(IxOsalSpinLock *slock); + +/** + * @ingroup IxOsal + * + * @brief Acquires a spinlock + * + * @param slock - Spinlock handle + * + * This routine disables local irqs & then acquires a slock + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @usage This API can be used in user context or bottom half when critical + * section is shared between user context or bottom half and the + * irq handler + * + * @return - returns IX_SUCCESS if spinlock is acquired. If the spinlock is not + * available then it busy loops/spins till slock available. If the + * spinlock handle passed is NULL then returns IX_FAIL. + */ + +PUBLIC IX_STATUS ixOsalSpinLockLockIrq(IxOsalSpinLock *slock); +/** + * @ingroup IxOsal + * + * @brief Releases the spinlock + * + * @param slock - Spinlock handle + * + * This routine releases the acquired spinlock & enables the local irqs + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @usage This API can be used in user context or bottom half when critical + * section is shared between user context or bottom half and + * irq handler + * + * @return - returns IX_SUCCESS if slock is unlocked. Returns IX_FAIL if the + * slock is NULL. + */ +PUBLIC IX_STATUS ixOsalSpinLockUnlockIrq(IxOsalSpinLock *slock); + +/** + * @ingroup IxOsal + * + * @brief Tries to acquire the spinlock + * + * @param slock - Spinlock handle + * + * This routine disables local irq & attempts to acquire a spinlock but + * doesn't block the thread if spinlock not available. + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @usage This API can be used in user context or bottom half when critical + * section is shared between user context or bottom half and + * irq handler + * + * @return -If spinlock is available then returns the IX_SUCCESS with + * spinlock locked. If spinlock not available then enables the + * local irqs & returns IX_FAIL + * + */ +PUBLIC IX_STATUS ixOsalSpinLockTryIrq(IxOsalSpinLock *slock); + +/** + * @ingroup IxOsal + * + * @brief Acquires a spinlock + * + * @param slock - Spinlock handle + * + * This routine disables bottom half & then acquires a slock + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @usage This API can be used in user context when critical section is + * shared between user context & bottom half handler + * + * @return - returns IX_SUCCESS if spinlock is acquired. If the spinlock is not + * available then it busy loops/spins till slock available. If the + * spinlock handle passed is NULL then returns IX_FAIL. + */ +PUBLIC IX_STATUS ixOsalSpinLockLockBh(IxOsalSpinLock *slock); + +/** + * @ingroup IxOsal + * + * @brief Releases the spin lock + * + * @param slock - Spinlock handle + * + * This routine releases the acquired spinlock & enables the + * bottom half handler + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @usage This API can be used in user context when critical section is + * shared between user context & bottom half handler + * + * @return - returns IX_SUCCESS if slock is released or unlocked. + * Returns IX_FAIL if the slock is NULL. + */ +PUBLIC IX_STATUS ixOsalSpinLockUnlockBh(IxOsalSpinLock *slock); + +/** + * @ingroup IxOsal + * + * @brief Tries to acquire the spin lock + * + * @param slock - Spinlock handle + * + * This routine disables bottom half handler & attempts to acquire a spinlock + * but doesn't block the thread if spinlock not available. It enables the bh & + * returns IX_FAIL if spinlock not available. + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @usage This API can be used in user context when critical section is + * shared between user context & bottom half handler + * + * @return -Returns the IX_SUCCESS with spinlock locked if the spinlock is + * available. Enables the local irqs & return IX_FAIL + * if spinlock is not available. + */ +PUBLIC IX_STATUS ixOsalSpinLockTryBh(IxOsalSpinLock *slock); + +/** + * @ingroup IxOsal + * + * @brief Acquires a spinlock + * + * @param slock - Spinlock handle + * @param flags - local irqs saved in flags + * + * @usage This API can be used when critical section is shared between + * irq routines + * + * This routine saves local irqs in flags & then acquires a spinlock + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - returns IX_SUCCESS if spinlock acquired. If the spinlock is not + * available then it busy loops/spins till slock available. + * If the spinlock handle passed is NULL then returns IX_FAIL. + */ +PUBLIC IX_STATUS ixOsalSpinLockLockIrqSave(IxOsalSpinLock *slock, \ + UINT32 *flags); + +/** + * @ingroup IxOsal + * + * @brief Releases the spin lock + * + * @param slock - Spinlock handle + * @param flags - local irqs saved in flags + * + * @usage This API can be used when critical section is shared between + * irq routines + * + * This routine releases the acquired spin lock & restores irqs in flags + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - returns IX_SUCCESS if slock is unlocked. Returns IX_FAIL if the + * slock is NULL. + */ +PUBLIC IX_STATUS ixOsalSpinLockUnlockIrqRestore(IxOsalSpinLock *slock, \ + UINT32 *flags); + +/** + * @ingroup IxOsal + * + * @brief Tries to acquire the spinlock + * + * @param slock - Spinlock handle + * @param flags - local irqs saved in flags + * + * This routine saves irq in flags & attempts to acquire a spinlock but + * doesn't block the thread if the spin lock not avialble. If the + * spinlock not available then it restore the irqs & return IX_FAIL. + * This API can be used when critical section is shared between irq routines + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return -Returns the IX_SUCCESS with spinlock locked if the spinlock is + * available. Enables the local irqs & returns IX_FAIL + * if spinlock not available. + */ +PUBLIC IX_STATUS ixOsalSpinLockTryIrqSave(IxOsalSpinLock *slock, UINT32 *flags); + +#endif /* ENABLE_SPINLOCK */ + +/** + * @ingroup IxOsal + * + * @brief Initializes value of atomic variable at compile time + * + * @param val IN - value that needs to be assigned to atomic variable + * + * Initializes the value of atomicVar at compile time + * Usage - IxOsalAtomic atomicVar = IX_OSAL_ATOMIC_INIT(0); + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return value initialized in atomic variable + */ + +#define IX_OSAL_ATOMIC_INIT(val) \ + IX_OSAL_OS_ATOMIC_INIT(val) + +/** + * @ingroup IxOsal + * + * @brief Atomically read the value of atomic variable + * + * @param atomicVar IN - atomic variable + * + * Atomically reads the value of atomicVar to the outValue + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return atomicVar value + */ + +PUBLIC UINT32 ixOsalAtomicGet(IxOsalAtomic *atomicVar); + + +/** + * @ingroup IxOsal + * + * @brief Atomically set the value of atomic variable + * + * @param inValue IN - atomic variable to be set equal to inValue + * + * @param atomicVar OUT - atomic variable + * + * Atomically sets the value of IxOsalAtomicVar to the value given + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return none + */ + +PUBLIC void ixOsalAtomicSet(UINT32 inValue,IxOsalAtomic *atomicVar); + +/** + * @ingroup IxOsal + * + * @brief add the value to atomic variable + * + * @param inValue (in) - value to be added to the atomic variable + * + * @param atomicVar (in & out) - atomic variable + * + * Atomically adds the value of inValue to the IxOsalAtomicVar + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return none + */ + +PUBLIC void ixOsalAtomicAdd(UINT32 inValue, IxOsalAtomic *atomicVar); + +/** + * @ingroup IxOsal + * + * @brief subtract the value from atomic variable + * + * @param inValue IN - atomic variable value to be subtracted by value + * + * @param atomicVar IN/OUT - atomic variable + * + * Atomically subtracts the value of IxOsalAtomicVar by inValue + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return none + */ + +PUBLIC void ixOsalAtomicSub(UINT32 inValue, IxOsalAtomic *atomicVar); + +/** + * @ingroup IxOsal + * + * @brief subtract the value from atomic variable and test result + * + * @param inValue IN - value to be subtracted from the atomic variable + * + * @param atomicVar IN/OUT - atomic variable + * + * Atomically subtracts the IxOsalAtomicVar value by inValue and + * test the result. + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return TRUE if the result is zero or FALSE for other cases. + */ + +PUBLIC IX_STATUS ixOsalAtomicSubAndTest( + UINT32 inValue, IxOsalAtomic *atomicVar); + +/** + * @ingroup IxOsal + * + * @brief increment value of atomic variable by 1 + * + * @param atomicVar IN/OUT - atomic variable + * + * Atomically increments the value of IxOsalAtomicVar by 1. + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return none + */ + +PUBLIC void ixOsalAtomicInc(IxOsalAtomic *atomicVar); + +/** + * @ingroup IxOsal + * + * @brief decrement value of atomic variable by 1 + * + * @param atomicVar IN/OUT - atomic variable + * + * Atomically decrements the value of IxOsalAtomicVar by 1. + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return none + */ + +PUBLIC void ixOsalAtomicDec(IxOsalAtomic *atomicVar); + +/** + * @ingroup IxOsal + * + * @brief decrement atomic variable value by 1 and test result + * + * @param atomicVar (IN/OUT) - atomic variable + * + * Atomically decrements the value of IxOsalAtomicVar by 1 and test + * result for zero. + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return TRUE if the result is zero or FALSE otherwise + */ + +PUBLIC IX_STATUS ixOsalAtomicDecAndTest(IxOsalAtomic *atomicVar); + +/** + * @ingroup IxOsal + * + * @brief increment atomic variable by 1 and test result + * + * @param atomicVar (IN/OUT) - atomic variable + * + * Atomically increments the value of IxOsalAtomicVar by 1 and test + * result for zero. + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return TRUE if the result is zero or FALSE otherwise + */ + +PUBLIC IX_STATUS ixOsalAtomicIncAndTest(IxOsalAtomic *atomicVar); + + +/** + * @ingroup IxOsal + * + * @brief memory barrier which orders both memory read and writes + * + * memory barrier that orders both memory read and writes + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return none + */ + +PUBLIC void ixOsalMemBarrier(void); + +/** + * @ingroup IxOsal + * + * @brief memory barrier which orders memory reads + * + * memory barrier that orders memory reads + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return none + */ + +PUBLIC void ixOsalReadMemBarrier(void); + +/** + * @ingroup IxOsal + * + * @brief memory barrier which orders memory writes + * + * memory barrier that orders memory writes + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return none + */ + +PUBLIC void ixOsalWriteMemBarrier(void); + + +/* ========================== Time functions =========================== + * + */ + +/** + * @ingroup IxOsal + * + * @brief Yields execution of current thread + * + * Yields the execution of the current thread + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - none + */ +PUBLIC void ixOsalYield (void); + +/** + * @ingroup IxOsal + * + * @brief Yielding sleep for a number of milliseconds + * + * @param milliseconds - number of milliseconds to sleep + * + * The calling thread will sleep for the specified number of milliseconds. + * This sleep is yielding, hence other tasks will be scheduled by the + * operating system during the sleep period. Calling this function with an + * argument of 0 will place the thread at the end of the current scheduling + * loop. + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - none + */ +PUBLIC void ixOsalSleep (UINT32 milliseconds); + +/** + * @ingroup IxOsal + * + * @brief Busy sleep for a number of microseconds + * + * @param microseconds - number of microseconds to sleep + * + * Sleeps for the specified number of microseconds, without explicitly + * yielding thread execution to the OS scheduler + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - none + */ +PUBLIC void ixOsalBusySleep (UINT32 microseconds); + +/** + * @ingroup IxOsal + * + * @brief Retrieves the current timestamp + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - The current timestamp + * + * @note The implementation of this function is platform-specific. Not + * all the platforms provide a high-resolution timestamp counter. + */ +PUBLIC UINT32 ixOsalTimestampGet (void); + +/** + * @ingroup IxOsal + * + * @brief Resolution of the timestamp counter + * + * Retrieves the resolution (frequency) of the timestamp counter. + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - The resolution of the timestamp counter + * + * @note The implementation of this function is platform-specific. Not all + * the platforms provide a high-resolution timestamp counter. + */ +PUBLIC UINT32 ixOsalTimestampResolutionGet (void); + +/** + * @ingroup IxOsal + * + * @brief System clock rate, in ticks + * + * Retrieves the resolution (number of ticks per second) of the system clock + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - The system clock rate + * + * @note The implementation of this function is platform and OS-specific. + * The system clock rate is not always available - + */ +PUBLIC UINT32 ixOsalSysClockRateGet (void); + +/** + * @ingroup IxOsal + * + * @brief Current system time + * + * @param tv - pointer to an IxOsalTimeval structure to store the current + * time in + * + * Retrieves the current system time (real-time) + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - none + * + * @note The implementation of this function is platform-specific. Not all + * platforms have a real-time clock. + */ +PUBLIC void ixOsalTimeGet (IxOsalTimeval * tv); + + + +/** + * @ingroup IxOsalInternal + * + * @brief Converts ixOsalTimeVal into ticks + * + * @param tv - an IxOsalTimeval structure + * + * Internal function to convert an IxOsalTimeval structure into OS ticks + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - Corresponding number of ticks + * + * Note: This function is OS-independent and internal to OSAL. + */ +PUBLIC UINT32 ixOsalTimevalToTicks (IxOsalTimeval tv); + + +/** + * @ingroup IxOsal + * + * @brief Converts ixOsalTimeVal into ticks + * + * @param tv - an IxOsalTimeval structure + * + * Converts an IxOsalTimeval structure into OS ticks + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - Corresponding number of ticks + * + * Note: This function is OS-independent. Implemented by core. + */ +#define IX_OSAL_TIMEVAL_TO_TICKS(tv) ixOsalTimevalToTicks(tv) + + + +/** + * @ingroup IxOsalInternal + * + * @brief Converts ticks into ixOsalTimeVal + * + * @param ticks - number of ticks + * @param pTv - pointer to the destination structure + * + * Internal function to convert the specified number of ticks into + * a IxOsalTimeval structure + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - Corresponding IxOsalTimeval structure + * Note: This function is OS-independent and internal to OSAL + */ + +PUBLIC void ixOsalTicksToTimeval (UINT32 ticks, IxOsalTimeval * pTv); + + +/** + * @ingroup IxOsal + * + * @brief Converts ticks into ixOsalTimeVal + * + * @param ticks - number of ticks + * @param pTv - pointer to the destination structure + * + * Converts the specified number of ticks into an IxOsalTimeval structure + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - Corresponding IxOsalTimeval structure + * Note: This function is OS-independent. Implemented by core. + */ +#define IX_OSAL_TICKS_TO_TIMEVAL(ticks, pTv) \ + ixOsalTicksToTimeval(ticks, pTv) + + + + +/** + * @ingroup IxOsal + * + * @brief Converts ixOsalTimeVal to milliseconds + * + * @param tv - IxOsalTimeval structure to convert + * + * Converts an IxOsalTimeval structure into milliseconds + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - Corresponding number of milliseconds + * Note: This function is OS-independent. Implemented by core. + */ +#define IX_OSAL_TIMEVAL_TO_MS(tv) ((tv.secs * 1000) + (tv.nsecs / IX_OSAL_MILLION)) + + +/** + * @ingroup IxOsal + * + * @brief Converts milliseconds to IxOsalTimeval + * + * @param milliseconds - number of milliseconds to convert + * @param pTv - pointer to the destination structure + * + * Converts a millisecond value into an IxOsalTimeval structure + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - Corresponding IxOsalTimeval structure + * Note: This function is OS-independent. Implemented by core. + */ +#define IX_OSAL_MS_TO_TIMEVAL(milliseconds, pTv) \ + ((IxOsalTimeval *) pTv)->secs = milliseconds / 1000; \ + ((IxOsalTimeval *) pTv)->nsecs = (milliseconds % 1000) * 1000000 + + +/** + * @ingroup IxOsal + * + * @brief "equal" comparison for IxOsalTimeval + * + * @param tvA, tvB - IxOsalTimeval structures to compare + * + * Compares two IxOsalTimeval structures for equality + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - TRUE if the structures are equal + * - FALSE otherwise + * Note: This function is OS-independant + */ +#define IX_OSAL_TIME_EQ(tvA, tvB) \ + ((tvA).secs == (tvB).secs && (tvA).nsecs == (tvB).nsecs) + + +/** + * @ingroup IxOsal + * + * @brief "less than" comparison for IxOsalTimeval + * + * @param tvA, tvB - IxOsalTimeval structures to compare + * + * Compares two IxOsalTimeval structures to determine if the first one is + * less than the second one + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - TRUE if tvA < tvB + * - FALSE otherwise + * Note: This function is OS-independent. Implemented by core. + */ +#define IX_OSAL_TIME_LT(tvA,tvB) \ + ((tvA).secs < (tvB).secs || \ + ((tvA).secs == (tvB).secs && (tvA).nsecs < (tvB).nsecs)) + + +/** + * @ingroup IxOsal + * + * @brief "greater than" comparison for IxOsalTimeval + * + * @param tvA, tvB - IxOsalTimeval structures to compare + * + * Compares two IxOsalTimeval structures to determine if the first one is + * greater than the second one + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - TRUE if tvA > tvB + * - FALSE otherwise + * Note: This function is OS-independent. + */ +#define IX_OSAL_TIME_GT(tvA, tvB) \ + ((tvA).secs > (tvB).secs || \ + ((tvA).secs == (tvB).secs && (tvA).nsecs > (tvB).nsecs)) + + +/** + * @ingroup IxOsal + * + * @brief "add" operator for IxOsalTimeval + * + * @param tvA, tvB - IxOsalTimeval structures to add + * + * Adds the second IxOsalTimevalStruct to the first one (equivalent to + * tvA += tvB) + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - none + * Note: This function is OS-independent. + */ +#define IX_OSAL_TIME_ADD(tvA, tvB) \ + (tvA).secs += (tvB).secs; \ + (tvA).nsecs += (tvB).nsecs; \ + if ((tvA).nsecs >= IX_OSAL_BILLION) \ + { \ + (tvA).secs++; \ + (tvA).nsecs -= IX_OSAL_BILLION; } + + +/** + * @ingroup IxOsal + * + * @brief "subtract" operator for IxOsalTimeval + * + * @param tvA, tvB - IxOsalTimeval structures to subtract + * + * Subtracts the second IxOsalTimevalStruct from the first one (equivalent + * to tvA -= tvB) + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - none + * Note: This function is OS-independent. Implemented by core. + */ +#define IX_OSAL_TIME_SUB(tvA, tvB) \ + if ((tvA).nsecs >= (tvB).nsecs) \ + { \ + (tvA).secs -= (tvB).secs; \ + (tvA).nsecs -= (tvB).nsecs; \ + } \ + else \ + { \ + (tvA).secs -= ((tvB).secs + 1); \ + (tvA).nsecs += IX_OSAL_BILLION - (tvB).nsecs; \ + } + +/** + * @ingroup IxOsal + * + * @brief "zero" comparison for IxOsalTimeval + * + * @param tvA - IxOsalTimeval structure to check for zero + * + * Checks if the IxOsalTimevalStruct passed has value zero (equivalent + * to tvA == 0) + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - none + * Note: This function is OS-independent. Implemented by core. + */ +#define IX_OSAL_TIME_ISZERO(tvA) \ + ((tvA).secs == 0 && (tvA).nsecs == 0) + +/** + * @ingroup IxOsal + * + * @brief "set" operator for IxOsalTimeval + * + * @param tvA, tvB - IxOsalTimeval structures to use for set + * + * Set the value of second IxOsalTimevalStruct to the first + * IxOsalTimevalStruct (equivalent to tvA = tvB) + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - none + * Note: This function is OS-independent. Implemented by core. + */ +#define IX_OSAL_TIME_SET(tvA,tvB) \ + { (tvA).secs = (tvB).secs; (tvA).nsecs = (tvB).nsecs; } + +/** + * @ingroup IxOsal + * + * @brief "normalize" operator for IxOsalTimeval + * + * @param tvA - IxOsalTimeval structure to normalize + * + * Check nanoseconds field of the IxOsalTimevalStruct and set it to a + * positive value less than IX_OSAL_BILLION by adjusting 'seconds' field + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - none + * Note: This function is OS-independent. Implemented by core. + */ +/* IX_OSSL_TIME_NORMALIZE */ +#define IX_OSAL_TIME_NORMALIZE(tvA) \ + { (tvA).secs += (tvA).nsecs / IX_OSAL_BILLION; \ + (tvA).nsecs = (tvA).nsecs % IX_OSAL_BILLION; } + +/** + * @ingroup IxOsal + * + * @brief Validity check for IxOsalTimeval + * + * @param tvA - IxOsalTimeval structure to check for validity + * + * Checks if the nanoseconds field of IxOsalTimevalStruct has a valid + * value + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - none + * Note: This function is OS-independent. Implemented by core. + */ +/* IX_OSSL_TIME_VALID */ +#define IX_OSAL_TIME_VALID(tvA) \ + ((tvA).nsecs >= 0 && (tvA).nsecs < IX_OSAL_BILLION) + +/** + * @ingroup IxOsal + * + * @brief "set to zero" operator for IxOsalTimeval + * + * @param tvA - IxOsalTimeval structure to set to zero + * + * Set the IxOsalTimevalStruct to contain value zero (equivalent + * to tvA = 0) + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - none + * Note: This function is OS-independent. Implemented by core. + */ +/* IX_OSSL_TIME_ZERO */ +#define IX_OSAL_TIME_ZERO(tvA) \ + { (tvA).secs = 0; (tvA).nsecs = 0; } + +/* ============================= Logging ============================== + * + */ + +/** + * @ingroup IxOsal + * + * @brief Setting the module name + * + * @param moduleName - the string to be prepended with OSAL log message + * + * A facility provided to the user to prepend module name with OSAL + * log messages. Example usage of this API to help the user to separate + * messages from other modules. After the API called the subsequent calls to + * ixOsalLog or ixOsalStdLog API's shall log the module name followed with + * regular OSAL log message. To disable module name prepend users need to + * invoke this API as ixOsalLogSetPrefix(""); + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - None. + * + */ +PUBLIC VOID ixOsalLogSetPrefix (CHAR * moduleName); + +/** + * @ingroup IxOsal + * + * @brief Interrupt-safe logging function + * + * @param level - identifier prefix for the message + * @param device - output device + * @param format - message format, in a printf format + * @param arg1, arg2, arg3, arg4, arg5, arg6 - up to 6 arguments to be printed + * + * IRQ-safe logging function, similar to printf. Accepts up to 6 arguments + * to print (excluding the level, device and the format). This function will + * actually display the message only if the level is lower than the current + * verbosity level or if the IX_OSAL_LOG_USER level is used. An output device + * must be specified (see IxOsalTypes.h). + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - Beside the exceptions documented in the note below, the returned + * value is the number of printed characters, or -1 if the parameters are + * incorrect (NULL format, unknown output device) + * + * @note The exceptions to the return value are: + * VxWorks*: The return value is 32 if the specified level is 1 and 64 + * if the specified level is greater than 1 and less or equal than 9. + * WinCE*: If compiled for EBOOT then the return value is always 0. + * + * @note The given print format should take into account the specified + * output device. IX_OSAL_STDOUT supports all the usual print formats, + * however a custom hex display specified by IX_OSAL_HEX would support + * only a fixed number of hexadecimal digits. + */ +PUBLIC INT32 ixOsalLog (IxOsalLogLevel level, + IxOsalLogDevice device, + char *format, + int arg1, + int arg2, int arg3, int arg4, int arg5, int arg6); + +/** + * @ingroup IxOsal + * + * @brief sets the current logging verbosity level + * + * @param level - new log verbosity level + * + * Sets the log verbosity level. The default value is IX_OSAL_LOG_ERROR. + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - Old log verbosity level + */ +PUBLIC UINT32 ixOsalLogLevelSet (UINT32 level); + +/** + * @ingroup IxOsal + * + * @brief simple logging function + * + * @param arg_pFmtString - message format, in printf format + * @param ... - variable arguments + * + * Logging function, similar to printf. This provides a barebones logging + * mechanism for users without differing verbosity levels. This interface + * is not quaranteed to be IRQ safe. + * + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - none + */ +IX_STATUS ixOsalStdLog(const char* arg_pFmtString, + ...); + + +/* ============================= Logging ============================== + * + */ + +/** + * @ingroup IxOsal + * + * @brief Schedules a repeating timer + * + * @param timer - handle of the timer object + * @param period - timer trigger period, in milliseconds + * @param priority - timer priority (0 being the highest) + * @param callback - user callback to invoke when the timer triggers + * @param param - custom parameter passed to the callback + * + * Schedules a timer to be called every period milliseconds. The timer + * will invoke the specified callback function possibly in interrupt + * context, passing the given parameter. If several timers trigger at the + * same time contention issues are dealt according to the specified timer + * priorities. + * + * @li Reentrant: no + * @li IRQ safe: no + * + * @return - IX_SUCCESS/IX_FAIL + */ +PUBLIC IX_STATUS ixOsalRepeatingTimerSchedule (IxOsalTimer * timer, + UINT32 period, + UINT32 priority, + IxOsalVoidFnVoidPtr callback, + void *param); + +/** + * @ingroup IxOsal + * + * @brief Schedules a single-shot timer + * + * @param timer - handle of the timer object + * @param period - timer trigger period, in milliseconds + * @param priority - timer priority (0 being the highest) + * @param callback - user callback to invoke when the timer triggers + * @param param - custom parameter passed to the callback + * + * Schedules a timer to be called after period milliseconds. The timer + * will cease to function past its first trigger. The timer will invoke + * the specified callback function, possibly in interrupt context, passing + * the given parameter. If several timers trigger at the same time contention + * issues are dealt according to the specified timer priorities. + * + * @li Reentrant: no + * @li IRQ safe: no + * + * @return - IX_SUCCESS/IX_FAIL + */ +PUBLIC IX_STATUS ixOsalSingleShotTimerSchedule (IxOsalTimer * timer, + UINT32 period, + UINT32 priority, + IxOsalVoidFnVoidPtr callback, void *param); + +/** + * @ingroup IxOsal + * + * @brief Cancels a running timer + * + * @param timer - handle of the timer object + * + * Cancels a single-shot or repeating timer. + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - IX_SUCCESS/IX_FAIL + */ +PUBLIC IX_STATUS ixOsalTimerCancel (IxOsalTimer * timer); + +/** + * @ingroup IxOsal + * + * @brief displays all the running timers + * + * Displays a list with all the running timers and their parameters (handle, + * period, type, priority, callback and user parameter) + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - none + */ +PUBLIC void ixOsalTimersShow (void); + + +/* ============================= Version ============================== + * + */ + +/** + * @ingroup IxOsal + * + * @brief provides the name of the Operating System running + * + * @param osName - Pointer to a NULL-terminated string of characters + * that holds the name of the OS running. + * This is both an input and an ouput parameter + * @param maxSize - Input parameter that defines the maximum number of + * bytes that can be stored in osName + * + * Returns a string of characters that describe the Operating System name + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * return - IX_SUCCESS for successful retrieval + * - IX_FAIL if (osType == NULL | maxSize =< 0) + */ +PUBLIC IX_STATUS ixOsalOsNameGet (INT8* osName, INT32 maxSize); + +/** + * @ingroup IxOsal + * + * @brief provides the version of the Operating System running + * + * @param osVersion - Pointer to a NULL terminated string of characters + * that holds the version of the OS running. + * This is both an input and an ouput parameter + * @param maxSize - Input parameter that defines the maximum number of + * bytes that can be stored in osVersion + * + * Returns a string of characters that describe the Operating System's version + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * return - IX_SUCCESS for successful retrieval + * - IX_FAIL if (osVersion == NULL | maxSize =< 0) + */ +PUBLIC IX_STATUS ixOsalOsVersionGet(INT8* osVersion, INT32 maxSize); + + +#ifdef ENABLE_PCI + +/* ============================= PCI ============================== + * + */ + +/** + * @ingroup IxOsal + * + * @brief Find the PCI device for the particular vendor and device. + * + * @param vendor_id - The vendor ID of the device to be found. + * @param device_id - The device ID of the device to be found. + * @param pci_device - The last found IxOsalPciDev or NULL. + * + * This function will find the PCI device for the particular vendor and device. + * The pci_device parameter should be NULL when calling for the first time + * and the last returned value when searching for multiple devices of + * the same ID. + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - IxOsalPciDev handle if found/NULL. + */ +PUBLIC IxOsalPciDev ixOsalPciDeviceFind(UINT32 vendor_id,UINT32 device_id,IxOsalPciDev pci_dev); + +/** + * @ingroup IxOsal + * + * @brief Obtain the bus, slot and function of the PCI device. + * + * @param pci_device - The IxOsalPciDev to query. + * @param bus - The returned bus or NULL if the bus is not needed. + * @param slot - The returned slot or NULL if the bus is not needed + * @param func - The returned func or NULL if the bus is not needed. + * + * This function will return the bus slot and function for an IxOsalPciDev + * previously obtained from ixOsalPciDeviceFind(). Any of the bus/slot/func + * parameters may be null if the information is not needed. + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - IX_SUCCESS/IX_FAIL. + */ +PUBLIC INT32 ixOsalPciSlotAddress(IxOsalPciDev pci_dev,UINT32 *bus,UINT32 *slot,UINT32 *func); + +/** + * @ingroup IxOsal + * + * @brief Retrieve byte of information from the PCI configuration space. + * + * @param pci_device - The IxOsalPciDev to query. + * @param offset - Offset from the base of the configuration space. + * @param val - Byte value fetched from the mentioned location + * + * This function retrieves a byte of information, starting at the specified + * offset, from the PCI configuration space on a particular PCI device. + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - IX_SUCCESS/Error code on failure. + */ +PUBLIC INT32 ixOsalPciConfigReadByte(IxOsalPciDev pci_dev,UINT32 offset,UINT8* val); + +/** + * @ingroup IxOsal + * + * @brief Retrieve word of information from the PCI configuration space. + * + * @param pci_device - The IxOsalPciDev to query. + * @param offset - Offset from the base of the configuration space. + * @param val - Word value fetched from the mentioned location + * + * This function retrieves a word of information, starting at the specified + * offset, from the PCI configuration space on a particular PCI device. + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - IX_SUCCESS/Error code on failure. + */ +PUBLIC INT32 ixOsalPciConfigReadShort(IxOsalPciDev pci_dev,UINT32 offset,UINT16* val); + +/** + * @ingroup IxOsal + * + * @brief Retrieve double word of information from the PCI configuration space. + * + * @param pci_device - The IxOsalPciDev to query. + * @param offset - Offset from the base of the configuration space. + * @param val - Double word value fetched from the mentioned location + * + * This function retrieves a double word of information, starting at the specified + * offset, from the PCI configuration space on a particular PCI device. + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - IX_SUCCESS/Error code on failure. + */ +PUBLIC INT32 ixOsalPciConfigReadLong(IxOsalPciDev pci_dev,UINT32 offset,UINT32* val); + +/** + * @ingroup IxOsal + * + * @brief Set byte information in the PCI configuration space. + * + * @param pci_device - The IxOsalPciDev to query. + * @param offset - Offset from the base of the configuration space. + * @param val - Byte value to be set at the mentioned location + * + * This function sets a byte of data, starting at the specified offset, to + * the PCI configuration space for a particular PCI device. + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - IX_SUCCESS/Error code on failure. + */ +PUBLIC INT32 ixOsalPciConfigWriteByte(IxOsalPciDev pci_dev,UINT32 offset,UINT8 val); + +/** + * @ingroup IxOsal + * + * @brief Set word information in the PCI configuration space. + * + * @param pci_device - The IxOsalPciDev to query. + * @param offset - Offset from the base of the configuration space. + * @param val - Word value to be set at the mentioned location + * + * This function sets a word of data, starting at the specified offset, to + * the PCI configuration space for a particular PCI device. + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - IX_SUCCESS/Error code on failure. + */ +PUBLIC INT32 ixOsalPciConfigWriteShort(IxOsalPciDev pci_dev,UINT32 offset,UINT16 val); + +/** + * @ingroup IxOsal + * + * @brief Set double word information in the PCI configuration space. + * + * @param pci_device - The IxOsalPciDev to query. + * @param offset - Offset from the base of the configuration space. + * @param val - Double word value to be set at the mentioned location + * + * This function sets a double word of data, starting at the specified offset, to + * the PCI configuration space for a particular PCI device. + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - IX_SUCCESS/Error code on failure. + */ +PUBLIC INT32 ixOsalPciConfigWriteLong(IxOsalPciDev pci_dev,UINT32 offset,UINT32 val); + +/** + * @ingroup IxOsal + * + * @brief Free a PCI device handle. + * + * @param pci_device - The IxOsalPciDev to free. + * + * This function free the IxOsalPciDev * that previously allocated with the + * ixOsalPciDeviceFind. + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - None. + */ +PUBLIC void ixOsalPciDeviceFree(IxOsalPciDev pci_dev); + +#endif /* ENABLE_PCI */ + +/* ============================= MATH ============================== + * + */ + +/** + * @ingroup IxOsal + * + * @brief UINT64 data type division with 32 bit divisor + * + * @param dividend - dividend (UINT64) + * + * @param divisor - divisor (UINT32) + * + * This function enable UINT64 datatype division for 32 bit system. + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - quotient (UINT64) + */ +#define IX_OSAL_UDIV64_32(dividend, divisor) \ + IX_OSAL_OS_UDIV64_32(dividend, divisor) + +/** + * @ingroup IxOsal + * + * @brief UINT64 data type mod with 32 bit divisor + * + * @param dividend - dividend (UINT64) + * + * @param divisor - divisor (UINT32) + * + * This function enable UINT64 datatype mod for 32 bit system. + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - remainder (UINT32) + */ +#define IX_OSAL_UMOD64_32(dividend, divisor) \ + IX_OSAL_OS_UMOD64_32(dividend, divisor) + +#ifdef IX_OSAL_MEM_MAP_GLUECODE + +/* + * Glue code for memory map + */ +PUBLIC void ixOsalGlueCodeMemoryMapInit(UINT32 index,UINT32 phyAddr,UINT32 mapSize,UINT32 virtAddr); + + +PUBLIC void ixOsalGlueCodeMemoryMapUnInit(UINT32 index,UINT32 *virtAddr); + +#endif /* IX_OSAL_MEM_MAP_GLUECODE */ + +/** + * @} IxOsal + */ + + +/** + * @ingroup IxOsal + * + * @brief get the Thread id of the current thread in execution. + * + * @param ptrTid - pointer IxOsalThread structure + * + * This function returns the Thread id. + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - IX_SUCCESS/Error code on failure. + */ + +PUBLIC +IX_STATUS ixOsalThreadGetId(IxOsalThread *ptrTid); + +/** + * @ingroup IxOsal + * + * @brief set the Policy and priority of the thread + * + * @param tid - pointer IxOsalThread structure + * + * @param policy - new Thread policy + * + * @param priority - new thread priority + * + * This function changes the Policy and priority of the thread. + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - IX_SUCCESS/Error code on failure. + */ + +PUBLIC +IX_STATUS ixOsalThreadSetPolicyAndPriority( + IxOsalThread *tid, + UINT32 policy, + UINT32 priority); + +/** + * @ingroup IxOsal + * + * @brief get the Policy and priority of the thread + * + * @param tid - pointer IxOsalThread structure + * + * @param policy (OUT) - Thread policy + * + * @param priority (OUT) - Thread priority + * + * This function queries for the Policy and priority of the thread. + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - IX_SUCCESS/Error code on failure. + */ + +PUBLIC +IX_STATUS ixOsalThreadGetPolicyAndPriority( + IxOsalThread *tid, + UINT32 *policy, + UINT32 *priority); + +/** + * @ingroup IxOsal + * + * @brief Waits on (decrements) a semaphore for specified time + * + * @param sid - semaphore handle + * @param timeout - timeout, in ms; IX_OSAL_WAIT_FOREVER (-1) if the thread + * is to block indefinitely or IX_OSAL_WAIT_NONE (0) if the thread is to + * return immediately even if the call fails + * + * Decrements a semaphore, blocking for specified time if the semaphore is + * unavailable (value is 0). + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - IX_SUCCESS/IX_FAIL + */ + +PUBLIC IX_STATUS ixOsalSemaphoreDownTimeout( + IxOsalSemaphore *sid, + INT32 timeout); + +/** + * @ingroup IxOsal + * + * @brief Waits on (decrements) a semaphore for specified time. + * + * @param sid - semaphore handle + * @param timeout - timeout, in ms; IX_OSAL_WAIT_FOREVER (-1) if the thread + * is to block indefinitely or IX_OSAL_WAIT_NONE (0) if the thread is to + * return immediately even if the call fails + * + * Decrements a semaphore, blocking for specified time if the semaphore is + * unavailable (value is 0).The current thread or process can be interrupted + * by a signal. + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - IX_SUCCESS/IX_FAIL + */ + +PUBLIC IX_STATUS ixOsalSemaphoreWaitInterruptible( + IxOsalSemaphore *sid, + INT32 timeout); + +/** + * @ingroup IxOsal + * + * @brief Wakes up thread blocked on semapohore. Increments a semaphore if + * the value leass than one and wakes up threads waiting on wait queue. + * + * @param sid - semaphore handle + * + * increments a semaphore if the value less than one and wakes up the thread + * which is waiting for the semaphore. + * + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - IX_SUCCESS/IX_FAIL + */ + +PUBLIC IX_STATUS ixOsalSemaphorePostWakeup(IxOsalSemaphore *sid); + +/** + * @ingroup IxOsal + * + * @brief Wakes up thread blocked on semapohore. Increments a semaphore if + * the value leass than one and wakes up all threads waiting on wait queue. + * + * @param sid - semaphore handle + * + * increments a semaphore if the value less than one and wakes up the all threads + * which is waiting for the semaphore. + * + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - IX_SUCCESS/IX_FAIL + */ + +PUBLIC IX_STATUS ixOsalSemaphoreFlush(IxOsalSemaphore *sid); + +/** + * @ingroup IxOsal + * + * @brief thread goes to sleep for number of ticks specified + * + * @param sleeptime_ticks - number of ticks + * + * Forces current thread of execution to sleep for speicfied number of ticks + * + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - IX_SUCCESS/IX_FAIL + */ + +PUBLIC IX_STATUS ixOsalSleepTick(UINT32 sleeptime_ticks); + +/** + * @ingroup IxOsal + * + * @brief thread goes to sleep for number of mili seconds specified, but the thread + * can be interrupted by a signal + * + * @param sleeptime_ms - number of ms + * + * Forces current thread of execution to sleep for speicfied number of ticks. + * The thread of execution which goes to sleep can be interrupted by a signal. + * + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @return - IX_SUCCESS/IX_FAIL + */ + +PUBLIC IX_STATUS ixOsalSleepUninterruptible( + UINT32 sleeptime_ms); + +/** + * @ingroup IxOsal + * + * @brief converts 16bit value from host to network byte order + * + * @param uData - 16bit number + * + * This function converts 16bit value from host to network byte order + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - 16bit network byte ordered value of uData + */ +#define IX_OSAL_HOST_TO_NW_16(uData) IX_OSAL_OEM_HOST_TO_NW_16(uData) + +/** + * @ingroup IxOsal + * + * @brief converts 32bit value from host to network byte order + * + * @param uData - 32bit number + * + * This function converts 32bit value from host to network byte order + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - 32bit network byte ordered value of uData + */ +#define IX_OSAL_HOST_TO_NW_32(uData) IX_OSAL_OEM_HOST_TO_NW_32(uData) + +/** + * @ingroup IxOsal + * + * @brief converts 64bit value from host to network byte order + * + * @param uData - 64bit number + * + * This function converts 64bit value from host to network byte order + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - 64bit network byte ordered value of uData + */ +#define IX_OSAL_HOST_TO_NW_64(uData) IX_OSAL_OEM_HOST_TO_NW_64(uData) + +/** + * @ingroup IxOsal + * + * @brief converts 128bit value from host to network byte order + * + * @param uDataSrc - UINT128 type source + * + * @param uDataDest - UINT128 type dest + * + * This function converts 128bit uDataSrc value from host type to + * network byte order in uDataDest. It is expected that both the + * function arguments are UINT128 type. To access the UINT28 users + * use the mUINT32 array. + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - None + */ +#define IX_OSAL_HOST_TO_NW_128(uDataSrc, uDataDest) \ + IX_OSAL_OEM_HOST_TO_NW_128(uDataSrc, uDataDest) + +/** + * @ingroup IxOsal + * + * @brief converts 16bit value from network to host byte order + * + * @param uData - 16bit number + * + * This function converts 16bit value from network to host byte order + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - 16bit host byte ordered value of uData + */ +#define IX_OSAL_NW_TO_HOST_16(uData) IX_OSAL_OEM_NW_TO_HOST_16(uData) + +/** + * @ingroup IxOsal + * + * @brief converts 32bit value from network to host byte order + * + * @param uData - 32bit number + * + * This function converts 32bit value from network to host byte order + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - 32bit host byte ordered value of uData + */ +#define IX_OSAL_NW_TO_HOST_32(uData) IX_OSAL_OEM_NW_TO_HOST_32(uData) + +/** + * @ingroup IxOsal + * + * @brief converts 64bit value from network to host byte order + * + * @param uData - 64bit number + * + * This function converts 64bit value from network to host byte order + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - 64bit host byte ordered value of uData + */ +#define IX_OSAL_NW_TO_HOST_64(uData) IX_OSAL_OEM_NW_TO_HOST_64(uData) + +/** + * @ingroup IxOsal + * + * @brief converts 128bit value from network to host byte order + * + * @param uDataSrc - UINT128 type source + * + * @param uDataDest - UINT128 type destination + * + * This function converts 128bit value from host to network + * byte order in uDataDest. It is expected that the function + * both the arguements are UINT128 type. To access the UINT128 users use + * mUINT32 array. + + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - None + */ +#define IX_OSAL_NW_TO_HOST_128(uDataSrc, uDataDest) \ + IX_OSAL_OEM_NW_TO_HOST_128(uDataSrc, uDataDest) + +/** + * @ingroup IxOsal + * + * @brief generates 32bitrandom number + * + * @param num - UINT32 pointer to number where the random number generated + * gets stored + * + * This function generates 32bit random number. + * + * @li Reentrant: no + * @li IRQ safe: no + * + * @return - None + */ +PUBLIC VOID ixOsalGetRandomNum32(UINT32 *num); + +#ifdef __cplusplus +} +#endif + +#endif /* IxOsal_H */ diff --git a/Acceleration/library/icp_utils/OSAL/common/include/IxOsalAssert.h b/Acceleration/library/icp_utils/OSAL/common/include/IxOsalAssert.h new file mode 100644 index 0000000..d830a82 --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/include/IxOsalAssert.h @@ -0,0 +1,144 @@ +/* + * @file IxOsalAssert.h + * @author Intel Corporation + * @date 25-08-2004 + * + * @brief description goes here + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +#ifndef IX_OSAL_ASSERT_H +#define IX_OSAL_ASSERT_H +#ifdef __cplusplus +extern "C"{ +#endif +/* + * Put the system defined include files required + * @par + * <TAGGED> + */ + +#include "IxOsalOsAssert.h" + +/** + * @brief Assert macro, assert the condition is true. This + * will not be compiled out. + * N.B. will result in a system crash if it is false. + */ + +/** + * @brief Ensure macro, ensure the condition is true. + * This will be conditionally compiled out and + * may be used for test purposes. + */ +#ifdef IX_OSAL_ENSURE_ON +#define IX_OSAL_ENSURE(c, str) do { \ +if (!(c)) ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT,"%s in file %s at line %d ", \ +(int)str,(int)__FILE__, (int)__LINE__, 0, 0, 0); } while (0) + + +#define IX_OSAL_ENSURE_RETURN(c, str) \ + if (NULL == c) { ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, \ + IX_OSAL_LOG_DEV_STDOUT, "%s in file %s at line %d ", \ + (int)str, (int)__FILE__, (int)__LINE__, 0, 0, 0); \ + return IX_FAIL; } + + +#define IX_OSAL_LOCAL_ENSURE(c, str, ret) \ + if (!(c)) { \ + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, \ + IX_OSAL_LOG_DEV_STDOUT, "%s in file %s at line %d ", \ + (int)str, (int)__FILE__, (int)__LINE__, 0, 0, 0); \ + return ret; } + +#define IX_OSAL_ENSURE_JUST_RETURN(c, str) \ + if (!(c)) { \ + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, \ + IX_OSAL_LOG_DEV_STDOUT, "%s in file %s at line %d ", \ + (int)str, (int)__FILE__, (int)__LINE__, 0, 0, 0); \ + return; } + +#define OSAL_ENSURE_CHECK_SUCCESS(c, str) \ + if (IX_SUCCESS != c) { ixOsalLog (IX_OSAL_LOG_LVL_ERROR, \ + IX_OSAL_LOG_DEV_STDOUT, "%s in file %s at line %d ", \ + (int)str, (int)__FILE__, (int)__LINE__, 0, 0, 0); \ + return IX_FAIL; } +#else +#define IX_OSAL_ENSURE(c, str) do {} while (0); +#define IX_OSAL_ENSURE_RETURN(c, str) do {} while (0); +#define IX_OSAL_LOCAL_ENSURE(c, str, ret) do {} while (0); +#define IX_OSAL_ENSURE_JUST_RETURN(c, str) do {} while (0); +#define OSAL_ENSURE_CHECK_SUCCESS(c, str) do {} while (0); +#endif + +#ifdef IX_OSAL_MEM_ASSERT_ON +#define IX_OSAL_MEM_ASSERT(c) IX_OSAL_OS_MEM_ASSERT(c) +#else +#define IX_OSAL_MEM_ASSERT(c) {\ +} +#endif + +#define IX_OSAL_ASSERT(c) IX_OSAL_OS_ASSERT(c) +#ifdef __cplusplus +} +#endif +#endif /* IX_OSAL_ASSERT_H */ diff --git a/Acceleration/library/icp_utils/OSAL/common/include/IxOsalConfig.h b/Acceleration/library/icp_utils/OSAL/common/include/IxOsalConfig.h new file mode 100644 index 0000000..d1a8831 --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/include/IxOsalConfig.h @@ -0,0 +1,108 @@ +/** + * @file IxOsalConfig.h + * + * @brief OSAL Configuration header file + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +/* + * This file contains user-editable fields for modules inclusion. + */ +#ifndef IxOsalConfig_H +#define IxOsalConfig_H +#ifdef __cplusplus +extern "C"{ +#endif + +/* Choose cache */ +/** + * @ingroup IxOsal + * + * @def IX_OSAL_CACHED + * + * @brief Choose cache when defined + */ +#define IX_OSAL_CACHED +/* #define IX_OSAL_UNCACHED */ + +/* + * Select the module headers to include + */ +#ifdef ENABLE_IOMEM +#include "IxOsalIoMem.h" /* I/O Memory Management module API */ +#endif /* ENABLE_IOMEM */ +#ifdef ENABLE_BUFFERMGT +#include "IxOsalBufferMgt.h" /* Buffer Management module API */ +#endif /* ENABLE_BUFFERMGT */ +#ifdef ENABLE_DDK +#include "IxOsalDdk.h" /* DDK module API */ +#endif /* ENABLE_DDK */ + +/* + * Select main platform header file to use + */ +#include "IxOsalOem.h" +#ifdef __cplusplus +} +#endif +#endif /* IxOsalConfig_H */ diff --git a/Acceleration/library/icp_utils/OSAL/common/include/IxOsalTypes.h b/Acceleration/library/icp_utils/OSAL/common/include/IxOsalTypes.h new file mode 100644 index 0000000..56c7c5e --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/include/IxOsalTypes.h @@ -0,0 +1,643 @@ +/** + * @file IxOsalTypes.h + * + * @brief Define OSAL basic data types. + * + * This file contains fundamental data types used by OSAL. + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + + +#ifndef IxOsalTypes_H +#define IxOsalTypes_H +#ifdef __cplusplus +extern "C"{ +#endif + +/* + * Include the OS-specific type definitions + */ +#include "IxOsalOsTypes.h" +/** + * @defgroup IxOsalTypes Osal basic data types. + * + * @brief Basic data types for Osal + * + * @{ + */ + +/** + * @typedef IX_STATUS + * @brief OSAL status + * + * @note Possible OSAL return status include IX_SUCCESS and IX_FAIL. + */ +typedef UINT32 IX_STATUS; + +/** + * @brief VUINT32 + * + * @note volatile UINT32 + */ +typedef volatile UINT32 VUINT32; + +/** + * @brief VINT32 + * + * @note volatile INT32 + */ +typedef volatile INT32 VINT32; + + +/** + * @ingroup IxOsalTypes + * + * @def NUMELEMS + * + * @brief Calculate number of elements + */ +#ifndef NUMELEMS +#define NUMELEMS(x) (sizeof(x) / sizeof((x)[0])) +#endif + + +/** + * @ingroup IxOsalTypes + * + * @def IX_OSAL_BILLION + * + * @brief Alias for 1,000,000,000 + * + */ +#define IX_OSAL_BILLION (1000000000) + +/** + * @ingroup IxOsalTypes + * + * @def IX_OSAL_MILLION + * + * @brief Alias for 1,000,000 + * + */ +#define IX_OSAL_MILLION (1000000) + +/** + * @ingroup IxOsalTypes + * + * @def IX_OSAL_THOUSAND + * + * @brief Alias for 1,000 + * + */ +#define IX_OSAL_THOUSAND (1000) + +/** + * @ingroup IxOsalTypes + * + * @def IX_OSAL_HUNDRED + * + * @brief Alias for 100 + * + */ +#define IX_OSAL_HUNDRED (100) + +/** + * @ingroup IxOsalTypes + * + * @def TRUE + * + * @brief Define for True + */ +#ifndef TRUE +#define TRUE 1L +#endif + +#if TRUE != 1 +#error TRUE is not defined to 1 +#endif + +/** + * @ingroup IxOsalTypes + * + * @def FALSE + * + * @brief Define for False + */ +#ifndef FALSE +#define FALSE 0L +#endif + +#if FALSE != 0 +#error FALSE is not defined to 0 +#endif + +/** + * @ingroup IxOsalTypes + * + * @def NULL + * + * @brief Define for Null + */ +#ifndef NULL +#define NULL 0L +#endif + +/** + * @ingroup IxOsalTypes + * + * @def IX_SUCCESS + * + * @brief Success status + * + */ +#ifndef IX_SUCCESS +#define IX_SUCCESS 0L /**< #defined as 0L */ +#endif + +/** + * @ingroup IxOsalTypes + * + * @def IX_FAIL + * + * @brief Failure status + * + */ +#ifndef IX_FAIL +#define IX_FAIL 1L /**< #defined as 1L */ +#endif + + +/** + * @ingroup IxOsalTypes + * + * @def PRIVATE + * + * @brief Private define + */ +#ifndef PRIVATE +#ifdef IX_PRIVATE_OFF +#define PRIVATE /* nothing */ +#else +#define PRIVATE static /**< #defined as static, except for debug builds */ +#endif /* IX_PRIVATE_OFF */ +#endif /* PRIVATE */ + +/* + * Placeholder for future use + */ +#ifndef RESTRICTED +#define RESTRICTED +#endif /* RESTRICTED */ + +/** + * @ingroup IxOsalTypes + * + * @def IX_OSAL_INLINE + * + * @brief Alias for __inline + * + */ +#ifndef _DIAB_TOOL + +#ifndef IX_OSAL_INLINE +#define IX_OSAL_INLINE __inline +#endif /* IX_OSAL_INLINE */ + +/** + * @ingroup IxOsalTypes + * + * @def __inline__ + * + * @brief Alias for __inline + */ +#ifndef __inline__ +#define __inline__ IX_OSAL_INLINE +#endif + +#else + +/** + * @ingroup IxOsalTypes + * + * @def IX_OSAL_INLINE + * + * @brief Alias for __inline + */ +#ifndef IX_OSAL_INLINE +#define IX_OSAL_INLINE __inline__ /* Diab Compiler uses __inline__ (compiler di + rective) */ +#endif /* IX_OSAL_INLINE */ + +#endif /*_DIAB_TOOL*/ + + +/* Each OS can define its own PUBLIC, otherwise it will be empty. */ +#ifndef PUBLIC +#define PUBLIC +#endif /* PUBLIC */ + + +/** + * @ingroup IxOsalTypes + * + * @def IX_OSAL_INLINE_EXTERN + * + * @brief Alias for __inline extern + * + */ +#ifndef IX_OSAL_INLINE_EXTERN +#define IX_OSAL_INLINE_EXTERN IX_OSAL_INLINE extern +#endif + +/** + * @ingroup IxOsalTypes + * + * @def IX_OSAL_ATTRIBUTE_PACKED + * + * @brief Defining packed attribute type in compiler/OS that supports it. + * + */ +#ifndef IX_OSAL_ATTRIBUTE_PACKED +#define IX_OSAL_ATTRIBUTE_PACKED TRUE +#endif + +/** + * @ingroup IxOsalTypes + * + * @def IX_OSAL_MAX_ALIGNMENT + * + * @brief Defining maximum alignment supported for aligned memory allocation. + * + */ +#define IX_OSAL_MAX_ALIGNMENT 256 + +#ifndef MILLISEC_TO_SEC_FACTOR +#define MILLISEC_TO_SEC_FACTOR 1000 +#endif /* MILLISEC_TO_SEC_FACTOR */ + + + +/** + * @ingroup IxOsalTypes + * @enum IxOsalLogDevice + * @brief This is an emum for OSAL log devices. + */ +typedef enum +{ + IX_OSAL_LOG_DEV_STDOUT = 0, /**< standard output (implemented by default) */ + IX_OSAL_LOG_DEV_STDERR = 1, /**< standard error (implemented */ + IX_OSAL_LOG_DEV_HEX_DISPLAY = 2, /**< hexadecimal display (not implemented) */ + IX_OSAL_LOG_DEV_ASCII_DISPLAY = 3 /**< ASCII-capable display (not implemented) */ +} IxOsalLogDevice; + + +/** + * @ingroup IxOsalTypes + * + * @def IX_OSAL_LOG_ERROR + * + * @brief Alias for -1, used as log function error status + * + */ +#define IX_OSAL_LOG_ERROR (-1) +#define IX_OSAL_NO_LOG (0) + +/** + * @ingroup IxOsalTypes + * @enum IxOsalLogLevel + * @brief This is an emum for OSAL log trace level. + */ +typedef enum +{ + IX_OSAL_LOG_LVL_NONE = 0, /**<No trace level */ + IX_OSAL_LOG_LVL_USER = 1, /**<Set trace level to user */ + IX_OSAL_LOG_LVL_FATAL = 2, /**<Set trace level to fatal */ + IX_OSAL_LOG_LVL_ERROR = 3, /**<Set trace level to error */ + IX_OSAL_LOG_LVL_WARNING = 4, /**<Set trace level to warning */ + IX_OSAL_LOG_LVL_MESSAGE = 5, /**<Set trace level to message */ + IX_OSAL_LOG_LVL_DEBUG1 = 6, /**<Set trace level to debug1 */ + IX_OSAL_LOG_LVL_DEBUG2 = 7, /**<Set trace level to debug2 */ + IX_OSAL_LOG_LVL_DEBUG3 = 8, /**<Set trace level to debug3 */ + IX_OSAL_LOG_LVL_ALL /**<Set trace level to all */ +} IxOsalLogLevel; + + +/** + * @ingroup IxOsalTypes + * @brief Void function pointer prototype + * + * @note accepts a void pointer parameter + * and does not return a value. + */ +typedef void (*IxOsalVoidFnVoidPtr) (void *); + +/** + * @ingroup IxOsalTypes + * @brief Void function pointer prototype + * + * @note accepts a void parameter + * and does not return a value. + */ +typedef void (*IxOsalVoidFnPtr) (void); + + +/** + * @brief Timeval structure + * + * @note Contain subfields of seconds and nanoseconds.. + */ +typedef struct +{ + UINT32 secs; /**< seconds */ + UINT32 nsecs; /**< nanoseconds */ +} IxOsalTimeval; + + +/** + * @ingroup IxOsalTypes + * @brief IxOsalTimer + * + * @note OSAL timer handle + * + */ +#ifndef USE_NATIVE_OS_TIMER_API +typedef UINT32 IxOsalTimer; +#else +typedef IxOsalOsTimer IxOsalTimer; +#endif + +/** + * @ingroup IxOsalTypes + * + * @def IX_OSAL_WAIT_FOREVER + * + * @brief Definition for timeout forever, OS-specific. + * + */ +#define IX_OSAL_WAIT_FOREVER IX_OSAL_OS_WAIT_FOREVER + +/** + * @ingroup IxOsalTypes + * + * @def IX_OSAL_WAIT_NONE + * + * @brief Definition for timeout 0, OS-specific. + * + */ +#define IX_OSAL_WAIT_NONE IX_OSAL_OS_WAIT_NONE + + +/** + * @ingroup IxOsalTypes + * @brief IxOsalMutex + * + * @note Mutex handle, OS-specific + * + */ +typedef IxOsalOsMutex IxOsalMutex; + +/** + * @ingroup IxOsalTypes + * @brief IxOsalFastMutex + * + * @note FastMutex handle, OS-specific + * + */ +typedef IxOsalOsFastMutex IxOsalFastMutex; + +/** + * @ingroup IxOsalTypes + * @brief IxOsalThread + * + * @note Thread handle, OS-specific + * + */ +typedef IxOsalOsThread IxOsalThread; + +/** + * @ingroup IxOsalTypes + * @brief IxOsalSemaphore + * + * @note Semaphore handle, OS-specific + * + */ +typedef IxOsalOsSemaphore IxOsalSemaphore; + +/** + * @ingroup IxOsalTypes + * @brief IxOsalMessageQueue + * + * @note Message Queue handle, OS-specific + * + */ +typedef IxOsalOsMessageQueue IxOsalMessageQueue; + + +#ifdef ENABLE_SPINLOCK +/** + * @ingroup IxOsalTypes + * @brief IxOsalOsSpinLock + * + * @note SpinLock handle, OS-specific + */ +typedef IxOsalOsSpinLock IxOsalSpinLock; + +#endif /* ENABLE_SPINLOCK */ + + +/** + * @brief Thread Attribute + * @note Default thread attribute + */ +typedef struct +{ + char *name; /**< name */ + UINT32 stackSize; /**< stack size */ + UINT32 priority; /**< priority */ + INT32 policy; /**< policy */ +} IxOsalThreadAttr; + + +/** + * @ingroup IxOsalTypes + * + * @def IX_OSAL_THREAD_DEFAULT_SCHED_POLICY + * + * @brief Default Thread Scheduling Policy, OS-specific. + * + */ +#define IX_OSAL_THREAD_DEFAULT_SCHED_POLICY (IX_OSAL_OS_THREAD_DEFAULT_SCHED_POLICY) + + +/** + * @ingroup IxOsalTypes + * + * @def IX_OSAL_THREAD_DEFAULT_STACK_SIZE + * + * @brief Default thread stack size, OS-specific. + * + */ +#define IX_OSAL_THREAD_DEFAULT_STACK_SIZE (IX_OSAL_OS_THREAD_DEFAULT_STACK_SIZE) + +/** + * @ingroup IxOsalTypes + * + * @def IX_OSAL_THREAD_MAX_STACK_SIZE + * + * @brief Max stack size, OS-specific. + * + */ +#define IX_OSAL_THREAD_MAX_STACK_SIZE (IX_OSAL_OS_THREAD_MAX_STACK_SIZE) + +/** + * @ingroup IxOsalTypes + * + * @def IX_OSAL_MAX_THREAD_NAME_LEN + * + * @brief Max size of thread name + * + */ +#define IX_OSAL_MAX_THREAD_NAME_LEN 16 + +/** + * @ingroup IxOsalTypes + * + * @def OSAL_MAX_MODULE_NAME_LENGTH + * + * @brief Max size of module Name Length to be prefixed for OSAL Log + * + */ +#define OSAL_MAX_MODULE_NAME_LENGTH 20 + +/** + * @ingroup IxOsalTypes + * + * @def IX_OSAL_MIN_THREAD_PRIORITY + * + * @brief Min thread priority, OS-specific. + * + */ +#ifdef IX_OSAL_OS_MIN_THREAD_PRIORITY +#define IX_OSAL_MIN_THREAD_PRIORITY (IX_OSAL_OS_MIN_THREAD_PRIORITY) +#else +#define IX_OSAL_MIN_THREAD_PRIORITY 0 +#endif + +/** + * @ingroup IxOsalTypes + * + * @def IX_OSAL_DEFAULT_THREAD_PRIORITY + * + * @brief Default thread priority, OS-specific. + * + */ +#define IX_OSAL_DEFAULT_THREAD_PRIORITY (IX_OSAL_OS_DEFAULT_THREAD_PRIORITY) + +/** + * @ingroup IxOsalTypes + * + * @def IX_OSAL_MAX_THREAD_PRIORITY + * + * @brief Max thread priority, OS-specific. + * + */ +#define IX_OSAL_MAX_THREAD_PRIORITY (IX_OSAL_OS_MAX_THREAD_PRIORITY) + +/** + * @ingroup IxOsalTypes + * + * @typedef IxOsalPciDev + * @brief IxOsalPciDev + * + * @note This is a data type that serves as a handle for allocated PCI device. + * + */ +typedef UINT8 *IxOsalPciDev; + +/** + * @ingroup IxOsalTypes + * + * @typedef IxOsalAtomic + * @brief IxOsalAtomic + * + * @note IxOsalAtomic Variable, OS-specific + * + */ + typedef IxOsalOsAtomic IxOsalAtomic; + +/** + * @brief UINT128 + * + * @note Union to hold UINT128 value + */ +typedef union UINT128_t +{ + UINT8 mUINT8[16]; /**< 16 UINT8 values */ + UINT16 mUINT16[8]; /**< 8 UINT16 values */ + UINT32 mUINT32[4]; /**< 4 UINT32 values */ + UINT64 mUINT64[2]; /**< 2 UINT64 values */ +} UINT128; + +#ifdef __cplusplus +} +#endif +#endif /* IxOsalTypes_H */ diff --git a/Acceleration/library/icp_utils/OSAL/common/include/IxOsalUtilitySymbols.h b/Acceleration/library/icp_utils/OSAL/common/include/IxOsalUtilitySymbols.h new file mode 100644 index 0000000..0d89cf0 --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/include/IxOsalUtilitySymbols.h @@ -0,0 +1,94 @@ +/** + * @file + * + * @brief OSAL Configuration header file + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +#ifndef IxOsalUtilitySymbols_H +#define IxOsalUtilitySymbols_H +#ifdef __cplusplus +extern "C"{ +#endif +#include "IxOsalOsUtilitySymbols.h" /* OS-specific utility symbol definitions */ + +#ifdef ENABLE_SPINLOCK +/** + * @ingroup IxOsalTypes + * @enum IxOsalSpinLockType + * @brief This is an emum for OSAL SpinLock types. + */ +typedef enum +{ + TYPE_IGNORE = 0, /**< Spin Lock type Ignore */ + NON_QUEUED = 1, /**< Non Queued Spin Lock type */ + QUEUED = 2, /**< Queued Spin Lock type */ + NON_QUEUED_AT_DPC_LEVEL = 3, /**< Non Queued Spin Lock type at DPC level */ + QUEUED_AT_DPC_LEVEL /**< Queued Spin Lock type at DPC level */ +}IxOsalSpinLockType; + +#endif /* ENABLE_SPINLOCK */ +#ifdef __cplusplus +} +#endif +#endif /* IxOsalUtilitySymbols_H */ diff --git a/Acceleration/library/icp_utils/OSAL/common/include/modules/bufferMgt/IxOsalBufferMgt.h b/Acceleration/library/icp_utils/OSAL/common/include/modules/bufferMgt/IxOsalBufferMgt.h new file mode 100644 index 0000000..6ea9eb2 --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/include/modules/bufferMgt/IxOsalBufferMgt.h @@ -0,0 +1,925 @@ +/** + * @file IxOsalBufferMgt.h + * + * @brief OSAL Buffer pool management and buffer management definitions. + * + * Design Notes: + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ +/* @par + * -- Copyright Notice -- + * + * @par + * Copyright 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994 + * The Regents of the University of California. All rights reserved. + * + * @par + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * @par + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @par + * -- End of Copyright Notice -- + */ + +#ifndef IxOsalBufferMgt_H +#define IxOsalBufferMgt_H +#ifdef __cplusplus +extern "C"{ +#endif +#include "IxOsal.h" +/** + * @defgroup IxOsalBufferMgt OSAL Buffer Management Module. + * + * @brief Buffer management module for IxOsal + * + * @{ + */ + +/** + * @ingroup IxOsalBufferMgt + * + * @def IX_OSAL_MBUF_MAX_POOLS + * + * @brief The maximum number of pools that can be allocated, must be + * a multiple of 32 as required by implementation logic. + * @note This can safely be increased if more pools are required. + */ +#define IX_OSAL_MBUF_MAX_POOLS 32 + +/** + * @ingroup IxOsalBufferMgt + * + * @def IX_OSAL_MBUF_POOL_NAME_LEN + * + * @brief The maximum string length of the pool name + */ +#define IX_OSAL_MBUF_POOL_NAME_LEN 64 + + + +/** + * Define IX_OSAL_MBUF + */ + + +/* forward declaration of internal structure */ +struct __ACP_BUF; + +/** + * @ingroup IxOsalBufferMgt + * + * @def IX_OSAL_ATTRIBUTE_ALIGN32 + * + * @brief OS can define it in IxOsalOs.h to skip the following + * definition. + */ +#ifndef IX_OSAL_ATTRIBUTE_ALIGN32 +#define IX_OSAL_ATTRIBUTE_ALIGN32 __attribute__ ((aligned(32))) +#endif + +/* release v1.4 backward compatible definitions */ +struct __IX_MBUF +{ + struct __ACP_BUF *ix_next IX_OSAL_ATTRIBUTE_ALIGN32; + /**< MBUF next pointer */ + struct __ACP_BUF *ix_nextPacket; + /**< Pointer to next packet */ + UINT8 *ix_data; /**< Data pointer */ + UINT32 ix_len; /**< Buffer length */ + UINT8 ix_type; /**< Type of buffer */ + UINT8 ix_flags; /**< Flags */ + UINT16 ix_reserved; /**< Reserved area */ + UINT32 ix_rsvd; /**< Reserve area-2 */ + UINT32 ix_PktLen; /**< Packet length */ + VOID *ix_priv; /**< Private pointer */ +}; + +/* Control header structure */ +struct __IX_CTRL +{ + UINT32 ix_reserved[2]; /**< Reserved field */ + UINT32 ix_signature; /**< Field to indicate if buffers are allocated by the system */ + UINT32 ix_allocated_len; /**< Allocated buffer length */ + UINT32 ix_allocated_data; /**< Allocated buffer data pointer */ + VOID *ix_pool; /**< pointer to the buffer pool */ + struct __ACP_BUF *ix_chain; /**< chaining */ + VOID *ix_osbuf_ptr; /**< Storage for OS-specific buffer pointer */ +}; + +#ifdef _DIAB_TOOL + +IX_OSAL_ATTRIBUTE_ALIGN32 struct __IX_NE_SHARED +{ + UINT32 reserved[8]; /**< Reserved area for PIU Service-specific usage */ +}; + +#else + +/* NE-Shared structure */ +struct __IX_NE_SHARED +{ + UINT32 reserved[8] IX_OSAL_ATTRIBUTE_ALIGN32; /**< Reserved area for PIU Service-specific usage */ +}; + +#endif + + +/* + * ACP buffer structure + */ +struct __ACP_BUF +{ + struct __IX_MBUF ix_mbuf IX_OSAL_ATTRIBUTE_ALIGN32; /**< buffer header */ + struct __IX_CTRL ix_ctrl; /**< buffer management */ + struct __IX_NE_SHARED ix_ne; /**< Reserved area for PIU Service-specific usage*/ +}; + + + +/** + * @ingroup IxOsalBufferMgt + * + * @brief IX_OSAL_MBUF + * + * @note Generic ACP mbuf format. + */ +typedef struct __ACP_BUF IX_OSAL_MBUF; + + +/** + * @ingroup IxOsalBufferMgt + * + * @def IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(m_blk_ptr) + * + * @brief Return pointer to the next mbuf in a single packet + */ +#define IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(m_blk_ptr) \ + (m_blk_ptr)->ix_mbuf.ix_next + + +/** + * @ingroup IxOsalBufferMgt + * + * @def IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m_blk_ptr) + * + * @brief Return pointer to the next packet in the chain + */ +#define IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m_blk_ptr) \ + (m_blk_ptr)->ix_mbuf.ix_nextPacket + + +/** + * @ingroup IxOsalBufferMgt + * + * @def IX_OSAL_MBUF_MDATA(m_blk_ptr) + * + * @brief Return pointer to the data in the mbuf + */ +#define IX_OSAL_MBUF_MDATA(m_blk_ptr) (m_blk_ptr)->ix_mbuf.ix_data + +/** + * @ingroup IxOsalBufferMgt + * + * @def IX_OSAL_MBUF_MLEN(m_blk_ptr) + * + * @brief Return the data length + */ +#define IX_OSAL_MBUF_MLEN(m_blk_ptr) \ + (m_blk_ptr)->ix_mbuf.ix_len + +/** + * @ingroup IxOsalBufferMgt + * + * @def IX_OSAL_MBUF_MTYPE(m_blk_ptr) + * + * @brief Return the data type in the mbuf + */ +#define IX_OSAL_MBUF_MTYPE(m_blk_ptr) \ + (m_blk_ptr)->ix_mbuf.ix_type + + +/** + * @ingroup IxOsalBufferMgt + * + * @def IX_OSAL_MBUF_FLAGS(m_blk_ptr) + * + * @brief Return the buffer flags + */ +#define IX_OSAL_MBUF_FLAGS(m_blk_ptr) \ + (m_blk_ptr)->ix_mbuf.ix_flags + + +/** + * @ingroup IxOsalBufferMgt + * + * @def IX_OSAL_MBUF_NET_POOL(m_blk_ptr) + * + * @brief Return pointer to a network pool + */ +#define IX_OSAL_MBUF_NET_POOL(m_blk_ptr) \ + (m_blk_ptr)->ix_ctrl.ix_pool + + + +/** + * @ingroup IxOsalBufferMgt + * + * @def IX_OSAL_MBUF_PKT_LEN(m_blk_ptr) + * + * @brief Return the total length of all the data in + * the mbuf chain for this packet + */ +#define IX_OSAL_MBUF_PKT_LEN(m_blk_ptr) \ + (m_blk_ptr)->ix_mbuf.ix_PktLen + + + + +/** + * @ingroup IxOsalBufferMgt + * + * @def IX_OSAL_MBUF_PRIV(m_blk_ptr) + * + * @brief Return the private field + */ +#define IX_OSAL_MBUF_PRIV(m_blk_ptr) \ + (m_blk_ptr)->ix_mbuf.ix_priv + + + +/** + * @ingroup IxOsalBufferMgt + * + * @def IX_OSAL_MBUF_SIGNATURE(m_blk_ptr) + * + * @brief Return the signature field of IX_OSAL_MBUF + */ +#define IX_OSAL_MBUF_SIGNATURE(m_blk_ptr) \ + (m_blk_ptr)->ix_ctrl.ix_signature + + +/** + * @ingroup IxOsalBufferMgt + * + * @def IX_OSAL_MBUF_OSBUF_PTR(m_blk_ptr) + * + * @brief Return ix_osbuf_ptr field of IX_OSAL_MBUF, which is used to store OS-specific buffer pointer during a buffer conversion. + */ +#define IX_OSAL_MBUF_OSBUF_PTR(m_blk_ptr) \ + (m_blk_ptr)->ix_ctrl.ix_osbuf_ptr + + +/** + * @ingroup IxOsalBufferMgt + * + * @def IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(m_blk_ptr) + * + * @brief Return the allocated buffer size + */ +#define IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(m_blk_ptr) \ + (m_blk_ptr)->ix_ctrl.ix_allocated_len + +/** + * @ingroup IxOsalBufferMgt + * + * @def IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(m_blk_ptr) + * + * @brief Return the allocated buffer pointer + */ +#define IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(m_blk_ptr) \ + (m_blk_ptr)->ix_ctrl.ix_allocated_data + + + +/* Name length */ +#define IX_OSAL_MBUF_POOL_NAME_LEN 64 + + +/**************************************************** + * Macros for buffer pool management + ****************************************************/ + +/** + * @ingroup IxOsalBufferMgt + * + * @def IX_OSAL_MBUF_POOL_FREE_COUNT + * + * @brief Return the total number of freed buffers left in the pool. + */ +#define IX_OSAL_MBUF_POOL_FREE_COUNT(m_pool_ptr) \ + ixOsalBuffPoolFreeCountGet(m_pool_ptr) + +/** + * @ingroup IxOsalBufferMgt + * + * @def IX_OSAL_MBUF_POOL_SIZE_ALIGN + * + * @brief This macro takes an integer as an argument and + * rounds it up to be a multiple of the memory cache-line + * size. + * + * @param size IN - the size integer to be rounded up + * + * @return int - the size, rounded up to a multiple of + * the cache-line size + */ +#if !defined(__linux_user) && !defined(__freebsd_user) + +#define IX_OSAL_MBUF_POOL_SIZE_ALIGN(size) \ + ((((size) + (IX_OSAL_CACHE_LINE_SIZE - 1)) / \ + IX_OSAL_CACHE_LINE_SIZE) * \ + IX_OSAL_CACHE_LINE_SIZE) + +#else /* __linux_user || __freebsd_user */ + +#define IX_OSAL_MBUF_POOL_SIZE_ALIGN(size) (size) + +#endif /* __linux_user || __freebsd_user */ + +/** + * @ingroup IxOsalBufferMgtInternal + * + * @brief This calculates, from the number of mbufs required, the + * size of the memory area required to contain the mbuf headers for the + * buffers in the pool. The size to be used for each mbuf header is + * rounded up to a multiple of the cache-line size, to ensure + * each mbuf header aligns on a cache-line boundary. + * + * @param count - the number of buffers the pool will contain + * + * @return int - the total size required for the pool mbuf area (aligned) + * + * @note Don't use this directly, use macro + */ +PUBLIC UINT32 ixOsalBuffPoolMbufAreaSizeGet (UINT32 count); + + +/** + * @ingroup IxOsalBufferMgt + * + * @def IX_OSAL_MBUF_POOL_MBUF_AREA_SIZE_ALIGNED + * + * @brief This macro calculates, from the number of mbufs required, the + * size of the memory area required to contain the mbuf headers for the + * buffers in the pool. The size to be used for each mbuf header is + * rounded up to a multiple of the cache-line size, to ensure + * each mbuf header aligns on a cache-line boundary. + * This macro is used by IX_OSAL_MBUF_POOL_MBUF_AREA_ALLOC() + * + * @param count IN - the number of buffers the pool will contain + * + * @return int - the total size required for the pool mbuf area (aligned) + */ +#define IX_OSAL_MBUF_POOL_MBUF_AREA_SIZE_ALIGNED(count) \ + ixOsalBuffPoolMbufAreaSizeGet(count) + + +/** + * @ingroup IxOsalBufferMgtInternal + * + * @brief This macro calculates, from the number of mbufs required and the + * size of the data portion for each mbuf, the size of the data memory area + * required. The size is adjusted to ensure alignment on cache line boundaries. + * This macro is used by IX_OSAL_MBUF_POOL_DATA_AREA_ALLOC() + * + * + * @param count IN - The number of mbufs in the pool. + * @param size IN - The desired size for each mbuf data portion. + * This size will be rounded up to a multiple of the + * cache-line size to ensure alignment on cache-line + * boundaries for each data block. + * + * @return the total size required for the pool data area (aligned) + * + * @note Don't use this directly, use macro + */ +PUBLIC UINT32 ixOsalBuffPoolDataAreaSizeGet (UINT32 count, UINT32 size); + + +/** + * @ingroup IxOsalBufferMgt + * + * @def IX_OSAL_MBUF_POOL_DATA_AREA_SIZE_ALIGNED + * + * @brief This macro calculates, from the number of mbufs required and the + * size of the data portion for each mbuf, the size of the data memory area + * required. The size is adjusted to ensure alignment on cache line boundaries. + * This macro is used by IX_OSAL_MBUF_POOL_DATA_AREA_ALLOC() + * + * + * @param count IN - The number of mbufs in the pool. + * @param size IN - The desired size for each mbuf data portion. + * This size will be rounded up to a multiple of the + * cache-line size to ensure alignment on cache-line + * boundaries for each data block. + * + * @return int - the total size required for the pool data area (aligned) + */ +#define IX_OSAL_MBUF_POOL_DATA_AREA_SIZE_ALIGNED(count, size) \ + ixOsalBuffPoolDataAreaSizeGet((count), (size)) + + +/** + * @ingroup IxOsalBufferMgt + * + * @def IX_OSAL_MBUF_POOL_MBUF_AREA_ALLOC + * + * @brief Allocates the memory area needed for the number of mbuf headers + * specified by <i>count</i>. + * This macro ensures the mbuf headers align on cache line boundaries. + * This macro evaluates to a pointer to the memory allocated. + * + * @param count IN - the number of mbufs the pool will contain + * @param memAreaSize OUT - the total amount of memory allocated + * + * @return void * - a pointer to the allocated memory area + */ +#if !defined(__linux_user) && !defined(__freebsd_user) + +#define IX_OSAL_MBUF_POOL_MBUF_AREA_ALLOC(count, memAreaSize) \ + IX_OSAL_CACHE_DMA_MALLOC((memAreaSize = \ + IX_OSAL_MBUF_POOL_MBUF_AREA_SIZE_ALIGNED(count))) + +#else /* __linux_user || __freebsd_user */ + +#define IX_OSAL_MBUF_POOL_MBUF_AREA_ALLOC(count, memAreaSize) \ + IX_OSAL_BUFF_MEM_ALLOC(count * memAreaSize) + +#endif /* __linux_user || __freebsd_user */ + +/** + * @ingroup IxOsalBufferMgt + * + * @def IX_OSAL_MBUF_POOL_DATA_AREA_ALLOC + * + * @brief Allocates the memory pool for the data portion of the pool mbufs. + * The number of mbufs is specified by <i>count</i>. The size of the data + * portion of each mbuf is specified by <i>size</i>. + * This macro ensures the mbufs are aligned on cache line boundaries + * This macro evaluates to a pointer to the memory allocated. + * + * @param count IN - the number of mbufs the pool will contain + * @param size IN - the desired size (in bytes) required for the data + * portion of each mbuf. Note that this size may be + * rounded up to ensure alignment on cache-line + * boundaries. + * @param memAreaSize IN - the total amount of memory allocated + * + * @return void * - a pointer to the allocated memory area + */ +#if !defined(__linux_user) && !defined(__freebsd_user) + +#define IX_OSAL_MBUF_POOL_DATA_AREA_ALLOC(count, size, memAreaSize) \ + IX_OSAL_CACHE_DMA_MALLOC((memAreaSize = \ + IX_OSAL_MBUF_POOL_DATA_AREA_SIZE_ALIGNED(count,size))) + +#else /* __linux_user */ + +#define IX_OSAL_MBUF_POOL_DATA_AREA_ALLOC(count, size, memAreaSize) \ + IX_OSAL_BUFF_MEM_ALLOC(count * size * memAreaSize) + +#endif /* __linux_user || freebsd_user */ + + +/** + * @ingroup IxOsalBufferMgt + * + * @def IX_OSAL_MBUF_POOL_INIT + * + * @brief Wrapper macro for ixOsalPoolInit() + * See function description below for details. + */ +#define IX_OSAL_MBUF_POOL_INIT(count, size, name) \ + ixOsalPoolInit((count), (size), (name)) + +/** + * @ingroup IxOsalBufferMgt + * + * @def IX_OSAL_MBUF_NO_ALLOC_POOL_INIT + * + * @return Pointer to the new pool or NULL if the initialization failed. + * + * @brief Wrapper macro for ixOsalNoAllocPoolInit() + * See function description below for details. + * + */ +#define IX_OSAL_MBUF_NO_ALLOC_POOL_INIT(bufPtr, dataPtr, count, size, name) \ + ixOsalNoAllocPoolInit( (bufPtr), (dataPtr), (count), (size), (name)) + +/** + * @ingroup IxOsalBufferMgt + * + * @def IX_OSAL_MBUF_POOL_GET + * + * @brief Wrapper macro for ixOsalMbufAlloc() + * See function description below for details. + */ +#define IX_OSAL_MBUF_POOL_GET(poolPtr) \ + ixOsalMbufAlloc(poolPtr) + +/** + * @ingroup IxOsalBufferMgt + * + * @def IX_OSAL_MBUF_POOL_PUT + * + * @brief Wrapper macro for ixOsalMbufFree() + * See function description below for details. + */ +#define IX_OSAL_MBUF_POOL_PUT(bufPtr) \ + ixOsalMbufFree(bufPtr) + +/** + * @ingroup IxOsalBufferMgt + * + * @def IX_OSAL_MBUF_POOL_PUT_CHAIN + * + * @brief Wrapper macro for ixOsalMbufChainFree() + * See function description below for details. + */ +#define IX_OSAL_MBUF_POOL_PUT_CHAIN(bufPtr) \ + ixOsalMbufChainFree(bufPtr) + +/** + * @ingroup IxOsalBufferMgt + * + * @def IX_OSAL_MBUF_POOL_SHOW + * + * @brief Wrapper macro for ixOsalMbufPoolShow() + * See function description below for details. + */ +#define IX_OSAL_MBUF_POOL_SHOW(poolPtr) \ + ixOsalMbufPoolShow(poolPtr) + +/** + * @ingroup IxOsalBufferMgt + * + * @def IX_OSAL_PIU_PRIV_SECTION_PTR + * + * @brief Wrapper macro for getting pointer to PIU(Programmable I/O Unit) + * private section + * + */ +#define IX_OSAL_PIU_PRIV_SECTION_PTR(buffer) buffer->ix_ne.reserved + +/** + * @ingroup IxOsalBufferMgt + * + * @def IX_OSAL_MBUF_POOL_MDATA_RESET + * + * @brief Wrapper macro for ixOsalMbufDataPtrReset() + * See function description below for details. + */ +#define IX_OSAL_MBUF_POOL_MDATA_RESET(bufPtr) \ + ixOsalMbufDataPtrReset(bufPtr) + +/** + * @ingroup IxOsalBufferMgt + * + * @def IX_OSAL_MBUF_POOL_UNINIT + * + * @brief Wrapper macro for ixOsalBuffPoolUninit() + * See function description below for details. + */ +#define IX_OSAL_MBUF_POOL_UNINIT(m_pool_ptr) \ + ixOsalBuffPoolUninit(m_pool_ptr) + +/* + * Added in Phase 2 + */ + +/* BUFFER INFO FLUSHING */ +/** + * @ingroup IxOsalBufferMgt + * + * @def IX_OSAL_BUFF_FLUSH_INFO + * + * @brief Flush buffer info + */ +#if !defined(__linux_user) && !defined(__freebsd_user) + +#define IX_OSAL_BUFF_FLUSH_INFO IX_OSAL_CACHE_FLUSH + +#else + +#define IX_OSAL_BUFF_FLUSH_INFO(ptr,size) + +#endif /* __linux_user || __freebsd_user */ + +/* MEMORY ALLOCATION IN BUFFER MANAGEMENT MODULE */ +/** + * @ingroup IxOsalBufferMgt + * + * @def IX_OSAL_BUFF_MEM_ALLOC + * + * @brief Buffer memory allocation + */ +#if !defined(__linux_user) && !defined(__freebsd_user) + +#define IX_OSAL_BUFF_MEM_ALLOC IX_OSAL_CACHE_DMA_MALLOC + +#else + +#define IX_OSAL_BUFF_MEM_ALLOC ixOsalMemAlloc + +#endif /* __linux_user || __freebsd_user */ + +/* MEMORY FREE IN BUFFER MANAGEMENT MODULE */ +/** + * @ingroup IxOsalBufferMgt + * + * @def IX_OSAL_BUFF_MEM_FREE + * + * @brief Buffer memory free + */ +#if !defined(__linux_user) && !defined(__freebsd_user) + +#define IX_OSAL_BUFF_MEM_FREE IX_OSAL_CACHE_DMA_FREE + +#else /* __linux_user || __freebsd_user */ + +#define IX_OSAL_BUFF_MEM_FREE ixOsalMemFree + +#endif /* __linux_user || __freebsd_user */ + + +/* + * Include OS-specific bufferMgt definitions + */ +#include "IxOsalOsBufferMgt.h" + + +/** + * @ingroup IxOsalBufferMgt + * + * @def IX_OSAL_CONVERT_OSBUF_TO_ACPBUF + * + * @brief Convert pre-allocated os-specific buffer format to OSAL ACP_BUF (IX_OSAL_MBUF) format. + * It is users' responsibility to provide pre-allocated and valid buffer pointers. + * @param osBufPtr (in) - a pre-allocated os-specific buffer pointer. + * @param acpBufPtr (in)- a pre-allocated OSAL ACP_BUF pointer + * @return None + */ +#define IX_OSAL_CONVERT_OSBUF_TO_ACPBUF(osBufPtr,acpBufPtr) \ + IX_OSAL_OS_CONVERT_OSBUF_TO_ACPBUF(osBufPtr,acpBufPtr) + + +/** + * @ingroup IxOsalBufferMgt + * + * @def IX_OSAL_CONVERT_ACPBUF_TO_OSBUF + * + * @brief Convert pre-allocated OSAL ACP_BUF (IX_OSAL_MBUF) format to os-specific buffer pointers. + * @param acpBufPtr (in) - OSAL ACP_BUF pointer + * @param osBufPtr (out) - os-specific buffer pointer. + * @return None + */ + +#define IX_OSAL_CONVERT_ACPBUF_TO_OSBUF(acpBufPtr,osBufPtr) \ + IX_OSAL_OS_CONVERT_ACPBUF_TO_OSBUF(acpBufPtr,osBufPtr) + + +/** + * @ingroup IxOsalBufferMgt + * + * @brief Initialize MBUF pool + * + * @param count IN - number of buffers to be in pool + * @param size IN - size of each buffer + * @param name IN - name for the pool + * + * Initialize a pool of mbufs with given count / size + * + * @li Reentrant: no + * @li IRQ safe: no + * + * @return - handle to the newly created/initialized pool + */ +PUBLIC IX_OSAL_MBUF_POOL *ixOsalPoolInit (UINT32 count, + UINT32 size, const char *name); + +/** + * @ingroup IxOsalBufferMgt + * + * @brief Initialize pool without allocating data space + * + * @param poolBufPtr - Buffer head pointer + * @param poolDataPtr - Data pointer for buffer pool + * @param count - number of buffers expected to be in pool + * @param size - size of pool + * @param name - name for buffer pool + * + * Initialize buffer pool without actually allocating data space + * + * @li Reentrant: no + * @li IRQ safe: no + * + * @return - Handle to newly initialized pool + */ +PUBLIC IX_OSAL_MBUF_POOL *ixOsalNoAllocPoolInit (VOID *poolBufPtr, + VOID *poolDataPtr, + UINT32 count, + UINT32 size, + const char *name); + +/** + * @ingroup IxOsalBufferMgt + * + * @brief Allocate buffer + * + * @param pool - pool handle + * + * Allcoate a buffer from the pool + * + * @li Reentrant: no + * @li IRQ safe: no + * + * @return - handle to allocated buffer + */ +PUBLIC IX_OSAL_MBUF *ixOsalMbufAlloc (IX_OSAL_MBUF_POOL * pool); + +/** + * @ingroup IxOsalBufferMgt + * + * @brief Free buffer + * + * @param mbuf - buffer handle + * + * Free buffer pointer to by handle + * + * @li Reentrant: no + * @li IRQ safe: no + * + * @return - Buffer handle + */ +PUBLIC IX_OSAL_MBUF *ixOsalMbufFree (IX_OSAL_MBUF * mbuf); + +/** + * @ingroup IxOsalBufferMgt + * + * @brief Free buffer chain + * + * @param mbuf - buffer handle + * + * Free the chain of buffers pointer to by given handle + * + * @li Reentrant: no + * @li IRQ safe: no + * + * @return - None + */ +PUBLIC VOID ixOsalMbufChainFree (IX_OSAL_MBUF * mbuf); + +/** + * @ingroup IxOsalBufferMgt + * + * @brief Reset data pointer for buffer + * + * @param mbuf - buffer pointer + * + * Reset the data pointer field in buffer + * + * @li Reentrant: no + * @li IRQ safe: no + * + * @return - None + */ +PUBLIC VOID ixOsalMbufDataPtrReset (IX_OSAL_MBUF * mbuf); + +/** + * @ingroup IxOsalBufferMgt + * + * @brief Show buffer pool info + * + * @param pool - pool handle + * + * Show info for buffer pool given by handle + * + * @li Reentrant: no + * @li IRQ safe: no + * + * @return - None + */ +PUBLIC VOID ixOsalMbufPoolShow (IX_OSAL_MBUF_POOL * pool); + +/** + * @ingroup IxOsalBufferMgt + * + * @brief Uninitialize buffer pool + * + * @param pool - pool handle + * + * Free up memory and destroy/uninitialize buffer pool + * + * @li Reentrant: no + * @li IRQ safe: no + * + * @return - IX_SUCCESS upon success, IX_FAIL otherwise + */ +PUBLIC IX_STATUS ixOsalBuffPoolUninit (IX_OSAL_MBUF_POOL * pool); + +/** + * @ingroup IxOsalBufferMgt + * + * @brief Get count of free buffers in pool + * + * @param pool - pool handle + * + * Returns the number of free buffers in given pool + * + * @li Reentrant: no + * @li IRQ safe: no + * + * @return - 32-bit count of number of free buffers + */ +PUBLIC UINT32 ixOsalBuffPoolFreeCountGet(IX_OSAL_MBUF_POOL * pool); + + +/** + * @} IxOsalBufferMgt + */ +#ifdef __cplusplus +} +#endif + +#endif /* IxOsalBufferMgt_H */ diff --git a/Acceleration/library/icp_utils/OSAL/common/include/modules/bufferMgt/IxOsalBufferMgtDefault.h b/Acceleration/library/icp_utils/OSAL/common/include/modules/bufferMgt/IxOsalBufferMgtDefault.h new file mode 100644 index 0000000..ac2a6a1 --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/include/modules/bufferMgt/IxOsalBufferMgtDefault.h @@ -0,0 +1,128 @@ +/** + * @file IxOsalBufferMgtDefault.h + * + * @brief Default buffer pool management and buffer management + * definitions. + * + * Design Notes: + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +#ifndef IX_OSAL_BUFFER_MGT_DEFAULT_H +#define IX_OSAL_BUFFER_MGT_DEFAULT_H +#ifdef __cplusplus +extern "C"{ +#endif + +/** + * @ingroup IxOsalBufferMgt + * + * @enum IxOsalMbufPoolAllocationType + * + * @brief Used to indicate how the pool memory was allocated + */ +typedef enum +{ + IX_OSAL_MBUF_POOL_TYPE_SYS_ALLOC = 0, /**< mbuf pool allocated by the system */ + IX_OSAL_MBUF_POOL_TYPE_USER_ALLOC /**< mbuf pool allocated by the user */ +} IxOsalMbufPoolAllocationType; + + +/** + * @ingroup IxOsalBufferMgt + * + * @brief IxOsalMbufPool + * + * @note Implementation of buffer pool structure for use with non-VxWorks OS + */ +typedef struct +{ + IX_OSAL_MBUF *nextFreeBuf; /**< Pointer to the next free mbuf */ + VOID *mbufMemPtr; /**< Pointer to the mbuf memory area */ + VOID *dataMemPtr; /**< Pointer to the data memory area */ + INT32 bufDataSize; /**< The size of the data portion of each mbuf */ + INT32 totalBufsInPool; /**< Total number of mbufs in the pool */ + INT32 freeBufsInPool; /**< Number of free mbufs currently in the pool */ + INT32 mbufMemSize; /**< The size of the pool mbuf memory area */ + INT32 dataMemSize; /**< The size of the pool data memory area */ + char name[IX_OSAL_MBUF_POOL_NAME_LEN + 1]; /**< Descriptive name for pool */ + IxOsalMbufPoolAllocationType poolAllocType; /**< Pool Allocation type */ + UINT32 poolIdx; /**< Pool Index */ +} IxOsalMbufPool; + +/** + * @ingroup IxOsalBufferMgt + * + * @brief IX_OSAL_MBUF_POOL + * + * @note Implementation of buffer pool structure for use with non-VxWorks OS + */ +typedef IxOsalMbufPool IX_OSAL_MBUF_POOL; + + +/* + * PUBLIC IX_STATUS ixOsalBuffPoolUninit (IX_OSAL_MBUF_POOL * pool); + */ +#ifdef __cplusplus +} +#endif +#endif /* IX_OSAL_BUFFER_MGT_DEFAULT_H */ diff --git a/Acceleration/library/icp_utils/OSAL/common/include/modules/ddk/IxOsalDdk.h b/Acceleration/library/icp_utils/OSAL/common/include/modules/ddk/IxOsalDdk.h new file mode 100644 index 0000000..0726a66 --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/include/modules/ddk/IxOsalDdk.h @@ -0,0 +1,180 @@ +/** + * @file IxOsalDdk.h + * + * @brief include file for OSAL's DDK module. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +#ifndef IxOsalDdk_H +#define IxOsalDdk_H +#ifdef __cplusplus +extern "C"{ +#endif +/* Basic types */ +#include "IxOsal.h" + +/* + * Include OS-specific ddk definitions + */ +#include "IxOsalOsDdk.h" +#if (!defined(__freebsd)) +/** + * @ingroup IxOsal + * + * @brief physical to virtual address translation + * + * @param physAddr - physical address + * + * Converts a physical address into its equivalent MMU-mapped virtual address + * + * @li Reentrant: no + * @li IRQ safe: yes + * + * @return Corresponding virtual address, as UINT32 + */ +#define IX_OSAL_MMU_PHYS_TO_VIRT(physAddr) \ + IX_OSAL_OS_MMU_PHYS_TO_VIRT(physAddr) + +#endif /*!defined(__freebsd)*/ + +/** + * @ingroup IxOsal + * + * @brief virtual to physical address translation + * + * @param virtAddr - virtual address + * + * Converts a virtual address into its equivalent MMU-mapped physical address + * + * @li Reentrant: no + * @li IRQ safe: yes + * + * @return Corresponding physical address, as UINT32 + */ +#define IX_OSAL_MMU_VIRT_TO_PHYS(virtAddr) \ + IX_OSAL_OS_MMU_VIRT_TO_PHYS(virtAddr) + + + +/** + * @ingroup IxOsal + * + * @brief cache to memory flush + * + * @param addr - memory address to flush from cache + * @param size - number of bytes to flush (rounded up to a cache line) + * + * Flushes the cached value of the memory zone pointed by "addr" into memory, + * rounding up to a cache line. Use before the zone is to be read by a + * processing unit which is not cache coherent with the main CPU. + * + * @li Reentrant: no + * @li IRQ safe: yes + * + * @return - none + */ +#define IX_OSAL_CACHE_FLUSH(addr, size) IX_OSAL_OS_CACHE_FLUSH(addr, size) + + + +/** + * @ingroup IxOsal + * + * @brief cache line invalidate + * + * @param addr - memory address to invalidate in cache + * @param size - number of bytes to invalidate (rounded up to a cache line) + * + * Invalidates the cached value of the memory zone pointed by "addr", + * rounding up to a cache line. Use before reading the zone from the main + * CPU, if the zone has been updated by a processing unit which is not cache + * coherent with the main CPU. + * + * @li Reentrant: no + * @li IRQ safe: yes + * + * @return - none + */ +#define IX_OSAL_CACHE_INVALIDATE(addr, size) IX_OSAL_OS_CACHE_INVALIDATE(addr, size) + +/** + * @ingroup IxOsal + * + * @brief cache line preload + * + * @param addr - memory address to cache + * @param size - number of bytes to cache (rounded up to a cache line) + * + * + * Preloads a section of memory to the cache memory in multiples of cache line size. + * + * @li Reentrant: no + * @li IRQ safe: yes + * + * @return - none + */ +#define IX_OSAL_CACHE_PRELOAD(addr, size) IX_OSAL_OS_CACHE_PRELOAD(addr, size) +#ifdef __cplusplus +} +#endif +#endif diff --git a/Acceleration/library/icp_utils/OSAL/common/include/modules/ioMem/IxOsalEndianess.h b/Acceleration/library/icp_utils/OSAL/common/include/modules/ioMem/IxOsalEndianess.h new file mode 100644 index 0000000..8e6809c --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/include/modules/ioMem/IxOsalEndianess.h @@ -0,0 +1,81 @@ +/** + * @file IxOsalEndianess.h (Obsolete file) + * + * @brief Header file for determining system endianess and OS + * + * @par + * @version $Revision: 1.1 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +#ifndef IxOsalEndianess_H +#define IxOsalEndianess_H +#ifdef __cplusplus +extern "C"{ +#endif + +#include "IxOsalOsOemIoMem.h" + +#ifdef __cplusplus +} +#endif +#endif /* IxOsalEndianess_H */ diff --git a/Acceleration/library/icp_utils/OSAL/common/include/modules/ioMem/IxOsalIoMem.h b/Acceleration/library/icp_utils/OSAL/common/include/modules/ioMem/IxOsalIoMem.h new file mode 100644 index 0000000..4952acf --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/include/modules/ioMem/IxOsalIoMem.h @@ -0,0 +1,414 @@ +/* + * @file IxOsalIoMem.h + * @author Intel Corporation + * @date 25-08-2004 + * + * @brief description goes here + */ + +/** + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +#ifndef IxOsalIoMem_H +#define IxOsalIoMem_H +#ifdef __cplusplus +extern "C"{ +#endif + +/* + * Decide OS and Endianess, such as IX_OSAL_VXWORKS_LE. + */ +#include "IxOsalEndianess.h" + +/** + * @defgroup IxOsalIoMem Osal IoMem module + * + * @brief I/O memory and endianess support. + * + * @{ + */ + + +/* Low-level conversion macros - DO NOT USE UNLESS ABSOLUTELY NEEDED */ + +/** + * @ingroup IxOsalIoMem + * + * @def IX_OSAL_SWAP_LONG + * + * @brief Swap long (32 bit) data + */ +#define IX_OSAL_SWAP_LONG(wData) IX_OSAL_OEM_SWAP_LONG(wData) + + +/** + * @ingroup IxOsalIoMem + * + * @def IX_OSAL_SWAP_SHORT + * + * @brief Swap short (16 bit) data + */ +#define IX_OSAL_SWAP_SHORT(sData) ((sData >> 8) | ((sData & 0xFF) << 8)) + +/** + * @ingroup IxOsalIoMem + * + * @def IX_OSAL_SWAP_SHORT_ADDRESS + * + * @brief Swap short (16 bit) address + */ +#define IX_OSAL_SWAP_SHORT_ADDRESS(sAddr) ((sAddr) ^ 0x2) + +/** + * @ingroup IxOsalIoMem + * + * @def IX_OSAL_SWAP_BYTE_ADDRESS + * + * @brief Swap byte address + */ +#define IX_OSAL_SWAP_BYTE_ADDRESS(bAddr) ((bAddr) ^ 0x3) + + +/* + * Decide SDRAM mapping, then implement read/write + */ +#include "IxOsalMemAccess.h" + + +/** + * @ingroup IxOsalIoMem + * @enum IxOsalMapEntryType + * @brief This is an emum for OSAL I/O mem map type. + */ +typedef enum +{ + IX_OSAL_STATIC_MAP = 0, /**<Set map entry type to static map */ + IX_OSAL_DYNAMIC_MAP /**<Set map entry type to dynamic map */ +} IxOsalMapEntryType; + + +/** + * @ingroup IxOsalIoMem + * @enum IxOsalMapEndianessType + * @brief This is an emum for OSAL I/O mem Endianess and Coherency mode. + */ +typedef enum +{ + IX_OSAL_BE = 0x1, /**<Set map endian mode to Big Endian */ + IX_OSAL_LE_AC = 0x2, /**<Set map endian mode to Little Endian, Address Coherent */ + IX_OSAL_LE_DC = 0x4, /**<Set map endian mode to Little Endian, Data Coherent */ + IX_OSAL_LE = 0x8 /**<Set map endian mode to Little Endian without specifying coherency mode */ +} IxOsalMapEndianessType; + + +/** + * @ingroup IxOsalIoMem + * + * @brief IxOsalMemoryMap + * + * @note IxOsalMemoryMap structure + */ +typedef struct _IxOsalMemoryMap +{ + IxOsalMapEntryType type; /**< map type - IX_OSAL_STATIC_MAP or IX_OSAL_DYNAMIC_MAP */ + + UINT32 physicalAddress; /**< physical address of the memory mapped I/O zone */ + + UINT32 size; /**< size of the map */ + + + UINT32 virtualAddress; /**< virtual address of the zone; must be predefined + in the global memory map for static maps and has + to be NULL for dynamic maps (populated on allocation) + */ + /* + * pointer to a map function called to map a dynamic map; + * will populate the virtualAddress field + */ + /**< pointer to a map function called to map a dynamic map */ + /** < void (*mapFunction) (struct _IxOsalMemoryMap * map); */ + IxOsalVoidFnVoidPtr mapFunction; + + /* + * pointer to a map function called to unmap a dynamic map; + * will reset the virtualAddress field to NULL + */ + /**< pointer to a map function called to unmap a dynamic map */ + /**< void (*unmapFunction) (struct _IxOsalMemoryMap * map); */ + IxOsalVoidFnVoidPtr unmapFunction; + + /* + * reference count describing how many components share this map; + * actual allocation/deallocation for dynamic maps is done only + * between 0 <=> 1 transitions of the counter + */ + UINT32 refCount; /**< reference count describing how many components share this map */ + + /* + * memory endian type for the map; can be a combination of IX_OSAL_BE (Big + * Endian) and IX_OSAL_LE or IX_OSAL_LE_AC or IX_OSAL_LE_DC + * (Little Endian, Address Coherent or Data Coherent). Any combination is + * allowed provided it contains at most one LE flag - e.g. + * (IX_OSAL_BE), (IX_OSAL_LE_AC), (IX_OSAL_BE | IX_OSAL_LE_DC), (IX_OSAL_LE) + * are valid combinations while (IX_OSAL_BE | IX_OSAL_LE_DC | IX_OSAL_LE_AC) + * is not. + */ + IxOsalMapEndianessType mapEndianType; /**< memory endian type for the map */ + + char *name; /**< user-friendly name */ +} IxOsalMemoryMap; + + + +/** + * @ingroup IxOsalIoMemInternal + * + * @brief Internal function to map a memory zone + * + * @param requestedAddress IN - Address to be mapped + * @param size IN - size of memory to be mapped + * @param requestedCoherency IN - requested cache coherency + * + * @return void + * + * @note This should not be called by the user. Use the macro + * IX_OSAL_MEM_MAP instead + */ +PUBLIC void *ixOsalIoMemMap (UINT32 requestedAddress, + UINT32 size, + IxOsalMapEndianessType requestedCoherency); + + +/** + * @ingroup IxOsalIoMemInternal + * + * @brief Internal function to unmap a memory zone + * + * @param requestedAddress IN - Address to be mapped + * @param coherency IN - cache coherency + * + * @return void + * + * @note This should not be called by the user. Use the macro + * IX_OSAL_MEM_UNMAP instead + */ +PUBLIC void ixOsalIoMemUnmap (UINT32 requestedAddress, UINT32 coherency); + +#if (!defined(__linux_user) || !defined(__freebsd_user)) + +/** + * @ingroup IxOsalIoMemInternal + * + * @brief Internal function to convert virtual address to physical address + * + * @param virtualAddress IN - Address to be mapped + * @param coherency IN - cache coherency + * + * @return UINT32 physical address + * + * @note This should not be called by the user. Use the macro + * IX_OSAL_MMAP_VIRT_TO_PHYS instead + */ +PUBLIC UINT32 ixOsalIoMemVirtToPhys (UINT32 virtualAddress, UINT32 coherency); + +/*Physical to virtual address mapping is not supported in FreeBSD release*/ +#if (!defined(__freebsd)) +/** + * @ingroup IxOsalIoMemInternal + * + * @brief Internal function to convert physical address to virtual address + * + * @param physicalAddress IN - Address to be mapped + * @param coherency IN - cache coherency + * + * @return UINT32 virtual address + * + * @note This should not be called by the user. Use the macro + * IX_OSAL_MMAP_PHYS_TO_VIRT instead + */ +PUBLIC UINT32 +ixOsalIoMemPhysToVirt (UINT32 physicalAddress, UINT32 coherency); +#endif /*!defined(freebsd)*/ + +#endif /* !defined(__linux_user) || !defined(__freebsd_user) */ + +/** + * @ingroup IxOsalIoMem + * + * @def IX_OSAL_MEM_MAP(physAddr, size) + * + * @brief Map an I/O mapped physical memory zone to virtual zone and return virtual + * pointer. + * @param physAddr - the physical address + * @param size - the size + * @return start address of the virtual memory zone. + * + * @note This function maps an I/O mapped physical memory zone of the given size + * into a virtual memory zone accessible by the caller and returns a cookie - + * the start address of the virtual memory zone. + * IX_OSAL_MMAP_PHYS_TO_VIRT should NOT therefore be used on the returned + * virtual address. + * The memory zone is to be unmapped using IX_OSAL_MEM_UNMAP once the caller has + * finished using this zone (e.g. on driver unload) using the cookie as + * parameter. + * The IX_OSAL_READ/WRITE_LONG/SHORT macros should be used to read and write + * the mapped memory, adding the necessary offsets to the address cookie. + */ +#define IX_OSAL_MEM_MAP(physAddr, size) \ + ixOsalIoMemMap((physAddr), (size), IX_OSAL_COMPONENT_MAPPING) + + +/** + * @ingroup IxOsalIoMem + * + * @def IX_OSAL_MEM_UNMAP(virtAddr) + * + * @brief Unmap a previously mapped I/O memory zone using virtual pointer obtained + * during the mapping operation. + * pointer. + * @param virtAddr - the virtual pointer to the zone to be unmapped. + * @return none + * + * @note This function unmaps a previously mapped I/O memory zone using + * the cookie obtained in the mapping operation. The memory zone in question + * becomes unavailable to the caller once unmapped and the cookie should be + * discarded. + * + * This function cannot fail if the given parameter is correct and does not + * return a value. + */ +#define IX_OSAL_MEM_UNMAP(virtAddr) \ + ixOsalIoMemUnmap ((virtAddr), IX_OSAL_COMPONENT_MAPPING) + +#if (!defined(__linux_user) || !defined(__freebsd_user)) + +/** + * @ingroup IxOsalIoMem + * + * @def IX_OSAL_MMAP_VIRT_TO_PHYS(virtAddr) + * + * @brief This function Converts a virtual address into a physical + * address, including the dynamically mapped memory. + * + * @param virtAddr - virtual address to convert + * Return value: corresponding physical address, or NULL + */ +#define IX_OSAL_MMAP_VIRT_TO_PHYS(virtAddr) \ + ixOsalIoMemVirtToPhys(virtAddr, IX_OSAL_COMPONENT_MAPPING) + +/*Physical to virtual address mapping is not supported in FreeBSD release*/ +#if (!defined(__freebsd)) + +/** + * @ingroup IxOsalIoMem + * + * @def IX_OSAL_MMAP_PHYS_TO_VIRT(physAddr) + * + * @brief This function Converts a virtual address into a physical + * address, including the dynamically mapped memory. + * + * @param physAddr - physical address to convert + * Return value: corresponding virtual address, or NULL + * + */ +#define IX_OSAL_MMAP_PHYS_TO_VIRT(physAddr) \ + ixOsalIoMemPhysToVirt(physAddr, IX_OSAL_COMPONENT_MAPPING) + +#endif + +/** + * @ingroup IxOsalIoMem + * + * @brief map physical memory into virtual address space + * + * @param physAddr - physical address to map + * @param size - size of the memory to map + * + * @return start address of the virtual memory zone. + * + */ +PUBLIC +UINT32 ixOsalIoRemap (UINT32 physAddr, UINT32 size); + +/** + * @ingroup IxOsalIoMem + * + * @brief unmap virtual address space which was mapped using ixOsalIoRemap + * + * @param virtAddr - virtual address + * + * Return value: void + * + */ +PUBLIC +void ixOsalIoUnmap (UINT32 virtAddr, UINT32 size); + + +#endif /* !defined(__linux_user) ||!defined(__freebsd_user) */ + +/** + * @} IxOsalIoMem + */ +#ifdef __cplusplus +} +#endif +#endif /* IxOsalIoMem_H */ diff --git a/Acceleration/library/icp_utils/OSAL/common/include/modules/ioMem/IxOsalMemAccess.h b/Acceleration/library/icp_utils/OSAL/common/include/modules/ioMem/IxOsalMemAccess.h new file mode 100644 index 0000000..4b608b2 --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/include/modules/ioMem/IxOsalMemAccess.h @@ -0,0 +1,628 @@ +/** + * @file IxOsalMemAccess.h + * + * @brief Header file for memory access + * + * @par + * @version $Revision: 1.0 $ + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +#ifndef IxOsalMemAccess_H +#define IxOsalMemAccess_H +#ifdef __cplusplus +extern "C"{ +#endif + +/* Global BE switch + * + * Should be set only in BE mode and only if the component uses I/O memory. + */ + +#if defined (__BIG_ENDIAN) +#define IX_OSAL_BE_MAPPING + +#endif /* Global switch */ + + +/** + * @ingroup IxOsalIoMem + * + * @def IX_OSAL_STATIC_MEMORY_MAP + * + * @brief By default only static memory maps in use. + * Define IX_OSAL_DYNAMIC_MEMORY_MAP per component if dynamic maps are + * used instead in that component + */ +#define IX_OSAL_STATIC_MEMORY_MAP + + +/* + * SDRAM coherency mode + * Must be defined to BE, LE_DATA_COHERENT or LE_ADDRESS_COHERENT. + * The mode changes depending on OS + */ +#if defined (IX_OSAL_LINUX_BE) || defined (IX_OSAL_VXWORKS_BE) + +#define IX_SDRAM_BE + +#elif defined (IX_OSAL_LINUX_LE) + +#ifdef IX_SDRAM_DC +#define IX_SDRAM_LE_DATA_COHERENT +#else +#define IX_SDRAM_LE +#endif + +#elif defined (IX_OSAL_VXWORKS_LE) + +#define IX_SDRAM_LE_DATA_COHERENT + +#elif defined (IX_OSAL_WINCE_LE) + +#define IX_SDRAM_LE_DATA_COHERENT + +#elif defined (IX_OSAL_EBOOT_LE) + +#define IX_SDRAM_LE_ADDRESS_COHERENT + +#elif defined (IX_OSAL_WINXPE_LE) + +#define IX_SDRAM_LE + +#elif defined (IX_OSAL_FREEBSD_LE) + +#define IX_SDRAM_LE +#define IX_OSAL_LE_MAPPING + +#endif + + + + +/************************************** + * Retrieve current component mapping * + **************************************/ + +/* + * Only use customized mapping for LE. + * + */ +#if defined (IX_OSAL_VXWORKS_LE) || defined (IX_OSAL_LINUX_LE) || defined (IX_OSAL_WINCE_LE) || defined (IX_OSAL_EBOOT_LE) || defined (IX_OSAL_WINXPE_LE) + +#include "IxOsalOsOemCustomizedMapping.h" +#endif + + +/******************************************************************* + * Turn off IX_STATIC_MEMORY map for components using dynamic maps * + *******************************************************************/ +#ifdef IX_OSAL_DYNAMIC_MEMORY_MAP + +#undef IX_OSAL_STATIC_MEMORY_MAP + +#endif + + +/************************************************************ + * Turn off BE access for components using LE or no mapping * + ************************************************************/ +#if defined (IX_OSAL_LE_AC_MAPPING) || defined (IX_OSAL_LE_DC_MAPPING) || \ + defined (IX_OSAL_LE_MAPPING) || defined (IX_OSAL_NO_MAPPING) + +#undef IX_OSAL_BE_MAPPING + +#endif + + +/***************** + * Safety checks * + *****************/ + +/* Default to no_mapping */ +#if !defined (IX_OSAL_BE_MAPPING) && !defined (IX_OSAL_LE_AC_MAPPING) && !defined (IX_OSAL_LE_DC_MAPPING) && !defined (IX_OSAL_LE_MAPPING) && !defined (IX_OSAL_NO_MAPPING) + +/** + * @def IX_OSAL_NO_MAPPING + * + * @brief No mapping + */ +#define IX_OSAL_NO_MAPPING + +#endif /* check at least one mapping */ + +/* No more than one mapping can be defined for a component */ +#if ( (defined (IX_OSAL_BE_MAPPING) && defined (IX_OSAL_LE_AC_MAPPING)) \ + ||(defined (IX_OSAL_BE_MAPPING) && defined (IX_OSAL_LE_DC_MAPPING)) \ + ||(defined (IX_OSAL_BE_MAPPING) && defined (IX_OSAL_LE_MAPPING)) \ + ||(defined (IX_OSAL_BE_MAPPING) && defined (IX_OSAL_NO_MAPPING)) \ + ||(defined (IX_OSAL_LE_DC_MAPPING) && defined (IX_OSAL_LE_AC_MAPPING)) \ + ||(defined (IX_OSAL_LE_DC_MAPPING) && defined (IX_OSAL_LE_MAPPING)) \ + ||(defined (IX_OSAL_LE_DC_MAPPING) && defined (IX_OSAL_NO_MAPPING)) \ + ||(defined (IX_OSAL_LE_AC_MAPPING) && defined (IX_OSAL_LE_MAPPING)) \ + ||(defined (IX_OSAL_LE_AC_MAPPING) && defined (IX_OSAL_NO_MAPPING)) \ + ||(defined (IX_OSAL_LE_MAPPING) && defined (IX_OSAL_NO_MAPPING))) + +#ifdef IX_OSAL_BE_MAPPING +#warning IX_OSAL_BE_MAPPING is defined +#endif + +#ifdef IX_OSAL_LE_AC_MAPPING +#warning IX_OSAL_LE_AC_MAPPING is defined +#endif + +#ifdef IX_OSAL_LE_DC_MAPPING +#warning IX_OSAL_LE_DC_MAPPING is defined +#endif + +#ifdef IX_OSAL_LE_MAPPING +#warning IX_OSAL_LE_MAPPING is defined +#endif + +#ifdef IX_OSAL_NO_MAPPING +#warning IX_OSAL_NO_MAPPING is defined +#endif + +#error More than one I/O mapping is defined, please check your component mapping + +#endif /* check at most one mapping */ + + +/* Now set IX_OSAL_COMPONENT_MAPPING */ + +/** + * @def IX_OSAL_COMPONENT_MAPPING + * + * @brief Set this based on mapping defines + */ +#ifdef IX_OSAL_BE_MAPPING +#define IX_OSAL_COMPONENT_MAPPING IX_OSAL_BE +#endif + +#ifdef IX_OSAL_LE_AC_MAPPING +#define IX_OSAL_COMPONENT_MAPPING IX_OSAL_LE_AC +#endif + +#ifdef IX_OSAL_LE_DC_MAPPING +#define IX_OSAL_COMPONENT_MAPPING IX_OSAL_LE_DC +#endif + +#ifdef IX_OSAL_LE_MAPPING +#define IX_OSAL_COMPONENT_MAPPING IX_OSAL_LE +#endif +#ifdef IX_OSAL_NO_MAPPING +#define IX_OSAL_COMPONENT_MAPPING IX_OSAL_LE +#endif + + +/* SDRAM coherency should be defined */ +#if !defined (IX_SDRAM_BE) && !defined (IX_SDRAM_LE_DATA_COHERENT) && !defined (IX_SDRAM_LE_ADDRESS_COHERENT) && !defined(IX_SDRAM_LE) + +#error SDRAM coherency must be defined + +#endif /* SDRAM coherency must be defined */ + +/* SDRAM coherency cannot be defined in several ways */ +#if (defined (IX_SDRAM_BE) && (defined (IX_SDRAM_LE_DATA_COHERENT) || \ + defined (IX_SDRAM_LE_ADDRESS_COHERENT) || \ + defined (IX_SDRAM_LE))) \ + || (defined (IX_SDRAM_LE_DATA_COHERENT) && (defined (IX_SDRAM_BE) || \ + defined (IX_SDRAM_LE_ADDRESS_COHERENT) || \ + defined (IX_SDRAM_LE))) \ + || (defined (IX_SDRAM_LE_ADDRESS_COHERENT) && (defined (IX_SDRAM_BE) || \ + defined (IX_SDRAM_LE_DATA_COHERENT) || \ + defined (IX_SDRAM_LE))) + +#error SDRAM coherency cannot be defined in more than one way + +#endif /* SDRAM coherency must be defined exactly once */ + + +/********************* + * Read/write macros * + *********************/ + +/* WARNING - except for addition of special cookie read/write macros (see below) + these macros are NOT user serviceable. Please do not modify */ + +/** + * @ingroup IxOsalIoMem + * + * @def IX_OSAL_READ_LONG_RAW + * + * @brief Read long data. + */ +#define IX_OSAL_READ_LONG_RAW(wAddr) (*(wAddr)) + +/** + * @ingroup IxOsalIoMem + * + * @def IX_OSAL_READ_SHORT_RAW + * + * @brief Read short data. + */ +#define IX_OSAL_READ_SHORT_RAW(sAddr) (*(sAddr)) + +/** + * @ingroup IxOsalIoMem + * + * @def IX_OSAL_READ_BYTE_RAW + * + * @brief Read byte data. + */ +#define IX_OSAL_READ_BYTE_RAW(bAddr) (*(bAddr)) + +/** + * @ingroup IxOsalIoMem + * + * @def IX_OSAL_WRITE_LONG_RAW + * + * @brief Write long data. + */ +#define IX_OSAL_WRITE_LONG_RAW(wAddr, wData) (*(wAddr) = (wData)) + +/** + * @ingroup IxOsalIoMem + * + * @def IX_OSAL_WRITE_SHORT_RAW + * + * @brief Write short data. + */ +#define IX_OSAL_WRITE_SHORT_RAW(sAddr,sData) (*(sAddr) = (sData)) + +/** + * @ingroup IxOsalIoMem + * + * @def IX_OSAL_WRITE_BYTE_RAW + * + * @brief Write Byte. + */ +#define IX_OSAL_WRITE_BYTE_RAW(bAddr, bData) (*(bAddr) = (bData)) + +#ifdef __linux + +/* Linux - specific cookie reads/writes. + Redefine per OS if dynamic memory maps are used + and I/O memory is accessed via functions instead of raw pointer access. */ + +#define IX_OSAL_READ_LONG_COOKIE(wCookie) (readl((UINT32) (wCookie) )) +#define IX_OSAL_READ_SHORT_COOKIE(sCookie) (readw((UINT32) (sCookie) )) +#define IX_OSAL_READ_BYTE_COOKIE(bCookie) (readb((UINT32) (bCookie) )) +#define IX_OSAL_WRITE_LONG_COOKIE(wCookie, wData) (writel(wData, (UINT32) (wCookie) )) +#define IX_OSAL_WRITE_SHORT_COOKIE(sCookie, sData) (writew(sData, (UINT32) (sCookie) )) +#define IX_OSAL_WRITE_BYTE_COOKIE(bCookie, bData) (writeb(bData, (UINT32) (bCookie) )) + +#endif /* linux */ + + +#ifdef __wince + +/* WinCE - specific cookie reads/writes. */ + +static __inline__ UINT32 +ixOsalWinCEReadLCookie (volatile UINT32 * lCookie) +{ + return *lCookie; +} + +static __inline__ UINT16 +ixOsalWinCEReadWCookie (volatile UINT16 * wCookie) +{ +#if 0 + UINT32 auxVal = *((volatile UINT32 *) wCookie); + if ((unsigned) wCookie & 3) + return (UINT16) (auxVal >> 16); + else + return (UINT16) (auxVal & 0xffff); +#else + return *wCookie; +#endif +} + +static __inline__ UINT8 +ixOsalWinCEReadBCookie (volatile UINT8 * bCookie) +{ +#if 0 + UINT32 auxVal = *((volatile UINT32 *) bCookie); + return (UINT8) ((auxVal >> (3 - (((unsigned) bCookie & 3) << 3)) & 0xff)); +#else + return *bCookie; +#endif +} + +static __inline__ void +ixOsalWinCEWriteLCookie (volatile UINT32 * lCookie, UINT32 lVal) +{ + *lCookie = lVal; +} + +static __inline__ void +ixOsalWinCEWriteWCookie (volatile UINT16 * wCookie, UINT16 wVal) +{ +#if 0 + volatile UINT32 *auxCookie = + (volatile UINT32 *) ((unsigned) wCookie & ~3); + if ((unsigned) wCookie & 3) + { + *auxCookie &= 0xffff; + *auxCookie |= (UINT32) wVal << 16; + } + else + { + *auxCookie &= ~0xffff; + *auxCookie |= (UINT32) wVal & 0xffff; + } +#else + *wCookie = wVal; +#endif +} + +static __inline__ void +ixOsalWinCEWriteBCookie (volatile UINT8 * bCookie, UINT8 bVal) +{ +#if 0 + volatile UINT32 *auxCookie = + (volatile UINT32 *) ((unsigned) bCookie & ~3); + *auxCookie &= 0xff << (3 - (((unsigned) bCookie & 3) << 3)); + *auxCookie |= (UINT32) bVal << (3 - (((unsigned) bCookie & 3) << 3)); +#else + *bCookie = bVal; +#endif +} + + +#define IX_OSAL_READ_LONG_COOKIE(wCookie) (ixOsalWinCEReadLCookie(wCookie)) +#define IX_OSAL_READ_SHORT_COOKIE(sCookie) (ixOsalWinCEReadWCookie(sCookie)) +#define IX_OSAL_READ_BYTE_COOKIE(bCookie) (ixOsalWinCEReadBCookie(bCookie)) +#define IX_OSAL_WRITE_LONG_COOKIE(wCookie, wData) (ixOsalWinCEWriteLCookie(wCookie, wData)) +#define IX_OSAL_WRITE_SHORT_COOKIE(sCookie, sData) (ixOsalWinCEWriteWCookie(sCookie, sData)) +#define IX_OSAL_WRITE_BYTE_COOKIE(bCookie, bData) (ixOsalWinCEWriteBCookie(bCookie, bData)) + +#endif /* wince */ + +#if defined (__vxworks) || (defined (__linux) && defined (IX_OSAL_STATIC_MEMORY_MAP)) || \ + (defined (__wince) && defined (IX_OSAL_STATIC_MEMORY_MAP)) || \ + defined (__winxpe) || defined (__freebsd_user) || defined(__freebsd) + +#define IX_OSAL_READ_LONG_IO(wAddr) IX_OSAL_READ_LONG_RAW(wAddr) +#define IX_OSAL_READ_SHORT_IO(sAddr) IX_OSAL_READ_SHORT_RAW(sAddr) +#define IX_OSAL_READ_BYTE_IO(bAddr) IX_OSAL_READ_BYTE_RAW(bAddr) +#define IX_OSAL_WRITE_LONG_IO(wAddr, wData) IX_OSAL_WRITE_LONG_RAW(wAddr, wData) +#define IX_OSAL_WRITE_SHORT_IO(sAddr, sData) IX_OSAL_WRITE_SHORT_RAW(sAddr, sData) +#define IX_OSAL_WRITE_BYTE_IO(bAddr, bData) IX_OSAL_WRITE_BYTE_RAW(bAddr, bData) + +#elif (defined (__linux) && !defined (IX_OSAL_STATIC_MEMORY_MAP)) || \ + (defined (__wince) && !defined (IX_OSAL_STATIC_MEMORY_MAP)) + +#ifndef __wince +#include <asm/io.h> +#endif /* ndef __wince */ + +#define IX_OSAL_READ_LONG_IO(wAddr) IX_OSAL_READ_LONG_COOKIE(wAddr) +#define IX_OSAL_READ_SHORT_IO(sAddr) IX_OSAL_READ_SHORT_COOKIE(sAddr) +#define IX_OSAL_READ_BYTE_IO(bAddr) IX_OSAL_READ_BYTE_COOKIE(bAddr) +#define IX_OSAL_WRITE_LONG_IO(wAddr, wData) IX_OSAL_WRITE_LONG_COOKIE(wAddr, wData) +#define IX_OSAL_WRITE_SHORT_IO(sAddr, sData) IX_OSAL_WRITE_SHORT_COOKIE(sAddr, sData) +#define IX_OSAL_WRITE_BYTE_IO(bAddr, bData) IX_OSAL_WRITE_BYTE_COOKIE(bAddr, bData) + +#endif + + +#if defined (IX_OSAL_BE_MAPPING) + +#define IX_OSAL_READ_LONG(wAddr) IX_OSAL_READ_LONG_BE(wAddr) +#define IX_OSAL_READ_SHORT(sAddr) IX_OSAL_READ_SHORT_BE(sAddr) +#define IX_OSAL_READ_BYTE(bAddr) IX_OSAL_READ_BYTE_BE(bAddr) +#define IX_OSAL_WRITE_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_BE(wAddr, wData) +#define IX_OSAL_WRITE_SHORT(sAddr, sData) IX_OSAL_WRITE_SHORT_BE(sAddr, sData) +#define IX_OSAL_WRITE_BYTE(bAddr, bData) IX_OSAL_WRITE_BYTE_BE(bAddr, bData) + +#elif defined (IX_OSAL_LE_AC_MAPPING) + +#define IX_OSAL_READ_LONG(wAddr) IX_OSAL_READ_LONG_LE_AC(wAddr) +#define IX_OSAL_READ_SHORT(sAddr) IX_OSAL_READ_SHORT_LE_AC(sAddr) +#define IX_OSAL_READ_BYTE(bAddr) IX_OSAL_READ_BYTE_LE_AC(bAddr) +#define IX_OSAL_WRITE_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_LE_AC(wAddr, wData) +#define IX_OSAL_WRITE_SHORT(sAddr, sData) IX_OSAL_WRITE_SHORT_LE_AC(sAddr, sData) +#define IX_OSAL_WRITE_BYTE(bAddr, bData) IX_OSAL_WRITE_BYTE_LE_AC(bAddr, bData) + +#elif defined (IX_OSAL_LE_DC_MAPPING) + +#define IX_OSAL_READ_LONG(wAddr) IX_OSAL_READ_LONG_LE_DC(wAddr) +#define IX_OSAL_READ_SHORT(sAddr) IX_OSAL_READ_SHORT_LE_DC(sAddr) +#define IX_OSAL_READ_BYTE(bAddr) IX_OSAL_READ_BYTE_LE_DC(bAddr) +#define IX_OSAL_WRITE_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_LE_DC(wAddr, wData) +#define IX_OSAL_WRITE_SHORT(sAddr, sData) IX_OSAL_WRITE_SHORT_LE_DC(sAddr, sData) +#define IX_OSAL_WRITE_BYTE(bAddr, bData) IX_OSAL_WRITE_BYTE_LE_DC(bAddr, bData) + +#elif defined (IX_OSAL_LE_MAPPING) + +#define IX_OSAL_READ_LONG(wAddr) IX_OSAL_READ_LONG_LE(wAddr) +#define IX_OSAL_READ_SHORT(sAddr) IX_OSAL_READ_SHORT_LE(sAddr) +#define IX_OSAL_READ_BYTE(bAddr) IX_OSAL_READ_BYTE_LE(bAddr) +#define IX_OSAL_WRITE_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_LE(wAddr, wData) +#define IX_OSAL_WRITE_SHORT(sAddr, sData) IX_OSAL_WRITE_SHORT_LE(sAddr, sData) +#define IX_OSAL_WRITE_BYTE(bAddr, bData) IX_OSAL_WRITE_BYTE_LE(bAddr, bData) + +#endif /* End of BE and LE coherency mode switch */ + +/* Reads/writes to and from memory shared with PIUs - depends on the + SDRAM coherency */ + +#if defined (IX_SDRAM_BE) + +#define IX_OSAL_READ_BE_SHARED_LONG(wAddr) IX_OSAL_READ_LONG_RAW(wAddr) +#define IX_OSAL_READ_BE_SHARED_SHORT(sAddr) IX_OSAL_READ_SHORT_RAW(sAddr) +#define IX_OSAL_READ_BE_SHARED_BYTE(bAddr) IX_OSAL_READ_BYTE_RAW(bAddr) + +#define IX_OSAL_WRITE_BE_SHARED_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_RAW(wAddr, wData) +#define IX_OSAL_WRITE_BE_SHARED_SHORT(sAddr, sData) IX_OSAL_WRITE_SHORT_RAW(sAddr, sData) +#define IX_OSAL_WRITE_BE_SHARED_BYTE(bAddr, bData) IX_OSAL_WRITE_BYTE_RAW(bAddr, bData) + +#define IX_OSAL_SWAP_BE_SHARED_LONG(wData) (wData) +#define IX_OSAL_SWAP_BE_SHARED_SHORT(sData) (sData) +#define IX_OSAL_SWAP_BE_SHARED_BYTE(bData) (bData) + +#elif defined (IX_SDRAM_LE_ADDRESS_COHERENT) + +#define IX_OSAL_READ_BE_SHARED_LONG(wAddr) IX_OSAL_READ_LONG_RAW(wAddr) +#define IX_OSAL_READ_BE_SHARED_SHORT(sAddr) IX_OSAL_READ_SHORT_RAW(IX_OSAL_SWAP_SHORT_ADDRESS(sAddr)) +#define IX_OSAL_READ_BE_SHARED_BYTE(bAddr) IX_OSAL_READ_BYTE_RAW(IX_OSAL_SWAP_BYTE_ADDRESS(bAddr)) + +#define IX_OSAL_WRITE_BE_SHARED_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_RAW(wAddr, wData) +#define IX_OSAL_WRITE_BE_SHARED_SHORT(sAddr, sData) IX_OSAL_WRITE_SHORT_RAW(IX_OSAL_SWAP_SHORT_ADDRESS(sAddr), sData) +#define IX_OSAL_WRITE_BE_SHARED_BYTE(bAddr, bData) IX_OSAL_WRITE_BYTE_RAW(IX_OSAL_SWAP_BYTE_ADDRESS(bAddr), bData) + +#define IX_OSAL_SWAP_BE_SHARED_LONG(wData) (wData) +#define IX_OSAL_SWAP_BE_SHARED_SHORT(sData) (sData) +#define IX_OSAL_SWAP_BE_SHARED_BYTE(bData) (bData) + +#elif defined (IX_SDRAM_LE_DATA_COHERENT) + +#define IX_OSAL_READ_BE_SHARED_LONG(wAddr) IX_OSAL_SWAP_LONG(IX_OSAL_READ_LONG_RAW(wAddr)) +#define IX_OSAL_READ_BE_SHARED_SHORT(sAddr) IX_OSAL_SWAP_SHORT(IX_OSAL_READ_SHORT_RAW(sAddr)) +#define IX_OSAL_READ_BE_SHARED_BYTE(bAddr) IX_OSAL_READ_BYTE_RAW(bAddr) + +#define IX_OSAL_WRITE_BE_SHARED_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_RAW(wAddr, IX_OSAL_SWAP_LONG(wData)) +#define IX_OSAL_WRITE_BE_SHARED_SHORT(sAddr, sData) IX_OSAL_WRITE_SHORT_RAW(sAddr, IX_OSAL_SWAP_SHORT(sData)) +#define IX_OSAL_WRITE_BE_SHARED_BYTE(bAddr, bData) IX_OSAL_WRITE_BYTE_RAW(bAddr, bData) + +#define IX_OSAL_SWAP_BE_SHARED_LONG(wData) IX_OSAL_SWAP_LONG(wData) +#define IX_OSAL_SWAP_BE_SHARED_SHORT(sData) IX_OSAL_SWAP_SHORT(sData) +#define IX_OSAL_SWAP_BE_SHARED_BYTE(bData) (bData) + +#elif defined (IX_SDRAM_LE) + +#define IX_OSAL_READ_BE_SHARED_LONG(wAddr) IX_OSAL_SWAP_LONG(IX_OSAL_READ_LONG_RAW(wAddr)) + +#define IX_OSAL_READ_BE_SHARED_SHORT(sAddr) IX_OSAL_SWAP_SHORT(IX_OSAL_READ_SHORT_RAW(sAddr)) + +#define IX_OSAL_READ_BE_SHARED_BYTE(bAddr) IX_OSAL_READ_BYTE_RAW(bAddr) + +#define IX_OSAL_WRITE_BE_SHARED_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_RAW(wAddr, IX_OSAL_SWAP_LONG(wData)) + +#define IX_OSAL_WRITE_BE_SHARED_SHORT(sAddr, sData) IX_OSAL_WRITE_SHORT_RAW(sAddr,IX_OSAL_SWAP_SHORT(sData)) + +#define IX_OSAL_WRITE_BE_SHARED_BYTE(bAddr, bData) IX_OSAL_WRITE_BYTE_RAW(bAddr, bData) + +#define IX_OSAL_SWAP_BE_SHARED_LONG(wData) IX_OSAL_SWAP_LONG(wData) +#define IX_OSAL_SWAP_BE_SHARED_SHORT(sData) IX_OSAL_SWAP_SHORT(sData) +#define IX_OSAL_SWAP_BE_SHARED_BYTE(bData) (bData) + +#endif + + +/** + * @ingroup IxOsalIoMem + * + * @def IX_OSAL_COPY_BE_SHARED_LONG_ARRAY + * + * @brief Copy Big Endian shared array. + */ +#define IX_OSAL_COPY_BE_SHARED_LONG_ARRAY(wDestAddr, wSrcAddr, wCount) \ + { \ + UINT32 i; \ + \ + for ( i = 0 ; i < wCount ; i++ ) \ + { \ + * (((UINT32 *) wDestAddr) + i) = IX_OSAL_READ_BE_SHARED_LONG(((UINT32 *) wSrcAddr) + i); \ + }; \ + }; + +/** + * @ingroup IxOsalIoMem + * + * @def IX_OSAL_READ_BE_SHARED_ARRAY + * + * @brief Read Big Endian shared array. + */ +#define IX_OSAL_READ_BE_SHARED_ARRAY(wSrcAddr, wCount, wDestAddr) \ + { \ + UINT32 i; \ + \ + for ( i = 0 ; i < wCount ; i++ ) \ + { \ + * (((UINT32 *) wDestAddr) + i) = IX_OSAL_READ_BE_SHARED_LONG(((UINT32 *) wSrcAddr) + i); \ + }; \ + }; + +/** + * @ingroup IxOsalIoMem + * + * @def IX_OSAL_WRITE_BE_SHARED_ARRAY + * + * @brief Write Big Endian shared array. + */ +#define IX_OSAL_WRITE_BE_SHARED_ARRAY(wSrcAddr, wCount, wDestAddr) \ + { \ + UINT32 i; \ + \ + for ( i = 0 ; i < wCount ; i++ ) \ + { \ + IX_OSAL_WRITE_BE_SHARED_LONG((((UINT32 *) wDestAddr) + i), * (((UINT32 *) wSrcAddr) + i)); \ + }; \ + }; + +#ifdef __cplusplus +} +#endif +#endif /* IxOsalMemAccess_H */ diff --git a/Acceleration/library/icp_utils/OSAL/common/os/linux/include/core/IxOsalOs.h b/Acceleration/library/icp_utils/OSAL/common/os/linux/include/core/IxOsalOs.h new file mode 100644 index 0000000..9651c55 --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/os/linux/include/core/IxOsalOs.h @@ -0,0 +1,191 @@ +/** + * @file IxOsalOs.h + * + * @brief linux-specific defines + * + * Design Notes: + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +#ifndef IxOsalOs_H +#define IxOsalOs_H + +#ifndef IX_OSAL_CACHED + +#error "Uncached memory not supported in linux environment" + +#endif + +#if KERNEL_VERSION(2,6,0) <= LINUX_VERSION_CODE + +#include <linux/dma-mapping.h> + +#include <asm/io.h> + +#include <linux/pci.h> + +#include <asm/div64.h> + +#else /* ! KERNEL_VERSION 2.6 */ + +#include <linux/cache.h> + +#endif + +#include <linux/mm.h> +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18) +#include <linux/autoconf.h> +#elif KERNEL_VERSION(2,6,16) >= LINUX_VERSION_CODE +#include <linux/config.h> +#endif + +#include <asm/pgalloc.h> + +/** + * Linux implementations of macros. + */ + +/** + * Protect this with a flag that is valid only for 2.6.X and above + */ +#if KERNEL_VERSION(2,6,0) <= LINUX_VERSION_CODE + +#define IX_OSAL_OS_UDIV64_32(dividend, divisor) \ +({ \ + UINT64 _div = dividend; \ + \ + do_div(_div, divisor); \ + \ + _div; \ +}) + +#define IX_OSAL_OS_UMOD64_32(dividend, divisor) \ +({ \ + UINT64 _div = dividend; \ + \ + do_div(_div, divisor); \ +}) + +#else /* If less than 2.6, then empty macro */ + +#define IX_OSAL_OS_UDIV64_32(dividend, divisor) \ + ixOsalLog(IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, \ + "UDIV64: Macro not implemented\n", \ + 0,0,0,0,0,0); + +#define IX_OSAL_OS_UMOD64_32(dividend, divisor) \ + ixOsalLog(IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, \ + "UMOD64: Macro not implemented\n", \ + 0,0,0,0,0,0); + +#endif /* KERNEL_VERSION */ + + +#define IX_OSAL_OS_MMU_VIRT_TO_PHYS(addr) ((addr) ? virt_to_phys((void*)(addr)) : 0) + +#define IX_OSAL_OS_MMU_PHYS_TO_VIRT(addr) ((addr) ? phys_to_virt((unsigned int)(addr)) : 0) + +#ifndef IX_HW_COHERENT_MEMORY + +#if KERNEL_VERSION(2,6,0) <= LINUX_VERSION_CODE + +#define IX_OSAL_OS_CACHE_INVALIDATE(addr, size) \ + (consistent_sync((void*)addr, (size_t) size, DMA_FROM_DEVICE)) + +#define IX_OSAL_OS_CACHE_FLUSH(addr, size) \ + (consistent_sync((void*)addr, (size_t) size, DMA_TO_DEVICE)) + +#else /* !KERNEL_VERSION 2.6 */ + +#define IX_OSAL_OS_CACHE_INVALIDATE(addr, size) \ + (invalidate_dcache_range((__u32)addr, (__u32)addr + size )) + +#define IX_OSAL_OS_CACHE_FLUSH(addr, size) \ + (clean_dcache_range((__u32)addr, (__u32)addr + size)) + +#endif /* KERNEL_VERSION */ + +#else /* IX_HW_COHERENT_MEMORY */ + +/* + * The non-coherent memory region is exposed as uncacheable memory. + * So there is no need for cache invalidation or cache flushing + */ +#define IX_OSAL_OS_CACHE_INVALIDATE(addr, size) do { } while(0); + +#define IX_OSAL_OS_CACHE_FLUSH(addr, size) do { } while(0); + +#endif /* IX_HW_COHERENT_MEMORY */ + +#define OSAL_OS_GET_STRING_LENGTH(str) strlen(str) + +#define IX_OSAL_OS_CACHE_PRELOAD(addr,size) do { } while(0); + +#define IX_OSAL_OS_ATOMIC_INIT(val) ATOMIC_INIT(val) + +/* + * s - memory size + * a - memory alignment + */ +#define IX_OSAL_MEM_PADDING(s, a) ( ( a - (s % a)) % a ) + +#endif /* IxOsalOs_H */ diff --git a/Acceleration/library/icp_utils/OSAL/common/os/linux/include/core/IxOsalOsAssert.h b/Acceleration/library/icp_utils/OSAL/common/os/linux/include/core/IxOsalOsAssert.h new file mode 100644 index 0000000..f6559ea --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/os/linux/include/core/IxOsalOsAssert.h @@ -0,0 +1,88 @@ +/** + * @file IxOsalOsAssert.h + * + * @brief Assert + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +#ifndef IxOsalOsAssert_H +#define IxOsalOsAssert_H +#define IX_OSAL_OS_ASSERT(c) if(!(c)) \ + { \ + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, "Assertion failure in file %s at line %d \n",(int)__FILE__,(int) __LINE__, 0, 0, 0, 0);\ + BUG(); \ + } + + +#define IX_OSAL_OS_MEM_ASSERT(c) if(!(c)) \ + { \ + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, "Assertion failure in file %s at line %d \n",(int)__FILE__,(int) __LINE__, 0, 0, 0, 0);\ + BUG(); \ + } + + + +/* + * Place holder. + */ +#endif /* IxOsalOsAssert_H */ diff --git a/Acceleration/library/icp_utils/OSAL/common/os/linux/include/core/IxOsalOsTypes.h b/Acceleration/library/icp_utils/OSAL/common/os/linux/include/core/IxOsalOsTypes.h new file mode 100644 index 0000000..ac00824 --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/os/linux/include/core/IxOsalOsTypes.h @@ -0,0 +1,311 @@ +/** + * @file IxOsalOsTypes.h + * + * @brief Linux-specific data type + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +#ifndef IxOsalOsTypes_H +#define IxOsalOsTypes_H + +#include <linux/types.h> +#include <linux/version.h> + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18) +#include <linux/autoconf.h> +#elif KERNEL_VERSION(2,6,16) >= LINUX_VERSION_CODE +#include <linux/config.h> +#endif + +#if KERNEL_VERSION(2,6,0) <= LINUX_VERSION_CODE + +#include <linux/sched.h> +#include <linux/kthread.h> + +#endif /* KERNEL_VERSION_2.6 */ + +#ifdef ENABLE_SPINLOCK + +#include <linux/spinlock.h> + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) +#include <linux/interrupt.h> +#endif /*< KERNEL_VERSION(2,6,18*/ + +#endif /* ENABLE_SPINLOCK */ + +#include <asm/atomic.h> +#include <linux/semaphore.h> + +#ifdef USE_NATIVE_OS_TIMER_API +#include <linux/timer.h> +#endif + +#include <linux/wait.h> + +#include "IxOsalUtilitySymbols.h" + +#ifndef __ACTYPES_H__ +typedef u8 UINT8; /**< 8-bit unsigned integer */ +typedef u16 UINT16; /**< 16-bit unsigned integer */ +typedef u32 UINT32; /**< 32-bit unsigned integer */ +typedef u64 UINT64; /**< 64-bit unsigned integer */ +typedef s64 INT64; /**< 64-bit signed integer */ +typedef s16 INT16; /**< 16-bit signed integer */ +typedef s32 INT32; /**< 32-bit signed integer */ +#endif /* __ACTYPES_H__ */ + +typedef s8 INT8; /**< 8-bit signed integer */ +typedef UINT32 ULONG; /**< alias for UINT32 */ +typedef UINT16 USHORT; /**< alias for UINT16 */ +typedef UINT8 UCHAR; /**< alias for UINT8 */ +typedef UINT32 BOOL; /**< alias for UINT32 */ +typedef INT8 CHAR; /**< alias for INT8*/ +typedef void VOID; + + +/* + * Detecting the kernel version that we compiled against. + * We did not lock down specifically to any revision here. + * We do it for some specific revisions now. + */ +#if (KERNEL_VERSION(2,6,0) <= LINUX_VERSION_CODE) && \ + (KERNEL_VERSION(2,7,0) > LINUX_VERSION_CODE) + +#define IX_OSAL_OS_LINUX_VERSION_2_6 1 /* Kernel 2.6 */ +#undef IX_OSAL_OS_LINUX_VERSION_2_4 + +#if (KERNEL_VERSION(2,6,16) == LINUX_VERSION_CODE) +#define IX_OSAL_OS_LINUX_VERSION_2_6_16 1 +#endif + +#if (KERNEL_VERSION(2,6,18) == LINUX_VERSION_CODE) +#define IX_OSAL_OS_LINUX_VERSION_2_6_18 1 +#endif + +#if (KERNEL_VERSION(2,6,20) == LINUX_VERSION_CODE) +#define IX_OSAL_OS_LINUX_VERSION_2_6_20 1 +#endif + +/* Defines for version greater than a specific minor ver number */ +#if (KERNEL_VERSION(2,6,18) <= LINUX_VERSION_CODE) +#define IX_OSAL_OS_LINUX_VER_GT_2_6_18 1 +#endif + +#if (KERNEL_VERSION(2,6,20) <= LINUX_VERSION_CODE) +#define IX_OSAL_OS_LINUX_VER_GT_2_6_20 1 +#endif + +#elif (KERNEL_VERSION(2,4,0) <= LINUX_VERSION_CODE) && \ + (KERNEL_VERSION(2,5,0) > LINUX_VERSION_CODE) + +#define IX_OSAL_OS_LINUX_VERSION_2_4 1 /* Kernel 2.4 */ +#undef IX_OSAL_OS_LINUX_VERSION_2_6 + +#else /* KERNEL_VERSION */ +#error "Non supported Linux kernel version" +#endif /* KERNEL_VERSION */ + + +/* Default stack limit is 10 KB */ +#define IX_OSAL_OS_THREAD_DEFAULT_STACK_SIZE (10240) + +/* Maximum stack limit is 32 MB */ +#define IX_OSAL_OS_THREAD_MAX_STACK_SIZE (33554432) /* 32 MBytes */ + +/* Thread minimum priority */ +#define IX_OSAL_OS_MIN_THREAD_PRIORITY (0) + +/* Default thread priority */ +#define IX_OSAL_OS_DEFAULT_THREAD_PRIORITY (MAX_RT_PRIO-1) + +/* Thread maximum priority (0 - 255). 0 - highest priority */ +#define IX_OSAL_OS_MAX_THREAD_PRIORITY (MAX_PRIO) + +/* Maximum input value for priority */ +#define IX_OSAL_PRIO_SET_MAX_VALID_VAL (255) + +/* Maximum supported priority value in ThreadPrioritySet */ +#define IX_OSAL_PRIO_SET_MAX_VAL (39) + +/* Difference of actual nice value and input value */ +#define IX_OSAL_NICE_VAL_DIFFERENCE (20) + +/* Default scheduling policy */ +#define IX_OSAL_OS_THREAD_DEFAULT_SCHED_POLICY SCHED_RR + +/* Thread scheduling policy - Round Robin */ +#define IX_OSAL_THREAD_SCHED_RR SCHED_RR + +/* Thread scheduling policy - FiFo */ +#define IX_OSAL_THREAD_SCHED_FIFO SCHED_FIFO + + /* Thread scheduling policy - Other */ +#define IX_OSAL_THREAD_SCHED_OTHER SCHED_OTHER + +#define IX_OSAL_OS_WAIT_FOREVER (-1) +#define IX_OSAL_OS_WAIT_NONE 0 +#undef IX_OSAL_ATTRIBUTE_PACKED +#define IX_OSAL_ATTRIBUTE_PACKED __attribute__((__packed__)) + + +#ifdef IX_OSAL_OS_LINUX_VERSION_2_6 + +/* Thread handle is a task_struct pointer */ +typedef struct task_struct *IxOsalOsThread; + +#else /* !KERNEL_VERSION 2.6 */ + +/* Thread handle is an int type */ +typedef int IxOsalOsThread; + +#endif /* IX_OSAL_OS_LINUX_VERSION_2_6 */ + + +/* Semaphore handle */ +typedef struct semaphore *IxOsalOsSemaphore; + +/* Mutex handle */ +typedef struct semaphore *IxOsalOsMutex; + +#ifdef IX_OSAL_OEM_FAST_MUTEX + +typedef int IxOsalOsFastMutex; + +#else /* ! IX_OSAL_OEM_FAST_MUTEX -> Generic */ + +/* + * Fast mutex handle - fast mutex operations are implemented + * using the linux atomic instructions. + */ +typedef atomic_t IxOsalOsFastMutex; + +#endif /* IX_OSAL_OEM_FAST_MUTEX */ + +#ifdef ENABLE_SPINLOCK +typedef spinlock_t IxOsalOsSpinLock; +#endif /* ENABLE_SPINLOCK */ + + +typedef struct +{ + UINT32 msgLen; /* Message Length */ + UINT32 maxNumMsg; /* max number of msg in the queue */ + UINT32 currNumMsg; /* current number of msg in the queue */ + INT8 msgKey; /* key used to generate the queue */ + INT8 queueId; /* queue ID */ + +} IxOsalOsMessageQueue; + +typedef atomic_t IxOsalOsAtomic; + +/* Dummy typedef for OsThreadAttr - This is not used in linux currently. + This needs to be defined appropriately when it is planned to be used */ +typedef int IxOsalOsThreadAttr; + +typedef void (*voidFnVoidPtr) (void *); +typedef void (*voidFnVoid) (void); + +#ifdef USE_NATIVE_OS_TIMER_API +typedef void (*voidFnULongPtr)(unsigned long); + +typedef struct +{ + BOOL inUse; /* status of timer active or cancel */ + BOOL isRepeating; /* Timer is repeating type */ + voidFnVoidPtr callback; /* Function to be called back after period ms */ + UINT32 priority; /* priority */ + void *callbackParam; /* parameter to be passed to callback function*/ + UINT32 period; /* period in mili seconds */ + struct timer_list timer; /* Linux OS timer struct */ +} IxOsalTimerRec; + +typedef IxOsalTimerRec *IxOsalOsTimer; +#endif /* USE_NATIVE_OS_TIMER_API */ + +/* + * On Linux kmalloc can allocat a max of 128 KB + */ +#define IX_OSAL_MAX_KMALLOC_MEM (1024 * 128) + +/* + * linux data struct to store the information on the + * memory allocated. This structure is stored at the beginning of + * the allocated chunck of memory + * size is the no of byte passed to the memory allocation functions + * mSize is the real size of the memory required to the OS + * + * +--------------------------+--------------------------------+ + * | ixOsalMemAllocInfoStruct | memory returned to user (size) | + * +--------------------------+--------------------------------+ + * ^ ^ + * mAllocMemPtr Ptr returned to the caller of MemAlloc* + * + */ +typedef struct _sMemAllocInfo +{ + VOID* mAllocMemPtr; /* memory addr returned by the kernel */ + UINT32 mSize; /* allocated size */ + +} ixOsalMemAllocInfoStruct; + +#endif /* IxOsalOsTypes_H */ diff --git a/Acceleration/library/icp_utils/OSAL/common/os/linux/include/core/IxOsalOsUtilitySymbols.h b/Acceleration/library/icp_utils/OSAL/common/os/linux/include/core/IxOsalOsUtilitySymbols.h new file mode 100644 index 0000000..97aa2b3 --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/os/linux/include/core/IxOsalOsUtilitySymbols.h @@ -0,0 +1,71 @@ +/** + * @file IxOsalOsUtilitySymbols.h + * + * @brief + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +#ifndef IxOsalOsUtilitySymbols_H +#define IxOsalOsUtilitySymbols_H + +#endif /* IxOsalOsUtilitySymbols_H */ diff --git a/Acceleration/library/icp_utils/OSAL/common/os/linux/include/modules/bufferMgt/IxOsalOsBufferMgt.h b/Acceleration/library/icp_utils/OSAL/common/os/linux/include/modules/bufferMgt/IxOsalOsBufferMgt.h new file mode 100644 index 0000000..390e4ed --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/os/linux/include/modules/bufferMgt/IxOsalOsBufferMgt.h @@ -0,0 +1,122 @@ +/** + * @file IxOsalOsBufferMgt.h + * + * @brief os-specific buffer management module definitions. + * + * Design Notes: + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + + +#ifndef IX_OSAL_OS_BUFFER_MGT_H +#define IX_OSAL_OS_BUFFER_MGT_H + +#include <linux/skbuff.h> +/* + * Use the defaul bufferMgt provided by OSAL + * framework. + */ +#define IX_OSAL_USE_DEFAULT_BUFFER_MGT + +#include "IxOsalBufferMgtDefault.h" + +/* Linux choose to allocate buffers + * separately by the defining IX_OSAL_BUFFER_ALLOC_SEPARATELY. + * As it has a relatively small page limit when allocating a + * continuous block. + */ +#define IX_OSAL_BUFFER_ALLOC_SEPARATELY + +/* Define os-specific buffer macros to access subfields */ +#define IX_OSAL_OSBUF_MDATA(osBufPtr) \ + ( ((struct sk_buff *) osBufPtr)->data ) + +#define IX_OSAL_OSBUF_MLEN(osBufPtr) \ + ( ((struct sk_buff *) osBufPtr)->len ) + +/* Conversion utilities for linux-specific buffers */ +#define IX_OSAL_OS_CONVERT_OSBUF_TO_ACPBUF( osBufPtr, acpBufPtr) \ + { \ + IX_OSAL_MBUF_OSBUF_PTR( (IX_OSAL_MBUF *) acpBufPtr) = (void *) osBufPtr; \ + IX_OSAL_MBUF_MDATA((IX_OSAL_MBUF *) acpBufPtr) = IX_OSAL_OSBUF_MDATA(osBufPtr); \ + IX_OSAL_MBUF_PKT_LEN((IX_OSAL_MBUF *) acpBufPtr) = IX_OSAL_OSBUF_MLEN(osBufPtr); \ + IX_OSAL_MBUF_MLEN((IX_OSAL_MBUF *) acpBufPtr) = IX_OSAL_OSBUF_MLEN(osBufPtr); \ + } + +#define IX_OSAL_OS_CONVERT_ACPBUF_TO_OSBUF( acpBufPtr, osBufPtr) \ + { \ + if (acpBufPtr == NULL) \ + { /* Do nothing */ } \ + else \ + { \ + (struct sk_buff *) osBufPtr = (struct sk_buff *) IX_OSAL_MBUF_OSBUF_PTR((IX_OSAL_MBUF *) acpBufPtr); \ + if (osBufPtr == NULL) \ + { /* Do nothing */ } \ + else \ + { \ + IX_OSAL_OSBUF_MLEN(osBufPtr) =IX_OSAL_MBUF_PKT_LEN((IX_OSAL_MBUF *) acpBufPtr); \ + } \ + } \ + } + + +#endif /* #define IX_OSAL_OS_BUFFER_MGT_H */ diff --git a/Acceleration/library/icp_utils/OSAL/common/os/linux/include/modules/ddk/IxOsalOsDdk.h b/Acceleration/library/icp_utils/OSAL/common/os/linux/include/modules/ddk/IxOsalOsDdk.h new file mode 100644 index 0000000..1f6b6e7 --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/os/linux/include/modules/ddk/IxOsalOsDdk.h @@ -0,0 +1,104 @@ +/** + * @file IxOsalOsDdk.h + * + * @brief Linux-specific OS Ddk definitions + * + * Design Notes: + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +#ifndef IxOsalOsDdk_H +#define IxOsalOsDdk_H + +/* + * Below macros and defines are used for OSAL CacheMMU APIs . + */ + +/* + * Definition of what is deemed a small memory allocation request. + * Memory requests for up to this size are deemed small and are + * handled differently from larger memory requests + */ +#define IX_OSAL_OS_SMALL_MEM_SIZE (512 - 32) + +/* Arbitrary numbers to detect memory corruption */ +#define IX_OSAL_OS_MAGIC_ALLOC_NUMBER (0xBABEFACE) +#define IX_OSAL_OS_MAGIC_DEALLOC_NUMBER (0xCAFEBABE) + +/* Number of information words maintained behind the user buffer */ +#define IX_OSAL_OS_NUM_INFO_WORDS (4) + +/* Number of bytes per word */ +#define IX_OSAL_OS_BYTES_PER_WORD (4) + +/* Index of information words maintained behind user buffer */ +#define IX_OSAL_OS_ORDER_OF_PAGES_INDEX (-4) +#define IX_OSAL_OS_MYPTR_INDEX (-3) +#define IX_OSAL_OS_REQUESTED_SIZE_INDEX (-2) +#define IX_OSAL_OS_MAGIC_NUMBER_INDEX (-1) + +/* Macro to round up a size to a multiple of a cache line */ +#define IX_OSAL_OS_CL_ROUND_UP(s) \ + (((s) + (IX_OSAL_CACHE_LINE_SIZE - 1)) & ~(IX_OSAL_CACHE_LINE_SIZE - 1)) + + +#endif /* IxOsalOsDdk_H */ diff --git a/Acceleration/library/icp_utils/OSAL/common/os/linux/include/modules/ioMem/IxOsalOsIoMem.h b/Acceleration/library/icp_utils/OSAL/common/os/linux/include/modules/ioMem/IxOsalOsIoMem.h new file mode 100644 index 0000000..761e9b5 --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/os/linux/include/modules/ioMem/IxOsalOsIoMem.h @@ -0,0 +1,76 @@ +/** + * @file IxOsalOsIoMem.h + * + * @brief Linux-specific OS IO/Mem definitions + * + * Design Notes: + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +#ifndef IxOsalOsIoMem_H +#define IxOsalOsIoMem_H + +/* + * Place holder. + */ + +#endif /* IxOsalOsIoMem_H */ diff --git a/Acceleration/library/icp_utils/OSAL/common/os/linux/make/macros.mk b/Acceleration/library/icp_utils/OSAL/common/os/linux/make/macros.mk new file mode 100644 index 0000000..5a20a2e --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/os/linux/make/macros.mk @@ -0,0 +1,106 @@ +# +# Macro definitions for os-specific makefile +# +# +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# Contact Information: +# Intel Corporation +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# +# +# NOTE! +# This file currently depends on the following environment variables: +# - HARDHAT_BASE +# - IX_TARGET +# - linuxbe_KERNEL_DIR or linuxle_KERNEL_DIR + + +##################################################################### +# Determine the build host OS +# +# Only Linux (and partially Cygwin) are currently supported for Linux builds + +IX_OSAL_MK_HOST_OS := $(OSTYPE) + +# If we don't have a valid OS name, try to use the Unix uname command +# to find it. +ifneq ($(IX_OSAL_MK_HOST_OS), linux) + IX_OSAL_MK_HOST_OS := $(shell uname) + IX_OSAL_MK_HOST_OS := $(subst Linux,linux,$(IX_OSAL_MK_HOST_OS)) +# We do not check for 'cygwin' here, as a windows box will often have +# a cygwin "uname" on its PATH even when not running in a true cygwin +# environment. We must rely on the OSTYPE environment variable to tell +# us if we're in a true cygwin environment. +endif + + +################################################################ +# Linux Compiler & linker commands + +LD := $(COMPILE_PREFIX)ld +CC := $(COMPILE_PREFIX)gcc +AR := $(COMPILE_PREFIX)ar + +################################################################ +# Compiler & linker options + +# Compiler flags + +# Linux linker flags +LDFLAGS := -r +MAKE_DEP_FLAG := -M + diff --git a/Acceleration/library/icp_utils/OSAL/common/os/linux/src/component.mk b/Acceleration/library/icp_utils/OSAL/common/os/linux/src/component.mk new file mode 100644 index 0000000..bd85f4b --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/os/linux/src/component.mk @@ -0,0 +1,61 @@ +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# Contact Information: +# Intel Corporation +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# +# Place Holder + diff --git a/Acceleration/library/icp_utils/OSAL/common/os/linux/src/core/IxOsalOsAtomic.c b/Acceleration/library/icp_utils/OSAL/common/os/linux/src/core/IxOsalOsAtomic.c new file mode 100644 index 0000000..674d375 --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/os/linux/src/core/IxOsalOsAtomic.c @@ -0,0 +1,271 @@ +/** + * @file IxOsalOsAtomic.c (linux) + * + * @brief OS-specific Atomic API's implementation. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ +#include "IxOsal.h" +#include <asm/atomic.h> + + + +/** + * @ingroup IxOsal + * + * @brief Atomically read the value of atomic variable + * + * @param atomicVar (in) - atomic variable + * + * Atomically reads the value of atomicVar to the outValue + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return atomicVar value + */ + +PUBLIC UINT32 +ixOsalAtomicGet(IxOsalAtomic *atomicVar) +{ + return (( UINT32 )atomic_read( atomicVar )); +} + +/** + * @ingroup IxOsal + * + * @brief Atomically set the value of atomic variable + * + * @param inValue (in) - atomic variable to be set equal to inValue + * + * @param atomicVar (out) - atomic variable + * + * Atomically sets the value of IxOsalAtomicVar to the value given + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return none + */ + +PUBLIC void +ixOsalAtomicSet(UINT32 inValue, IxOsalAtomic *atomicVar) +{ + atomic_set(atomicVar,inValue); +} + +/** + * @ingroup IxOsal + * + * @brief add the value to atomic variable + * + * @param inValue (in) - value to be added to the atomic variable + * + * @param atomicVar (in & out) - atomic variable + * + * Atomically adds the value of inValue to the IxOsalAtomicVar + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return none + */ + +PUBLIC void +ixOsalAtomicAdd(UINT32 inValue, IxOsalAtomic *atomicVar) +{ + atomic_add((int)inValue, atomicVar); +} + +/** + * @ingroup IxOsal + * + * @brief subtract the value from atomic variable + * + * @param inValue (in) - atomic variable value to be subtracted by value + * + * @param atomicVar (in & out) - atomic variable + * + * Atomically subtracts the value of IxOsalAtomicVar by inValue + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return none + */ + +PUBLIC void +ixOsalAtomicSub(UINT32 inValue, IxOsalAtomic *atomicVar) +{ + atomic_sub((int)inValue, atomicVar); +} + +/** + * @ingroup IxOsal + * + * @brief subtract the value from atomic variable and test result + * + * @param inValue (in) - value to be subtracted from the atomic variable + * + * @param atomicVar (in & out) - atomic variable + * + * Atomically subtracts the IxOsalAtomicVar value by inValue and + * test the result. + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return TRUE if the result is zero or FALSE for other cases. + */ + +PUBLIC IX_STATUS +ixOsalAtomicSubAndTest(UINT32 inValue, IxOsalAtomic *atomicVar) +{ + return (IX_STATUS)(atomic_sub_and_test((int)inValue, atomicVar)); +} + +/** + * @ingroup IxOsal + * + * @brief increment value of atomic variable by 1 + * + * @param atomicVar (in & out) - atomic variable + * + * Atomically increments the value of IxOsalAtomicVar by 1. + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return none + */ + +PUBLIC void +ixOsalAtomicInc(IxOsalAtomic *atomicVar) +{ + atomic_inc(atomicVar); +} + +/** + * @ingroup IxOsal + * + * @brief decrement value of atomic variable by 1 + * + * @param atomicVar (out) - atomic variable + * + * Atomically decrements the value of IxOsalAtomicVar by 1. + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return none + */ + +PUBLIC void +ixOsalAtomicDec(IxOsalAtomic *atomicVar) +{ + atomic_dec(atomicVar); +} + +/** + * @ingroup IxOsal + * + * @brief decrement atomic variable value by 1 and test result + * + * @param atomicVar (in & out) - atomic variable + * + * Atomically decrements the value of IxOsalAtomicVar by 1 and test + * result for zero. + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return TRUE if the result is zero or FALSE otherwise + */ + +PUBLIC IX_STATUS +ixOsalAtomicDecAndTest(IxOsalAtomic *atomicVar) +{ + return (IX_STATUS)(atomic_dec_and_test(atomicVar)); +} + +/** + * @ingroup IxOsal + * + * @brief increment atomic variable by 1 and test result + * + * @param atomicVar (in & out) - atomic variable + * + * Atomically increments the value of IxOsalAtomicVar by 1 and test + * result for zero. + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return TRUE if the result is zero or FALSE otherwise + */ + +PUBLIC IX_STATUS +ixOsalAtomicIncAndTest(IxOsalAtomic *atomicVar) +{ + return (IX_STATUS)(atomic_inc_and_test(atomicVar)); +} + diff --git a/Acceleration/library/icp_utils/OSAL/common/os/linux/src/core/IxOsalOsMemBarrier.c b/Acceleration/library/icp_utils/OSAL/common/os/linux/src/core/IxOsalOsMemBarrier.c new file mode 100644 index 0000000..217134f --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/os/linux/src/core/IxOsalOsMemBarrier.c @@ -0,0 +1,135 @@ +/** + * @file IxOsalOsMemBarrier.c (linux) + * + * @brief OS-specific Memory Barrier API's implementation. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ +#include "IxOsal.h" + +#include <asm/system.h> + + + +/** + * @ingroup IxOsal + * + * @brief memory barrier which orders both memory read and writes + * + * @param none + * + * memory barrier that orders both memory read and writes + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return none + */ + +PUBLIC void +ixOsalMemBarrier(void) +{ + mb(); +} + +/** + * @ingroup IxOsal + * + * @brief memory barrier which orders memory reads + * + * @param none + * + * memory barrier that orders memory reads + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return none + */ + +PUBLIC void +ixOsalReadMemBarrier(void) +{ + rmb(); +} + +/** + * @ingroup IxOsal + * + * @brief memory barrier which orders memory writes + * + * @param none + * + * memory barrier that orders memory writes + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return none + */ + +PUBLIC void +ixOsalWriteMemBarrier(void) +{ + wmb(); +} + diff --git a/Acceleration/library/icp_utils/OSAL/common/os/linux/src/core/IxOsalOsMsgQ.c b/Acceleration/library/icp_utils/OSAL/common/os/linux/src/core/IxOsalOsMsgQ.c new file mode 100644 index 0000000..22a69bb --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/os/linux/src/core/IxOsalOsMsgQ.c @@ -0,0 +1,143 @@ +/** + * @file IxOsalOsMsgQ.c (linux) + * + * @brief OS-specific Message Queue implementation. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ +#include "IxOsal.h" + +#include <linux/linkage.h> +#include <linux/spinlock.h> +#include <linux/ipc.h> +#include <linux/msg.h> +#include <linux/interrupt.h> + + + +/******************************* + * Public functions + *******************************/ +PUBLIC IX_STATUS +ixOsalMessageQueueCreate (IxOsalMessageQueue * queue, + UINT32 msgCount, UINT32 msgLen) +{ + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, + IX_OSAL_LOG_DEV_STDOUT, + "ixOsalMessageQueueCreate(): Not implemented in Linux \n", 0, 0, 0, 0, + 0, 0); + return IX_SUCCESS; +} + +PUBLIC IX_STATUS +ixOsalSyncMessageQueueCreate (IxOsalMessageQueue * msgQueue, + UINT32 msgCount, UINT32 msgLen) +{ + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, + IX_OSAL_LOG_DEV_STDOUT, + "ixOsalSyncMessageQueueCreate():" + "Not implemented in Linux \n", 0, 0, 0, + 0, 0, 0); + return IX_SUCCESS; +} + +PUBLIC IX_STATUS +ixOsalMessageQueueDelete (IxOsalMessageQueue * queue) +{ + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, + IX_OSAL_LOG_DEV_STDOUT, + "ixOsalMessageQueueDelete(): Not implemented in Linux \n", 0, 0, 0, 0, + 0, 0); + return IX_SUCCESS; +} + +PUBLIC IX_STATUS +ixOsalMessageQueueSend (IxOsalMessageQueue * queue, UINT8 * message) +{ + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, + IX_OSAL_LOG_DEV_STDOUT, + "ixOsalMessageQueueSend(): Not implemented in Linux \n", 0, 0, 0, 0, + 0, 0); + return IX_SUCCESS; +} + +PUBLIC IX_STATUS +ixOsalMessageQueueReceive (IxOsalMessageQueue * queue, UINT8 * message) +{ + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, + IX_OSAL_LOG_DEV_STDOUT, + "ixOsalMessageQueueReceive(): Not implemented in Linux \n", 0, 0, 0, + 0, 0, 0); + return IX_SUCCESS; +} + +PUBLIC IX_STATUS +ixOsalSyncMessageQueueReceive (IxOsalMessageQueue * queue, UINT8 * message, + INT32 timeout) +{ + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, + IX_OSAL_LOG_DEV_STDOUT, + "ixOsalSyncMessageQueueReceive():" + "Not implemented in Linux \n", 0, 0, 0, + 0, 0, 0); + return IX_SUCCESS; +} diff --git a/Acceleration/library/icp_utils/OSAL/common/os/linux/src/core/IxOsalOsSemaphore.c b/Acceleration/library/icp_utils/OSAL/common/os/linux/src/core/IxOsalOsSemaphore.c new file mode 100644 index 0000000..5b55a5a --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/os/linux/src/core/IxOsalOsSemaphore.c @@ -0,0 +1,607 @@ +/** + * @file IxOsalOsSemaphore.c (linux) + * + * @brief Implementation for semaphore and mutex. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ +#include "IxOsal.h" +#include <linux/slab.h> +#include <linux/version.h> +#include <linux/semaphore.h> +#include <asm/atomic.h> + + + +#ifdef IX_OSAL_OS_LINUX_VERSION_2_6 + +#include <linux/hardirq.h> + +#else /* !KERNEL VERSION 2.6 */ + +#include <asm/hardirq.h> + +#endif /* KERNEL_VERSION */ + + +/* Define a large number */ +#define IX_OSAL_MAX_LONG (0x7FFFFFFF) + +/* Max timeout in MS, used to guard against possible overflow */ +#define IX_OSAL_MAX_TIMEOUT_MS (IX_OSAL_MAX_LONG/HZ) + + +PUBLIC IX_STATUS +ixOsalSemaphoreInit (IxOsalSemaphore * sid, UINT32 start_value) +{ + + if (NULL == sid) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, + IX_OSAL_LOG_DEV_STDOUT, + "ixOsalSemaphoreInit: NULL semaphore pointer \n", + 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + + *sid = kmalloc (sizeof (struct semaphore), GFP_KERNEL); + if (!(*sid)) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, + IX_OSAL_LOG_DEV_STDOUT, + "ixOsalSemaphoreInit: fail to allocate for semaphore \n", + 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + + sema_init (*sid, start_value); + + return IX_SUCCESS; +} + +/** + * DESCRIPTION: If the semaphore is 'empty', the calling thread is blocked. + * If the semaphore is 'full', it is taken and control is returned + * to the caller. If the time indicated in 'timeout' is reached, + * the thread will unblock and return an error indication. If the + * timeout is set to 'IX_OSAL_WAIT_NONE', the thread will never block; + * if it is set to 'IX_OSAL_WAIT_FOREVER', the thread will block until + * the semaphore is available. + * + * + */ + + +PUBLIC IX_STATUS +ixOsalSemaphoreWait (IxOsalOsSemaphore * sid, INT32 timeout) +{ + + IX_STATUS ixStatus = IX_SUCCESS; + unsigned long timeoutTime; + + if (sid == NULL) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, + IX_OSAL_LOG_DEV_STDOUT, + "ixOsalSemaphoreWait(): NULL semaphore handle \n", + 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + + /* + * Guard against illegal timeout values + */ + if ((timeout < 0) && (timeout != IX_OSAL_WAIT_FOREVER)) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, + IX_OSAL_LOG_DEV_STDOUT, + "ixOsalSemaphoreWait(): illegal timeout value \n", + 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + + if (timeout == IX_OSAL_WAIT_FOREVER) + { + down (*sid); + } + else if (timeout == IX_OSAL_WAIT_NONE) + { + if (down_trylock (*sid)) + { + ixStatus = IX_FAIL; + } + } + else if (timeout > IX_OSAL_MAX_TIMEOUT_MS) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, + "ixOsalSemaphoreWait(): use a smaller timeout value to avoid \ + overflow \n", 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + else + { + /* Convert timeout in milliseconds to HZ */ + timeoutTime = jiffies + (timeout * HZ) /IX_OSAL_THOUSAND; + while (1) + { + if (!down_trylock (*sid)) + { + break; + } + else + { + if (time_after(jiffies, timeoutTime)) + { + ixStatus = IX_FAIL; + break; + } + } + /* Switch to next running process instantly */ + set_current_state((long)TASK_INTERRUPTIBLE); + schedule_timeout(1); + + } /* End of while loop */ + } /* End of if */ + + return ixStatus; + +} + +/* + * Attempt to get semaphore, return immediately, + * no error info because users expect some failures + * when using this API. + */ +PUBLIC IX_STATUS +ixOsalSemaphoreTryWait (IxOsalSemaphore * sid) +{ + if (sid == NULL) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, + IX_OSAL_LOG_DEV_STDOUT, + "ixOsalSemaphoreTryWait(): NULL semaphore handle \n", + 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + if (down_trylock (*sid)) + { + return IX_FAIL; + } + return IX_SUCCESS; +} + +/** + * + * DESCRIPTION: This function causes the next available thread in the pend queue + * to be unblocked. If no thread is pending on this semaphore, the + * semaphore becomes 'full'. + */ +PUBLIC IX_STATUS +ixOsalSemaphorePost (IxOsalSemaphore * sid) +{ + if (sid == NULL) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, + IX_OSAL_LOG_DEV_STDOUT, + "ixOsalSemaphorePost(): NULL semaphore handle \n", + 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + up (*sid); + return IX_SUCCESS; +} + +PUBLIC IX_STATUS +ixOsalSemaphoreDestroy (IxOsalSemaphore * sid) +{ + if (sid == NULL) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, + "ixOsalSemaphoreDestroy(): NULL semaphore handle \n", + 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + + kfree (*sid); + *sid = 0; + + return IX_SUCCESS; +} + +/**************************** + * Mutex + ****************************/ + +PUBLIC IX_STATUS +ixOsalMutexInit (IxOsalMutex * mutex) +{ + if (mutex == NULL) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, + "ixOsalMutexInit(): NULL mutex handle \n", 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + *mutex =(struct semaphore *) kmalloc(sizeof(struct semaphore), GFP_KERNEL); + if (*mutex == NULL) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, + IX_OSAL_LOG_DEV_STDOUT, + "ixOsalMutexInit(): Fail to allocate for mutex \n", + 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + + init_MUTEX (*mutex); + return IX_SUCCESS; +} + +PUBLIC IX_STATUS +ixOsalMutexLock (IxOsalMutex * mutex, INT32 timeout) +{ + unsigned long timeoutTime; + + if (mutex == NULL) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, + IX_OSAL_LOG_DEV_STDOUT, + "ixOsalMutexLock(): NULL mutex handle \n", 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + + if ((timeout < 0) && (timeout != IX_OSAL_WAIT_FOREVER)) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, + IX_OSAL_LOG_DEV_STDOUT, + "ixOsalMutexLock(): Illegal timeout value \n", 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + + if (timeout == IX_OSAL_WAIT_FOREVER) + { + down (*mutex); + } + else if (timeout == IX_OSAL_WAIT_NONE) + { + if (down_trylock (*mutex)) + { + return IX_FAIL; + } + } + else if (timeout > IX_OSAL_MAX_TIMEOUT_MS) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, + IX_OSAL_LOG_DEV_STDOUT, + "ixOsalMutexLock(): use smaller timeout value to avoid overflow \n", + 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + else + { + timeoutTime = jiffies + (timeout * HZ) / IX_OSAL_THOUSAND; + while (1) + { + if (!down_trylock (*mutex)) + { + break; + } + else + { + if (time_after(jiffies, timeoutTime)) + { + return IX_FAIL; + } + } + + /* Switch to next running process if not in atomic state */ + if (!in_atomic()) + { + set_current_state((long)TASK_INTERRUPTIBLE); + schedule_timeout(1); + } + } /* End of while loop */ + } /* End of if */ + return IX_SUCCESS; +} + +PUBLIC IX_STATUS +ixOsalMutexUnlock (IxOsalMutex * mutex) +{ + if (mutex == NULL) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, + IX_OSAL_LOG_DEV_STDOUT, + "ixOsalMutexUnlock(): NULL mutex handle \n", 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + + up (*mutex); + return IX_SUCCESS; +} + +/* + * Attempt to get mutex, return immediately, + * no error info because users expect some failures + * when using this API. + */ +PUBLIC IX_STATUS +ixOsalMutexTryLock (IxOsalMutex * mutex) +{ + if (mutex == NULL) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, + IX_OSAL_LOG_DEV_STDOUT, + "ixOsalMutexTryLock(): NULL mutex handle \n", 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + + if (down_trylock (*mutex)) + { + return IX_FAIL; + } + + return IX_SUCCESS; +} + +PUBLIC IX_STATUS +ixOsalMutexDestroy (IxOsalMutex * mutex) +{ + if (mutex == NULL) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, + IX_OSAL_LOG_DEV_STDOUT, + "ixOsalMutexDestroy(): NULL mutex handle \n", 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + kfree (*mutex); + *mutex = 0; + + return IX_SUCCESS; +} + + + +#ifdef IX_OSAL_OEM_FAST_MUTEX + +PUBLIC IX_STATUS +ixOsalFastMutexInit (IxOsalFastMutex * mutex) +{ + return IX_OSAL_OEM_FAST_MUTEX_INIT (mutex); +} + +PUBLIC IX_STATUS +ixOsalFastMutexTryLock(IxOsalFastMutex *mutex) +{ + return IX_OSAL_OEM_FAST_MUTEX_TRYLOCK(mutex); +} + +PUBLIC IX_STATUS +ixOsalFastMutexUnlock (IxOsalFastMutex * mutex) +{ + if (mutex == NULL) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, + IX_OSAL_LOG_DEV_STDOUT, + "ixOsalFastMutexUnlock(): NULL mutex handle \n", + 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + return IX_OSAL_OEM_FAST_MUTEX_UNLOCK(mutex); +} + +PUBLIC IX_STATUS +ixOsalFastMutexDestroy (IxOsalFastMutex * mutex) +{ + if (mutex == NULL) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, + IX_OSAL_LOG_DEV_STDOUT, + "ixOsalFastMutexDestroy(): NULL mutex handle \n", + 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + + return IX_OSAL_OEM_FAST_MUTEX_DESTROY(mutex); +} + +#else /* ! OEM_FAST_MUTEX */ + +PUBLIC IX_STATUS +ixOsalFastMutexInit (IxOsalFastMutex * mutex) +{ + if (mutex) + { + atomic_set(mutex,1); + return IX_SUCCESS; + } + else + { + return IX_FAIL; + } +} + +PUBLIC IX_STATUS +ixOsalFastMutexTryLock(IxOsalFastMutex *mutex) +{ + if (atomic_dec_and_test(mutex)) + { + return IX_SUCCESS; + } + else + { + atomic_inc(mutex); + return IX_FAIL; + } +} + +PUBLIC IX_STATUS +ixOsalFastMutexUnlock (IxOsalFastMutex * mutex) +{ + if (mutex) + { + atomic_inc(mutex); + return IX_SUCCESS; + } + else + { + return IX_FAIL; + } +} + +PUBLIC IX_STATUS +ixOsalFastMutexDestroy (IxOsalFastMutex * mutex) +{ + atomic_set(mutex,1); + return IX_SUCCESS; +} + +#endif /* IX_OSAL_OEM_FAST_MUTEX */ + + +PUBLIC +IX_STATUS ixOsalSemaphoreDownTimeout( + IxOsalSemaphore *sid, + INT32 timeout) +{ + IX_STATUS ixStatus; + ixStatus = ixOsalSemaphoreWait (sid, timeout); + return ixStatus; + +} /* ixOsalSemaphoreDownTimeout */ + + + +PUBLIC +IX_STATUS ixOsalSemaphoreWaitInterruptible( + IxOsalSemaphore *sid, + INT32 timeout) +{ + IX_STATUS ixStatus = IX_SUCCESS; + unsigned long timeoutTime; + + if (sid == NULL) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, + "ixOsalSemaphoreWaitInterruptible(): NULL handle \n", + 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + + /* + * Guard against illegal timeout values + */ + if ((timeout < 0) && (timeout != IX_OSAL_WAIT_FOREVER)) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, + "ixOsalSemaphoreWaitInterruptible: illegal timeout value\n", + 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + + if (timeout == IX_OSAL_WAIT_FOREVER) + { + // stupid morons wrote that code, what can I do? + if (down_interruptible(*sid)) + return IX_FAIL; // well i can do that, this might probably be less harmful than the original "i don't care" + // approach, and less stupid than a busy waiting approach, but anyway i don't really give a + // fuck about that absurd amount of shit + } + else if (timeout == IX_OSAL_WAIT_NONE) + { + if (down_trylock (*sid)) + { + ixStatus = IX_FAIL; + } + } + else if (timeout > IX_OSAL_MAX_TIMEOUT_MS) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, + "ixOsalSemaphoreWaitInterruptible():use smaller timeout \ + value to avoid overflow \n", 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + else + { + /* Convert timeout in milliseconds to HZ */ + timeoutTime = jiffies + (timeout * HZ) /IX_OSAL_THOUSAND; + while (1) + { + if (!down_trylock (*sid)) + { + break; + } + else + { + if (time_after(jiffies, timeoutTime)) + { + ixStatus = IX_FAIL; + break; + } + } + /* Switch to next running process instantly */ + set_current_state((long)TASK_INTERRUPTIBLE); + schedule_timeout(1); + + } /* End of while loop */ + } /* End of if */ + + return ixStatus; + +} /* ixOsalSemaphoreWaitInterruptible */ diff --git a/Acceleration/library/icp_utils/OSAL/common/os/linux/src/core/IxOsalOsServices.c b/Acceleration/library/icp_utils/OSAL/common/os/linux/src/core/IxOsalOsServices.c new file mode 100644 index 0000000..db99c48 --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/os/linux/src/core/IxOsalOsServices.c @@ -0,0 +1,586 @@ +/** + * @file IxOsalOsServices.c (linux) + * + * @brief Implementation for Mem and Sleep. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ +#include "IxOsal.h" +#include "IxOsalOsTypes.h" + +#include <linux/version.h> + +#include <linux/delay.h> +#include <linux/kernel.h> +#include <linux/time.h> +#include <linux/sched.h> +#include <linux/slab.h> + +#include <linux/mm.h> +#include <linux/mempool.h> +#include <linux/vmalloc.h> + +/* More generic include */ +#include <linux/highmem.h> +#include <asm/pgtable.h> +#include <linux/random.h> + +/* Trace Message Logging Levels */ + +static char *traceHeaders[] = { + "", + "[fatal] ", + "[error] ", + "[warning] ", + "[message] ", + "[debug1] ", + "[debug2] ", + "[debug3] ", + "[all]" +}; + +static CHAR osalModuleName[OSAL_MAX_MODULE_NAME_LENGTH] = ""; + +/* by default trace all but debug message */ +PRIVATE unsigned int ixOsalCurrLogLevel = IX_OSAL_LOG_LVL_MESSAGE; + +#define IS_VMALLOC_ADDR(addr) (((UINT32)(addr) >= VMALLOC_START) && \ + ((UINT32)(addr) < VMALLOC_END)) + +/* Maximum memory (in bytes) that can be allocated using kmalloc. + Beyond this, vmalloc is to be used to allcoate memory */ +#define IX_OSAL_MAX_KMALLOC_MEM (1024 * 128) + + +/********************* + * Log function + *********************/ + +INT32 +ixOsalLog (IxOsalLogLevel level, + IxOsalLogDevice device, + char *format, int arg1, int arg2, int arg3, int arg4, int arg5, int arg6) +{ + /* + * Return -1 for custom display devices + */ + if ((device != IX_OSAL_LOG_DEV_STDOUT) + && (device != IX_OSAL_LOG_DEV_STDERR)) + { + printk + ("ixOsalLog: only IX_OSAL_LOG_DEV_STDOUT and \ + IX_OSAL_LOG_DEV_STDERR are supported \n"); + return (IX_OSAL_LOG_ERROR); + } + + if (level <= ixOsalCurrLogLevel && level != IX_OSAL_LOG_LVL_NONE) + { + INT32 return_val; + int headerByteCount = + (level == + IX_OSAL_LOG_LVL_USER) ? 0 : printk (traceHeaders[level - 1]); + + + if ( OSAL_OS_GET_STRING_LENGTH(osalModuleName) != 0 ) + { + headerByteCount += + printk("%s :",osalModuleName); + } + headerByteCount += + printk (format, + arg1, arg2, arg3, arg4, arg5,arg6); + return_val = (INT32)headerByteCount; + return return_val; + } + else + { + /* + * Return zero byte printed + */ + return (IX_OSAL_NO_LOG); + } +} + +PUBLIC UINT32 +ixOsalLogLevelSet (UINT32 level) +{ + UINT32 oldLevel; + + /* + * Check value first + */ + if ((level < IX_OSAL_LOG_LVL_NONE) || (level > IX_OSAL_LOG_LVL_ALL)) + { + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, + IX_OSAL_LOG_DEV_STDOUT, + "ixOsalLogLevelSet: Log Level is between %d and%d \n", + IX_OSAL_LOG_LVL_NONE, IX_OSAL_LOG_LVL_ALL, 0, 0, 0, 0); + return IX_OSAL_LOG_LVL_NONE; + } + oldLevel = ixOsalCurrLogLevel; + + ixOsalCurrLogLevel = level; + + return oldLevel; +} + +/************************************** + * Task services + *************************************/ + +PUBLIC void +ixOsalBusySleep (UINT32 microseconds) +{ + udelay (microseconds); +} + +PUBLIC void +ixOsalSleep (UINT32 milliseconds) +{ + if (milliseconds != 0) + { + set_current_state((long)TASK_INTERRUPTIBLE); + schedule_timeout ((milliseconds * HZ) / IX_OSAL_THOUSAND); + } + else + { + schedule (); + } +} + +/************************************** + * Memory functions + *************************************/ + +void * +ixOsalMemAlloc (UINT32 memsize) +{ + if(memsize > IX_OSAL_MAX_KMALLOC_MEM) + { + return ( vmalloc(memsize) ); + } + + return (kmalloc (memsize, GFP_KERNEL)); +} + +void +ixOsalMemFree (void *ptr) +{ + IX_OSAL_MEM_ASSERT (ptr != NULL); + + if(IS_VMALLOC_ADDR(ptr)) + { + vfree(ptr); + return; + } + + kfree (ptr); +} + +/* + * Copy count bytes from src to dest , + * returns pointer to the dest mem zone. + */ +void * +ixOsalMemCopy (void *dest, const void *src, UINT32 count) +{ + IX_OSAL_MEM_ASSERT (dest != NULL); + IX_OSAL_MEM_ASSERT (src != NULL); + return (memcpy (dest, src, count)); +} + +/* + * Fills a memory zone with a given constant byte, + * returns pointer to the memory zone. + */ +void * +ixOsalMemSet (void *ptr, UINT8 filler, UINT32 count) +{ + IX_OSAL_MEM_ASSERT (ptr != NULL); + return (memset (ptr, filler, count)); +} + +/** + * Compares count bytes from src and dest + * returns IX_SUCCESS/IX_FAIL + */ +PUBLIC IX_STATUS ixOsalMemCmp (void *dest, void *src, UINT32 count) +{ + IX_STATUS status = IX_FAIL; + IX_OSAL_MEM_ASSERT (dest != NULL); + IX_OSAL_MEM_ASSERT (src != NULL); + if( memcmp (dest, src, count) ==0) + { + status=IX_SUCCESS; + } + return status; +} + +/***************************** + * + * Time + * + *****************************/ + +/* Retrieve current system time */ +void +ixOsalTimeGet (IxOsalTimeval * ptime) +{ + /* + * linux struct timeval has subfields: + * -- time_t (type long, second) + * -- suseconds_t ( type long, usecond) + */ + do_gettimeofday ((struct timeval *) ptime); + + /* + * Translate microsecond to nanosecond, + * second field is identical so no translation + * there. + */ + ptime->nsecs *= IX_OSAL_THOUSAND; + +} + + +PUBLIC void +ixOsalYield (void) +{ + schedule (); +} + +PUBLIC IX_STATUS +ixOsalOsNameGet (INT8* osName, INT32 maxSize) +{ + IX_STATUS status = IX_FAIL; + + /* Ensure that the input parameters are valid */ + if (osName == NULL || maxSize <= 0) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, + IX_OSAL_LOG_DEV_STDOUT, + "ixOsalOsNameGet: invalid input parameters\n", + 0, 0, 0, 0, 0, 0); + + return status; + } + + status = IX_OSAL_OEM_OS_NAME_GET(osName, maxSize); + + return status; +} + +PUBLIC IX_STATUS +ixOsalOsVersionGet(INT8* osVersion, INT32 maxSize) +{ + IX_STATUS status = IX_FAIL; + + /* Ensure that the input parameters are valid */ + if (osVersion == NULL || maxSize <= 0) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, + "ixOsalOsVersionGet: invalid input parameters\n", + 0, 0, 0, 0, 0, 0); + return status; + } + + status = IX_OSAL_OEM_OS_VERSION_GET(osVersion, maxSize); + return status; +} + + +PUBLIC +IX_STATUS ixOsalSleepTick(UINT32 sleeptime_ticks) +{ + if(sleeptime_ticks < 1) + { + schedule(); + return IX_SUCCESS; + } + else + { + set_current_state((long)TASK_UNINTERRUPTIBLE); + schedule_timeout(sleeptime_ticks); + } + + return IX_SUCCESS; +} /* ixOsalSleepTick */ + + +PUBLIC +IX_STATUS ixOsalSleepUninterruptible( + UINT32 sleeptime_ms) +{ + struct timespec value; + + if(sleeptime_ms < 1) + { + schedule(); + return IX_SUCCESS; + } + + value.tv_sec = sleeptime_ms/IX_OSAL_THOUSAND; + { + INT64 ll_sleeptime; + ll_sleeptime = (sleeptime_ms % IX_OSAL_THOUSAND) * IX_OSAL_MILLION; + ixOsalMemCopy(&value.tv_nsec, &ll_sleeptime, sizeof (value.tv_nsec)); + } + /*Block added to remove parasoft issue*/ + { + unsigned long l_sleep_time = timespec_to_jiffies(&value); + ixOsalMemCopy(&sleeptime_ms, &l_sleep_time, sizeof (UINT32)); + } + { + struct task_struct* aTask = current; + aTask->state = (long)TASK_UNINTERRUPTIBLE; + schedule_timeout(sleeptime_ms); + } + return IX_SUCCESS; +} /* ixOsalSleepUninterruptible */ + +/* + * The function allocate a chunck of memory bigger that the required size + * It then calculate the aligned ptr that should be returned to the user. + * In the memory just above the returned chunck, the funcion stores the + * structure with the memory information + * + * +---+-------------------------+------------------------------- +---+ + * |xxx|ixOsalMemAllocInfoStruct | memory returned to user (size) |xxx| + * +---+-------------------------+--------------------------------+---+ + * ^ ^ + * mAllocMemPtr Ptr returned to the caller of MemAlloc + * + */ +PUBLIC VOID * +ixOsalMemAllocAligned(UINT32 space, UINT32 size, UINT32 alignment) +{ + + VOID* ptr = NULL; + UINT32 toPadSize = 0; + UINT32 padding = 0; + VOID* pRet = NULL; + UINT32 alignment_offset = 0; + + ixOsalMemAllocInfoStruct memInfo = {0}; + + if (size == 0 || alignment < 1) + { + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "[ixOsalMemAllocAligned] size or alignment are zero \n", + size, alignment, 0, 0, 0, 0); + return NULL; + } + + if (alignment & (alignment-1)) + { + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "[ixOsalMemAllocAligned] Expecting alignment of a power " + "of two but did not get one\n", 0, 0, 0, 0, 0, 0); + return NULL; + } + + if (1 == alignment) + { + toPadSize = sizeof(ixOsalMemAllocInfoStruct); + padding = 0; + } + else if (sizeof(ixOsalMemAllocInfoStruct) > alignment) + { + toPadSize = sizeof(ixOsalMemAllocInfoStruct) + alignment; + padding = IX_OSAL_MEM_PADDING(toPadSize, alignment); + } + else + { + toPadSize = alignment; + padding = 0; + } + + memInfo.mSize = size + toPadSize + padding; + + if (memInfo.mSize > IX_OSAL_MAX_KMALLOC_MEM) + { + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "[ixOsalMemAllocAligned] Total size needed for this " + "set of size and alignment (%ld) exceeds the OS " + "limit %ld\n", memInfo.mSize, IX_OSAL_MAX_KMALLOC_MEM, + 0, 0, 0, 0); + + + return NULL; + } + + ptr = kmalloc (memInfo.mSize, GFP_KERNEL); + + if (ptr == NULL) + { + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "[ixOsalMemAllocAligned] memory allocation " + "failed %ld/%d\n", + size, alignment, 0, 0, 0, 0); + + return NULL; + } + + + alignment_offset = (UINT32)ptr % alignment; + memInfo.mAllocMemPtr = ptr; + + pRet = (VOID*) ((CHAR*)ptr + toPadSize + padding + alignment_offset); + memcpy((VOID*)((CHAR*)pRet - sizeof(ixOsalMemAllocInfoStruct)), + (VOID*)(&memInfo), + sizeof(ixOsalMemAllocInfoStruct)); + + return pRet; + +} + +VOID +ixOsalMemAlignedFree (VOID *ptr, UINT32 size) +{ + ixOsalMemAllocInfoStruct *memInfo = NULL; + + memInfo = (ixOsalMemAllocInfoStruct *)((CHAR *)ptr - + sizeof(ixOsalMemAllocInfoStruct)); + + if (memInfo->mSize == 0 || memInfo->mAllocMemPtr == NULL) + { + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "[ixOsalMemAlignedFree] ERROR: Detected the corrupted " + "data: memory leak!! \n", 0, 0, 0, 0, 0, 0); + + return; + } + + kfree (memInfo->mAllocMemPtr); + +} + +PUBLIC VOID +ixOsalGetRandomNum32(UINT32 *num) +{ + get_random_bytes((void *)num, sizeof (UINT32)); +} + +PUBLIC VOID +ixOsalLogSetPrefix(CHAR * moduleName) +{ + UINT8 stringLength; + + if (moduleName == NULL) + { + return; + } + + stringLength = (UINT8)OSAL_OS_GET_STRING_LENGTH(moduleName); + + if (stringLength >= OSAL_MAX_MODULE_NAME_LENGTH) + { + stringLength = OSAL_MAX_MODULE_NAME_LENGTH -1 ; + } + + ixOsalMemCopy(osalModuleName,moduleName,stringLength); + osalModuleName[stringLength] = '\0'; + return; +} + +/** + * @ingroup IxOsal + * + * @brief simple logging function + * + * @param arg_pFmtString - message format, in printk format + * arg1 - argument 1 + * arg2 - argument 2 + * arg3 - argument 3 + * arg4 - argument 4 + * arg5 - argument 5 + * arg6 - argument 6 + * + * Logging function, similar to printk. This provides a barebones logging + * mechanism for users without differing verbosity levels. This interface + * is not quaranteed to be IRQ safe. + * + * @li Reentrant: yes + * @li IRQ safe: no + */ + + +IX_STATUS ixOsalStdLog( + const char* arg_pFmtString, + ... + ) +{ + IX_STATUS err = IX_SUCCESS; + va_list argList; + + va_start(argList, arg_pFmtString); + if ( OSAL_OS_GET_STRING_LENGTH(osalModuleName) != 0 ) + { + printk("%s :",osalModuleName); + } + vprintk(arg_pFmtString, argList); + va_end(argList); + + return err; + +} /* ixOsalStdLog */ + diff --git a/Acceleration/library/icp_utils/OSAL/common/os/linux/src/core/IxOsalOsSpinLock.c b/Acceleration/library/icp_utils/OSAL/common/os/linux/src/core/IxOsalOsSpinLock.c new file mode 100644 index 0000000..531d5ed --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/os/linux/src/core/IxOsalOsSpinLock.c @@ -0,0 +1,507 @@ +/** + * @file IxOsalOsSpinLock.c (linux) + * + * @brief Implementation for spinlocks + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +#include "IxOsal.h" + +/** + *********************************************************** + * @function: ixOsalSpinLockInit + * + * @param: slock - IN - pointer to a spinlock_t type + * @param: slockType - IN - not used + * + * @return: IX_STATUS - IX_SUCCESS or IX_FAIL + * + * @brief: Initialize Spin Lock. + *********************************************************** + */ +PUBLIC IX_STATUS +ixOsalSpinLockInit(IxOsalSpinLock *slock, IxOsalSpinLockType slockType) +{ + IX_OSAL_LOCAL_ENSURE(slock, + "ixOsalSpinLockInit(): Null spinlock pointer", + IX_FAIL); + + /* Spinlock type is ignored in case of Linux */ + spin_lock_init (slock); /* Kernel function call */ + + return IX_SUCCESS; +} + +/** + *********************************************************** + * @function: ixOsalSpinLockLock + * + * @param: slock - IN - pointer to a spinlock_t type + * + * @return: IX_STATUS - IX_SUCCESS or IX_FAIL + * + * @brief: Acquire the basic SpinLock + *********************************************************** + */ +PUBLIC IX_STATUS +ixOsalSpinLockLock(IxOsalSpinLock *slock) +{ + IX_OSAL_LOCAL_ENSURE(slock, + "ixOsalSpinLockLock(): Null spinlock pointer", + IX_FAIL); + + spin_lock (slock); /* kernel function call */ + + return IX_SUCCESS; +} + +/** + *********************************************************** + * + * @param: slock - IN - pointer to a spinlock_t type + * + * @return: IX_STATUS - IX_SUCCESS or IX_FAIL + * + * @brief: Release the SpinLock. + *********************************************************** + */ +PUBLIC IX_STATUS +ixOsalSpinLockUnlock(IxOsalSpinLock *slock) +{ + IX_OSAL_LOCAL_ENSURE(slock, + "ixOsalSpinLockUnlock(): Null spinlock pointer", + IX_FAIL); + + spin_unlock (slock); /* kernel function call */ + + return IX_SUCCESS; +} + +/** + *********************************************************** + * @function: ixOsalSpinLockTry + * + * @param: slock - IN - pointer to a spinlock_t type + * + * @return: IX_STATUS - IX_SUCCESS or IX_FAIL + * + * @brief: Try to acquire the SpinLock. + *********************************************************** + */ +PUBLIC IX_STATUS +ixOsalSpinLockTry(IxOsalSpinLock *slock) +{ + IX_OSAL_LOCAL_ENSURE(slock, + "ixOsalSpinLockTry(): Null spinlock pointer", + IX_FAIL); + + /* kernel function call */ + return spin_trylock(slock) ? IX_SUCCESS : IX_FAIL; +} + +/** + *********************************************************** + * @function: ixOsalSpinLockDestroy + * + * @param: slock - IN - pointer to a spinlock_t type + * + * @return: IX_STATUS - IX_SUCCESS or IX_FAIL + * + * @brief: Destroy the SpinLock. This is done by freeing + * the memory allocated to Spinlock. + *********************************************************** + */ +PUBLIC IX_STATUS +ixOsalSpinLockDestroy(IxOsalSpinLock *slock) +{ + IX_OSAL_LOCAL_ENSURE(slock, + "ixOsalSpinLockDestroy(): Null spinlock pointer", + IX_FAIL); + return IX_SUCCESS; +} + +/** + * @ingroup IxOsal + * + * @brief checks whether spinlock can be acquired + * + * @param slock - Spinlock handle + * + * This routine checks whether spinlock available for lock + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - IX_SUCCESS if spinlock is locked. Returns IX_FAIL if spinlock + * is not locked. + */ + +PUBLIC IX_STATUS ixOsalSpinLockIsLocked(IxOsalSpinLock *slock) +{ + /* SpinLock NULL pointer check. */ + IX_OSAL_LOCAL_ENSURE(slock, + "ixOsalSpinLockIsLocked(): NULL spinlock pointer", + IX_FAIL); + + return spin_is_locked(slock) ? IX_SUCCESS : IX_FAIL; +} + + +/** + * @ingroup IxOsal + * + * @brief Acquires a spinlock + * + * @param slock - Spinlock handle + * + * This routine disables local irqs & then acquires a slock + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @usage This API can be used in user context or bottom half when critical + * section is shared between user context or bottom half and the + * irq handler + * + * @return - returns IX_SUCCESS if spinlock is acquired. If the spinlock is not + * available then it busy loops/spins till slock available. If the + * spinlock handle passed is NULL then returns IX_FAIL. + */ + +PUBLIC IX_STATUS ixOsalSpinLockLockIrq(IxOsalSpinLock *slock) +{ + /* SpinLock NULL pointer check. */ + IX_OSAL_LOCAL_ENSURE(slock, + "ixOsalSpinLockLockIrq(): NULL spinlock pointer", + IX_FAIL); + + spin_lock_irq(slock); + return IX_SUCCESS; +} + +/** + * @ingroup IxOsal + * + * @brief Releases the spinlock + * + * @param slock - Spinlock handle + * + * This routine releases the acquired spinlock & enables the local irqs + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @usage This API can be used in user context or bottom half when critical + * section is shared between user context or bottom half and + * irq handler + * + * @return - returns IX_SUCCESS if slock is unlocked. Returns IX_FAIL if the + * slock is NULL. + */ +PUBLIC IX_STATUS ixOsalSpinLockUnlockIrq(IxOsalSpinLock *slock) +{ + /* SpinLock NULL pointer check. */ + IX_OSAL_LOCAL_ENSURE(slock, + "ixOsalSpinLockUnlockIrq(): Null spinlock pointer", + IX_FAIL); + + spin_unlock_irq(slock); + return IX_SUCCESS; +} + +/** + * @ingroup IxOsal + * + * @brief Tries to acquire the spinlock + * + * @param slock - Spinlock handle + * + * This routine disables local irq & attempts to acquire a spinlock but + * doesn't block the thread if spinlock not available. + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @usage This API can be used in user context or bottom half when critical + * section is shared between user context or bottom half and + * irq handler + * + * @return -If spinlock is available then returns the IX_SUCCESS with + * spinlock locked. If spinlock not available then enables the + * local irqs & returns IX_FAIL + * + */ + +PUBLIC IX_STATUS ixOsalSpinLockTryIrq(IxOsalSpinLock *slock) +{ + /* SpinLock NULL pointer check. */ + IX_OSAL_LOCAL_ENSURE(slock, + "ixOsalSpinLockTryIrq(): Null spinlock pointer", + IX_FAIL); + + return spin_trylock_irq(slock) ? IX_SUCCESS : IX_FAIL; + +} + +/** + * @ingroup IxOsal + * + * @brief Acquires a spinlock + * + * @param slock - Spinlock handle + * + * This routine disables bottom half & then acquires a slock + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @usage This API can be used in user context when critical section is + * shared between user context & bottom half handler + * + * @return - returns IX_SUCCESS if spinlock is acquired. If the spinlock is not + * available then it busy loops/spins till slock available. If the + * spinlock handle passed is NULL then returns IX_FAIL. + */ + +PUBLIC IX_STATUS ixOsalSpinLockLockBh(IxOsalSpinLock *slock) +{ + /* SpinLock NULL pointer check. */ + IX_OSAL_LOCAL_ENSURE(slock, + "ixOsalSpinLockLockBh(): Null spinlock pointer", + IX_FAIL); + + spin_lock_bh(slock); + return IX_SUCCESS; + +} + +/** + * @ingroup IxOsal + * + * @brief Releases the spin lock + * + * @param slock - Spinlock handle + * + * This routine releases the acquired spinlock & enables the + * bottom half handler + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @usage This API can be used in user context when critical section is + * shared between user context & bottom half handler + * + * @return - returns IX_SUCCESS if slock is released or unlocked. + * Returns IX_FAIL if the slock is NULL. + */ +PUBLIC IX_STATUS ixOsalSpinLockUnlockBh(IxOsalSpinLock *slock) +{ + /* SpinLock NULL pointer check. */ + IX_OSAL_LOCAL_ENSURE(slock, + "ixOsalSpinLockUnlockBh(): Null spinlock pointer", + IX_FAIL); + + spin_unlock_bh(slock); + return IX_SUCCESS; +} + +/** + * @ingroup IxOsal + * + * @brief Tries to acquire the spin lock + * + * @param slock - Spinlock handle + * + * This routine disables bottom half handler & attempts to acquire a spinlock + * but doesn't block the thread if spinlock not available. It enables the bh & + * returns IX_FAIL if spinlock not available. + * + * @li Reentrant: yes + * @li IRQ safe: no + * + * @usage This API can be used in user context when critical section is + * shared between user context & bottom half handler + * + * @return -Returns the IX_SUCCESS with spinlock locked if the spinlock is + * available. Enables the local irqs & return IX_FAIL + * if spinlock is not available. + */ +PUBLIC IX_STATUS ixOsalSpinLockTryBh(IxOsalSpinLock *slock) +{ + /* SpinLock NULL pointer check. */ + IX_OSAL_LOCAL_ENSURE(slock, + "ixOsalSpinLockTryBh(): Null spinlock pointer", + IX_FAIL); + + return spin_trylock_bh(slock) ? IX_SUCCESS : IX_FAIL; +} + +/** + * @ingroup IxOsal + * + * @brief Acquires a spinlock + * + * @param slock - Spinlock handle + * @param flags - local irqs saved in flags + * + * @usage This API can be used when critical section is shared between + * irq routines + * + * This routine saves local irqs in flags & then acquires a spinlock + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - returns IX_SUCCESS if spinlock acquired. If the spinlock is not + * available then it busy loops/spins till slock available. + * If the spinlock handle passed is NULL then returns IX_FAIL. + */ + +PUBLIC IX_STATUS ixOsalSpinLockLockIrqSave(IxOsalSpinLock *slock, + UINT32 *flags) +{ + /* SpinLock NULL pointer check. */ + IX_OSAL_LOCAL_ENSURE(slock, + "ixOsalSpinLockLockIrqSave(): Null spinlock pointer", + IX_FAIL); + + IX_OSAL_LOCAL_ENSURE(flags, + "ixOsalSpinLockLockIrqSave(): Null flags pointer", + IX_FAIL); + + // ugly hack because of ugly source code + spin_lock_irqsave(slock, *((unsigned long *)flags)); + return IX_SUCCESS; +} + +/** + * @ingroup IxOsal + * + * @brief Releases the spin lock + * + * @param slock - Spinlock handle + * @param flags - local irqs saved in flags + * + * @usage This API can be used when critical section is shared between + * irq routines + * + * This routine releases the acquired spin lock & restores irqs in flags + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return - returns IX_SUCCESS if slock is unlocked. Returns IX_FAIL if the + * slock is NULL. + */ +PUBLIC IX_STATUS ixOsalSpinLockUnlockIrqRestore(IxOsalSpinLock *slock, + UINT32 *flags) +{ + /* SpinLock NULL pointer check. */ + IX_OSAL_LOCAL_ENSURE(slock, + "ixOsalSpinLockUnlockIrqRestore(): Null spinlock pointer", + IX_FAIL); + + IX_OSAL_LOCAL_ENSURE(flags, + "ixOsalSpinLockUnlockIrqRestore(): Null flags pointer", + IX_FAIL); + + spin_unlock_irqrestore(slock, *((unsigned long *)flags)); + + return IX_SUCCESS; +} + +/** + * @ingroup IxOsal + * + * @brief Tries to acquire the spinlock + * + * @param slock - Spinlock handle + * @param flags - local irqs saved in flags + * + * This routine saves irq in flags & attempts to acquire a spinlock but + * doesn't block the thread if the spin lock not avialble. If the + * spinlock not available then it restore the irqs & return IX_FAIL + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @usage This API can be used when critical section is shared between + * irq routines + * + * @return -Returns the IX_SUCCESS with spinlock locked if the spinlock is + * available. Enables the local irqs & returns IX_FAIL + * if spinlock not available. + */ +PUBLIC IX_STATUS ixOsalSpinLockTryIrqSave(IxOsalSpinLock *slock, UINT32 *flags) +{ + /* SpinLock NULL pointer check. */ + IX_OSAL_LOCAL_ENSURE(slock, + "ixOsalSpinLockTryIrqSave(): Null spinlock pointer", + IX_FAIL); + + IX_OSAL_LOCAL_ENSURE(flags, + "ixOsalSpinLockTryIrqSave(): Null flags pointer", + IX_FAIL); + + return spin_trylock_irqsave(slock, *((unsigned long *)flags)) + ? IX_SUCCESS : IX_FAIL; +} diff --git a/Acceleration/library/icp_utils/OSAL/common/os/linux/src/core/IxOsalOsSymbols.c b/Acceleration/library/icp_utils/OSAL/common/os/linux/src/core/IxOsalOsSymbols.c new file mode 100644 index 0000000..81b9e52 --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/os/linux/src/core/IxOsalOsSymbols.c @@ -0,0 +1,207 @@ +/* + * @file IxOsalOsSymbols.c + * @author Intel Corporation + * @date 25-08-2004 + * + * @brief description goes here + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ +#include "IxOsal.h" + +#ifdef IX_OSAL_MODULE +#include <linux/init.h> +#include <linux/module.h> +MODULE_LICENSE("Dual BSD/GPL"); +#endif + +#ifdef OSAL_EXPORT_SYMBOLS + +EXPORT_SYMBOL (ixOsalMemAlloc); +EXPORT_SYMBOL (ixOsalMemFree); +EXPORT_SYMBOL (ixOsalMemCopy); +EXPORT_SYMBOL (ixOsalMemSet); +EXPORT_SYMBOL (ixOsalMemCmp); + + +EXPORT_SYMBOL (ixOsalThreadCreate); +EXPORT_SYMBOL (ixOsalThreadStart); +EXPORT_SYMBOL (ixOsalThreadKill); +EXPORT_SYMBOL (ixOsalThreadExit); +EXPORT_SYMBOL (ixOsalThreadPrioritySet); +EXPORT_SYMBOL (ixOsalThreadSuspend); +EXPORT_SYMBOL (ixOsalThreadResume); +EXPORT_SYMBOL (ixOsalThreadGetPolicyAndPriority); + +#ifdef IX_OSAL_THREAD_EXIT_GRACEFULLY +EXPORT_SYMBOL (ixOsalThreadStopCheck); +#endif /* IX_OSAL_THREAD_EXIT_GRACEFULLY */ + +EXPORT_SYMBOL (ixOsalMessageQueueCreate); +EXPORT_SYMBOL (ixOsalMessageQueueDelete); +EXPORT_SYMBOL (ixOsalMessageQueueSend); +EXPORT_SYMBOL (ixOsalMessageQueueReceive); +EXPORT_SYMBOL (ixOsalSyncMessageQueueReceive); +EXPORT_SYMBOL (ixOsalSyncMessageQueueCreate); + +EXPORT_SYMBOL (ixOsalMutexInit); +EXPORT_SYMBOL (ixOsalMutexLock); +EXPORT_SYMBOL (ixOsalMutexUnlock); +EXPORT_SYMBOL (ixOsalMutexTryLock); +EXPORT_SYMBOL (ixOsalMutexDestroy); +EXPORT_SYMBOL (ixOsalFastMutexInit); +EXPORT_SYMBOL (ixOsalFastMutexTryLock); +EXPORT_SYMBOL (ixOsalFastMutexUnlock); +EXPORT_SYMBOL (ixOsalFastMutexDestroy); + +EXPORT_SYMBOL (ixOsalSemaphoreInit); +EXPORT_SYMBOL (ixOsalSemaphorePost); +EXPORT_SYMBOL (ixOsalSemaphoreWait); +EXPORT_SYMBOL (ixOsalSemaphoreTryWait); +EXPORT_SYMBOL (ixOsalSemaphoreDestroy); +EXPORT_SYMBOL (ixOsalSemaphoreWaitInterruptible); +EXPORT_SYMBOL (ixOsalSleepTick); +EXPORT_SYMBOL (ixOsalSleepUninterruptible); +EXPORT_SYMBOL (ixOsalSemaphoreDownTimeout); + +EXPORT_SYMBOL (ixOsalYield); +EXPORT_SYMBOL (ixOsalSleep); +EXPORT_SYMBOL (ixOsalBusySleep); +EXPORT_SYMBOL (ixOsalTimeGet); +EXPORT_SYMBOL (ixOsalTimevalToTicks); +EXPORT_SYMBOL (ixOsalTicksToTimeval); + +EXPORT_SYMBOL (ixOsalLog); +EXPORT_SYMBOL (ixOsalStdLog); +EXPORT_SYMBOL (ixOsalLogLevelSet); +EXPORT_SYMBOL (ixOsalLogSetPrefix); +EXPORT_SYMBOL (ixOsalRepeatingTimerSchedule); +EXPORT_SYMBOL (ixOsalSingleShotTimerSchedule); +EXPORT_SYMBOL (ixOsalTimerCancel); +EXPORT_SYMBOL (ixOsalTimersShow); + +EXPORT_SYMBOL (ixOsalOsNameGet); +EXPORT_SYMBOL (ixOsalOsVersionGet); + +/* New Functions */ +EXPORT_SYMBOL (ixOsalThreadGetId); +EXPORT_SYMBOL (ixOsalThreadSetPolicyAndPriority); + + +#ifdef ENABLE_SPINLOCK + +EXPORT_SYMBOL (ixOsalSpinLockInit); +EXPORT_SYMBOL (ixOsalSpinLockLock); +EXPORT_SYMBOL (ixOsalSpinLockUnlock); +EXPORT_SYMBOL (ixOsalSpinLockTry); +EXPORT_SYMBOL (ixOsalSpinLockDestroy); +EXPORT_SYMBOL (ixOsalSpinLockIsLocked); +EXPORT_SYMBOL (ixOsalSpinLockLockBh); +EXPORT_SYMBOL (ixOsalSpinLockUnlockBh); +EXPORT_SYMBOL (ixOsalSpinLockTryBh); +EXPORT_SYMBOL (ixOsalSpinLockLockIrq); +EXPORT_SYMBOL (ixOsalSpinLockUnlockIrq); +EXPORT_SYMBOL (ixOsalSpinLockTryIrq); +EXPORT_SYMBOL (ixOsalSpinLockLockIrqSave); +EXPORT_SYMBOL (ixOsalSpinLockUnlockIrqRestore); +EXPORT_SYMBOL (ixOsalSpinLockTryIrqSave); + +#endif /* ENABLE_SPINLOCK */ + +EXPORT_SYMBOL (ixOsalAtomicGet); +EXPORT_SYMBOL (ixOsalAtomicSet); +EXPORT_SYMBOL (ixOsalAtomicAdd); +EXPORT_SYMBOL (ixOsalAtomicSub); +EXPORT_SYMBOL (ixOsalAtomicSubAndTest); +EXPORT_SYMBOL (ixOsalAtomicInc); +EXPORT_SYMBOL (ixOsalAtomicDec); +EXPORT_SYMBOL (ixOsalAtomicDecAndTest); +EXPORT_SYMBOL (ixOsalAtomicIncAndTest); + +EXPORT_SYMBOL (ixOsalMemBarrier); +EXPORT_SYMBOL (ixOsalReadMemBarrier); +EXPORT_SYMBOL (ixOsalWriteMemBarrier); + +EXPORT_SYMBOL (ixOsalGetRandomNum32); +EXPORT_SYMBOL (ixOsalMemAllocAtomic); +EXPORT_SYMBOL (ixOsalMemAllocAligned); +EXPORT_SYMBOL (ixOsalMemAlignedFree); + +#endif /* OSAL_EXPORT_SYMBOLS */ + +#ifdef IX_OSAL_MODULE + +static int osal_init( void ) +{ + printk( "Loading OSAL Module ...\n" ) ; + return 0; +} + + +static void osal_exit( void ) +{ + printk("Unloading OSAL Module ...\n" ) ; +} + +module_init(osal_init); +module_exit(osal_exit); + +#endif + diff --git a/Acceleration/library/icp_utils/OSAL/common/os/linux/src/core/IxOsalOsThread.c b/Acceleration/library/icp_utils/OSAL/common/os/linux/src/core/IxOsalOsThread.c new file mode 100644 index 0000000..ceba2ed --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/os/linux/src/core/IxOsalOsThread.c @@ -0,0 +1,467 @@ +/** + * @file IxOsalOsThread.c (linux) + * + * @brief OS-specific thread implementation. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +#include "IxOsal.h" + +#include <linux/sched.h> + +#ifdef IX_OSAL_OS_LINUX_VERSION_2_6 + +#include <linux/list.h> +#include <linux/kthread.h> +#include <linux/hardirq.h> + +#endif /* IX_OSAL_OS_LINUX_VERSION_2_6 */ + +/* Thread Data structure */ +struct IxOsalOsThreadData +{ + IxOsalVoidFnVoidPtr entryPoint; + void *arg; +}; + +/* declaring mutexes */ +DECLARE_MUTEX (IxOsalThreadMutex); +DECLARE_MUTEX (IxOsalThreadStopMutex); + +#ifndef IX_OSAL_OS_LINUX_VERSION_2_6 /* ! Linux-Kernel Version 2.6 */ + +struct IxOsalOsThreadData thread_data; +struct task_struct *kill_task = NULL; + +#endif + + +#ifdef IX_OSAL_OS_LINUX_VERSION_2_6 /* Linux Kernel Version 2.6 */ + +/* Thread info structure */ +struct IxOsalOsThreadInfo +{ + struct IxOsalOsThreadData data; + IxOsalThread ptid; + struct list_head list; +}; + + +/* Thread attribute is ignored in Create */ + +PUBLIC IX_STATUS +ixOsalThreadCreate (IxOsalThread * ptrTid, + IxOsalThreadAttr * threadAttr, IxOsalVoidFnVoidPtr entryPoint, void *arg) +{ + *ptrTid = kthread_create((void *)entryPoint, arg, "%s", + (NULL != threadAttr && NULL != threadAttr->name) + ? threadAttr->name: "OSAL"); + + return IX_SUCCESS; +} + + +PUBLIC IX_OSAL_INLINE BOOL +ixOsalThreadStopCheck(void) +{ + INT32 err = kthread_should_stop(); + return err ? TRUE : FALSE; +} + +/** + * Start the thread + */ +PUBLIC IX_STATUS +ixOsalThreadStart (IxOsalThread *tId) +{ + if (NULL == *tId) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, + "ixOsalThreadStart(): Invalid Thread ID!\n", 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + + wake_up_process(*tId); + return IX_SUCCESS; +} + +#ifdef IX_OSAL_THREAD_EXIT_GRACEFULLY +/* Exit status check is possible only in kernel 2.6.10 and greater */ + +/* + * Kill the kernel thread. This shall not be used if the thread function + * implements do_exit() + */ +PUBLIC IX_STATUS +ixOsalThreadKill (IxOsalThread * tid) +{ + struct task_struct *task = (struct task_struct*)*tid; + + /* Can't kill already defunc thread */ + if (EXIT_DEAD == task->exit_state || EXIT_ZOMBIE == task->exit_state) + { + return IX_FAIL; + } + + if (-EINTR == kthread_stop(task)) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, + "ixOsalThreadKill(): Failed to kill thread\n", 0, 0, 0, 0, 0, 0); + + return IX_FAIL; + } + + return IX_SUCCESS; +} + +#else /* __! EXIT_GRACEFULLY */ + +PUBLIC IX_STATUS +ixOsalThreadKill (IxOsalThread * tid) +{ + kill_proc ((pid_t)*tid, SIGKILL, 1); + return IX_SUCCESS; +} + +#endif /* IX_OSAL_THREAD_EXIT_GRACEFULLY */ + + + +/******************************************************************** + * UINT32 priority - the value of priority can range from 0 to 39 * + * with 0 being the highest priority. * + * * + * Any value for priority more than 39 will be silently rounded off * + * to 39 in this implementation. Internally, the range is converted * + * to the corresponding nice value that can range from -20 to 19. * + ********************************************************************/ + +PUBLIC IX_STATUS +ixOsalThreadPrioritySet (IxOsalThread * tid, UINT32 priority) +{ + struct task_struct *pTask = (struct task_struct*)*tid; + + IX_OSAL_LOCAL_ENSURE(tid, + "ixOsalThreadPrioritySet(): Null pointer", + IX_FAIL); + + if (priority > IX_OSAL_PRIO_SET_MAX_VALID_VAL) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, + "ixOsalThreadPrioritySet(): FAIL \n", 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + + if (priority > IX_OSAL_PRIO_SET_MAX_VAL) + { + priority = IX_OSAL_PRIO_SET_MAX_VAL; + } + if (priority < 0) + { + priority = 0; + } + + /* sending the nice equivalent of priority as the parameter */ + set_user_nice ( pTask, priority - IX_OSAL_NICE_VAL_DIFFERENCE ); + + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "ixOsalThreadPrioritySet(): Priority changed successfully \n", + 0, 0, 0, 0, 0, 0); + + return IX_SUCCESS; +} + +/** + *********************************************************** + * End of code cleanup section + *********************************************************** + */ + +#else /* ! LINUX_VERSION_2_6 */ + +PUBLIC IX_OSAL_INLINE BOOL +ixOsalThreadStopCheck() +{ + if (current == kill_task) + { + kill_task = NULL; + up(&IxOsalThreadStopMutex); + return TRUE; + } + return FALSE; +} + +static int +thread_internal (void *unused) +{ + IxOsalVoidFnVoidPtr entryPoint = thread_data.entryPoint; + void *arg = thread_data.arg; + static int seq = 0; + + daemonize(); + reparent_to_init (); + exit_files (current); + + snprintf(current->comm, sizeof(current->comm), "IxOsal %d", ++seq); + + up (&IxOsalThreadMutex); + + entryPoint (arg); + return 0; +} + +/* Thread attribute is ignored */ +PUBLIC IX_STATUS +ixOsalThreadCreate (IxOsalThread * ptrTid, + IxOsalThreadAttr * threadAttr, IxOsalVoidFnVoidPtr entryPoint, void *arg) +{ + down (&IxOsalThreadMutex); + thread_data.entryPoint = entryPoint; + thread_data.arg = arg; + + /* + * kernel_thread takes: int (*fn)(void *) as the first input. + */ + *ptrTid = kernel_thread (thread_internal, NULL, CLONE_SIGHAND); + + if (*ptrTid < 0) + { + up (&IxOsalThreadMutex); + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, + "ixOsalThreadCreate(): fail to generate thread \n", + 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + + return IX_SUCCESS; + +} + +/* + * Start thread after given its thread handle + */ +PUBLIC IX_STATUS +ixOsalThreadStart (IxOsalThread * tId) +{ + /* Thread already started upon creation */ + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "ixOsalThreadStart(): not implemented in linux\n", + 0, 0, 0, 0, 0, 0); + return IX_SUCCESS; +} + + +PUBLIC IX_STATUS +ixOsalThreadKill (IxOsalThread * tid) +{ + down(&IxOsalThreadStopMutex); + kill_task = find_task_by_pid(*tid); + + if (kill_task) + { + wake_up_process(kill_task); + + return IX_SUCCESS; + } + + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, + "ixOsalThreadKill: Task %d was dead\n", *tid, 0, 0, 0, 0, 0); + + /* Kill failed, remove the mutex */ + up(&IxOsalThreadStopMutex); + return IX_FAIL; +} + +#endif /* IX_OSAL_OS_LINUX_VERSION_2_6 */ + +PUBLIC void +ixOsalThreadExit (void) +{ + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "ixOsalThreadExit(): not implemented in linux\n", 0, 0, 0, 0, 0, 0); +} + +PUBLIC IX_STATUS +ixOsalThreadSuspend (IxOsalThread * tId) +{ + ixOsalLog (IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDOUT, + "ixOsalThreadSuspend(): not implemented in linux\n", 0, 0, 0, 0, 0, 0); + return IX_SUCCESS; +} + +PUBLIC IX_STATUS +ixOsalThreadResume (IxOsalThread * tId) +{ + ixOsalLog (IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDOUT, + "ixOsalThreadResume(): not implemented in linux \n", 0, 0, 0, 0, 0, 0); + return IX_SUCCESS; + +} + +IX_STATUS +ixOsalThreadGetId(IxOsalThread *ptrTid) +{ + *ptrTid = (IxOsalThread)current->pid; + + return IX_SUCCESS; + +} /* ixOsalThreadGetId */ + + +IX_STATUS +ixOsalThreadSetPolicyAndPriority( + IxOsalThread *tid, + UINT32 policy, + UINT32 priority) +{ + +#ifdef IX_OSAL_OS_LINUX_VER_GT_2_6_18 + struct task_struct *pTask = (struct task_struct*)*tid; + struct sched_param param1; + INT32 status; + + IX_OSAL_LOCAL_ENSURE(tid, + "ixOsalThreadSetPolicyAndPriority(): Null pointer", + IX_FAIL); + /* set the policy of existing */ + policy = policy; + param1.sched_priority = priority; + status = sched_setscheduler(pTask, policy, ¶m1); + if(status) + { + return IX_FAIL; + } + else + { + return IX_SUCCESS; + } +#else + IX_STATUS err = IX_SUCCESS; + struct task_struct *pTask; + + IX_OSAL_LOCAL_ENSURE(tid, + "ixOsalThreadSetPolicyAndPriority(): Null pointer", + IX_FAIL); + lock_kernel(); + + /* In case of Linux Kernel 2.4: + * pTask = find_task_by_pid(*tid); */ + + /* In case of Kernel 2.6(default for OSSL-Shim) */ + pTask = *tid; + + if(pTask == 0) + { + err = IX_FAIL; + }else{ + pTask->policy = policy; + pTask->rt_priority = priority; + } + + unlock_kernel(); + return err; +#endif /* IX_OSAL_OS_LINUX_VER_BT_2_6_18 */ + +} /* ixOsalThreadSetPolicyAndPriority */ + +PUBLIC IX_STATUS +ixOsalThreadGetPolicyAndPriority( + IxOsalThread *tid, + UINT32 *policy, + UINT32 *priority) +{ +#ifdef IX_OSAL_OS_LINUX_VER_GT_2_6_18 + struct task_struct *pTask = (struct task_struct*)*tid; + + IX_OSAL_ENSURE_RETURN(tid, "Null pointer"); + /* set the policy of existing */ + *policy = pTask->policy; + *priority = pTask->rt_priority; + return IX_SUCCESS; + +#else + IX_STATUS err = IX_SUCCESS; + struct task_struct *pTask; + + IX_OSAL_ENSURE_RETURN(tid, "Null pointer"); + lock_kernel(); + + /* In case of Linux Kernel 2.4: + * pTask = find_task_by_pid(*tid); */ + + pTask = *tid; + + if(pTask == 0) + { + err = IX_FAIL; + }else{ + *policy = pTask->policy; + *priority = pTask->rt_priority; + } + + unlock_kernel(); + return err; +#endif /* IX_OSAL_OS_LINUX_VER_BT_2_6_18 */ + +} + diff --git a/Acceleration/library/icp_utils/OSAL/common/os/linux/src/core/IxOsalOsTimer.c b/Acceleration/library/icp_utils/OSAL/common/os/linux/src/core/IxOsalOsTimer.c new file mode 100644 index 0000000..1171305 --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/os/linux/src/core/IxOsalOsTimer.c @@ -0,0 +1,275 @@ +/** + * @file IxOsalOsTimer.c (linux) + * + * @brief Implementation for Timer API's. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ +#include "IxOsal.h" + +#include <linux/timer.h> + + +static void callback_repeat_timer(unsigned long ptr) +{ + IxOsalTimerRec *nTimerPtr; + + nTimerPtr = (IxOsalTimerRec *)ptr; + /* if timer inUse then only reregister the timer */ + if(nTimerPtr->inUse == TRUE) + { + /* call callback function registered by user */ + nTimerPtr->callback(nTimerPtr->callbackParam); + nTimerPtr->timer.expires = jiffies + nTimerPtr->period; + /* add timer to call the callback after period */ + add_timer(&nTimerPtr->timer); + } +} + +/** + * @ingroup IxOsal + * + * @brief Schedules a repeating timer + * + * @param timer - handle of the timer object + * @param period - timer trigger period, in milliseconds + * @param priority - timer priority (0 being the highest) + * @param callback - user callback to invoke when the timer triggers + * @param param - custom parameter passed to the callback + * + * Schedules a timer to be called every period milliseconds. The timer + * will invoke the specified callback function possibly in interrupt + * context, passing the given parameter. If several timers trigger at the + * same time contention issues are dealt according to the specified timer + * priorities. + * + * @li Reentrant: no + * @li IRQ safe: no + * + * @return - IX_SUCCESS/IX_FAIL + */ +PUBLIC IX_STATUS ixOsalRepeatingTimerSchedule (IxOsalTimer *timer, + UINT32 period, + UINT32 priority, + IxOsalVoidFnVoidPtr callback, + void *param) +{ + IxOsalTimerRec *timerPtr; + IX_OSAL_LOCAL_ENSURE(timer, + "ixOsalRepeatingTimerSchedule(): Null IxOsalTimer pointer", + IX_FAIL); + + IX_OSAL_LOCAL_ENSURE(callback, + "ixOsalRepeatingTimerSchedule(): NULL callback function pointer", + IX_FAIL); + + *timer = kmalloc (sizeof (IxOsalTimerRec), GFP_KERNEL); + if (!(*timer)) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, + IX_OSAL_LOG_DEV_STDOUT, + "ixOsalRepeatingTimerSchedule(): " + "Fail to allocate for IxOsalTimer \n", + 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + + timerPtr = *timer; + timerPtr->inUse = TRUE; + init_timer(&(timerPtr->timer)); + timerPtr->timer.function = callback_repeat_timer; + timerPtr->timer.data = (unsigned long)timerPtr; + timerPtr->timer.expires = jiffies + \ + ((period*HZ)/IX_OSAL_THOUSAND); + + /* store period to call the callback at regular intervals in jiffies*/ + timerPtr->period = ((period*HZ)/IX_OSAL_THOUSAND); + timerPtr->callback = callback; + timerPtr->callbackParam = param; + timerPtr->isRepeating = TRUE; + add_timer(&(timerPtr->timer)); + + return IX_SUCCESS; +} + +/** + * @ingroup IxOsal + * + * @brief Schedules a single-shot timer + * + * @param timer - handle of the timer object + * @param period - timer trigger period, in milliseconds + * @param priority - timer priority (0 being the highest) + * @param callback - user callback to invoke when the timer triggers + * @param param - custom parameter passed to the callback + * + * Schedules a timer to be called after period milliseconds. The timer + * will cease to function past its first trigger. The timer will invoke + * the specified callback function, possibly in interrupt context, passing + * the given parameter. If several timers trigger at the same time contention + * issues are dealt according to the specified timer priorities. + * + * @li Reentrant: no + * @li IRQ safe: no + * + * @return - IX_SUCCESS/IX_FAIL + */ +PUBLIC IX_STATUS +ixOsalSingleShotTimerSchedule (IxOsalTimer *timer, + UINT32 period, + UINT32 priority, + IxOsalVoidFnVoidPtr callback, void *param) +{ + IxOsalTimerRec *timerPtr; + + IX_OSAL_LOCAL_ENSURE(timer, + "ixOsalSingleShotTimerSchedule(): NULL IxOsalTimer pointer", + IX_FAIL); + + IX_OSAL_LOCAL_ENSURE(callback, + "ixOsalSingleShotTimerSchedule(): NULL callback function pointer", + IX_FAIL); + + *timer = kmalloc (sizeof (IxOsalTimerRec), GFP_KERNEL); + if (!(*timer)) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, + IX_OSAL_LOG_DEV_STDOUT, + "ixOsalSingleShotTimerSchedule() Fail to allocate IxOsalTimer \n", + 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + + timerPtr = *timer; + timerPtr->inUse = TRUE; + init_timer(&timerPtr->timer); + timerPtr->timer.function = (voidFnULongPtr)callback; + timerPtr->timer.data = (unsigned long)param; + timerPtr->timer.expires = jiffies + \ + ((period*HZ)/IX_OSAL_THOUSAND); + timerPtr->isRepeating = FALSE; + add_timer(&timerPtr->timer); + + return IX_SUCCESS; +} + +/** + * @ingroup IxOsal + * + * @brief Cancels a running timer + * + * @param timer - handle of the timer object + * + * Cancels a single-shot or repeating timer. + * + * @li Reentrant: no + * @li IRQ safe: yes + * + * @return - IX_SUCCESS/IX_FAIL + */ +PUBLIC IX_STATUS ixOsalTimerCancel (IxOsalTimer * timer) +{ + IxOsalTimerRec *timerPtr; + IX_OSAL_LOCAL_ENSURE(timer, + "ixOsalTimerCancel(): Null IxOsalTimer pointer\n", + IX_FAIL); + + timerPtr = *timer; + if(timerPtr->inUse == FALSE) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, + "ixOsalTimerCancel(): Timer is already deleted\n", + 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + + timerPtr->inUse = FALSE; + /* free & call del_timer in callback fn for repeat timer */ + del_timer(&(timerPtr->timer)); + kfree (*timer); + + return IX_SUCCESS; +} + +/** + * @ingroup IxOsal + * + * @brief displays all the running timers + * + * Displays a list with all the running timers and their parameters (handle, + * period, type, priority, callback and user parameter) + * + * @li Reentrant: no + * @li IRQ safe: no + * + * @return - none + */ +PUBLIC void ixOsalTimersShow (void) +{ + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "ixOsalTimersShow not Supported in linux native mode implemenattion\n", + 0, 0, 0, 0, 0, 0); + + return ; +} + + diff --git a/Acceleration/library/icp_utils/OSAL/common/os/linux/src/core/component.mk b/Acceleration/library/icp_utils/OSAL/common/os/linux/src/core/component.mk new file mode 100644 index 0000000..d9d25b8 --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/os/linux/src/core/component.mk @@ -0,0 +1,85 @@ +# +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# Contact Information: +# Intel Corporation +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# + +core_os_OBJ := \ + IxOsalOsThread.o \ + IxOsalOsServices.o \ + IxOsalOsSemaphore.o \ + IxOsalOsSymbols.o \ + IxOsalOsMsgQ.o \ + IxOsalOsAtomic.o \ + IxOsalOsMemBarrier.o + +ifneq (,$(findstring ENABLE_SPINLOCK,$(CFLAGS))) +core_os_OBJ += IxOsalOsSpinLock.o +endif + +ifneq (,$(findstring USE_NATIVE_OS_TIMER_API,$(CFLAGS))) +core_os_OBJ += IxOsalOsTimer.o +endif + +ifneq (,$(findstring IX_OSAL_MODULE,$(CFLAGS))) +core_os_OBJ += IxOsalOsModule.o +endif + +# Add CFLAGS per source file here if needed +core_os_CFLAGS := + diff --git a/Acceleration/library/icp_utils/OSAL/common/os/linux/src/modules/ddk/IxOsalOsDdkCacheMMU.c b/Acceleration/library/icp_utils/OSAL/common/os/linux/src/modules/ddk/IxOsalOsDdkCacheMMU.c new file mode 100644 index 0000000..fd8b61d --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/os/linux/src/modules/ddk/IxOsalOsDdkCacheMMU.c @@ -0,0 +1,226 @@ +/** + * @file IxOsalOsDdkCacheMMU.c (linux) + * + * @brief Cache MemAlloc and MemFree. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ +#include "IxOsal.h" +#include <linux/kernel.h> +#include <linux/slab.h> + + + +/* + * Allocate on a cache line boundary (null pointers are + * not affected by this operation). This operation is NOT cache safe. + */ +void * +ixOsalCacheDmaMalloc (UINT32 size) +{ + struct page *page; + UINT32 order; + UINT32 *userPtr; + UINT32 *myPtr; + UINT32 mySize; + + /* The minimum allocation size is 32 */ + if (size < IX_OSAL_CACHE_LINE_SIZE) + { + size = IX_OSAL_CACHE_LINE_SIZE; + } + + /* + * myPtr userPtr end of last cache line + * _________________________________________________________ + * | | | | | | | + * |Or|Ptr|Sz|Ma| USER BUFFER | | + * |__|___|__|__|_________________________________|_________| + * + * myPtr: The pointer returned by kmalloc. This may not be 32 byte aligned + * userPtr: The pointer returned to the user. This is guaranteed + * to be 32 byte aligned + * Or: The order of pages that was allocated. This info is needed + * for deallocating the buffer + * Ma: Arbitrary number 0xBABEFACE that allows to check against + * memory corruption + * Sz: The value of the requested memory allocation size + * Ptr: This 4-byte field records the value of myPtr. This info is + * needed in order to deallocate the buffer + */ + + /* Check whether the request is for a "small" memory chunck */ + if (size <= IX_OSAL_OS_SMALL_MEM_SIZE) + { + /* + * Ensure that the size is rounded up to a multiple of a cache line + * and add to it a cache line for storing internal information + */ + mySize = size + + (IX_OSAL_OS_NUM_INFO_WORDS * IX_OSAL_OS_BYTES_PER_WORD); + mySize = IX_OSAL_OS_CL_ROUND_UP(mySize); + mySize += IX_OSAL_CACHE_LINE_SIZE; + myPtr = (UINT32 *)kmalloc(mySize, GFP_KERNEL); + + IX_OSAL_LOCAL_ENSURE( (NULL != myPtr), + "ixOsalCacheDmaMalloc(): Fail to alloc small memory \n", + NULL); + + /* Pass to the user a pointer that is cache line aligned */ + userPtr = myPtr + IX_OSAL_OS_NUM_INFO_WORDS; + userPtr = (UINT32 *) IX_OSAL_OS_CL_ROUND_UP((UINT32)userPtr); + + /* It is imperative that the user pointer be 32 byte aligned */ + IX_OSAL_LOCAL_ENSURE( + (((UINT32) userPtr % IX_OSAL_CACHE_LINE_SIZE) == 0), + "ixOsalCacheDmaMalloc(): " + "Error memory allocated is not 32 byte aligned\n", + NULL); + } + else + { + /* + * Increase the size by a full cacheline for size information. + */ + { + ULONG temp_size = PAGE_ALIGN (size + IX_OSAL_CACHE_LINE_SIZE); + /*size = PAGE_ALIGN (size + IX_OSAL_CACHE_LINE_SIZE);*/ + ixOsalMemCopy(&size,&temp_size,sizeof(UINT32)); + } + order = (UINT32)get_order (size); + page = alloc_pages (GFP_KERNEL, order); + if (!page) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, + "ixOsalCacheDmaMalloc(): Fail to alloc page \n", + 0, 0, 0, 0, 0, 0); + return NULL; + } + myPtr = (UINT32 *) page_address (page); + + /* The client's pointer is 32 bytes ahead of my pointer */ + userPtr = (UINT32 *)((UINT32) myPtr + IX_OSAL_CACHE_LINE_SIZE); + /* Store the page order 4 words behind the client's pointer */ + userPtr[IX_OSAL_OS_ORDER_OF_PAGES_INDEX] = order; + } + + /* Store the allocated pointer 3 words behind the client's pointer */ + userPtr[IX_OSAL_OS_MYPTR_INDEX] = (UINT32)myPtr; + /* Store the requested size 2 words behind the client's pointer */ + userPtr[IX_OSAL_OS_REQUESTED_SIZE_INDEX] = size; + /* Store the allocation identifier 1 word behind the client's pointer */ + userPtr[IX_OSAL_OS_MAGIC_NUMBER_INDEX] = IX_OSAL_OS_MAGIC_ALLOC_NUMBER; + + return ((void *)userPtr); +} + +/* + * + * Frees the memory buffer allocated in previous function + */ +void +ixOsalCacheDmaFree (void *ptr) +{ + UINT32 order; + UINT32 *memptr; + UINT32 size; + UINT32 *clientPtr = ptr; + + if ( NULL == ptr) + { + ixOsalLog(IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, + "ixOsalCacheDmaFree(): NULL Ptr passed \n", + 0, 0, 0, 0, 0, 0); + return; + } + + /* Make sure that the pointer passed in belongs to us */ + if (clientPtr[IX_OSAL_OS_MAGIC_NUMBER_INDEX] + != IX_OSAL_OS_MAGIC_ALLOC_NUMBER) + { + ixOsalLog(IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, + "ixOsalCacheDmaFree(): Memory being freed is invalid \n", + 0, 0, 0, 0, 0, 0); + return; + } + + /* Detect multiple deallocation */ + clientPtr[IX_OSAL_OS_MAGIC_NUMBER_INDEX] = IX_OSAL_OS_MAGIC_DEALLOC_NUMBER; + + /* Rewind ptr to retrieve requested-size information */ + memptr = (UINT32 *)clientPtr[IX_OSAL_OS_MYPTR_INDEX]; + size = clientPtr[IX_OSAL_OS_REQUESTED_SIZE_INDEX]; + + /* The requested size will determine how the memory will be freed */ + if (size <= IX_OSAL_OS_SMALL_MEM_SIZE) + { + /* Free the "small" page */ + kfree(memptr); + } + else + { + /* Get the order information */ + order = clientPtr[IX_OSAL_OS_ORDER_OF_PAGES_INDEX]; + /* Free the memory page(s) */ + free_pages ((unsigned int) memptr, order); + } +} diff --git a/Acceleration/library/icp_utils/OSAL/common/os/linux/src/modules/ddk/IxOsalOsDdkClk.c b/Acceleration/library/icp_utils/OSAL/common/os/linux/src/modules/ddk/IxOsalOsDdkClk.c new file mode 100644 index 0000000..24548aa --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/os/linux/src/modules/ddk/IxOsalOsDdkClk.c @@ -0,0 +1,94 @@ +/** + * @file IxOsalOsDdkClk.c (linux) + * + * @brief System Clock Rate and TimeStamp functions. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ +#include "IxOsal.h" +#include <asm/system.h> +#include <linux/delay.h> +#include <linux/time.h> + + + + +/* TimeStamp is implemented in OEM */ +PUBLIC UINT32 +ixOsalTimestampGet (void) +{ + return IX_OSAL_OEM_TIMESTAMP_GET (); +} + +/* OEM-specific implementation for TimeStamp Resolution */ +PUBLIC UINT32 +ixOsalTimestampResolutionGet (void) +{ + return IX_OSAL_OEM_TIMESTAMP_RESOLUTION_GET (); +} + +/* OEM-specific implementation for System Clock Rate */ +PUBLIC UINT32 +ixOsalSysClockRateGet (void) +{ + return IX_OSAL_OEM_SYS_CLOCK_RATE_GET (); +} diff --git a/Acceleration/library/icp_utils/OSAL/common/os/linux/src/modules/ddk/IxOsalOsDdkIrq.c b/Acceleration/library/icp_utils/OSAL/common/os/linux/src/modules/ddk/IxOsalOsDdkIrq.c new file mode 100644 index 0000000..7295cd2 --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/os/linux/src/modules/ddk/IxOsalOsDdkIrq.c @@ -0,0 +1,388 @@ +/** + * @file IxOsalOsDdkIrq.c (linux) + * + * @brief System Interrupt functions. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +#include "IxOsal.h" + +#include <linux/version.h> +#ifdef IX_OSAL_OS_LINUX_VER_GT_2_6_20 +#include <linux/irq.h> +#endif +#ifdef IX_OSAL_OS_LINUX_VERSION_2_6 +#include <linux/hardirq.h> +#include <linux/interrupt.h> +#endif + +#include <asm/hardirq.h> +#include <asm/system.h> +#include <asm/irq.h> + +#include "IxOsalOsOem.h" +#include "IxOsalOsOemIrq.h" + + + +/* + * Note: being referenced by some release 1.4 linux + * components as global . + */ +/** + * This needs to be moved to IxOsalOem.h file + */ +typedef struct IxOsalInfoType +{ + voidFnVoidPtr routine; + void *parameter; +} IxOsalInfoType; + +static IxOsalInfoType IxOsalInfo[NR_IRQS]; + +/* + * General interrupt handler + */ + +/* + * Private utility function for ixOsalIrqBind to translate IRQ vector number to + * IRQ name. + */ +PRIVATE const char* +ixOsalGetIrqNameByVector(UINT32 vector) +{ + if (unlikely (ARRAY_SIZE(irq_name) <= vector)) + { + return (invalid_irq_name); + } + + return (irq_name[vector]); +} + + +#ifdef IX_OSAL_OS_LINUX_VERSION_2_6 +static irqreturn_t +#else +static void +#endif +/* Definition of request_irq changed for 2.6.20 onwards */ +#ifdef IX_OSAL_OS_LINUX_VER_GT_2_6_20 +ixOsalOsIsrProxy (int irq, void *dev_id) +#else +ixOsalOsIsrProxy (int irq, void *dev_id, struct pt_regs *regs) +#endif +{ + IxOsalInfoType *isr_proxy_info = (IxOsalInfoType *) dev_id; + +#ifdef IX_OSAL_OS_LINUX_VERSION_2_6 + IX_OSAL_LOCAL_ENSURE(isr_proxy_info, + "ixOsalOsIsrProxy: Interrupt used before " + "ixOsalIrqBind was invoked (isr_proxy_info == NULL)\n", + IRQ_NONE); + + IX_OSAL_LOCAL_ENSURE(isr_proxy_info->routine, + "ixOsalOsIsrProxy: Interrupt used before " + "ixOsalIrqBind was invoked (isr_proxy_info->routine == NULL)\n", + IRQ_NONE); +#else + IX_OSAL_ENSURE_JUST_RETURN(isr_proxy_info, + "ixOsalOsIsrProxy: Interrupt used before " + "ixOsalIrqBind was invoked (isr_proxy_info == NULL)\n"); + + IX_OSAL_ENSURE_JUST_RETURN(isr_proxy_info->routine, + "ixOsalOsIsrProxy: Interrupt used before " + "ixOsalIrqBind was invoked (isr_proxy_info->routine == NULL)\n"); +#endif + + isr_proxy_info->routine (isr_proxy_info->parameter); + + +#ifdef IX_OSAL_OS_LINUX_VERSION_2_6 + return IRQ_HANDLED; +#endif + +} + +/* + * Interrupt handler for XScale PMU interrupts + * This handler saves the interrupted Program Counter (PC) + * into a global variable + */ + +/* Definition of request_irq changed for 2.6.20 onwards */ +#ifdef IX_OSAL_OS_LINUX_VER_GT_2_6_20 + +static irqreturn_t + +ixOsalOsIsrProxyWithPC (int irq, void *dev_id) +{ + + IX_OSAL_OEM_SET_INTERRUPTED_PC(get_irq_regs()); + + return ixOsalOsIsrProxy(irq, dev_id); + +} + +/* prior to 2.6.20 */ +#else + +#ifdef IX_OSAL_OS_LINUX_VERSION_2_6 +static irqreturn_t +#else +static void +#endif +ixOsalOsIsrProxyWithPC (int irq, void *dev_id, struct pt_regs *regs) +{ + /** + * The variable to me moved to IxOSalOem.h file + */ + IX_OSAL_OEM_SET_INTERRUPTED_PC(regs); + +#ifdef IX_OSAL_OS_LINUX_VERSION_2_6 + return ixOsalOsIsrProxy(irq, dev_id, regs); +#else + ixOsalOsIsrProxy(irq, dev_id, regs); +#endif + +} + +#endif /*endif prior to 2.6.20 */ + + + + + +/************************************** + * Irq services + *************************************/ + +PUBLIC IX_STATUS +ixOsalIrqBind (UINT32 vector, IxOsalVoidFnVoidPtr routine, void *parameter) +{ + + if (vector >= NR_IRQS) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, + "ixOsalIrqBind: Invalid Interrupt Number %d \n", vector, \ + 0, 0, 0, 0, 0); + return IX_FAIL; + } + + if (IxOsalInfo[vector].routine) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, + IX_OSAL_LOG_DEV_STDOUT, + /*"ixOsalIrqBind: NULL function routine. \n", 0, 0, 0, 0, 0, 0); */ + "ixOsalIrqBind: interrupt vector %d already binded. \n", + vector, 0, 0, 0, 0, 0); + return IX_FAIL; + } + + IxOsalInfo[vector].routine = routine; + IxOsalInfo[vector].parameter = parameter; + + /* + * The PMU interrupt handler is a special case in the sense + * that it needs to save the address of the interrupted PC + * In the case of the IA/XScale PMU interrupt, the ixOsalOsIsrProxyWithPC + * function is registered + */ + + if (vector == IX_OSAL_OEM_IRQ_PMU) + { + /* + * request_irq will enable interrupt automatically + * A non-zero return value suggest a failure. + */ + if (request_irq (vector, ixOsalOsIsrProxyWithPC, IRQF_SHARED, + ixOsalGetIrqNameByVector(vector), + &IxOsalInfo[vector])) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, + "ixOsalIrqBind: Fail to request irq. \n", + 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + } + else + { + /* + * request_irq will enable interrupt automatically + * A non-zero return value suggest a failure. + */ + if (request_irq (vector, ixOsalOsIsrProxy, IRQF_SHARED, + ixOsalGetIrqNameByVector(vector), &IxOsalInfo[vector])) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, + "ixOsalIrqBind: Fail to request irq. \n", + 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + } + return IX_SUCCESS; +} + +PUBLIC IX_STATUS +ixOsalIrqUnbind (UINT32 vector) +{ + if (!IxOsalInfo[vector].routine) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, + IX_OSAL_LOG_DEV_STDOUT, + "ixOsalIrqUnbind: NULL function routine. \n", 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + + free_irq (vector, &IxOsalInfo[vector]); + IxOsalInfo[vector].routine = NULL; + + return IX_SUCCESS; +} + +PUBLIC UINT32 +ixOsalIrqLock (void) +{ + unsigned long flags; +#ifdef IX_OSAL_OS_LINUX_VERSION_2_6 + /* local_irq_save() gives a compilation warning against s32 + * data type. */ + + local_save_flags(flags); + + local_irq_disable(); +#else + + save_flags (flags); + cli (); + +#endif /* LINUX_VERSION */ + + return (UINT32)flags; +} + +/* Enable interrupts and task scheduling, + * input parameter: irqEnable status returned + * by ixOsalIrqLock(). + */ +PUBLIC void +ixOsalIrqUnlock (UINT32 lockKey) +{ +#ifdef IX_OSAL_OS_LINUX_VERSION_2_6 + local_irq_restore((unsigned long)lockKey); +#else + restore_flags (lockKey); +#endif +} + +PUBLIC UINT32 +ixOsalIrqLevelSet (UINT32 level) +{ + /* + * Not supported + */ + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "ixOsalIrqLevelSet: not supported \n", 0, 0, 0, 0, 0, 0); + return 0; +} + +PUBLIC void +ixOsalIrqEnable (UINT32 irqLevel) +{ + if (irqLevel < NR_IRQS) + { + enable_irq(irqLevel); + } + else + { + /* + * Not supported + */ + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "ixOsalIrqEnable: IRQ %d not supported \n", irqLevel, + 0, 0, 0, 0, 0); + } +} + +PUBLIC void +ixOsalIrqDisable (UINT32 irqLevel) +{ + if (irqLevel < NR_IRQS) + { + disable_irq(irqLevel); + } + else + { + /* + * Not supported + */ + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "ixOsalIrqDisable: IRQ %d not supported \n", irqLevel, + 0, 0, 0, 0, 0); + } +} + +void * +ixOsalMemAllocAtomic (UINT32 memsize) +{ + return (kmalloc (memsize, GFP_ATOMIC)); +} + diff --git a/Acceleration/library/icp_utils/OSAL/common/os/linux/src/modules/ddk/IxOsalOsDdkPci.c b/Acceleration/library/icp_utils/OSAL/common/os/linux/src/modules/ddk/IxOsalOsDdkPci.c new file mode 100644 index 0000000..1827315 --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/os/linux/src/modules/ddk/IxOsalOsDdkPci.c @@ -0,0 +1,222 @@ +/** + * @file IxOsalOsDdkPci.c (linux) + * + * @brief Implementation for PCI functionality. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ +#include "IxOsal.h" +#include <linux/pci.h> + + + +PUBLIC +IxOsalPciDev ixOsalPciDeviceFind(UINT32 vendor_id,UINT32 device_id,IxOsalPciDev pci_dev) +{ + struct pci_dev *pdev = (struct pci_dev *)pci_dev; + + pdev = pci_get_device(vendor_id, device_id, pdev); + + return (IxOsalPciDev)pdev; +} + +PUBLIC +INT32 ixOsalPciSlotAddress(IxOsalPciDev pci_dev,UINT32 *bus,UINT32 *slot,UINT32 *func) +{ + struct pci_dev *pdev = (struct pci_dev *)pci_dev; + + /* Ensure PCI device handle is not NULL */ + if(!pdev) { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, + IX_OSAL_LOG_DEV_STDOUT, + "ixOsalPciSlotAddress: Null PCI handle \n", 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + + if(bus) { + *bus = pdev->bus->number; + } + if(slot) { + *slot = PCI_SLOT(pdev->devfn); + } + if(func) { + *func = PCI_FUNC(pdev->devfn); + } + return IX_SUCCESS; +} + +PUBLIC +INT32 ixOsalPciConfigReadByte(IxOsalPciDev pci_dev,UINT32 offset,UINT8* val) +{ + struct pci_dev *pdev = (struct pci_dev *)pci_dev; + + /* Ensure PCI device handle is not NULL */ + if(!pdev) { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, + IX_OSAL_LOG_DEV_STDOUT, + "ixOsalPciConfigReadByte: Null PCI handle \n", 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + + return pci_read_config_byte(pdev, offset, val); +} + +PUBLIC +INT32 ixOsalPciConfigReadShort(IxOsalPciDev pci_dev,UINT32 offset,UINT16* val) +{ + struct pci_dev *pdev = (struct pci_dev *)pci_dev; + + /* Ensure PCI device handle is not NULL */ + if(!pdev) { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, + IX_OSAL_LOG_DEV_STDOUT, + "ixOsalPciConfigReadShort: Null PCI handle \n", 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + + return pci_read_config_word(pdev, offset, val); +} + +PUBLIC +INT32 ixOsalPciConfigReadLong(IxOsalPciDev pci_dev,UINT32 offset,UINT32* val) +{ + struct pci_dev *pdev = (struct pci_dev *)pci_dev; + + /* Ensure PCI device handle is not NULL */ + if(!pdev) { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, + IX_OSAL_LOG_DEV_STDOUT, + "ixOsalPciConfigReadLong: Null PCI handle \n", 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + + return pci_read_config_dword(pdev, offset, val); +} + +PUBLIC +INT32 ixOsalPciConfigWriteByte(IxOsalPciDev pci_dev,UINT32 offset,UINT8 val) +{ + struct pci_dev *pdev = (struct pci_dev *)pci_dev; + + /* Ensure PCI device handle is not NULL */ + if(!pdev) { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, + IX_OSAL_LOG_DEV_STDOUT, + "ixOsalPciConfigWriteByte: Null PCI handle \n", 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + + return pci_write_config_byte(pdev, offset, val); +} + +PUBLIC +INT32 ixOsalPciConfigWriteShort(IxOsalPciDev pci_dev,UINT32 offset,UINT16 val) +{ + struct pci_dev *pdev = (struct pci_dev *)pci_dev; + + /* Ensure PCI device handle is not NULL */ + if(!pdev) { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, + IX_OSAL_LOG_DEV_STDOUT, + "ixOsalPciConfigWriteShort: Null PCI handle \n", 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + + return pci_write_config_word(pdev, offset, val); +} + +PUBLIC +INT32 ixOsalPciConfigWriteLong(IxOsalPciDev pci_dev,UINT32 offset,UINT32 val) +{ + struct pci_dev *pdev = (struct pci_dev *)pci_dev; + + /* Ensure PCI device handle is not NULL */ + if(!pdev) { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, + IX_OSAL_LOG_DEV_STDOUT, + "ixOsalPciConfigWriteLong: Null PCI handle \n", 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + + return pci_write_config_dword(pdev, offset, val); +} + +PUBLIC +void ixOsalPciDeviceFree(IxOsalPciDev pci_dev) +{ + struct pci_dev *pdev = (struct pci_dev *)pci_dev; + + /* Ensure PCI device handle is not NULL */ + if(!pdev) { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, + IX_OSAL_LOG_DEV_STDOUT, + "ixOsalPciDeviceFree: Null PCI handle \n", 0, 0, 0, 0, 0, 0); + return; + } + + /* + * this takes care of decrementing reference count so that + * the kernel may free the space when the count becomes + * zero. + */ + pci_dev_put(pdev); +} diff --git a/Acceleration/library/icp_utils/OSAL/common/os/linux/src/modules/ddk/IxOsalOsDdkSymbols.c b/Acceleration/library/icp_utils/OSAL/common/os/linux/src/modules/ddk/IxOsalOsDdkSymbols.c new file mode 100644 index 0000000..389ef28 --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/os/linux/src/modules/ddk/IxOsalOsDdkSymbols.c @@ -0,0 +1,101 @@ +/* + * @file IxOsalOsSymbols.c + * @author Intel Corporation + * @date 25-10-2005 + * + * @brief description goes here + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ +#ifdef OSAL_EXPORT_SYMBOLS + +#include "IxOsal.h" +#include <linux/module.h> + + +EXPORT_SYMBOL (ixOsalIrqBind); +EXPORT_SYMBOL (ixOsalIrqUnbind); +EXPORT_SYMBOL (ixOsalIrqLock); +EXPORT_SYMBOL (ixOsalIrqUnlock); +EXPORT_SYMBOL (ixOsalIrqLevelSet); +EXPORT_SYMBOL (ixOsalIrqEnable); +EXPORT_SYMBOL (ixOsalIrqDisable); + +EXPORT_SYMBOL (ixOsalCacheDmaMalloc); +EXPORT_SYMBOL (ixOsalCacheDmaFree); + +EXPORT_SYMBOL (ixOsalTimestampGet); +EXPORT_SYMBOL (ixOsalTimestampResolutionGet); +EXPORT_SYMBOL (ixOsalSysClockRateGet); + +#ifdef ENABLE_PCI +EXPORT_SYMBOL (ixOsalPciDeviceFind); +EXPORT_SYMBOL (ixOsalPciSlotAddress); +EXPORT_SYMBOL (ixOsalPciConfigReadByte); +EXPORT_SYMBOL (ixOsalPciConfigReadShort); +EXPORT_SYMBOL (ixOsalPciConfigReadLong); +EXPORT_SYMBOL (ixOsalPciConfigWriteByte); +EXPORT_SYMBOL (ixOsalPciConfigWriteShort); +EXPORT_SYMBOL (ixOsalPciConfigWriteLong); +EXPORT_SYMBOL (ixOsalPciDeviceFree); +#endif /* ENABLE_PCI */ + +#endif /* OSAL_EXPORT_SYMBOLS */ diff --git a/Acceleration/library/icp_utils/OSAL/common/os/linux/src/modules/ddk/component.mk b/Acceleration/library/icp_utils/OSAL/common/os/linux/src/modules/ddk/component.mk new file mode 100644 index 0000000..db5dd19 --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/os/linux/src/modules/ddk/component.mk @@ -0,0 +1,72 @@ +#@par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# Contact Information: +# Intel Corporation +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# +# Place holder + +ddk_os_CFLAGS := + +ddk_os_OBJ := IxOsalOsDdkCacheMMU.o \ + IxOsalOsDdkClk.o \ + IxOsalOsDdkSymbols.o \ + IxOsalOsDdkIrq.o + +ifneq (,$(findstring ENABLE_PCI,$(CFLAGS))) +ddk_os_OBJ += IxOsalOsDdkPci.o +endif + diff --git a/Acceleration/library/icp_utils/OSAL/common/os/linux/src/modules/ioMem/IxOsalOsIoMem.c b/Acceleration/library/icp_utils/OSAL/common/os/linux/src/modules/ioMem/IxOsalOsIoMem.c new file mode 100644 index 0000000..624bfd0 --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/os/linux/src/modules/ioMem/IxOsalOsIoMem.c @@ -0,0 +1,108 @@ +/** + * @file IsOsalOsIoMem.c + * + * @brief Linux-specific IO/Mem implementation. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +#include "IxOsal.h" + +#include <linux/version.h> + +#ifdef IX_OSAL_OS_LINUX_VERSION_2_6 + +#include <asm/page.h> + +#endif + +#include <asm/io.h> +#include <linux/ioport.h> + +#include "IxOsal.h" + +/* Linux-specific map/unmap functions to be used with dynamic maps */ +PUBLIC void +ixOsalLinuxMemMap (IxOsalMemoryMap * map) +{ + map->virtualAddress = (UINT32) ioremap (map->physicalAddress, map->size); +} + +PUBLIC void +ixOsalLinuxMemUnmap (IxOsalMemoryMap * map) +{ + iounmap ((void *) map->virtualAddress); + map->virtualAddress = 0; +} + +PUBLIC +UINT32 ixOsalIoRemap (UINT32 physAddr, UINT32 size) +{ + return ((UINT32) ioremap (physAddr, size)); +} + +PUBLIC +void ixOsalIoUnmap (UINT32 virtAddr, UINT32 size) +{ + iounmap ((void *) virtAddr); +} + diff --git a/Acceleration/library/icp_utils/OSAL/common/os/linux/src/modules/ioMem/IxOsalOsIoMemSymbols.c b/Acceleration/library/icp_utils/OSAL/common/os/linux/src/modules/ioMem/IxOsalOsIoMemSymbols.c new file mode 100644 index 0000000..a02142a --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/os/linux/src/modules/ioMem/IxOsalOsIoMemSymbols.c @@ -0,0 +1,87 @@ +/* + * @file IxOsalOsIoMemSymbols.c + * @author Intel Corporation + * @date 25-08-2004 + * + * @brief description goes here + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ +#ifdef OSAL_EXPORT_SYMBOLS + +#include "IxOsal.h" +#include <linux/module.h> + + +EXPORT_SYMBOL (ixOsalIoMemMap); +EXPORT_SYMBOL (ixOsalIoMemUnmap); +EXPORT_SYMBOL (ixOsalIoMemVirtToPhys); +EXPORT_SYMBOL (ixOsalIoMemPhysToVirt); +EXPORT_SYMBOL (ixOsalIoRemap); +EXPORT_SYMBOL (ixOsalIoUnmap); + +#ifdef IX_OSAL_MEM_MAP_GLUECODE + +EXPORT_SYMBOL (ixOsalGlueCodeMemoryMapInit); +EXPORT_SYMBOL (ixOsalGlueCodeMemoryMapUnInit); + +#endif /* IX_OSAL_MEM_MAP_GLUECODE */ +#endif /* XPORT_SYMBOLS */ diff --git a/Acceleration/library/icp_utils/OSAL/common/os/linux/src/modules/ioMem/component.mk b/Acceleration/library/icp_utils/OSAL/common/os/linux/src/modules/ioMem/component.mk new file mode 100644 index 0000000..4c585ed --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/os/linux/src/modules/ioMem/component.mk @@ -0,0 +1,66 @@ +# +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# Contact Information: +# Intel Corporation +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# + +ioMem_os_CFLAGS := + +ioMem_os_OBJ := IxOsalOsIoMem.o \ + IxOsalOsIoMemSymbols.o + diff --git a/Acceleration/library/icp_utils/OSAL/common/src/component.mk b/Acceleration/library/icp_utils/OSAL/common/src/component.mk new file mode 100644 index 0000000..7a93b7f --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/src/component.mk @@ -0,0 +1,60 @@ +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# Contact Information: +# Intel Corporation +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# +# place holder diff --git a/Acceleration/library/icp_utils/OSAL/common/src/core/IxOsalServices.c b/Acceleration/library/icp_utils/OSAL/common/src/core/IxOsalServices.c new file mode 100644 index 0000000..ff7aed1 --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/src/core/IxOsalServices.c @@ -0,0 +1,70 @@ +/** + * @file IxOsalServices.c + * + * @brief OS-independent implementation for some OSAL + * functions. + * + * + * Design Notes: + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + diff --git a/Acceleration/library/icp_utils/OSAL/common/src/core/IxOsalTime.c b/Acceleration/library/icp_utils/OSAL/common/src/core/IxOsalTime.c new file mode 100644 index 0000000..ee3bdbc --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/src/core/IxOsalTime.c @@ -0,0 +1,1027 @@ +/** + * @ingroup IxOsal + * @file IxOsalTime.c + * + * @brief OS-independant implementation for timer-related + * functions. + * + * + * Contents: + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +#include "IxOsal.h" + + + +/* include the OS independant implementation if native OS calls are not used */ +#ifndef USE_NATIVE_OS_TIMER_API + +/* Define a warning threshhold */ +#define IX_OSAL_TIMER_WARNING_THRESHOLD (IX_OSAL_MAX_TIMERS - 20) + +/* Define 100 ms max callback time */ +/* IX_MAX_TIMER_CALLBACK_TIME is in nsecs */ +#define IX_MAX_TIMER_CALLBACK_TIME (100000000) + +/* define IX_OSAL_MAX_TIMERS */ +#define IX_OSAL_MAX_TIMERS 100 + +/* define two semaphore values */ +#define IX_OSAL_TIMER_SEM_UNAVAILABLE 0 +#define IX_OSAL_TIMER_SEM_AVAILABLE 1 + +#define TIMER_INIT 10 + +/* Define Timer struct */ +typedef struct +{ + BOOL inUse; + BOOL isRepeating; + UINT32 id; + UINT32 priority; + void *callbackParam; + IxOsalTimeval period; + IxOsalTimeval expires; + IxOsalVoidFnVoidPtr callback; +} IxOsalTimerRec; + + +/* define private data structs */ +PRIVATE IxOsalTimerRec ixOsalTimers[IX_OSAL_MAX_TIMERS]; +PRIVATE IxOsalSemaphore ixOsalTimerRecalcSem; +PRIVATE IxOsalSemaphore ixOsalCriticalSectSem; +PRIVATE UINT32 lastTimerId = 0; +PRIVATE UINT32 ixOsalHigestTimeSlotUsed = 0; +PRIVATE BOOL ixOsalThresholdErr = FALSE; +PRIVATE UINT32 ixOsalTimerCbCnt = 0; +/* ixOsalTimerInited takes three values: TRUE, FALSE and TIMER_INIT */ +PRIVATE UINT8 ixOsalTimerInited = FALSE; + +/* + * Private function definitions + */ + +PRIVATE IX_STATUS +createNewTimer (IxOsalVoidFnVoidPtr func, void *param, UINT32 priority, + UINT32 interval, BOOL isRepeating, UINT32 * pTimerId); + +PRIVATE IxOsalTimerRec *evaluateTimerPriority (IxOsalTimerRec * first, + IxOsalTimerRec * second); + +PRIVATE IxOsalTimerRec *findNextTimeout (IxOsalTimeval now); + +PRIVATE void timerSleep (IxOsalTimerRec * nextTimer, IxOsalTimeval now); + +PRIVATE void rescheduleTimer (IxOsalTimerRec * nextTimer); + +PRIVATE void +callTimerCallback (IxOsalVoidFnVoidPtr callback, void *callbackParam); + +PRIVATE int timerLoop (void); + +PRIVATE IX_STATUS timerInit (void); + +#endif /* !USE_NATIVE_OS_TIMER_API */ + +PRIVATE UINT32 MAX_UINT32 = 0xFFFFFFFF; + +/* Return code if IxOsalTimavalToTicks called with too larg timeval */ +#define IX_OSAL_TIMEVAL_TOO_LARGE 0 +/* Public timeval functions */ + + +/** + * @ingroup IxOsal + * + * @brief Calculates the number of Ticks that correspond to + * the time interval provided + * + * @param IxOsalTimeval tv (in) - Time interval + * + * Calculates the number of Ticks that correspond to the time + * interval provided + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return The number of Ticks that correspond to the time + * interval provided + */ + +PUBLIC UINT32 +ixOsalTimevalToTicks (IxOsalTimeval tv) +{ + UINT32 tickPerSecs = 0; + UINT32 nanoSecsPerTick = 0; + UINT32 maxSecs = 0; + + tickPerSecs = ixOsalSysClockRateGet (); + nanoSecsPerTick = IX_OSAL_BILLION / tickPerSecs; + + /* + * Make sure we do not overflow + */ + maxSecs = (MAX_UINT32 / tickPerSecs) - (tv.nsecs / IX_OSAL_BILLION); + + if ( maxSecs < tv.secs ) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, + "ixOsalTimevalToTicks(): Timeval too high . Maximum value " + "allowed in seconds is %u < %u \n", + maxSecs , tv.secs, 0, 0, 0, 0); + return IX_OSAL_TIMEVAL_TOO_LARGE; + + } + + return ((tv.secs * tickPerSecs) + (tv.nsecs / nanoSecsPerTick)); +} + + + +/** + * @ingroup IxOsal + * + * @brief Calculates the time interval correspond to + * the number of Ticks provided provided + * + * @param UINT32 ticks (in) - Number of Ticks + * @param IxOsalTimeval * pTv(in/out) - Time interval + * +* Calculates the time interval correspond to + * the number of Ticks provided provided + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return Nothing + */ + + +PUBLIC void +ixOsalTicksToTimeval (UINT32 ticks, IxOsalTimeval * pTv) +{ + UINT32 tickPerSecs = 0; + UINT32 nanoSecsPerTick = 0; + /* + * Reset the time value + */ + pTv->secs = 0; + pTv->nsecs = 0; + + tickPerSecs = ixOsalSysClockRateGet (); + nanoSecsPerTick = IX_OSAL_BILLION / tickPerSecs; + + /* + * value less than 1 sec + */ + if (tickPerSecs > ticks) /* value less then 1 sec */ + { + pTv->nsecs = ticks * nanoSecsPerTick; + } + else + { + pTv->secs = ticks / tickPerSecs; + pTv->nsecs = (ticks % tickPerSecs) * nanoSecsPerTick; + } +} + +/* include the OS independant implementation if native OS calls are not used */ +#ifndef USE_NATIVE_OS_TIMER_API + +/* + * Public timer functions + */ + +/** + * @ingroup IxOsal + * + * @brief Schedules a single shot timer + * + * @param IxOsalTimer * timer (in) - Timer id + * UINT32 period - Period of timer + * UINT32 priority - Priority of the scheduled timer + * IxOsalVoidFnVoidPtr callback - Callback function for the scheduled timer + * void *param - Parameters of the callback function + * + * Schedules a single shot timer setting its priority and callback function and arguments + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return IX_SUCCESS on successfully scheduling the Timer, IX_FAIL otherwise + */ + +PUBLIC IX_STATUS +ixOsalSingleShotTimerSchedule (IxOsalTimer * timer, + UINT32 period, UINT32 priority, IxOsalVoidFnVoidPtr callback, void *param) +{ + IX_STATUS ixStatus = IX_FAIL; + + if (ixOsalTimerInited == FALSE) + { + /* + * Init timer + */ + ixStatus = timerInit (); + if (ixStatus != IX_SUCCESS) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, + "ixOsalSingleShotTimerSchedule: fail to init timer \n", + 0, 0, 0, 0, 0, 0); + ixOsalTimerInited = FALSE; + return IX_FAIL; + } + } + + if (ixOsalTimerInited == TIMER_INIT) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, + "ixOsalSingleShotTimerSchedule:Timer Init in Progress \n", + 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + + /* Call createNewTimer() with FALSE as we want a non-repeating timer */ + ixStatus = + createNewTimer (callback, param, priority, period, FALSE, timer); + + if (ixStatus != IX_SUCCESS) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, + "ixOsalSingleShotTimerSchedule: fail to create timer \n", + 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + + return IX_SUCCESS; +} + + +/** + * @ingroup IxOsal + * + * @brief Schedules a repeating timer + * + * @param IxOsalTimer * timer (in) - Timer id + * UINT32 period - Period of timer + * UINT32 priority - Priority of the scheduled timer + * IxOsalVoidFnVoidPtr callback - Callback function for the scheduled timer + * void *param - Parameters of the callback function + * + * Schedules a repeating timer setting its priority and callback function and arguments + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return IX_SUCCESS on success, IX_FAIL otherwise + */ + +PUBLIC IX_STATUS +ixOsalRepeatingTimerSchedule (IxOsalTimer * timer, + UINT32 period, UINT32 priority, IxOsalVoidFnVoidPtr callback, void *param) +{ + IX_STATUS ixStatus = IX_FAIL; + + if (ixOsalTimerInited == FALSE) + { + /* + * Init timer + */ + ixStatus = timerInit (); + if (ixStatus != IX_SUCCESS) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, + "ixOsalRepeatingTimerSchedule: fail to init timer \n", + 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + } + + if (ixOsalTimerInited == TIMER_INIT) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, + "ixOsalSingleShotTimerSchedule:Timer Init in Progress \n", + 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + + /* Call createNewTimer() with TRUE as we want a repeating timer */ + ixStatus = + createNewTimer (callback, param, priority, period, TRUE, timer); + + if (ixStatus != IX_SUCCESS) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, + "ixOsalRepeatingTimerSchedule: fail to create timer \n", + 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + + return IX_SUCCESS; +} + + +/** + * @ingroup IxOsal + * + * @brief Cancels a timer + * + * @param IxOsalTimer * timer (in) - Timer id + * + * Cancels a timer + * + * @li Reentrant: yes + * @li IRQ safe: yes + * + * @return IX_SUCCESS on successfully canceling the timer, IX_FAIL otherwise + */ + +PUBLIC IX_STATUS +ixOsalTimerCancel (IxOsalTimer * timer) +{ + UINT32 id; + UINT32 i; + IX_STATUS status = IX_FAIL; + + if (ixOsalTimerInited != TRUE) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, + "ixOsalTimerCancel: call schedule APIs first to start timer \n", + 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + + id = *timer; + + status = + ixOsalSemaphoreWait (&ixOsalCriticalSectSem, IX_OSAL_WAIT_FOREVER); + OSAL_ENSURE_CHECK_SUCCESS(status, "fail to get ixOsalCriticalSectSem "); + /* + * NOTE : there is no need to get the timer callback thread to wake + * up and recalculate. If this timer is the next to expire, then + * the timer callback thread will wake up but not find any timers to + * callback and will just go back to sleep again anyway. + */ + + /* + * NOTE2 : We cancel a timer by doing a linear search for the timer id. + * This is not terribly efficient but is the safest way to ensure that + * cancellations do not cancel the wrong timer by mistake. Also we + * assume timer cancellation does not occur often. If the timer to + * be cancelled is not found, an error is logged. + */ + + for (i = 0; i < ixOsalHigestTimeSlotUsed; i++) + { + if (ixOsalTimers[i].inUse && ixOsalTimers[i].id == id) + { + ixOsalTimers[i].inUse = FALSE; + break; + } + } + + status = ixOsalSemaphorePost (&ixOsalCriticalSectSem); + OSAL_ENSURE_CHECK_SUCCESS(status, "fail to ixOsalCriticalSectSem "); + + /* If i == ixOsalHigestTimeSlotUsed then we have exausted the ixOsalTimers[] array */ + if (i == ixOsalHigestTimeSlotUsed) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, + "ixOsalTimerCancel: Timer not found\n", 0, 0, 0, 0, 0, 0); + return IX_FAIL; + } + return IX_SUCCESS; +} + + + +/** + * @ingroup IxOsal + * + * @brief Displays a list with all the running timers and their parameters + * + * Displays a list with all the running timers and their parameters (handle, period, type, priority, callback and user parameter) + * + * @li Reentrant: yes + * @li IRQ safe: No + * + * @return Nothing + */ + + +PUBLIC void +ixOsalTimersShow (void) +{ + UINT32 i = 0; + UINT32 count = 0; + + if (ixOsalTimerInited != TRUE ) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, + "ixOsalTimersShow: call schedule APIs first to start timer \n", + 0, 0, 0, 0, 0, 0); + return; + } + + ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, + "Timers\n", 0, 0, 0, 0, 0, 0); + + for (i = 0; i < ixOsalHigestTimeSlotUsed; i++) + { + if (ixOsalTimers[i].inUse == TRUE) + { + ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, + "id=%d, repeat=%d, priority=%d\n", + ixOsalTimers[i].id, ixOsalTimers[i].isRepeating, + ixOsalTimers[i].priority, 0, 0, 0); + count++; + } + } + + ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, + "total=%d\n", count, 0, 0, 0, 0, 0); + + ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, + "num called=%u\n", ixOsalTimerCbCnt, 0, 0, 0, 0, 0); + + ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, + "Timer threshold reached Error Flag: %d\n", ixOsalThresholdErr, + 0, 0, 0, 0, 0); + +} + +/* Private functions only used in this file */ + +/** + * @ingroup Private + * + * @brief Initializes the timer API + * + * @param Nothing + * + * Initializes the timer API + * + * @li Reentrant: Yes + * @li IRQ safe: No + * + * @return Nothing + */ + +PRIVATE IX_STATUS +timerInit (void) +{ + IxOsalThread taskId; + IX_STATUS ixStatus; + IxOsalThreadAttr timerThreadAttr; + + /* Make sure that the API is not initialized or being initialized */ + if (ixOsalTimerInited != FALSE) { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, + "timerInit: API currently not to uninitialised state\n", + 0, 0, 0, 0, 0, 0); + + return IX_FAIL; + } + /* Set the flag that the API is being initialised */ + ixOsalTimerInited = TIMER_INIT; + + /* Initialize the semaphores */ + ixStatus = + ixOsalSemaphoreInit (&ixOsalCriticalSectSem, + IX_OSAL_TIMER_SEM_AVAILABLE); + OSAL_ENSURE_CHECK_SUCCESS(ixStatus, "fail to Init ixOsalCriticalSectSem "); + ixStatus = + ixOsalSemaphoreInit (&ixOsalTimerRecalcSem, + IX_OSAL_TIMER_SEM_AVAILABLE); + OSAL_ENSURE_CHECK_SUCCESS(ixStatus, "fail to Init ixOsalTimerRecalcSem"); + + /* Set the attributes of the timerThreadAttr in order to define the characteristics of the timer thread */ + + timerThreadAttr.stackSize = IX_OSAL_THREAD_DEFAULT_STACK_SIZE; + timerThreadAttr.priority = IX_OSAL_DEFAULT_THREAD_PRIORITY; + timerThreadAttr.name = "tOSALTimer"; + + /* Create the timer thread */ + ixStatus = ixOsalThreadCreate (&taskId, &timerThreadAttr, \ + (IxOsalVoidFnVoidPtr) timerLoop, NULL); + + + if (ixStatus != IX_SUCCESS) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, + "timerInit: fail to create thread \n", + 0, 0, 0, 0, 0, 0); + ixOsalTimerInited = FALSE; + return IX_FAIL; + } + + /* Start the thread now */ + ixStatus = ixOsalThreadStart (&taskId); + + OSAL_ENSURE_CHECK_SUCCESS(ixStatus, "fail to start Thread"); + + ixOsalTimerInited = TRUE; + + return IX_SUCCESS; +} + +/** + * @ingroup Private + * + * @brief Allocates a new timer + * + * @param IxOsalVoidFnVoidPtr func (in) - Callback function for the scheduled timer + * void *param (in) - Parameters of the callback function + * UINT32 priority (in) - Priority of the scheduled timer + * UINT32 interval (in) - Interval of the scheduled timer + * BOOL isRepeating (in) - Flag if a repeating timer + * UINT32 * timerId (in) - Timer id + * + * Allocates a new timer. It is used by Schedule and ScheduleRepeating. + * + * @li Reentrant: Yes + * @li IRQ safe: No + * + * @return IX_SUCCESS on successfully allocating a new timer, IX_FAIL otherwise + */ + +PRIVATE IX_STATUS +createNewTimer (IxOsalVoidFnVoidPtr func, void *param, UINT32 priority, + UINT32 interval, BOOL isRepeating, UINT32 * timerId) +{ + UINT32 i; + IX_STATUS status = IX_SUCCESS; + int osTicks; + IxOsalTimeval timeVal; + + osTicks = (int)ixOsalSysClockRateGet (); + /* + * Figure out how many milisecond per tick and compare against interval + */ + if (interval < (UINT32) (IX_OSAL_THOUSAND/ osTicks) || (interval == 0 )) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, + "client requested time interval (%d) finer than clock ticks\n", + interval, 0, 0, 0, 0, 0); + return IX_FAIL; + } + + /* + * Increment timerId + */ + *timerId = ++lastTimerId; + + status = + ixOsalSemaphoreWait (&ixOsalCriticalSectSem, IX_OSAL_WAIT_FOREVER); + OSAL_ENSURE_CHECK_SUCCESS(status, "fail to start Thread"); + + for (i = 0; i < IX_OSAL_MAX_TIMERS; i++) + { + if (!ixOsalTimers[i].inUse) + { + break; + } + } + + if ((i >= IX_OSAL_TIMER_WARNING_THRESHOLD) + && (ixOsalThresholdErr == FALSE)) + { + /* + * This error serves as an early indication that the number of + * available timer slots will need to be increased. This is done + * by increasing IX_OSAL_MAX_TIMERS + */ + ixOsalLog (IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDOUT, + "Timer threshold reached. Only %d timer slots now available\n", + IX_OSAL_MAX_TIMERS - i, 0, 0, 0, 0, 0); + ixOsalThresholdErr = TRUE; + } + + if (i == IX_OSAL_MAX_TIMERS) + { + /* + * If you get this error, increase MAX_TIMERS above + */ + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, + "Out of timer slots %d used - request ignored\n", + i, 0, 0, 0, 0, 0); + status = ixOsalSemaphorePost (&ixOsalCriticalSectSem); + OSAL_ENSURE_CHECK_SUCCESS(status, "fail to post Semaphore"); + status = IX_FAIL; + } + else + { + ixOsalTimers[i].inUse = TRUE; + + IX_OSAL_MS_TO_TIMEVAL (interval, &timeVal); + + ixOsalTimers[i].period = timeVal; + ixOsalTimers[i].isRepeating = isRepeating; + ixOsalTimeGet (&(ixOsalTimers[i].expires)); + IX_OSAL_TIME_ADD ((ixOsalTimers[i].expires), (ixOsalTimers[i].period)); + ixOsalTimers[i].priority = priority; + ixOsalTimers[i].callback = func; + ixOsalTimers[i].callbackParam = param; + ixOsalTimers[i].id = *timerId; + + if ( i >= ixOsalHigestTimeSlotUsed) + { + ixOsalHigestTimeSlotUsed = i + 1; + } + + status = ixOsalSemaphorePost (&ixOsalTimerRecalcSem); + OSAL_ENSURE_CHECK_SUCCESS(status, "fail to post Semaphore"); + status = ixOsalSemaphorePost (&ixOsalCriticalSectSem); + OSAL_ENSURE_CHECK_SUCCESS(status, "fail to post Semaphore"); + } + + return status; +} + +/** + * @ingroup Private + * + * @brief Evaluates the priority between two timer + * + * @param IxOsalTimerRec * first (in) - Timer record + * IxOsalTimerRec * second (in) + * + * Evaluates the priority between two timers + * + * @li Reentrant: Yes + * @li IRQ safe: No + * + * @return The timer record of the two that has higher priority + */ + + +PRIVATE IxOsalTimerRec * +evaluateTimerPriority (IxOsalTimerRec * first, IxOsalTimerRec * second) +{ + IX_OSAL_ASSERT (first != NULL || second != NULL); + + if (first == NULL) + { + return second; + } + + if (second == NULL) + { + return first; + } + + /* + * For now we just compare the values of the priority with lower + * values getting higher priority. + * + * If someone needs to change priorities of different purposes without + * modifying the order of the enums, then more code will be required + * here. + */ + + return ((first->priority <= second->priority) ? first : second); +} + + +/** + * @ingroup Private + * + * @brief Evaluates the next timeout + * + * @param IxOsalTimeval now(in) - Timer record + * + * Evaluates the next timer about to go off. We do this by starting with a time + * infinitely far in the future and successively finding better timers + * (ones that go off sooner). + * + * If a timer is found that has already expired, the flag bestTimerExpired is + * set. If another timer is found that has also expired, their respective + * priorities are compared using the function evaluateTimerPriority() + * + * @li Reentrant: Yes + * @li IRQ safe: No + * + * @return The record of the next expiring timer, or NULL if there is no next expiring timer + */ + +PRIVATE IxOsalTimerRec * +findNextTimeout (IxOsalTimeval now) +{ + IxOsalTimeval timeoutAt = { ULONG_MAX, LONG_MAX }; + UINT32 i; + IxOsalTimerRec *bestTimer = NULL; + BOOL bestTimerExpired = FALSE; + BOOL thisTimerExpired = FALSE; + + for (i = 0; i < ixOsalHigestTimeSlotUsed; i++) + { + if (ixOsalTimers[i].inUse) + { + thisTimerExpired = FALSE; + + /* + * Check if this timer has expired, + * i.e. 'now' must be greater than ixOsalTimers[i].expired + */ + + if (!IX_OSAL_TIME_GT (ixOsalTimers[i].expires, now)) + { + thisTimerExpired = TRUE; + } + + /* + * If more than one timer has expired, determine + * which callback to call first based on a priority scheme + * i.e. the bestTimer + */ + + if ((bestTimerExpired && thisTimerExpired) || + IX_OSAL_TIME_EQ (ixOsalTimers[i].expires, timeoutAt)) + { + bestTimer = + evaluateTimerPriority (bestTimer, &ixOsalTimers[i]); + timeoutAt = bestTimer->expires; + } + else if (IX_OSAL_TIME_LT (ixOsalTimers[i].expires, timeoutAt)) + { + bestTimer = &ixOsalTimers[i]; + timeoutAt = ixOsalTimers[i].expires; + } + + /* + * bestTimer can not be NULL here because any timer will + * have a shorter timeout than the default. + */ + if(bestTimer != NULL) + { + if ((IX_OSAL_TIME_GT (bestTimer->expires, now)) != TRUE) + { + bestTimerExpired = TRUE; + } + } + } + } + return bestTimer; +} + + +/** + * @ingroup Private + * + * @brief Puts a timer to sleep + * + * @param IxOsalTimerRec * nextTimer (in) - Timer record + * IxOsalTimeval now(in) - Timeval + * + * Puts a timer to sleep + * + * @li Reentrant: Yes + * @li IRQ safe: No + * + * @return Nothing + */ + +PRIVATE void +timerSleep (IxOsalTimerRec * nextTimer, IxOsalTimeval now) +{ + UINT32 milliseconds; + IxOsalTimeval temp; + + if (nextTimer == NULL) + { + ixOsalSemaphoreWait (&ixOsalTimerRecalcSem, IX_OSAL_WAIT_FOREVER); + } + else + { + temp.secs = nextTimer->expires.secs; + temp.nsecs = nextTimer->expires.nsecs; + + IX_OSAL_TIME_SUB (temp, now); + + milliseconds = IX_OSAL_TIMEVAL_TO_MS (temp); + + /* + * We should sleep but the period is less than a tick + * * away, rounding up. + */ + if (milliseconds == 0) + { + milliseconds = 1; + } + + /* The post hapens in the timerCreate function. So far this has not caused problems but + maybe there is a clearer way to do this*/ + ixOsalSemaphoreWait (&ixOsalTimerRecalcSem, milliseconds); + } +} + +/** + * @ingroup Private + * + * @brief Reschedules a timer + * + * @param IxOsalTimerRec * nextTimer (in) - Timer record + * + * Reschedules a timer + * + * @li Reentrant: Yes + * @li IRQ safe: No + * + * @return Nothing + */ + +PRIVATE void +rescheduleTimer (IxOsalTimerRec * nextTimer) +{ + if (nextTimer->isRepeating) + { + IX_OSAL_TIME_ADD (nextTimer->expires, nextTimer->period); + } + else + { + nextTimer->inUse = FALSE; + } +} + +/** + * @ingroup Private + * + * @brief Calls the timer callback function + * + * @param IxOsalVoidFnVoidPtr callback (in) - Pointer to the callback function + * @param void *callbackParam (in) - Parameters of the callback function + * + * Calls the timer callback function + * + * + * @li Reentrant: Yes + * @li IRQ safe: No + * + * @return Nothing + */ + +PRIVATE void +callTimerCallback (IxOsalVoidFnVoidPtr callback, void *callbackParam) +{ + IxOsalTimeval timevalCbBegin, timevalCbFinish; + static BOOL errorReported = FALSE; + + ixOsalTimerCbCnt++; + ixOsalTimeGet (&timevalCbBegin); + + callback (callbackParam); + + ixOsalTimeGet (&timevalCbFinish); + + IX_OSAL_TIME_SUB (timevalCbFinish, timevalCbBegin); + + /* + * Maximum time spent in a call-back is defined as 100 millisec. (one + * tenth of a second). + */ + + + if ((timevalCbFinish.nsecs > IX_MAX_TIMER_CALLBACK_TIME) + || (timevalCbFinish.secs > 0)) + { + if (!errorReported) + { + ixOsalLog (IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDOUT, + "Slow timer callback - %d Secs, %d nSecs \n", + timevalCbFinish.secs, timevalCbFinish.nsecs, 0, 0, 0, 0); + errorReported = TRUE; + } + } +} + + + +/** + * @ingroup Private + * + * @brief Main timer thread + * + * @param Nothing + * + * This is a thread that is being spawned by OSAL for the timer API. It is an infinite loop that + * constantly monitors timers if they go off and if so it calls their callback functions. + * + * @li Reentrant: Yes + * @li IRQ safe: No + * + * @return IX_FAIL if failed, otherwise it will loop for ever + */ + +PRIVATE int +timerLoop (void) +{ + IxOsalTimeval now; + IxOsalVoidFnVoidPtr callback = NULL; + void *callbackParam = NULL; + IxOsalTimerRec *nextTimer; + IX_STATUS status=IX_SUCCESS; + + while (status==IX_SUCCESS) + { + /* + * This loop catches all cases in a simple way. If multiple + * timers expire together, then lowest will be <=0 until all + * have been processed and the queue get won't get invoked. + */ + + status = + ixOsalSemaphoreWait (&ixOsalCriticalSectSem, + IX_OSAL_WAIT_FOREVER); + OSAL_ENSURE_CHECK_SUCCESS(status, "fail to get Semaphore"); + + ixOsalTimeGet (&now); + nextTimer = findNextTimeout (now); + + if ((nextTimer == NULL) + || IX_OSAL_TIME_GT ((nextTimer->expires), (now))) + { + callback = NULL; + } + else + { + rescheduleTimer (nextTimer); + callback = nextTimer->callback; + callbackParam = nextTimer->callbackParam; + } + + status = ixOsalSemaphorePost (&ixOsalCriticalSectSem); + OSAL_ENSURE_CHECK_SUCCESS(status, "fail to post Semaphore"); + + if (callback != NULL) + { + callTimerCallback (callback, callbackParam); + } + else + { + timerSleep (nextTimer, now); + } + } + return IX_FAIL; +} + +#endif /* !USE_NATIVE_OS_TIMER_API */ diff --git a/Acceleration/library/icp_utils/OSAL/common/src/core/component.mk b/Acceleration/library/icp_utils/OSAL/common/src/core/component.mk new file mode 100644 index 0000000..6d4749d --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/src/core/component.mk @@ -0,0 +1,68 @@ +# +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# Contact Information: +# Intel Corporation +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# + +# Place holder +core_CFLAGS := + +#core_OBJ := +core_OBJ := IxOsalTime.o IxOsalServices.o + + diff --git a/Acceleration/library/icp_utils/OSAL/common/src/modules/ddk/component.mk b/Acceleration/library/icp_utils/OSAL/common/src/modules/ddk/component.mk new file mode 100644 index 0000000..d91c7fa --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/src/modules/ddk/component.mk @@ -0,0 +1,64 @@ +# +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# Contact Information: +# Intel Corporation +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# + +ddk_CFLAGS := + +ddk_OBJ := diff --git a/Acceleration/library/icp_utils/OSAL/common/src/modules/ioMem/IxOsalIoMem.c b/Acceleration/library/icp_utils/OSAL/common/src/modules/ioMem/IxOsalIoMem.c new file mode 100644 index 0000000..83dd807 --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/src/modules/ioMem/IxOsalIoMem.c @@ -0,0 +1,398 @@ +/** + * @file IxOsalIoMem.c + * + * @brief OS-independent IO/Mem implementation + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +/* Access to the global mem map is only allowed in this file */ +#define IXOSALIOMEM_C + +/*#include "IxOsalDdk.h"*/ +#include "IxOsal.h" + +#define SEARCH_PHYSICAL_ADDRESS (1) +#define SEARCH_VIRTUAL_ADDRESS (2) + +/* + * Searches for map using one of the following criteria: + * + * - enough room to include a zone starting with the physical "requestedAddress" of size "size" (for mapping) + * - includes the virtual "requestedAddress" in its virtual address space (already mapped, for unmapping) + * - correct coherency + * + * Returns a pointer to the map or NULL if a suitable map is not found. + */ +PRIVATE IxOsalMemoryMap * +ixOsalMemMapFind (UINT32 requestedAddress, UINT32 size, + UINT32 searchCriteria, UINT32 requestedEndianType) +{ + UINT32 mapIndex; + static BOOL initialized = FALSE; + + UINT32 numMapElements = + sizeof (ixOsalGlobalMemoryMap) / sizeof (IxOsalMemoryMap); + + /* + * Initialize the memory mapping table before use + */ + if (!initialized) + { + IX_STATUS status; + status = ixOsalMemMapInit(ixOsalGlobalMemoryMap, numMapElements); + IX_OSAL_ASSERT (status == IX_SUCCESS); + initialized = TRUE; + } + + for (mapIndex = 0; mapIndex < numMapElements; mapIndex++) + { + IxOsalMemoryMap *map = &ixOsalGlobalMemoryMap[mapIndex]; + + if (searchCriteria == SEARCH_PHYSICAL_ADDRESS + && requestedAddress >= map->physicalAddress + && (requestedAddress + size) <= (map->physicalAddress + map->size) + && (map->mapEndianType & requestedEndianType) != 0) + { + return map; + } + else if (searchCriteria == SEARCH_VIRTUAL_ADDRESS + && requestedAddress >= map->virtualAddress + && requestedAddress <= (map->virtualAddress + map->size) + && (map->mapEndianType & requestedEndianType) != 0) + { + return map; + } + else if (searchCriteria == SEARCH_PHYSICAL_ADDRESS) + { +#ifndef BOOTLOADER_BLD + ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3, IX_OSAL_LOG_DEV_STDOUT, + "Osal: Checking [phys addr 0x%x:size 0x%x:endianType %d]\n", + map->physicalAddress, map->size, map->mapEndianType, 0, 0, 0); +#endif + } + } + + /* + * not found + */ + return NULL; +} + +/* + * This function maps an I/O mapped physical memory zone of the given size + * into a virtual memory zone accessible by the caller and returns a cookie - + * the start address of the virtual memory zone. + * IX_OSAL_MMAP_PHYS_TO_VIRT should NOT therefore be used on the returned + * virtual address. + * The memory zone is to be unmapped using ixOsalMemUnmap once the caller has + * finished using this zone (e.g. on driver unload) using the cookie as + * parameter. + * The IX_OSAL_READ/WRITE_LONG/SHORT macros should be used to read and write + * the mapped memory, adding the necessary offsets to the address cookie. + * + * Note: this function is not to be used directly. Use IX_OSAL_MEM_MAP + * instead. + */ +PUBLIC void * +ixOsalIoMemMap (UINT32 requestedAddress, + UINT32 size, IxOsalMapEndianessType requestedEndianType) +{ + IxOsalMemoryMap *map; + +#ifndef BOOTLOADER_BLD + ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3, + IX_OSAL_LOG_DEV_STDOUT, + "OSAL: Mapping [addr 0x%x:size 0x%x:endianType %d]\n", + requestedAddress, size, requestedEndianType, 0, 0, 0); +#endif + + if (requestedEndianType == IX_OSAL_LE) + { + IX_OSAL_OEM_COMPONENT_COHERENCY_MODE_CHECK( + ixOsalIoMemMap, return NULL); + } + + map = ixOsalMemMapFind (requestedAddress, + size, SEARCH_PHYSICAL_ADDRESS, requestedEndianType); + if (map != NULL) + { + UINT32 offset = requestedAddress - map->physicalAddress; + +#ifndef BOOTLOADER_BLD + + ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3, IX_OSAL_LOG_DEV_STDOUT, + "OSAL: Found map [", 0, 0, 0, 0, 0, 0); + ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3, + IX_OSAL_LOG_DEV_STDOUT, map->name, 0, 0, 0, 0, 0, 0); + ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3, + IX_OSAL_LOG_DEV_STDOUT, + ":addr 0x%x: virt 0x%x:size 0x%x:ref %d:endianType %d]\n", + map->physicalAddress, map->virtualAddress, + map->size, map->refCount, map->mapEndianType, 0); +#endif + + if (map->type == IX_OSAL_DYNAMIC_MAP && map->virtualAddress == 0) + { + if (map->mapFunction != NULL) + { + map->mapFunction (map); + + if (map->virtualAddress == 0) + { + /* + * failed + */ + ixOsalLog (IX_OSAL_LOG_LVL_FATAL,IX_OSAL_LOG_DEV_STDERR, + "OSAL: Remap failed[addr 0x%x:size 0x%x:endianType %d]\n", + requestedAddress, size, requestedEndianType, 0, 0, 0); + return NULL; + } + } + else + { + /* + * error, no map function for a dynamic map + */ + ixOsalLog (IX_OSAL_LOG_LVL_FATAL, IX_OSAL_LOG_DEV_STDERR, + "OSAL: No map function for a dynamic map - " + "[addr 0x%x:size 0x%x:endianType %d]\n", + requestedAddress, size, requestedEndianType, 0, 0, 0); + + return NULL; + } + } + + /* + * increment reference count + */ + map->refCount++; + + return (void *) (map->virtualAddress + offset); + } + + /* + * requested address is not described in the global memory map + */ + ixOsalLog (IX_OSAL_LOG_LVL_FATAL, IX_OSAL_LOG_DEV_STDERR, + "OSAL: No mapping found - [addr 0x%x:size 0x%x:endianType %d]\n", + requestedAddress, size, requestedEndianType, 0, 0, 0); + return NULL; +} + +/* + * This function unmaps a previously mapped I/O memory zone using + * the cookie obtained in the mapping operation. The memory zone in question + * becomes unavailable to the caller once unmapped and the cookie should be + * discarded. + * + * This function cannot fail if the given parameter is correct and does not + * return a value. + * + * Note: this function is not to be used directly. Use IX_OSAL_MEM_UNMAP + * instead. + */ +PUBLIC void +ixOsalIoMemUnmap (UINT32 requestedAddress, UINT32 endianType) +{ + IxOsalMemoryMap *map; + + /* This bounds checking is unnecessary since IX_OSAL_LE is + * a valid endiantype for IA platform + */ + if (endianType == IX_OSAL_LE) + { + IX_OSAL_OEM_COMPONENT_COHERENCY_MODE_CHECK(ixOsalIoMemUnmap, return ); + } + + if (requestedAddress == 0) + { + /* + * invalid virtual address + */ + return; + } + + map = + ixOsalMemMapFind (requestedAddress, 0, SEARCH_VIRTUAL_ADDRESS, + endianType); + + if (map != NULL) + { + if (map->refCount > 0) + { + /* + * decrement reference count + */ + map->refCount--; + + if (map->refCount == 0) + { + /* + * no longer used, deallocate + */ + if (map->type == IX_OSAL_DYNAMIC_MAP + && map->unmapFunction != NULL) + { + map->unmapFunction (map); + } + } + } + } + else + { + ixOsalLog (IX_OSAL_LOG_LVL_WARNING, + IX_OSAL_LOG_DEV_STDERR, + "OSAL: ixOsServMemUnmap didn't find the requested map " + "[virt addr 0x%x: endianType %d], ignoring call\n", + requestedAddress, endianType, 0, 0, 0, 0); + } +} + +#if !defined(__linux_user) && !defined(__freebsd_user) + +/* + * This function Converts a virtual address into a physical + * address, including the dynamically mapped memory. + * + * Parameters virtAddr - virtual address to convert + * Return value: corresponding physical address, or NULL + * if there is no physical address addressable + * by the given virtual address + * OS: VxWorks, Linux, WinCE, QNX, eCos + * Reentrant: Yes + * IRQ safe: Yes + */ +PUBLIC UINT32 +ixOsalIoMemVirtToPhys (UINT32 virtualAddress, UINT32 requestedCoherency) +{ + IxOsalMemoryMap *map = + ixOsalMemMapFind (virtualAddress, 0, SEARCH_VIRTUAL_ADDRESS, + requestedCoherency); + + if (map != NULL) + { + return map->physicalAddress + virtualAddress - map->virtualAddress; + } + else + { + return (UINT32) IX_OSAL_MMU_VIRT_TO_PHYS (virtualAddress); + } +} +#if (!defined(__freebsd)) +/* + * This function Converts a virtual address into a physical + * address, including the dynamically mapped memory. + * + * Parameters virtAddr - virtual address to convert + * Return value: corresponding physical address, or NULL + * if there is no physical address addressable + * by the given virtual address + * OS: VxWorks, Linux, WinCE, QNX, eCos + * Reentrant: Yes + * IRQ safe: Yes + */ + +PUBLIC UINT32 +ixOsalIoMemPhysToVirt (UINT32 physicalAddress, UINT32 requestedCoherency) +{ + IxOsalMemoryMap *map = + ixOsalMemMapFind (physicalAddress, 0, SEARCH_PHYSICAL_ADDRESS, + requestedCoherency); + + if (map != NULL) + { + return map->virtualAddress + physicalAddress - map->physicalAddress; + } + else + { + return (UINT32) IX_OSAL_MMU_PHYS_TO_VIRT (physicalAddress); + } +} +#endif /*!defined(__freebsd)*/ +#endif /* linux_user || freebsd_user */ + +#ifdef IX_OSAL_MEM_MAP_GLUECODE +/* + * Gluecode for Memory Map + */ +PUBLIC void +ixOsalGlueCodeMemoryMapInit(UINT32 index,UINT32 phyAddr, + UINT32 mapSize,UINT32 virtAddr) +{ + ixOsalGlobalMemoryMap[index].physicalAddress = phyAddr; + ixOsalGlobalMemoryMap[index].size = mapSize; + ixOsalGlobalMemoryMap[index].virtualAddress = virtAddr; + strncpy(ixOsalGlobalMemoryMap[index].name, + "GLUE_CODE_MEMORY_MAP", + OSAL_OS_GET_STRING_LENGTH("GLUE_CODE_MEMORY_MAP")); +} + +PUBLIC void +ixOsalGlueCodeMemoryMapUnInit(UINT32 index,UINT32 *virtAddr) +{ + *virtAddr = ixOsalGlobalMemoryMap[index].virtualAddress; + + ixOsalGlobalMemoryMap[index].virtualAddress = 0; +} + +#endif /* IX_OSAL_MEM_MAP_GLUECODE */ diff --git a/Acceleration/library/icp_utils/OSAL/common/src/modules/ioMem/component.mk b/Acceleration/library/icp_utils/OSAL/common/src/modules/ioMem/component.mk new file mode 100644 index 0000000..afab94f --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/common/src/modules/ioMem/component.mk @@ -0,0 +1,64 @@ +# +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# Contact Information: +# Intel Corporation +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# + +ioMem_CFLAGS := + +ioMem_OBJ := IxOsalIoMem.o diff --git a/Acceleration/library/icp_utils/OSAL/platforms/EP805XX/include/IxOsalOem.h b/Acceleration/library/icp_utils/OSAL/platforms/EP805XX/include/IxOsalOem.h new file mode 100644 index 0000000..f46e5dd --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/platforms/EP805XX/include/IxOsalOem.h @@ -0,0 +1,162 @@ +/** + * @file IxOsalOem.h + * + * @brief this file contains platform-specific defines. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +#ifndef IxOsalOem_H +#define IxOsalOem_H + +#include "IxOsalTypes.h" + +/* OS-specific header for Platform package */ + +#include "IxOsalOsOem.h" + + +/* + * Platform Name + */ +#define IX_OSAL_PLATFORM_NAME EP805XX + +/* + * IRQ PMU for EP805XX - place holder + */ +#define IRQ_EP805XX_IA_PMU 0 + +/* + * Cache line size + */ +#define IX_OSAL_CACHE_LINE_SIZE (64) + + +/* Various default module inclusions */ + +/* From IxOsalIoMem.h */ +#define IX_OSAL_OEM_SWAP_LONG(wData) ((wData >> 24) | (((wData >> 16) & 0xFF) << 8) | (((wData >> 8) & 0xFF) << 16) | ((wData & 0xFF) << 24)) + + +/* PF specific definitions */ +#define IX_OSAL_READ_LONG_LE(wAddr) IX_OSAL_LE_BUSTOIAL(IX_OSAL_READ_LONG_IO((volatile UINT32 *) (wAddr) )) +#define IX_OSAL_READ_SHORT_LE(sAddr) IX_OSAL_LE_BUSTOIAS(IX_OSAL_READ_SHORT_IO((volatile UINT16 *) (sAddr) )) +#define IX_OSAL_READ_BYTE_LE(bAddr) IX_OSAL_LE_BUSTOIAB(IX_OSAL_READ_BYTE_IO((volatile UINT8 *) (bAddr) )) +#define IX_OSAL_WRITE_LONG_LE(wAddr, wData) IX_OSAL_WRITE_LONG_IO((volatile UINT32 *) (wAddr), IX_OSAL_LE_IATOBUSL((UINT32) (wData) )) +#define IX_OSAL_WRITE_SHORT_LE(sAddr, sData) IX_OSAL_WRITE_SHORT_IO((volatile UINT16 *) (sAddr), IX_OSAL_LE_IATOBUSS((UINT16) (sData) )) +#define IX_OSAL_WRITE_BYTE_LE(bAddr, bData) IX_OSAL_WRITE_BYTE_IO((volatile UINT8 *) (bAddr), IX_OSAL_LE_IATOBUSB((UINT8) (bData) )) + + +#define IX_OSAL_LE_IATOBUSL(wData) (wData) +#define IX_OSAL_LE_IATOBUSS(sData) (sData) +#define IX_OSAL_LE_IATOBUSB(bData) (bData) +#define IX_OSAL_LE_BUSTOIAL(wData) (wData) +#define IX_OSAL_LE_BUSTOIAS(sData) (sData) +#define IX_OSAL_LE_BUSTOIAB(bData) (bData) + + +/* Platform-specific fastmutex implementation */ +//PUBLIC IX_STATUS ixOsalOemFastMutexTryLock (IxOsalFastMutex * mutex); + +/* Platform-specific init (MemMap) */ +PUBLIC IX_STATUS +ixOsalOemInit (void); + +/* Platform-specific unload (MemMap) */ +PUBLIC void +ixOsalOemUnload (void); + +#ifdef ENABLE_IOMEM + +/** + * Memory mapping table init. This function is public within OSAL only. + * It is a dummy interface for EP805XX as dynamic memory map is done by HAL or + drivers instead of OSAL */ +PUBLIC IX_STATUS +ixOsalMemMapInit (IxOsalMemoryMap *map, UINT32 numElement); + +#endif /* ENABLE_IOMEM */ + +/* Default implementations */ + +PUBLIC UINT32 +ixOsalEP805XXSharedTimestampGet (void); + +UINT32 +ixOsalEP805XXSharedTimestampRateGet (void); + +UINT32 +ixOsalEP805XXSharedSysClockRateGet (void); + +void +ixOsalEP805XXSharedTimeGet (IxOsalTimeval * tv); + + +INT32 +ixOsalEP805XXSharedLog (UINT32 level, UINT32 device, char *format, + int arg1, int arg2, int arg3, int arg4, + int arg5, int arg6); + +/* A Null macro since IX_OSAL_LE is a valid endianness type for IA */ +#define IX_OSAL_OEM_COMPONENT_COHERENCY_MODE_CHECK(fun_name, return_exp) + +#endif /* IxOsalOem_H */ diff --git a/Acceleration/library/icp_utils/OSAL/platforms/EP805XX/os/linux/include/IxOsalOsOem.h b/Acceleration/library/icp_utils/OSAL/platforms/EP805XX/os/linux/include/IxOsalOsOem.h new file mode 100644 index 0000000..435efb8 --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/platforms/EP805XX/os/linux/include/IxOsalOsOem.h @@ -0,0 +1,210 @@ +/** + * @file IxOsalOsOem.h + * + * @brief OS and platform specific definitions + * + * Design Notes: + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +#ifndef IxOsalOsOem_H +#define IxOsalOsOem_H + +/* This is used in IxOsalOs.h */ +#include <asm/io.h> + +/* This is used in IxOsalOs.h */ +#include <linux/pci.h> + +/* This is used in IxOsalOsTypes.h*/ +#include <asm/atomic.h> + +/* + * Important Note: The current #defines in this file are just place-holders and should + * be replaced and filled once the actual values are available. + * This file has portions that has glue-code/logic/stubs and should cease to exist in + * the final code. + */ + +/* physical addresses to be used when requesting memory with IX_OSAL_MEM_MAP */ +#define IX_OSAL_EP805XX_DUMMY_PHYS_BASE (0x0) + +/* map sizes to be used when requesting memory with IX_OSAL_MEM_MAP */ +#define IX_OSAL_EP805XX_DUMMY_MAP_SIZE (0x0) /**< DUMMY map size */ + +/* virtual addresses to be used when requesting memory with IX_OSAL_MEM_MAP */ +#define IX_OSAL_EP805XX_DUMMY_VIRT_BASE (0x0) + +/* + * Interrupt Levels + */ +#define IX_OSAL_EP805XX_DUMMY_IRQ_LVL (0x0) + + +/* + * IRQ for PMU + */ +/*#define IX_OSAL_OEM_IRQ_PMU (0x0)*/ +#define IX_OSAL_OEM_IRQ_PMU IRQ_EP805XX_IA_PMU + +/* + * OS name retrieval + */ +#define IX_OSAL_OEM_OS_NAME_GET(name, limit) \ +ixOsalOsEP805XXNameGet((INT8*)(name), (INT32) (limit)) + +/* + * OS version retrieval + */ +#define IX_OSAL_OEM_OS_VERSION_GET(version, limit) \ +ixOsalOsEP805XXVersionGet((INT8*)(version), (INT32) (limit)) + +/* + * Function to retrieve the OS name + */ +PUBLIC IX_STATUS ixOsalOsEP805XXNameGet(INT8* osName, INT32 maxSize); + +/* + * Function to retrieve the OS version + */ +PUBLIC IX_STATUS ixOsalOsEP805XXVersionGet(INT8* osVersion, INT32 maxSize); + +/* + * TimestampGet + */ +PUBLIC UINT32 ixOsalOsEP805XXTimestampGet (void); + +/* + * Timestamp + */ +#define IX_OSAL_OEM_TIMESTAMP_GET ixOsalOsEP805XXTimestampGet + + +/* + * Timestamp resolution + */ +PUBLIC UINT32 ixOsalOsEP805XXTimestampResolutionGet (void); + +#define IX_OSAL_OEM_TIMESTAMP_RESOLUTION_GET ixOsalOsEP805XXTimestampResolutionGet + +/* + * Retrieves the system clock rate + */ +PUBLIC UINT32 ixOsalOsEP805XXSysClockRateGet (void); + +#define IX_OSAL_OEM_SYS_CLOCK_RATE_GET ixOsalOsEP805XXSysClockRateGet + +/* + * required by FS but is not really platform-specific. + */ +#define IX_OSAL_OEM_TIME_GET(pTv) ixOsalTimeGet(pTv) + +/* + * Get PC + */ +#define IX_OSAL_OEM_GET_PC(regs) ixOsalOsEP805XXGetPc(regs) + +#ifdef ENABLE_IOMEM + +/* linux map/unmap functions */ +PUBLIC void ixOsalLinuxMemMap (IxOsalMemoryMap * map); + +PUBLIC void ixOsalLinuxMemUnmap (IxOsalMemoryMap * map); + +#endif /* ENABLE_IOMEM */ + +#include "IxOsalOsOemSys.h" + + +void ixOsalEP805XXSetInterruptedPc(struct pt_regs *regs); + +#define IX_OSAL_OEM_SET_INTERRUPTED_PC(regs) ixOsalEP805XXSetInterruptedPc(regs) + +/* ===================== End - Irq ====================== */ + + +#define IX_OSAL_OEM_HOST_TO_NW_16(uData) cpu_to_be16(uData) + +#define IX_OSAL_OEM_HOST_TO_NW_32(uData) cpu_to_be32(uData) + +#define IX_OSAL_OEM_HOST_TO_NW_64(uData) cpu_to_be64(uData) + +#define IX_OSAL_OEM_HOST_TO_NW_128(uDataSrc, uDataDest) \ + (uDataDest)->mUINT32[0] = IX_OSAL_OEM_HOST_TO_NW_32((uDataSrc)->mUINT32[0]);\ + (uDataDest)->mUINT32[1] = IX_OSAL_OEM_HOST_TO_NW_32((uDataSrc)->mUINT32[1]);\ + (uDataDest)->mUINT32[2] = IX_OSAL_OEM_HOST_TO_NW_32((uDataSrc)->mUINT32[2]);\ + (uDataDest)->mUINT32[3] = IX_OSAL_OEM_HOST_TO_NW_32((uDataSrc)->mUINT32[3]); + + +#define IX_OSAL_OEM_NW_TO_HOST_16(uData) be16_to_cpu(uData) + +#define IX_OSAL_OEM_NW_TO_HOST_32(uData) be32_to_cpu(uData) + +#define IX_OSAL_OEM_NW_TO_HOST_64(uData) be64_to_cpu(uData) + +#define IX_OSAL_OEM_NW_TO_HOST_128(uDataSrc, uDataDest) \ + (uDataDest)->mUINT32[0] = IX_OSAL_OEM_NW_TO_HOST_32((uDataSrc)->mUINT32[0]);\ + (uDataDest)->mUINT32[1] = IX_OSAL_OEM_NW_TO_HOST_32((uDataSrc)->mUINT32[1]);\ + (uDataDest)->mUINT32[2] = IX_OSAL_OEM_NW_TO_HOST_32((uDataSrc)->mUINT32[2]);\ + (uDataDest)->mUINT32[3] = IX_OSAL_OEM_NW_TO_HOST_32((uDataSrc)->mUINT32[3]); + +#endif /* #define IxOsalOsOem_H */ diff --git a/Acceleration/library/icp_utils/OSAL/platforms/EP805XX/os/linux/include/IxOsalOsOemCustomizedMapping.h b/Acceleration/library/icp_utils/OSAL/platforms/EP805XX/os/linux/include/IxOsalOsOemCustomizedMapping.h new file mode 100644 index 0000000..3c0435f --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/platforms/EP805XX/os/linux/include/IxOsalOsOemCustomizedMapping.h @@ -0,0 +1,87 @@ +/** + * @file IxOsalOsOemCustomizedMapping.h + * + * @brief Set LE coherency modes for components. + * The default setting is IX_OSAL_NO_MAPPING for LE. + * + * + * By default IX_OSAL_STATIC_MEMORY_MAP is defined for all the components. + * If any component uses a dynamic memory map it must define + * IX_OSAL_DYNAMIC_MEMORY_MAP in its corresponding section. + * + * + * @par + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +#ifndef IxOsalOsOemCustomizedMapping_H +#define IxOsalOsOemCustomizedMapping_H + +/* + * Important Note: The current #defines in this file are just place-holders and should + * be replaced and filled once the actual values are available. + * This file has portions that has glue-code/logic/stubs and should cease to exist in + * the final code. + */ +#define IX_OSAL_LE_MAPPING + +#endif /* IxOsalOsOemCustomizedMapping_H */ diff --git a/Acceleration/library/icp_utils/OSAL/platforms/EP805XX/os/linux/include/IxOsalOsOemIoMem.h b/Acceleration/library/icp_utils/OSAL/platforms/EP805XX/os/linux/include/IxOsalOsOemIoMem.h new file mode 100644 index 0000000..7a4e981 --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/platforms/EP805XX/os/linux/include/IxOsalOsOemIoMem.h @@ -0,0 +1,80 @@ +/** + * @file IxOsalOsOemIoMem.h + * + * @brief Implementaion of platform specific IoMem for Linux + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +#ifndef IxOsalOsOemIoMem_H +#define IxOsalOsOemIoMem_H + + +#undef __BIG_ENDIAN + +#ifndef __LITTLE_ENDIAN + #define __LITTLE_ENDIAN +#endif /* __LITTLE_ENDIAN */ + +#define IX_OSAL_LINUX_LE + +#endif /* IxOsalOsOemIoMem_H */ diff --git a/Acceleration/library/icp_utils/OSAL/platforms/EP805XX/os/linux/include/IxOsalOsOemIrq.h b/Acceleration/library/icp_utils/OSAL/platforms/EP805XX/os/linux/include/IxOsalOsOemIrq.h new file mode 100644 index 0000000..6df146b --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/platforms/EP805XX/os/linux/include/IxOsalOsOemIrq.h @@ -0,0 +1,114 @@ +/** + * @file IxOsalOsOemIrq.h + * + * @brief Implementaion of platform specific IRQ for Linux + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +#ifndef IxOsalOsOemIrq_H +#define IxOsalOsOemIrq_H + +static const char *irq_name[] = { + "EP805XXX RESERVED", /* IRQ 0 */ + "EP805XXX RESERVED", + "EP805XXX RESERVED", + "EP805XXX RESERVED", + "EP805XXX RESERVED", + "EP805XXX RESERVED", + "EP805XXX RESERVED", + "EP805XXX RESERVED", + "EP805XXX RESERVED", + "EP805XXX RESERVED", + "EP805XXX RESERVED", /* IRQ 10 */ + "EP805XXX RESERVED", + "EP805XXX RESERVED", + "EP805XXX RESERVED", + "EP805XXX RESERVED", + "EP805XXX RESERVED", + "EP805XXX RESERVED", + "EP805XXX RESERVED", + "EP805XXX RESERVED" + "EP805XXX RESERVED", /* IRQ 20 */ + "EP805XXX RESERVED", + "EP805XXX RESERVED", + "EP805XXX RESERVED", + "EP805XXX RESERVED", + "EP805XXX RESERVED", + "EP805XXX RESERVED", + "EP805XXX RESERVED", + "EP805XXX RESERVED", + "EP805XXX RESERVED", + "EP805XXX RESERVED", /* IRQ 30 */ + "EP805XXX RESERVED", + "EP805XXX RESERVED" +}; + +/* + * String to return when the vector number is invalid. + */ + +const char *invalid_irq_name = "Invalid EP805XX IRQ"; + + +#endif /* IxOsalOsOemIrq_H */ + diff --git a/Acceleration/library/icp_utils/OSAL/platforms/EP805XX/os/linux/include/IxOsalOsOemSys.h b/Acceleration/library/icp_utils/OSAL/platforms/EP805XX/os/linux/include/IxOsalOsOemSys.h new file mode 100644 index 0000000..ea312d9 --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/platforms/EP805XX/os/linux/include/IxOsalOsOemSys.h @@ -0,0 +1,132 @@ +/** + * @file IxOsalOsOemSys.h + * + * @brief linux and EP805XX specific defines + * + * Design Notes: + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +#ifndef IxOsalOsOemSys_H +#define IxOsalOsOemSys_H + +/* + * Important Note: The current #defines in this + * file are just place-holders and should be + * replaced and filled once the actual values + * are available. This file has portions that + * has glue-code/logic/stubs and should cease + * to exist in the final code. + */ + + +#ifndef IxOsalOsOem_H +#error "Error: IxOsalOsOemSys.h cannot be included directly before IxOsalOsOem.h" +#endif + +/* Memory Base Address */ + +/* Memory Mapping size */ + +/* Expansion Bus */ + +/* Time Stamp Resolution */ +#define IX_OSAL_EP805XX_TIME_STAMP_RESOLUTION (846596000) /**< 846.596 MHz */ + +/********************* + * Memory map + ********************/ + +/* Note: - dynamic maps will be mapped using ioremap() with the base addresses and sizes declared in this array (matched to include the requested zones, + but not using the actual IxOsalMemoryMap requests) + - static maps have to be also declared + - the user-friendly name will be made available in /proc for dynamically allocated maps + - the declared order of the maps is important if the maps overlap - when a common zone is requested only the + first usable map will be always chosen */ + + +/* Global memmap only visible to IO MEM module */ + + +#ifdef IXOSALIOMEM_C +IxOsalMemoryMap ixOsalGlobalMemoryMap[] = { + /* + * Dummy - Place holder. + */ + { + IX_OSAL_STATIC_MAP, /* type */ + IX_OSAL_EP805XX_DUMMY_PHYS_BASE, /* physicalAddress */ + IX_OSAL_EP805XX_DUMMY_MAP_SIZE, /* size */ + IX_OSAL_EP805XX_DUMMY_VIRT_BASE, /* virtualAddress */ + 0, /* mapFunction */ + 0, /* unmapFunction */ + 0, /* refCount */ + IX_OSAL_LE, /* endianType */ + "Dummy" /* name */ + } +}; + +#endif /* IXOSALIOMEM_C */ + +#endif /* IxOsalOsOemSys_H */ + + diff --git a/Acceleration/library/icp_utils/OSAL/platforms/EP805XX/os/linux/make/OemMake.mk b/Acceleration/library/icp_utils/OSAL/platforms/EP805XX/os/linux/make/OemMake.mk new file mode 100644 index 0000000..2f62c67 --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/platforms/EP805XX/os/linux/make/OemMake.mk @@ -0,0 +1,100 @@ +# +# Macro definitions for platform-specific makefile +# +# +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# +# + +# Linux EP805XX Compiler and Linker Commands +IX_LINUX_CROSSCOMPILER ?= /usr/bin/ + +LINUX_CROSS_COMPILE := $(IX_LINUX_CROSSCOMPILER) +LINUX_UTILS := /bin/ +COPY := $(LINUX_UTILS)cp -f + +#COMPILE_PREFIX := $(strip $(LINUX_CROSS_COMPILE)) +COMPILE_PREFIX := + +# Compiler flags +ifneq ($(IX_LINUXVER), 2.6.18) +$(warning IX_LINUXVER=$(IX_LINUXVER)) +$(error IX_LINUXVER should always be 2.6.18 -- no matter how strange that looks) +CFLAGS += -nostdinc -iwithprefix include -D__KERNEL__ -DEXPORT_SYMTAB -DMODULE -I$(LINUX_SRC)/include -Wall -Wstrict-prototypes -Wno-trigraphs -fno-strict-aliasing -fno-common -Os -fomit-frame-pointer -g -Wdeclaration-after-statement -pipe -msoft-float -m32 -fno-builtin-sprintf -fno-builtin-log2 -fno-builtin-puts -mpreferred-stack-boundary=2 -fno-unit-at-a-time -march=i686 -mregparm=3 -Iinclude/asm-i386/mach-default -D__EP805XX__ -D__linux + +else +# BUGBUG are they the right flags for a 2.6.32 (or other version) build??? + +$(warning REAL_LINUX_VERSION=$(REAL_LINUX_VERSION)) + +ifeq ($(REAL_LINUX_VERSION), 2.6.18) +CFLAGS += -D__KERNEL__ -DEXPORT_SYMTAB -DMODULE -I$(LINUX_SRC)/include -I$(LINUX_SRC)/arch/x86/include -include $(LINUX_SRC)/include/linux/autoconf.h -include $(LINUX_SRC)/include/linux/utsrelease.h -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs -fno-strict-aliasing -fno-common -Wstrict-prototypes -Wundef -Werror-implicit-function-declaration -Os -pipe -msoft-float -fno-builtin-sprintf -fno-builtin-log2 -fno-builtin-puts -mpreferred-stack-boundary=2 -march=i686 -mtune=i686 -mregparm=3 -ffreestanding -Iinclude/asm-i386/mach-generic -Iinclude/asm-i386/mach-default -fomit-frame-pointer -fasynchronous-unwind-tables -g -fno-stack-protector -Wdeclaration-after-statement -Wno-pointer-sign -D"KBUILD_STR(s)=\#s" -D"KBUILD_BASENAME=KBUILD_STR(osal_lib)" -D"KBUILD_MODNAME=KBUILD_STR(osal_module)" -D__EP805XX__ -D__linux +else +ifeq ($(REAL_LINUX_VERSION), 2.6.32) +CFLAGS += -D__KERNEL__ -DMODULE -I$(LINUX_SRC)/include -I$(LINUX_SRC)/arch/x86/include -include $(LINUX_SRC)/include/linux/autoconf.h -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs -Werror-implicit-function-declaration -Wno-format-security -Wno-sign-compare -Wframe-larger-than=1024 -Wdeclaration-after-statement -Wno-pointer-sign -fno-strict-aliasing -fno-common -fstack-protector -fconserve-stack -freg-struct-return -fno-delete-null-pointer-checks -fno-strict-overflow -fno-dwarf2-cfi-asm -ffreestanding -fomit-frame-pointer -fno-asynchronous-unwind-tables -Os -m32 -pipe -msoft-float -march=i686 -mtune=generic -mregparm=3 -mpreferred-stack-boundary=2 -mno-sse -mno-mmx -mno-sse2 -mno-3dnow -Wa,-mtune=generic32 -D"KBUILD_STR(s)=\#s" -D"KBUILD_BASENAME=KBUILD_STR(osal_lib)" -D"KBUILD_MODNAME=KBUILD_STR(osal_module)" -D__EP805XX__ -D__linux +else +$(error REAL_LINUX_VERSION=$(REAL_LINUX_VERSION) not supported) +endif +endif + +endif + +CFLAGS += $(OSAL_CFLAGS) + +INCLUDE_DIRS += $(LINUX_SRC)/include/asm/ $(LINUX_SRC)/include/asm/mach-default/ diff --git a/Acceleration/library/icp_utils/OSAL/platforms/EP805XX/os/linux/make/OsalConfig.mk b/Acceleration/library/icp_utils/OSAL/platforms/EP805XX/os/linux/make/OsalConfig.mk new file mode 100644 index 0000000..98a69c0 --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/platforms/EP805XX/os/linux/make/OsalConfig.mk @@ -0,0 +1,172 @@ +# +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# Contact Information: +# Intel Corporation +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# +# + +########################################################### +# This file is to be included in user build to configure +# OSAL features. +# +# This is specific to EP805XX/Linux build of OSAL only. +########################################################### + + +########################################################### +# Set OSAL_SRC_PATH to the absolute path where ixp_osal/ is +# located + + +OSAL_SRC_PATH := $(OSAL_SRCDIR) + + +PLATFORM_DIR_NAME := $(IX_DEVICE) + +ifdef KERNEL_SOURCE_ROOT +LINUX_SRC := $(KERNEL_SOURCE_ROOT) +endif + +########################################################### +# All defines that are valid for OSAL on Linux + +# Set this to enable graceful thread exit +#ENABLE_PCI=1 + +# Set this to using Data Coherent SDRAM definitions +ENABLE_SPINLOCK=1 + +# Set this to use buffer management module of OSAL +#ENABLE_BUFFERMGT=1 + +# Set this to use IOMEM module of OSAL +ENABLE_IOMEM=1 + +# Set this to use buffer management module of OSAL +ENABLE_DDK=1 + + +########################################################### +# Compilation flags for using configurable features of OSAL +# Set CFLAGS += $(OSAL_CFLAGS) in the including Makefile to +# include the flags set here + +OSAL_CFLAGS := -D__LITTLE_ENDIAN \ + -DIX_HW_COHERENT_MEMORY \ + -DIX_OSAL_MEM_MAP_GLUECODE \ + -DIX_OSAL_THREAD_EXIT_GRACEFULLY \ + -DUSE_NATIVE_OS_TIMER_API + +ifdef ENABLE_PCI +OSAL_CFLAGS += -DENABLE_PCI +endif + +ifdef ENABLE_SPINLOCK +OSAL_CFLAGS += -DENABLE_SPINLOCK +endif + +ifdef ENABLE_BUFFERMGT +OSAL_CFLAGS += -DENABLE_BUFFERMGT +endif + +ifdef ENABLE_IOMEM +OSAL_CFLAGS += -DENABLE_IOMEM +endif + +ifdef ENABLE_DDK +OSAL_CFLAGS += -DENABLE_DDK +endif + +ifdef IX_OSAL_ENSURE_ON +OSAL_CFLAGS += -DIX_OSAL_ENSURE_ON +endif + +ifdef OSAL_EXPORT_SYMBOLS +OSAL_CFLAGS += -DOSAL_EXPORT_SYMBOLS +endif + +OSAL_LDFLAGS := + +########################################################### +# OSAL_INCLUDES lists all the include paths to be included +# in order to use OSAL headers. This needs OSAL_SRC_PATH to be +# set to the absolute path where osal is located. +# Include $(OSAL_INCLUDES) to the INCLUDE_DIRS as +# INCLUDE_DIRS += $(OSAL_INCLUDES) for using. + +# Common includes +OSAL_INCLUDES := -I$(OSAL_SRC_PATH)/common/include \ + -I$(OSAL_SRC_PATH)/common/include/modules \ + -I$(OSAL_SRC_PATH)/common/include/modules/ddk \ + -I$(OSAL_SRC_PATH)/common/os/linux/include/core \ + -I$(OSAL_SRC_PATH)/common/os/linux/include/modules \ + -I$(OSAL_SRC_PATH)/common/os/linux/include/modules/ddk \ + -I$(OSAL_SRC_PATH)/platforms/$(PLATFORM_DIR_NAME)/include \ + -I$(OSAL_SRC_PATH)/platforms/$(PLATFORM_DIR_NAME)/os/linux/include + +ifdef ENABLE_BUFFERMGT +OSAL_INCLUDES += -I$(OSAL_SRC_PATH)/common/include/modules/bufferMgt \ + -I$(OSAL_SRC_PATH)/common/os/linux/include/modules/bufferMgt +endif + +ifdef ENABLE_IOMEM +OSAL_INCLUDES += -I$(OSAL_SRC_PATH)/common/os/linux/include/modules/ioMem \ + -I$(OSAL_SRC_PATH)/common/include/modules/ioMem +endif + + diff --git a/Acceleration/library/icp_utils/OSAL/platforms/EP805XX/os/linux/make/RelMake.mk b/Acceleration/library/icp_utils/OSAL/platforms/EP805XX/os/linux/make/RelMake.mk new file mode 100644 index 0000000..2a9d8d2 --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/platforms/EP805XX/os/linux/make/RelMake.mk @@ -0,0 +1,63 @@ +# +# plafrom specific Macro definitions & release build rules +# +# +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# + diff --git a/Acceleration/library/icp_utils/OSAL/platforms/EP805XX/os/linux/src/IxOsalOsOem.c b/Acceleration/library/icp_utils/OSAL/platforms/EP805XX/os/linux/src/IxOsalOsOem.c new file mode 100644 index 0000000..cb0f9e9 --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/platforms/EP805XX/os/linux/src/IxOsalOsOem.c @@ -0,0 +1,150 @@ +/** + * @file IxOsalOsOem.c (linux) + * + * @brief this file contains implementation for platform-specific + * functionalities. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +#include <linux/utsname.h> +#include "IxOsal.h" + +PRIVATE BOOL IxOsalOemInitialized = FALSE; + +PUBLIC UINT32 ixOsalLinuxInterruptedPc = 0; + +PUBLIC UINT32 +ixOsalOsEP805XXTimestampGet (void) +{ + UINT32 timestamp; + /* Read the 32-bit LSB of the time stamp counter */ + rdtscl(timestamp); + return (timestamp); +} + +PUBLIC UINT32 +ixOsalOsEP805XXTimestampResolutionGet (void) +{ + return (UINT32)IX_OSAL_EP805XX_TIME_STAMP_RESOLUTION ; +} + +UINT32 +ixOsalOsEP805XXSysClockRateGet (void) +{ + return HZ; +} + +#ifdef ENABLE_IOMEM +/* + * Dummy MemMapInit + */ +PUBLIC IX_STATUS +ixOsalMemMapInit (IxOsalMemoryMap *map, UINT32 numElement) +{ + return IX_SUCCESS; +} + +#endif /* ENABLE_IOMEM */ + +PUBLIC IX_STATUS +ixOsalOemInit (void) +{ + /* + * Check flag + */ + if (IxOsalOemInitialized == TRUE) + { + return IX_SUCCESS; + } + + IxOsalOemInitialized = TRUE; + return IX_SUCCESS; +} + +PUBLIC IX_STATUS +ixOsalOsEP805XXNameGet(INT8* osName, INT32 maxSize) +{ + strncpy(osName, init_utsname()->sysname, maxSize); + return IX_SUCCESS; +} + +PUBLIC IX_STATUS +ixOsalOsEP805XXVersionGet(INT8* osVersion, INT32 maxSize) +{ + strncpy(osVersion, init_utsname()->release, maxSize); + return IX_SUCCESS; +} + +PUBLIC void +ixOsalOemUnload (void) +{ + IxOsalOemInitialized = FALSE; +} + +void +ixOsalEP805XXSetInterruptedPc(struct pt_regs *regs) +{ + /* ixOsalLinuxInterruptedPc = regs->eip; */ + /* disabled by xilun: ixOsalLinuxInterruptedPc is unused */ +} + +/* ===================== End - Irq ====================== */ diff --git a/Acceleration/library/icp_utils/OSAL/platforms/EP805XX/os/linux/src/IxOsalOsOemSymbols.c b/Acceleration/library/icp_utils/OSAL/platforms/EP805XX/os/linux/src/IxOsalOsOemSymbols.c new file mode 100644 index 0000000..0987a45 --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/platforms/EP805XX/os/linux/src/IxOsalOsOemSymbols.c @@ -0,0 +1,88 @@ +/* + * @file IxOsalOsOemSymbols.c + * @author Intel Corporation + * @date 25-08-2004 + * + * @brief description goes here + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +#ifdef OSAL_EXPORT_SYMBOLS + +#include <linux/module.h> +#include "IxOsal.h" + +EXPORT_SYMBOL (ixOsalOemInit); +EXPORT_SYMBOL (ixOsalOemUnload); +EXPORT_SYMBOL (ixOsalOsEP805XXTimestampGet); +EXPORT_SYMBOL (ixOsalOsEP805XXTimestampResolutionGet); +EXPORT_SYMBOL (ixOsalOsEP805XXSysClockRateGet); + +#ifdef ENABLE_IOMEM + +EXPORT_SYMBOL (ixOsalLinuxMemMap); +EXPORT_SYMBOL (ixOsalLinuxMemUnmap); +EXPORT_SYMBOL (ixOsalMemMapInit); + +#endif /* ENABLE_IOMEM */ + +#endif /* OSAL_EXPORT_SYMBOLS */ diff --git a/Acceleration/library/icp_utils/OSAL/platforms/EP805XX/os/linux/src/component.mk b/Acceleration/library/icp_utils/OSAL/platforms/EP805XX/os/linux/src/component.mk new file mode 100644 index 0000000..339788d --- /dev/null +++ b/Acceleration/library/icp_utils/OSAL/platforms/EP805XX/os/linux/src/component.mk @@ -0,0 +1,70 @@ +# +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# Contact Information: +# Intel Corporation +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# + +#NOTE: Create protection + +platform_FLAGS := + +#NOTE: List all Platform specific files here. +platform_OBJ := IxOsalOsOem.o\ + IxOsalOsOemSymbols.o + + diff --git a/Install/install_voice.sh b/Install/install_voice.sh new file mode 100644 index 0000000..e12b8ff --- /dev/null +++ b/Install/install_voice.sh @@ -0,0 +1,154 @@ +#!/bin/sh + +############################################################################### +# +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# +# +############################################################################### +BUILD_OUTPUT_DIR=$2 +cd $BUILD_OUTPUT_DIR + +MODULE_DIR=/lib/modules/`uname -r` +OBJ_LIST="tdm_infra.ko tdm_setup_driver.ko hssvoice_driver.ko" +MICROCODE="IxPiuMicrocode.dat" + +usage() { +echo +echo ---------------------------------- +echo USAGE: +echo ---------------------------------- +echo "# $0 install||uninstall BUILD_OUTPUT_DIR " +echo "#" +echo ---------------------------------- + +exit 1 + +} +case $1 in + install) + + echo "Copy PIU MicroCode to /lib/firmware" + for microcode_obj in $MICROCODE + do + cp $microcode_obj /lib/firmware + done + + # delete the existing kernel objects if they exist in the /lib/modules + # folder + echo "Copying VOICE kernel objects to lib/modules/`uname -r`" + for kern_obj in $OBJ_LIST + do + install -D -m 644 $kern_obj $MODULE_DIR/$kern_obj + done + echo "Creating module.dep file for VOICE released kernel objects" + echo "This will take a few moments" + /sbin/depmod -a + + echo "Creating start and kill scripts" + cp voice_service /etc/init.d + + chkconfig --add voice_service + + echo "Starting VOICE service" + /etc/init.d/voice_service start + + ;; + + uninstall) + echo "Unloading Voice kernel objects" + /etc/init.d/voice_service stop + + echo "Removing startup scripts" + # Check if one of the /etc/rc3.d script exist, then all the + # startup scripts would exist + if [ -e /etc/rc3.d/S99voice_service ]; + then + chkconfig --del voice_service + /bin/rm -f /etc/init.d/voice_service + fi + + + + echo "Removing the PIU MicroCode" + for bin_obj in $MICROCODE + do + if [ -e /lib/firmware/$bin_obj ]; + then + /bin/rm -f /lib/firmware/$bin_obj + fi + done + + echo "Removing kernel objects from /lib/modules/`uname -r`" + for kern_obj in $OBJ_LIST + do + if [ -e $MODULE_DIR/$kern_obj ] ; + then + /bin/rm -f $MODULE_DIR/$kern_obj + fi + done + echo "Rebuilding the module.dep file, this will take a few moments" + /sbin/depmod -a + + ;; + + *) + usage + ;; +esac + diff --git a/Install/voice_service b/Install/voice_service new file mode 100644 index 0000000..f9be54d --- /dev/null +++ b/Install/voice_service @@ -0,0 +1,146 @@ +#!/bin/sh +################################################################# +# +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# +# +################################################################# + +# voice_service Start/Stop the Intel Voice Components. +# +# chkconfig: 345 99 99 +# description: modprobe the Voice components. +# + + + + +OBJ_LIST_INSTALL="tdm_infra tdm_setup_driver hssvoice_driver" +OBJ_LIST_UNINSTALL="hssvoice_driver tdm_setup_driver tdm_infra" +DEVENTRY=(tdm_setup hssvoicedrv) +DEVICE=(tdm-setup hss-voice) +NUM_DEV=5; + + +usage() { +echo +echo ---------------------------------- +echo USAGE: +echo ---------------------------------- +echo "# $0 start||stop " +echo "#" +echo ---------------------------------- + +exit 1 +} + +install(){ + for voice_obj in $OBJ_LIST_INSTALL + do + modprobe $voice_obj + done +} + + +uninstall(){ + for voice_obj in $OBJ_LIST_UNINSTALL + do + modprobe -r $voice_obj + done +} + + +create_device_files(){ + for ((i=0; i < NUM_DEV; i++)) + do + major=$(awk "\$2==\"${DEVENTRY[i]}\" {print \$1}" /proc/devices) + # create the file + mknod /dev/${DEVICE[i]} c $major 0 + done +} + +remove_device_files(){ + for ((i=0; i < NUM_DEV; i++)) + do + rm -rf /dev/${DEVICE[i]} + done +} + + +case "$1" in + Start|start) + # First remove any previous installation + uninstall + remove_device_files + + install + create_device_files + ;; + Stop|stop) + uninstall + remove_device_files + ;; + *) + usage + ;; +esac +exit 0 + + + + diff --git a/LICENSE.GPL b/LICENSE.GPL new file mode 100644 index 0000000..d511905 --- /dev/null +++ b/LICENSE.GPL @@ -0,0 +1,339 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. By contrast, the GNU General Public +License is intended to guarantee your freedom to share and change free +software--to make sure the software is free for all its users. This +General Public License applies to most of the Free Software +Foundation's software and to any other program whose authors commit to +using it. (Some other Free Software Foundation software is covered by +the GNU Lesser General Public License instead.) You can apply it to +your programs, too. + + When we speak of free software, we are referring to freedom, not +price. Our General Public Licenses are designed to make sure that you +have the freedom to distribute copies of free software (and charge for +this service if you wish), that you receive source code or can get it +if you want it, that you can change the software or use pieces of it +in new free programs; and that you know you can do these things. + + To protect your rights, we need to make restrictions that forbid +anyone to deny you these rights or to ask you to surrender the rights. +These restrictions translate to certain responsibilities for you if you +distribute copies of the software, or if you modify it. + + For example, if you distribute copies of such a program, whether +gratis or for a fee, you must give the recipients all the rights that +you have. You must make sure that they, too, receive or can get the +source code. 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Each licensee is addressed as "you". + +Activities other than copying, distribution and modification are not +covered by this License; they are outside its scope. The act of +running the Program is not restricted, and the output from the Program +is covered only if its contents constitute a work based on the +Program (independent of having been made by running the Program). +Whether that is true depends on what the Program does. + + 1. You may copy and distribute verbatim copies of the Program's +source code as you receive it, in any medium, provided that you +conspicuously and appropriately publish on each copy an appropriate +copyright notice and disclaimer of warranty; keep intact all the +notices that refer to this License and to the absence of any warranty; +and give any other recipients of the Program a copy of this License +along with the Program. + +You may charge a fee for the physical act of transferring a copy, and +you may at your option offer warranty protection in exchange for a fee. + + 2. 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But when you +distribute the same sections as part of a whole which is a work based +on the Program, the distribution of the whole must be on the terms of +this License, whose permissions for other licensees extend to the +entire whole, and thus to each and every part regardless of who wrote it. + +Thus, it is not the intent of this section to claim rights or contest +your rights to work written entirely by you; rather, the intent is to +exercise the right to control the distribution of derivative or +collective works based on the Program. + +In addition, mere aggregation of another work not based on the Program +with the Program (or with a work based on the Program) on a volume of +a storage or distribution medium does not bring the other work under +the scope of this License. + + 3. You may copy and distribute the Program (or a work based on it, +under Section 2) in object code or executable form under the terms of +Sections 1 and 2 above provided that you also do one of the following: + + a) Accompany it with the complete corresponding machine-readable + source code, which must be distributed under the terms of Sections + 1 and 2 above on a medium customarily used for software interchange; or, + + b) Accompany it with a written offer, valid for at least three + years, to give any third party, for a charge no more than your + cost of physically performing source distribution, a complete + machine-readable copy of the corresponding source code, to be + distributed under the terms of Sections 1 and 2 above on a medium + customarily used for software interchange; or, + + c) Accompany it with the information you received as to the offer + to distribute corresponding source code. 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For software which is copyrighted by the Free +Software Foundation, write to the Free Software Foundation; we sometimes +make exceptions for this. Our decision will be guided by the two goals +of preserving the free status of all derivatives of our free software and +of promoting the sharing and reuse of software generally. + + NO WARRANTY + + 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY +FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN +OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES +PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED +OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS +TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE +PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, +REPAIR OR CORRECTION. + + 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING +WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR +REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, +INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING +OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED +TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY +YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER +PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. + + END OF TERMS AND CONDITIONS + + How to Apply These Terms to Your New Programs + + If you develop a new program, and you want it to be of the greatest +possible use to the public, the best way to achieve this is to make it +free software which everyone can redistribute and change under these terms. + + To do so, attach the following notices to the program. It is safest +to attach them to the start of each source file to most effectively +convey the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + <one line to give the program's name and a brief idea of what it does.> + Copyright (C) <year> <name of author> + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + <signature of Ty Coon>, 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. diff --git a/LISEZMOI b/LISEZMOI new file mode 100644 index 0000000..32b9ad2 --- /dev/null +++ b/LISEZMOI @@ -0,0 +1,31 @@ +Ce dépôt contient des sources dérivées du package "Telephony" pour EP80579 +d'Intel, version L.1.0.1-89, Date : 04/03/2009 (qui est toujours la dernière +publiée en date du 2012/07/11) + +Modifications par Avencall : + +- suppression de toute la partie cryptographique + fait + +- suppression des drivers custom des cartes Intel analogiques et t1/e1 + fait + +- adaptations pour cartes prototypes XIOH v4 + fait + +- adaptations pour Linux 2.6.32 et dahdi 2.6 + à pré-valider + à améliorer + +- utilisation simple de Kbuild pour la construction + tdm_infra.ko fait + hssvoice_driver.ko à faire + tdm_setup_driver.ko à faire + +- intégration au reste des drivers + suppression spi/leb fait + interfaçage à l'arrache fait + améliorations à faire + +- nettoyages / améliorations + à faire diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..b073af7 --- /dev/null +++ b/Makefile @@ -0,0 +1,102 @@ +############################################################################### +# +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +############################################################################### + +# Ensure The ICP_ROOT var is defined. +ifndef ICP_ROOT +$(error ICP_ROOT is undefined. Please set the path to the code \ + "-> setenv ICP_ROOT <path to code>") +endif + +DATE=$(shell date '+%m_%d_%y') +ICP_BUILD_OUTPUT?=$(ICP_ROOT)/build_$(DATE) +VOICE_INSTALL_SCRIPT=install_voice.sh + +all: Accel + + +Accel: + @cd Acceleration/ && make ICP_BUILD_OUTPUT=$(ICP_BUILD_OUTPUT); + +clean: Accel_clean + @test $(ICP_BUILD_OUTPUT) && rm -rf $(ICP_BUILD_OUTPUT) + +Accel_clean: + @test $(ICP_BUILD_OUTPUT) && rm -rf $(ICP_BUILD_OUTPUT)/icp*.ko ; + @cd Acceleration/ && make clean; + +install: Accel_install Voice_install + +Accel_install: + @echo 'Installing Security modules'; + $(ICP_BUILD_OUTPUT)/$(INSTALL_SCRIPT) install $(ICP_BUILD_OUTPUT); + +Voice_install: + @echo 'Installing Voice modules'; + $(ICP_BUILD_OUTPUT)/$(VOICE_INSTALL_SCRIPT) install $(ICP_BUILD_OUTPUT); + +uninstall: Accel_uninstall Voice_uninstall + @echo 'Un-installing Security modules'; + +Accel_uninstall: + $(ICP_BUILD_OUTPUT)/$(INSTALL_SCRIPT) uninstall ; + +Voice_uninstall: + @echo 'Un-installing Voice modules'; + $(ICP_BUILD_OUTPUT)/$(VOICE_INSTALL_SCRIPT) uninstall; + @@ -1 +0,0 @@ -developpement repo susceptible of stalinism diff --git a/build_system/build_files/Core/ia.mk b/build_system/build_files/Core/ia.mk new file mode 100644 index 0000000..a54d738 --- /dev/null +++ b/build_system/build_files/Core/ia.mk @@ -0,0 +1,69 @@ +###### +# +# Makefile IA Core specific Definitions for the Common build system +# +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# Contact Information: +# Intel Corporation +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# +###### + +# Setup compiler, linker definitions depending on target +COMPILER?=gcc +LINKER=ld +ARCHIVER=ar diff --git a/build_system/build_files/OS/linux_2.6.mk b/build_system/build_files/OS/linux_2.6.mk new file mode 100644 index 0000000..c51a15b --- /dev/null +++ b/build_system/build_files/OS/linux_2.6.mk @@ -0,0 +1,103 @@ +###### +# +# Makefile Linux 2.6 Kernel Specific Definitions for the Tolapai build system +# +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# +###### + +ifndef OS_LEVEL +OS_LEVEL=$(IX_OS_LEVEL) +endif + + +$(info Building for linux_2.6) + + +INCLUDES+=-I ./#path to production header files and to add another "-I <path to another directory of include files>" + + +ifeq ($(OS_LEVEL), user_space) +CFLAGS+=-fPIC $(DEBUGFLAGS) -Wall -Wpointer-arith -O2 $(INCLUDES) +endif + + +#ifeq ($(OS_LEVEL), kernel_space) +#CFLAGS+= +#endif + + +ifeq ($(EXTRA_WARNINGS),y) +EXTRA_CFLAGS+= -Wno-div-by-zero -Wfloat-equal -Wtraditional -Wundef -Wno-endif-labels \ + -Wshadow -Wbad-function-cast -Wcast-qual -Wcast-align -Wwrite-strings -Wconversion -Wsign-compare -Waggregate-return \ + -Wstrict-prototypes -Wmissing-prototypes -Wmissing-declarations -Wmissing-noreturn \ + -Wmissing-format-attribute -Wno-multichar -Wno-deprecated-declarations -Wpacked -Wpadded -Wredundant-decls -Wnested-externs -Wunreachable-code \ + -Winline -Wlong-long -Wdisabled-optimization + +## unrecognized options +## -Wextra -Wdeclaration-after-statement -Wlarger-than-len -Wold-style-definition -Wmissing-field-initializers -Winvalid-pch +## -Wvariadic-macros -Wno-pointer-sign +endif + + +LIB_SHARED_FLAGS=-shared -soname $(LIB_SHARED) +LIB_STATIC_FLAGS= +EXE_FLAGS= + + diff --git a/build_system/build_files/OS/linux_2.6_kernel_space_rules.mk b/build_system/build_files/OS/linux_2.6_kernel_space_rules.mk new file mode 100644 index 0000000..6f941ab --- /dev/null +++ b/build_system/build_files/OS/linux_2.6_kernel_space_rules.mk @@ -0,0 +1,104 @@ +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# Contact Information: +# Intel Corporation +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# + +$(OBJECTS): + @echo Error: $@: To get object files in kernel space, you need to build a static library or a module; + +ifndef SOURCES +obj-m+=$(OUTPUT_NAME).o +$(OUTPUT_NAME)-objs := $(patsubst %.c,%.o, $(MODULE_SOURCES)) $(ADDITIONAL_KERNEL_LIBS) +else +obj-m+=$(OUTPUT_NAME).o +$(OUTPUT_NAME)-objs :=lib.a $(patsubst %.c,%.o, $(MODULE_SOURCES)) $(ADDITIONAL_KERNEL_LIBS) +lib-m := $(patsubst %.c,%.o, $(SOURCES)) +endif + +$(LIB_STATIC): dirs + @echo 'Creating static library ${LIB_STATIC}'; \ + make -C $(KERNEL_SOURCE_ROOT)/ M=$(PWD) obj-m=""; \ + echo 'Copying outputs';\ + mv -f $(OBJ) $(FINAL_OUTPUT_DIR);\ + test -f built-in.o && mv -f built-in.o $(FINAL_OUTPUT_DIR);\ + test -f lib.a && mv lib.a $(FINAL_OUTPUT_DIR)/$(LIB_STATIC);\ + test -f $(OUTPUT_NAME).ko && mv -f $(OUTPUT_NAME).ko $(FINAL_OUTPUT_DIR);\ + test -f $(OUTPUT_NAME).o && mv -f $(OUTPUT_NAME).o $(FINAL_OUTPUT_DIR);\ + $(RM) -rf *.mod.* .*.cmd; + + +$(MODULENAME): dirs + @echo 'Creating kernel module'; \ + make -C $(KERNEL_SOURCE_ROOT)/ M=$(PWD); \ + echo 'Copying outputs';\ + mv -f $(OBJ) $(FINAL_OUTPUT_DIR);\ + test -f built-in.o && mv -f built-in.o $(FINAL_OUTPUT_DIR);\ + test -f lib.a && mv lib.a $(FINAL_OUTPUT_DIR)/$(LIB_STATIC);\ + test -f $(OUTPUT_NAME).ko && mv -f $(OUTPUT_NAME).ko $(FINAL_OUTPUT_DIR);\ + test -f $(OUTPUT_NAME).o && mv -f $(OUTPUT_NAME).o $(FINAL_OUTPUT_DIR);\ + $(RM) -rf *.mod.* .*.cmd; + + +$(LIB_SHARED): + @echo Error: $@: You cannot build shared libraries in kernel space; + +$(EXECUTABLE): + @echo Error: $@: You cannot build executables in kernel space; + + + diff --git a/build_system/build_files/OS/linux_2.6_user_space_rules.mk b/build_system/build_files/OS/linux_2.6_user_space_rules.mk new file mode 100644 index 0000000..2fc315b --- /dev/null +++ b/build_system/build_files/OS/linux_2.6_user_space_rules.mk @@ -0,0 +1,60 @@ +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# Contact Information: +# Intel Corporation +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# +include $(BUILDSYSTEM_PATH)/build_files/OS/linux_common_$(OS_LEVEL)_rules.mk diff --git a/build_system/build_files/OS/linux_common_user_space_rules.mk b/build_system/build_files/OS/linux_common_user_space_rules.mk new file mode 100644 index 0000000..76e8bac --- /dev/null +++ b/build_system/build_files/OS/linux_common_user_space_rules.mk @@ -0,0 +1,115 @@ +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# Contact Information: +# Intel Corporation +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# + +ifeq ($(OS_LEVEL), user_space) + +# Compile the object files with the CFLAGS +$(OBJECTS): %.o: %.c + @echo 'Compiling $<' ;\ + echo $(COMPILER) $(CFLAGS) $(EXTRA_CFLAGS) -c $(PWD)/$< -o $(FINAL_OUTPUT_DIR)/$@;\ + $(COMPILER) $(CFLAGS) $(EXTRA_CFLAGS) -c $(PWD)/$< -o $(FINAL_OUTPUT_DIR)/$@; + + +# Create the shared library +$(LIB_SHARED): obj + @echo 'Creating shared library ${LIB_SHARED}'; \ + cd $(FINAL_OUTPUT_DIR);\ + echo $(LINKER) $(LIB_SHARED_FLAGS) -o $@ -lc $(OBJECTS) $(ADDITIONAL_OBJECTS);\ + $(LINKER) $(LIB_SHARED_FLAGS) -o $@ -lc $(OBJECTS) $(ADDITIONAL_OBJECTS); + + +# Create the static library +$(LIB_STATIC): obj + @echo 'Creating static library ${LIB_STATIC}'; \ + cd $(FINAL_OUTPUT_DIR);\ + echo $(ARCHIVER) $(LIB_STATIC_FLAGS) r $@ $(OBJECTS) $(ADDITIONAL_OBJECTS);\ + $(ARCHIVER) $(LIB_STATIC_FLAGS) r $@ $(OBJECTS) $(ADDITIONAL_OBJECTS); + + +#Create executable output +$(EXECUTABLE): obj + @echo 'Creating executable ${OUTPUT_NAME}'; \ + cd $(FINAL_OUTPUT_DIR);\ + $(COMPILER) $(EXE_FLAGS) -o $@ $(OBJECTS) $(ADDITIONAL_OBJECTS); + + +$(MODULENAME): + @echo Error: $@: You cannot build modules in user_space; + + + +depend: + + @echo 'Creating\Checking dependencies' ;\ + if [[ ! -f $(FINAL_OUTPUT_DIR)/.depend ]]; then \ + echo '$(CFLAGS) $(EXTRA_CFLAGS) -E -MM $(SOURCES)'; \ + $(CC) $(CFLAGS) $(EXTRA_CFLAGS) -E -MM $(SOURCES) > $(FINAL_OUTPUT_DIR)/.depend ;\ + fi; + + +###################Dependency creating/checking#################### +DEPEND_EXIST= $(shell ls $(FINAL_OUTPUT_DIR)/.depend) +ifeq ($(DEPEND_EXIST),$(FINAL_OUTPUT_DIR)/.depend) +$(info .depend found ) +include $(FINAL_OUTPUT_DIR)/.depend +endif +###################End of dependency creation and creating######### + +endif diff --git a/build_system/build_files/common.mk b/build_system/build_files/common.mk new file mode 100644 index 0000000..d42a317 --- /dev/null +++ b/build_system/build_files/common.mk @@ -0,0 +1,144 @@ +###### +# +# Makefile Common Definitions for the Tolapai build system +# +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# +##### + +ifndef OS_LEVEL +OS_LEVEL=$(IX_OS_LEVEL) +endif + +######Support ICP_ and previous vars################################# +ifdef ICP_KERNEL_SOURCE_ROOT +KERNEL_SOURCE_ROOT=$(ICP_KERNEL_SOURCE_ROOT) +endif +ifdef ICP_OS +OS=$(ICP_OS) +endif +ifdef ICP_OS_LEVEL +OS_LEVEL=$(ICP_OS_LEVEL) +endif +ifdef ICP_BUILDSYSTEM_PATH +BUILDSYSTEM_PATH=$(ICP_BUILDSYSTEM_PATH) +endif +ifdef ICP_ENV_DIR +ENV_DIR=$(ICP_ENV_DIR) +endif +ifdef ICP_BUILD_OUTPUT_DIR +BUILD_OUTPUT_DIR=$(ICP_BUILD_OUTPUT_DIR) +endif +ifdef ICP_EXTRA_WARNINGS +EXTRA_WARNINGS=$(ICP_EXTRA_WARNINGS) +endif +ifdef ICP_DEBUG +DEBUG=$(ICP_DEBUG) +endif +ifdef ICP_CORE +CORE=$(ICP_CORE) +endif +CORE?=ia +OS?=linux_2.6 +#################################################################### + +#Check to ensure that the BUILDSYSTEM is defined, it should point to the top of the build dir structure where build_files are located +ifndef BUILDSYSTEM_PATH +$(error BUILDSYSTEM_PATH is undefined. Please set the path to the top of the build structure \ + "-> setenv BUILDSYSTEM_PATH <path>") +endif + +# Ensure the ENV_DIR environmental var is defined. +ifndef ENV_DIR +$(error ENV_DIR is undefined. Please set the path to your environment makefile \ + "-> setenv ENV_DIR <path>") +endif + +#Add your project environment Makefile +include $(ENV_DIR)/environment.mk + +# Compiler, Linker and Archive commands are defined in the core specific makefile +CC=$(COMPILER) +LD=$(LINKER) +AR=$(ARCHIVER) + +# CFLAGS+=-O2 + + +PWD= $(shell pwd) + +##directories +# path where to store all the build outputs +# only this one can be overwritten by users. +# This way, and with the 3 variables, we can prevent any rm -rf `pwd` +# when doing `make clean or distclean' +BUILD_OUTPUT_DIR?=$(PWD) +MID_OUTPUT_DIR=$(BUILD_OUTPUT_DIR)/build +FINAL_OUTPUT_DIR=$(MID_OUTPUT_DIR)/$(OS)/$(OS_LEVEL)/ + +# Defines a loop macro for making subdirectories +define LOOP +@for dir in $(SUBDIRS); do \ + (echo ; echo $$dir :; cd $$dir && \ + $(MAKE) $@ || return 1) \ + done +endef + +include $(BUILDSYSTEM_PATH)/build_files/Core/$(CORE).mk +include $(BUILDSYSTEM_PATH)/build_files/OS/$(OS).mk diff --git a/build_system/build_files/includes.mk b/build_system/build_files/includes.mk new file mode 100644 index 0000000..2bd230b --- /dev/null +++ b/build_system/build_files/includes.mk @@ -0,0 +1,89 @@ +#################### +# Include paths +# +# +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# +# +#################### + + +INCLUDES= \ + -I$(ICP_ROOT)/Acceleration/include \ + -I$(ICP_ROOT)/Acceleration/include/hss \ + -I$(ICP_ROOT)/Acceleration/include/accel_infra \ + -I$(ICP_ROOT)/Acceleration/library/icp_utils/OSAL/common/include \ + -I$(ICP_ROOT)/Acceleration/library/icp_utils/OSAL/common/include/modules/bufferMgt \ + -I$(ICP_ROOT)/Acceleration/library/icp_utils/OSAL/common/include/modules/ddk \ + -I$(ICP_ROOT)/Acceleration/library/icp_utils/OSAL/common/include/modules/ioMem \ + -I$(ICP_ROOT)/Acceleration/library/icp_utils/OSAL/common/os/linux/include/core \ + -I$(ICP_ROOT)/Acceleration/library/icp_utils/OSAL/common/os/linux/include/modules/bufferMgt \ + -I$(ICP_ROOT)/Acceleration/library/icp_utils/OSAL/common/os/linux/include/modules/ddk \ + -I$(ICP_ROOT)/Acceleration/library/icp_utils/OSAL/common/os/linux/include/modules/ioMem \ + -I$(ICP_ROOT)/Acceleration/library/icp_utils/OSAL/platforms/EP805XX/include \ + -I$(ICP_ROOT)/Acceleration/library/icp_utils/OSAL/platforms/EP805XX/os/linux/include \ + -I$(ICP_ROOT)/Acceleration/library/icp_telephony/tdm_io_access/include \ + -I$(ICP_ROOT)/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/include \ + -I$(ICP_ROOT)/Acceleration/library/icp_telephony/tdm_infrastructure_queue_manager/include \ + -I$(ICP_ROOT)/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include \ + -I$(ICP_ROOT)/Acceleration/drivers/icp_tdm/include \ + -I$(ICP_ROOT)/Acceleration/drivers/icp_tdm/tdm_setup_driver/include + +ifdef ICP_OCF_SRC_DIR +INCLUDES+= -I$(ICP_OCF_SRC_DIR) +endif diff --git a/build_system/build_files/rules.mk b/build_system/build_files/rules.mk new file mode 100644 index 0000000..0a73fff --- /dev/null +++ b/build_system/build_files/rules.mk @@ -0,0 +1,161 @@ +#################### +# RULES +# +# +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# +#################### + + +######Support ICP_ and previous vars################################# +# PROJECT SPECIFIC +ifdef ICP_KERNEL_SOURCE_ROOT +KERNEL_SOURCE_ROOT=$(ICP_KERNEL_SOURCE_ROOT) +endif +ifdef ICP_OS +OS=$(ICP_OS) +endif +ifdef ICP_OS_LEVEL +OS_LEVEL=$(ICP_OS_LEVEL) +endif +ifdef ICP_BUILDSYSTEM_PATH +BUILDSYSTEM_PATH=$(ICP_BUILDSYSTEM_PATH) +endif +ifdef ICP_ENV_DIR +ENV_DIR=$(ICP_ENV_DIR) +endif +ifdef ICP_BUILD_OUTPUT_DIR +BUILD_OUTPUT_DIR=$(ICP_BUILD_OUTPUT_DIR) +endif +ifdef ICP_EXTRA_WARNINGS +EXTRA_WARNINGS=$(ICP_EXTRA_WARNINGS) +endif +ifdef ICP_DEBUG +DEBUG=$(ICP_DEBUG) +endif +ifdef ICP_CORE +CORE=$(ICP_CORE) +endif +#################################################################### + + +# Build and Install Everything, this is the default rule. +all: install + +#Top-level var for turning on debug# +ifdef DEBUG +EXTRA_CFLAGS+=-DDEBUG=1 +endif + +# create .o's from the list of source files +# and keep only the name of the files +OBJECTS=$(notdir $(foreach file,$(SOURCES),$(file:.c=.o))) +OBJ=$(foreach file,$(SOURCES),$(file:.c=.o)) +OBJ+=$(foreach file,$(MODULE_SOURCES),$(file:.c=.o)) + +LIB_SHARED=$(OUTPUT_NAME)_s.so +EXECUTABLE=$(OUTPUT_NAME) + +LIB_STATIC=$(OUTPUT_NAME).a +MODULENAME=$(OUTPUT_NAME).o + +obj: dirs depend $(OBJECTS) +lib_shared: $(LIB_SHARED) +exe: $(EXECUTABLE) +lib_static: $(LIB_STATIC) +module: $(MODULENAME) + +vpath %.o $(FINAL_OUTPUT_DIR) +vpath %.c $(dir $(SOURCES)) + +.PHONY: clean all help + +# Cleanup +clean: + @echo 'Removing derived objects...'; \ + $(RM) -rf $(OBJECTS) $(LIB_STATIC) $(LIB_SHARED) $(EXECUTABLE) *.o *.cov *.a *.so* *.mod.* *.ko .*.cmd; \ + $(RM)r .tmp_versions; \ + $(RM) -rf $(FINAL_OUTPUT_DIR); + +distclean:: clean cleandepend + $(RM) -rf $(MID_OUTPUT_DIR); + + + +# rules to create the output directories +dirs: + @echo 'Creating output directory' ;\ + test -d $(FINAL_OUTPUT_DIR) || mkdir -p $(FINAL_OUTPUT_DIR); + + +cleandepend: + @echo 'Clearing Dependencies' ;\ + $(RM) -f $(FINAL_OUTPUT_DIR)/.depend + + + +#include specific rules according to OS and IX_OS_LEVEL +include $(BUILDSYSTEM_PATH)/build_files/OS/$(OS)_$(OS_LEVEL)_rules.mk + + +ifdef ICP_ACCEL_INC +include $(ICP_BUILDSYSTEM_PATH)/build_files/includes.mk +endif + + diff --git a/clean_2.6.26.sh b/clean_2.6.26.sh new file mode 100755 index 0000000..526aee7 --- /dev/null +++ b/clean_2.6.26.sh @@ -0,0 +1,7 @@ +#!/bin/bash + +export KERNEL_SOURCE_ROOT=/usr/src/linux-headers-2.6.26-2-686 + +source ./make_intel_func + +clean_intel_very "$@" diff --git a/clean_2.6.32.sh b/clean_2.6.32.sh new file mode 100755 index 0000000..a8fa8ad --- /dev/null +++ b/clean_2.6.32.sh @@ -0,0 +1,7 @@ +#!/bin/bash + +export KERNEL_SOURCE_ROOT=/usr/src/linux-source-2.6.32 + +source ./make_intel_func + +clean_intel_very "$@" diff --git a/make_2.6.26.sh b/make_2.6.26.sh new file mode 100755 index 0000000..10240e7 --- /dev/null +++ b/make_2.6.26.sh @@ -0,0 +1,9 @@ +#!/bin/bash + +set -e + +export KERNEL_SOURCE_ROOT=/usr/src/linux-headers-2.6.26-2-686 + +source ./make_intel_func + +make_intel "$@" diff --git a/make_2.6.32.sh b/make_2.6.32.sh new file mode 100755 index 0000000..564f834 --- /dev/null +++ b/make_2.6.32.sh @@ -0,0 +1,9 @@ +#!/bin/bash + +set -e + +export KERNEL_SOURCE_ROOT=/usr/src/linux-source-2.6.32 + +source ./make_intel_func + +make_intel "$@" diff --git a/make_intel_func b/make_intel_func new file mode 100644 index 0000000..be130f6 --- /dev/null +++ b/make_intel_func @@ -0,0 +1,30 @@ +make_intel() { + export ICP_ROOT=$(pwd) + + # fun stuff: in one of Intel's makefile, IX_LINUXVER + # version is set to 2.6.18 + # Because I need to test the *REAL* version and not a + # completely arbitrary number, I add one more variable. + + export REAL_LINUX_VERSION="$(make -s -C $KERNEL_SOURCE_ROOT kernelversion)" + + echo "FOR LINUX $REAL_LINUX_VERSION: make $@" + echo + + make "$@" +} + +clean_intel_very() { + make_intel "$@" clean + + find -iname *.o -delete + find -iname Module.symvers -delete + find -iname build -exec rm -r {} \; + rmdir ./Acceleration/library/icp_services/RuntimeTargetLibrary/bin_linux_le/EP80579 + rmdir ./Acceleration/library/icp_services/RuntimeTargetLibrary/lib_linux_le/EP80579 + rm -r ./Acceleration/library/icp_utils/OSAL/lib/ + find -iname .tmp_versions -exec rm -r {} \; + find -iname '.*.o.cmd' -exec rm {} \; + find -iname '.*.o.d' -exec rm {} \; + find -iname 'modules.order' -exec rm {} \; +} |