From ed6f4dbfa44f154af94776093a2b43fc7a8a7320 Mon Sep 17 00:00:00 2001 From: Noé Rubinstein Date: Wed, 28 Jul 2010 12:25:26 +0200 Subject: GPIO kernel interface driver --- xhfc/xhfc_leb.h | 154 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 154 insertions(+) create mode 100644 xhfc/xhfc_leb.h (limited to 'xhfc/xhfc_leb.h') diff --git a/xhfc/xhfc_leb.h b/xhfc/xhfc_leb.h new file mode 100644 index 0000000..e9ee292 --- /dev/null +++ b/xhfc/xhfc_leb.h @@ -0,0 +1,154 @@ +/* + * (C) 2007 Copyright Cologne Chip AG + * Authors : Martin Bachem, Joerg Ciesielski + * Contact : info@colognechip.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + + +/*****************************************************************************/ + +#ifndef _XHFC_LEB_H_ +#define _XHFC_LEB_H_ + +#include +#include "xhfc.h" + +#define DRV_NAME "tolapai_leb_mode3m" + +#define LEB_CSRBAR 0 +#define LEB_MMBAR 1 + +/* === Registers EXP_TIMING_CSn === */ + + +/* Enable CS */ +#define LEB_TCS_CS_EN ( 1u << 31) + +/* Enable parity */ +#define LEB_TCS_PAR_EN ( 1u << 30) + +#define LEB_TCS_T1_ADDR_TM(x) (((x) & 3u) << 28) +#define LEB_TCS_T2_SU_CS_TM(x) (((x) & 3u) << 26) +#define LEB_TCS_T3_STRB_TM(x) (((x) & 15u) << 22) +#define LEB_TCS_T4_HOLD_TM(x) (((x) & 3u) << 20) +#define LEB_TCS_T5_RCVRY_TM(x) (((x) & 15u) << 16) + +#define LEB_TCS_CYC_TYPE(x) (((x) & 3u) << 14) +#define LEB_TCS_CYC_TYPE_INTEL LEB_TCS_CYC_TYPE(0) + +#define LEB_TCS_CNFG_4_0(x) (((x) & 31u) << 9) +#define LEB_TCS_CNFG_512_B LEB_TCS_CNFG_4_0(0) +#define LEB_TCS_CNFG_1_KiB LEB_TCS_CNFG_4_0(2) +#define LEB_TCS_CNFG_2_KiB LEB_TCS_CNFG_4_0(4) +#define LEB_TCS_CNFG_4_KiB LEB_TCS_CNFG_4_0(6) +#define LEB_TCS_CNFG_8_KiB LEB_TCS_CNFG_4_0(8) +#define LEB_TCS_CNFG_16_KiB LEB_TCS_CNFG_4_0(10) +#define LEB_TCS_CNFG_32_KiB LEB_TCS_CNFG_4_0(12) +#define LEB_TCS_CNFG_64_KiB LEB_TCS_CNFG_4_0(14) +#define LEB_TCS_CNFG_128_KiB LEB_TCS_CNFG_4_0(16) +#define LEB_TCS_CNFG_256_KiB LEB_TCS_CNFG_4_0(18) +#define LEB_TCS_CNFG_512_KiB LEB_TCS_CNFG_4_0(20) +#define LEB_TCS_CNFG_1_MiB LEB_TCS_CNFG_4_0(22) +#define LEB_TCS_CNFG_2_MiB LEB_TCS_CNFG_4_0(24) +#define LEB_TCS_CNFG_4_MiB LEB_TCS_CNFG_4_0(26) +#define LEB_TCS_CNFG_8_MiB LEB_TCS_CNFG_4_0(28) +#define LEB_TCS_CNFG_16_MiB LEB_TCS_CNFG_4_0(30) +/* Now the weird one (which also changes + * the memory map of MMBAR if used at least once): */ +#define LEB_TCS_CNFG_32_MiB LEB_TCS_CNFG_4_0(1) + +/* Synchronous Intel StrataFlash: */ +#define LEB_TCS_SYNC_INTEL ( 1u << 8) + +/* Target device is an EP80579 (hm, WTF??? TODONE ask Intel <- the conf is correct ) */ +#define LEB_TCS_EXP_CHIP ( 1u << 7) + +/* Byte read access to half-word device */ +#define LEB_TCS_BYTE_RD16 ( 1u << 6) + +/* For HPI (CS4 to CS7 only) + * 0 => Polarity low true + * 1 => Polarity high true + * + * Don't set if not HPI + */ +#define LEB_TCS_HRDY_POL ( 1u << 5) + +/* Enable address/data multiplexing: */ +#define LEB_TCS_MUX_EN ( 1u << 4) + +/* Split transaction on internal bus: */ +#define LEB_TCS_SPLT_EN ( 1u << 3) + +/* bit 2 is rsvd, a 0 must be written at this position */ + +/* Enable writes: */ +#define LEB_TCS_WR_EN ( 1u << 1) + +/* 8-bit device: + * 0 => 16-bit-wide data bus + * 1 => 8-bit data bus */ +#define LEB_TCS_BYTE_EN ( 1u << 0) + +#define IRQ_TLP_GPIO_30 31 + +extern uint trigger; + +static inline __u8 +read_xhfc(struct xhfc * xhfc, __u8 reg_addr) +{ + u8 __iomem *cs_n0 = xhfc->pi->cs_n0; + + return readb(&cs_n0[(trigger << 8) + reg_addr]); +} + +static inline void +write_xhfc(struct xhfc * xhfc, __u8 reg_addr, __u8 value) +{ + u8 __iomem *cs_n0 = xhfc->pi->cs_n0; + + writeb(value, &cs_n0[(trigger << 8) + reg_addr]); +} + +#if VERBOSE_TRANSACTIONS +#define read_xhfc(x, reg) ({ \ + u8 _res = read_xhfc(x, reg); \ + printk(KERN_INFO #reg " -> %02x\n", _res); \ + _res; \ + }) + +#define write_xhfc(x, reg, val) ({ \ + printk(KERN_INFO #reg " <- %02x\n", val); \ + write_xhfc(x, reg, val); \ + }) +#endif + +struct tlp_leb_regs { + u32 timing_cs[8]; + u32 cnfg0; + u32 _rsvd1[63]; + u32 parity_status; +}; + +void leb_init(struct xhfc_pi *leb); + +int __devinit xhfc_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); +void __devexit xhfc_remove_one(struct pci_dev *pdev); +void xhfc_shutdown(struct pci_dev *pdev); + +#endif /* _XHFC_LEB_H_ */ -- cgit v1.2.3