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authorNoé Rubinstein <nrubinstein@proformatique.com>2010-07-28 12:25:26 +0200
committerNoé Rubinstein <nrubinstein@proformatique.com>2010-07-28 12:25:26 +0200
commited6f4dbfa44f154af94776093a2b43fc7a8a7320 (patch)
treef005809a0ba245d6ca4f7ecfa1e6075db1fe7687 /gpio/common.h
parentf10dbbcb7cd35ac9bc3406dab41177572faa884d (diff)
GPIO kernel interface driver
Diffstat (limited to 'gpio/common.h')
-rw-r--r--gpio/common.h134
1 files changed, 134 insertions, 0 deletions
diff --git a/gpio/common.h b/gpio/common.h
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+
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * Contact Information:
+ * Intel Corporation
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ * version: Embedded.L.1.0.3-144
+ */
+
+/*****************************************************************************
+ * Module name:
+ * gpio
+ *
+ * Abstract:
+ * This header file is to be included by the gpio.c file only.
+ * It is OS independent.
+ *
+ * Revision:
+ *
+ *
+ *****************************************************************************/
+
+#ifndef COMMON_H
+#define COMMON_H
+
+#define SEL 2
+#define LVL 2
+
+//offset into low pin count(LPC) config space of the GPIO base address
+#define GPIO_BAR_OFFSET 0x48
+
+//vendor and device IDs of LPC device
+#define LPC_VENDOR_ID 0x8086
+#define LPC_DEVICE_ID 0x5031
+
+//Location of the LPC device on the PCI bus
+#define LPC_BUS_NUM 0
+#define LPC_DEVICE_NUM 31
+#define LPC_FUNCTION_NUM 0
+
+#define MAX_GPIO_SIGNALS 64
+
+//GPIO register memory size in bytes
+#define GPIO_MEM_SIZE 64
+
+//msb bit number of a GPIO register
+#define GPIO_REG_MSB 31
+
+//number of bits in a GPIO register
+#define GPIO_REG_BITS 32
+
+// offsets for gpio registers
+#define GPIO_USE_SEL 0x00
+#define GP_IO_SEL 0x04
+#define GP_LVL 0x0c
+#define GPO_BLINK 0x18
+#define GPI_INV 0x2c
+#define GPIO_USE_SEL2 0x30
+#define GP_IO_SEL2 0x34
+#define GP_LVL2 0x38
+
+
+/******************************************************************************
+ Description:
+ This structure contains an IO address to each of the gpio registers
+ contained in the hardware device memory. Each register can then be
+ accessed using the IO address.
+ *****************************************************************************/
+struct gpio_regs
+{
+ unsigned int gpio_use_sel; // alternative or gpio function (signals 0-31)
+ unsigned int gp_io_sel; // input or output (signals 0-31)
+ unsigned int gp_lvl; // low or high level (signals 0-31)
+ unsigned int gpo_blink; // blink function (signals 0-31)
+ unsigned int gpi_inv; // invert function (signals 0-31)
+ unsigned int gpio_use_sel2; // alternative or gpio function (signals 32-63)
+ unsigned int gp_io_sel2; // input or output (signals 32-63)
+ unsigned int gp_lvl2; // low or high level (signals 32-63)
+};
+
+#endif