/*
 * This file is part of the coreboot project.
 *
 * Copyright (C) 2008 Arastra, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 */

#ifndef NORTHBRIDGE_INTEL_I3100_RAMINIT_EP80579_H
#define NORTHBRIDGE_INTEL_I3100_RAMINIT_EP80579_H

#define DIMM_SOCKETS 2

#define BAR 0x90000000

/* EMR(1) settings:
	 *    12 11 10 987 6 543 2 1 0 (bit numbers)
	 * 000 0  1  0 111 0 000 1 0 0 (value)
	 * [0] DLL - enable
	 * [1] ODS - full
	 * [6,2] Rtt - disable
	 * [5:2] Additive CAS - 0
	 * [9:7] OCD program: 111 - enable default, 000 - exit (maintain setting)
	 * [10]  DQS# - Enable
	 * [11]  RDQS - Disable (only 1 slot, Micron TN-47-12)
	 * [12]  Outputs - Enabled (req'd by Micron)
	 * [15:13] Reserved - must be 0
	 * */
#define EMR1 0x03800001
/* EMR(2) settings:
 *   High temp refresh rate is off
 */
#define EMR2 0x00000000
/* EMR(3) settings:
 *   All reserved at this time
 */
#define EMR3 0x00000000

/* DIOMON offset - DDR I/O monitor register */
#define DIOMON 0xf0
/* Bit positions in DIOMON */
#define DSAMP 24
#define VRESULT 16
#define DDRIO_ENABLE 15
#define BIASSEL 11
#define DQLEGSELOUT 7
#define DIOPWR 6
#define CALEGSELOUT 0

#define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0 | DEVPRES_D4F0)

struct mem_controller {
	u32 node_id;
	device_t f0;
	u16 channel0[DIMM_SOCKETS];
};

/* Function prototypes. */
void sdram_initialize(int controllers, const struct mem_controller *ctrl);
void sdram_set_registers(const struct mem_controller *ctrl);
void sdram_set_spd_registers(const struct mem_controller *ctrl);
void sdram_enable(int controllers, const struct mem_controller *ctrl);
int memory_initialized(void);
int spd_read_byte(unsigned int device, unsigned int address);
void dump_dcal_regs(void);
#endif			/* NORTHBRIDGE_INTEL_I3100_RAMINIT_EP80579_H */