From 858231bdb223916d6fa56fd0278074905cc201c1 Mon Sep 17 00:00:00 2001 From: Bart Van Assche Date: Thu, 21 Sep 2023 12:22:47 -0700 Subject: scsi: ufs: core: Move the 4K alignment code into the Exynos driver The DMA alignment for the Exynos controller follows directly from the PRDT segment size configured in ufs-exynos.c. Hence, move the DMA alignment code into the Exynos driver source code. Cc: Alim Akhtar Signed-off-by: Bart Van Assche Link: https://lore.kernel.org/r/20230921192335.676924-3-bvanassche@acm.org Reviewed-by: Alim Akhtar Tested-by: Alim Akhtar Signed-off-by: Martin K. Petersen --- include/ufs/ufshcd.h | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) (limited to 'include/ufs') diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h index 7d07b256e906..e0d6590d163d 100644 --- a/include/ufs/ufshcd.h +++ b/include/ufs/ufshcd.h @@ -28,6 +28,7 @@ #define UFSHCD "ufshcd" +struct scsi_device; struct ufs_hba; enum dev_cmd_type { @@ -371,6 +372,7 @@ struct ufs_hba_variant_ops { int (*get_outstanding_cqs)(struct ufs_hba *hba, unsigned long *ocqs); int (*config_esi)(struct ufs_hba *hba); + void (*config_scsi_dev)(struct scsi_device *sdev); }; /* clock gating state */ @@ -596,11 +598,6 @@ enum ufshcd_quirks { */ UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING = 1 << 13, - /* - * Align DMA SG entries on a 4 KiB boundary. - */ - UFSHCD_QUIRK_4KB_DMA_ALIGNMENT = 1 << 14, - /* * This quirk needs to be enabled if the host controller does not * support UIC command -- cgit v1.2.3