From 1c6c924a49e0cd8f908409fb2a68570d9a4b2998 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Wed, 3 Jan 2018 13:41:03 +0100 Subject: arm64: dts: renesas: r8a7795: move scif node into alphabetical order MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move scif node so that sub-nodes of the root node are in alphabetical order. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven Tested-by: Niklas Söderlund --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index d12df6f2ff09..24e9209ea54e 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -165,13 +165,6 @@ clock-frequency = <0>; }; - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - /* External PCIe clock - can be overridden by the board */ pcie_bus_clk: pcie_bus { compatible = "fixed-clock"; @@ -208,6 +201,13 @@ method = "smc"; }; + /* External SCIF clock - to be overridden by boards that provide it */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; -- cgit v1.2.3 From dd149e851ace00a7832846e46ddefc6b181522c2 Mon Sep 17 00:00:00 2001 From: Dien Pham Date: Wed, 3 Jan 2018 13:41:04 +0100 Subject: arm64: dts: renesas: r8a7795: Add OPPs table for cpu devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define OOP tables for all CPUs. This allows CPUFreq to function. Based in part on work by Hien Dang. Signed-off-by: Dien Pham Signed-off-by: Takeshi Kihara Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven Tested-by: Niklas Söderlund --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 61 ++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 24e9209ea54e..1485e6a8e112 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -41,6 +41,8 @@ power-domains = <&sysc R8A7795_PD_CA57_CPU0>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7795_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; }; a57_1: cpu@1 { @@ -50,6 +52,8 @@ power-domains = <&sysc R8A7795_PD_CA57_CPU1>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7795_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; }; a57_2: cpu@2 { @@ -59,6 +63,8 @@ power-domains = <&sysc R8A7795_PD_CA57_CPU2>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7795_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; }; a57_3: cpu@3 { @@ -68,6 +74,8 @@ power-domains = <&sysc R8A7795_PD_CA57_CPU3>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7795_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; }; a53_0: cpu@100 { @@ -77,6 +85,8 @@ power-domains = <&sysc R8A7795_PD_CA53_CPU0>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; }; a53_1: cpu@101 { @@ -86,6 +96,8 @@ power-domains = <&sysc R8A7795_PD_CA53_CPU1>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; }; a53_2: cpu@102 { @@ -95,6 +107,8 @@ power-domains = <&sysc R8A7795_PD_CA53_CPU2>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; }; a53_3: cpu@103 { @@ -104,6 +118,8 @@ power-domains = <&sysc R8A7795_PD_CA53_CPU3>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; }; L2_CA57: cache-controller-0 { @@ -165,6 +181,51 @@ clock-frequency = <0>; }; + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <830000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <830000>; + clock-latency-ns = <300000>; + }; + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <830000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + opp-1600000000 { + opp-hz = /bits/ 64 <1600000000>; + opp-microvolt = <900000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + opp-1700000000 { + opp-hz = /bits/ 64 <1700000000>; + opp-microvolt = <960000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + }; + + cluster1_opp: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + }; + /* External PCIe clock - can be overridden by the board */ pcie_bus_clk: pcie_bus { compatible = "fixed-clock"; -- cgit v1.2.3 From da7e3113344fda50b10f1ad2c633abaaaf25d21b Mon Sep 17 00:00:00 2001 From: Dien Pham Date: Wed, 3 Jan 2018 13:41:05 +0100 Subject: arm64: dts: renesas: r8a7796: Add OPPs table for cpu devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define OOP tables for all CPUs. This allows CPUFreq to function. Based in part on work by Hien Dang. Signed-off-by: Dien Pham Signed-off-by: Takeshi Kihara Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven Tested-by: Niklas Söderlund --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 62 ++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index c5192d513d7d..e06bde6e2853 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -71,6 +71,8 @@ power-domains = <&sysc R8A7796_PD_CA57_CPU0>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7796_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; }; a57_1: cpu@1 { @@ -80,6 +82,8 @@ power-domains = <&sysc R8A7796_PD_CA57_CPU1>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7796_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; }; a53_0: cpu@100 { @@ -89,6 +93,8 @@ power-domains = <&sysc R8A7796_PD_CA53_CPU0>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; }; a53_1: cpu@101 { @@ -98,6 +104,8 @@ power-domains = <&sysc R8A7796_PD_CA53_CPU1>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; }; a53_2: cpu@102 { @@ -107,6 +115,8 @@ power-domains = <&sysc R8A7796_PD_CA53_CPU2>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; }; a53_3: cpu@103 { @@ -116,6 +126,8 @@ power-domains = <&sysc R8A7796_PD_CA53_CPU3>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; }; L2_CA57: cache-controller-0 { @@ -147,6 +159,56 @@ clock-frequency = <0>; }; + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1600000000 { + opp-hz = /bits/ 64 <1600000000>; + opp-microvolt = <900000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + opp-1700000000 { + opp-hz = /bits/ 64 <1700000000>; + opp-microvolt = <900000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <960000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + }; + + cluster1_opp: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + }; + /* External PCIe clock - can be overridden by the board */ pcie_bus_clk: pcie_bus { compatible = "fixed-clock"; -- cgit v1.2.3 From 479e5d70a9cee635d0feda260eed3719fb565ca8 Mon Sep 17 00:00:00 2001 From: Niklas Söderlund Date: Thu, 4 Jan 2018 17:03:20 +0100 Subject: arm64: dts: renesas: r8a7796: add thermal cooling management MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add nodes and properties for thermal cooling management support. Signed-off-by: Niklas Söderlund Acked-by: Eduardo Valentin Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 38 ++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index e06bde6e2853..ef10fb548681 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -73,6 +73,7 @@ enable-method = "psci"; clocks =<&cpg CPG_CORE R8A7796_CLK_Z>; operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; }; a57_1: cpu@1 { @@ -84,6 +85,7 @@ enable-method = "psci"; clocks =<&cpg CPG_CORE R8A7796_CLK_Z>; operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; }; a53_0: cpu@100 { @@ -2060,12 +2062,24 @@ thermal-sensors = <&tsc 0>; trips { + sensor1_passive: sensor1-passive { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; sensor1_crit: sensor1-crit { temperature = <120000>; hysteresis = <2000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&sensor1_passive>; + cooling-device = <&a57_0 5 5>; + }; + }; }; sensor_thermal2: sensor-thermal2 { @@ -2074,12 +2088,24 @@ thermal-sensors = <&tsc 1>; trips { + sensor2_passive: sensor2-passive { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; sensor2_crit: sensor2-crit { temperature = <120000>; hysteresis = <2000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&sensor2_passive>; + cooling-device = <&a57_0 5 5>; + }; + }; }; sensor_thermal3: sensor-thermal3 { @@ -2088,12 +2114,24 @@ thermal-sensors = <&tsc 2>; trips { + sensor3_passive: sensor3-passive { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; sensor3_crit: sensor3-crit { temperature = <120000>; hysteresis = <2000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&sensor3_passive>; + cooling-device = <&a57_0 5 5>; + }; + }; }; }; -- cgit v1.2.3 From 0c38c54ef9bc2a1062900adb01833e0b824f8462 Mon Sep 17 00:00:00 2001 From: Niklas Söderlund Date: Thu, 4 Jan 2018 17:03:19 +0100 Subject: arm64: dts: renesas: r8a7795: add thermal cooling management MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add nodes and properties for thermal cooling management support. Signed-off-by: Niklas Söderlund Acked-by: Eduardo Valentin Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 40 ++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 1485e6a8e112..19b7de57704c 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -43,6 +43,7 @@ enable-method = "psci"; clocks =<&cpg CPG_CORE R8A7795_CLK_Z>; operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; }; a57_1: cpu@1 { @@ -54,6 +55,7 @@ enable-method = "psci"; clocks =<&cpg CPG_CORE R8A7795_CLK_Z>; operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; }; a57_2: cpu@2 { @@ -65,6 +67,7 @@ enable-method = "psci"; clocks =<&cpg CPG_CORE R8A7795_CLK_Z>; operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; }; a57_3: cpu@3 { @@ -76,6 +79,7 @@ enable-method = "psci"; clocks =<&cpg CPG_CORE R8A7795_CLK_Z>; operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; }; a53_0: cpu@100 { @@ -2418,12 +2422,24 @@ thermal-sensors = <&tsc 0>; trips { + sensor1_passive: sensor1-passive { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; sensor1_crit: sensor1-crit { temperature = <120000>; hysteresis = <2000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&sensor1_passive>; + cooling-device = <&a57_0 4 4>; + }; + }; }; sensor_thermal2: sensor-thermal2 { @@ -2432,12 +2448,24 @@ thermal-sensors = <&tsc 1>; trips { + sensor2_passive: sensor2-passive { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; sensor2_crit: sensor2-crit { temperature = <120000>; hysteresis = <2000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&sensor2_passive>; + cooling-device = <&a57_0 4 4>; + }; + }; }; sensor_thermal3: sensor-thermal3 { @@ -2446,12 +2474,24 @@ thermal-sensors = <&tsc 2>; trips { + sensor3_passive: sensor3-passive { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; sensor3_crit: sensor3-crit { temperature = <120000>; hysteresis = <2000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&sensor3_passive>; + cooling-device = <&a57_0 4 4>; + }; + }; }; }; -- cgit v1.2.3 From ece30287af4e08e681f27c3d58853b68cdde658b Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Fri, 22 Dec 2017 21:11:46 +0100 Subject: arm64: dts: renesas: salvator-common: add GPIO extender We need to configure its GPIOs later. Signed-off-by: Wolfram Sang Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/salvator-common.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index c3fafb6025b3..89cbb3b95acd 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -338,6 +338,13 @@ &i2c4 { status = "okay"; + pca9654: gpio@20 { + compatible = "onnn,pca9654"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + csa_vdd: adc@7c { compatible = "maxim,max9611"; reg = <0x7c>; -- cgit v1.2.3 From 7569d1ee01c75b8581521bc67e595a575a7eafce Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Wed, 20 Dec 2017 13:25:49 +0100 Subject: arm64: dts: renesas: r8a77970: move node which has no reg property out of bus Move timer node from soc node to root node. The node that have been moved do not have any register properties and thus shouldn't be placed on the bus. This problem is flagged by the compiler as follows: $ make W=1 ... DTC arch/arm64/boot/dts/renesas/r8a77970-eagle.dtb arch/arm64/boot/dts/renesas/r8a77970-eagle.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property DTC arch/arm64/boot/dts/renesas/r8a77970-v3msk.dtb arch/arm64/boot/dts/renesas/r8a77970-v3msk.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77970.dtsi | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index c35a117fc447..566a7f704830 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -92,18 +92,6 @@ resets = <&cpg 408>; }; - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - rwdt: watchdog@e6020000 { compatible = "renesas,r8a77970-wdt", "renesas,rcar-gen3-wdt"; @@ -442,4 +430,12 @@ #size-cells = <0>; }; }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + }; }; -- cgit v1.2.3 From f320eead5dad37f296201bbcc00a88188a63a7da Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Wed, 20 Dec 2017 13:24:42 +0100 Subject: arm64: dts: renesas: r8a77995: move nodes which have no reg property out of bus Move pmu_a53 and timer nodes from soc node to root node. The nodes that have been moved do not have any register properties and thus shouldn't be placed on the bus. This problem is flagged by the compiler as follows: $ make W=1 ... arch/arm64/boot/dts/renesas/r8a77995-draak.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property arch/arm64/boot/dts/renesas/r8a77995-draak.dtb: Warning (simple_bus_reg): Node /soc/pmu_a53 missing or empty reg/ranges property Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77995.dtsi | 30 +++++++++++++----------------- 1 file changed, 13 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index cff42cd1a6c8..23f763beab46 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -58,6 +58,11 @@ clock-frequency = <0>; }; + pmu_a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + }; + scif_clk: scif { compatible = "fixed-clock"; #clock-cells = <0>; @@ -88,18 +93,6 @@ resets = <&cpg 408>; }; - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - rwdt: watchdog@e6020000 { compatible = "renesas,r8a77995-wdt", "renesas,rcar-gen3-wdt"; @@ -110,11 +103,6 @@ status = "disabled"; }; - pmu_a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts = ; - }; - ipmmu_vi0: mmu@febd0000 { compatible = "renesas,ipmmu-r8a77995"; reg = <0 0xfebd0000 0 0x1000>; @@ -637,4 +625,12 @@ status = "disabled"; }; }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + }; }; -- cgit v1.2.3 From cd8325dc194d6fa0707c9d5b427ca1fed6893b53 Mon Sep 17 00:00:00 2001 From: Niklas Söderlund Date: Fri, 5 Jan 2018 16:54:46 +0100 Subject: arm64: dts: renesas: r8a7795: update register size for thermal MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To be able to read fused calibration values from hardware the size of the register resource of TSC1 needs to be incremented to cover one more register which holds the information if the calibration values have been fused or not. Instead of increasing TSC1 size to the value from the datasheet update all TSC's size to the smallest granularity of the address decoder circuitry Signed-off-by: Niklas Söderlund Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 19b7de57704c..ce85704976f0 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -2385,9 +2385,9 @@ tsc: thermal@e6198000 { compatible = "renesas,r8a7795-thermal"; - reg = <0 0xe6198000 0 0x68>, - <0 0xe61a0000 0 0x5c>, - <0 0xe61a8000 0 0x5c>; + reg = <0 0xe6198000 0 0x100>, + <0 0xe61a0000 0 0x100>, + <0 0xe61a8000 0 0x100>; interrupts = , , ; -- cgit v1.2.3 From a052d934a4e03a81e1f6cf1c63ac693b04e9a441 Mon Sep 17 00:00:00 2001 From: Niklas Söderlund Date: Fri, 5 Jan 2018 16:54:47 +0100 Subject: arm64: dts: renesas: r8a7796: update register size for thermal MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To be able to read fused calibration values from hardware the size of the register resource of TSC1 needs to be incremented to cover one more register which holds the information if the calibration values have been fused or not. Instead of increasing TSC1 size to the value from the datasheet update all TSC's size to the smallest granularity of the address decoder circuitry. Signed-off-by: Niklas Söderlund Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index ef10fb548681..f8e9313f9405 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -1625,9 +1625,9 @@ tsc: thermal@e6198000 { compatible = "renesas,r8a7796-thermal"; - reg = <0 0xe6198000 0 0x68>, - <0 0xe61a0000 0 0x5c>, - <0 0xe61a8000 0 0x5c>; + reg = <0 0xe6198000 0 0x100>, + <0 0xe61a0000 0 0x100>, + <0 0xe61a8000 0 0x100>; interrupts = , , ; -- cgit v1.2.3 From ffcd060fd51682d2695da7334aa607a807e3838e Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Mon, 29 Jan 2018 16:45:44 +0100 Subject: arm64: dts: renesas: r8a77995: add I2C support Defines R-Car D3 I2C controllers 0-3. Signed-off-by: Ulrich Hecht Reviewed-by: Geert Uytterhoeven Acked-by: Wolfram Sang Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77995.dtsi | 67 +++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index 23f763beab46..22e633c87d4c 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -536,6 +536,73 @@ status = "disabled"; }; + i2c0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77995", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6500000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 931>; + dmas = <&dmac1 0x91>, <&dmac1 0x90>, + <&dmac2 0x91>, <&dmac2 0x90>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c1: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77995", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 930>; + dmas = <&dmac1 0x93>, <&dmac1 0x92>, + <&dmac2 0x93>, <&dmac2 0x92>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c2: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77995", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6510000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 929>; + dmas = <&dmac1 0x95>, <&dmac1 0x94>, + <&dmac2 0x95>, <&dmac2 0x94>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c3: i2c@e66d0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77995", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 928>; + dmas = <&dmac0 0x97>, <&dmac0 0x96>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + pwm0: pwm@e6e30000 { compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; reg = <0 0xe6e30000 0 0x8>; -- cgit v1.2.3 From 86e7a972adec5093e24e888ae3a949ee185dc533 Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Mon, 29 Jan 2018 16:45:45 +0100 Subject: arm64: dts: renesas: draak: enable I2C controller 0 and EEPROM Enables EEPROM on I2C0 on the Draak board. Signed-off-by: Ulrich Hecht Reviewed-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts index 09de73b11db8..6ff9d3eb7540 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts +++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts @@ -46,6 +46,11 @@ }; }; + i2c0_pins: i2c0 { + groups = "i2c0"; + function = "i2c0"; + }; + pwm0_pins: pwm0 { groups = "pwm0_c"; function = "pwm0"; @@ -67,6 +72,18 @@ }; }; +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + status = "okay"; + + eeprom@50 { + compatible = "rohm,br24t01", "atmel,24c01"; + reg = <0x50>; + pagesize = <8>; + }; +}; + &ehci0 { status = "okay"; }; -- cgit v1.2.3 From 41337aa1556a38a0b6861447ba7861c3a34bc204 Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Mon, 29 Jan 2018 16:45:46 +0100 Subject: arm64: dts: renesas: draak: enable I2C controller 1 No devices to add, I2C1 has an external connector only. Signed-off-by: Ulrich Hecht Reviewed-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts index 6ff9d3eb7540..af07da240be0 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts +++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts @@ -51,6 +51,11 @@ function = "i2c0"; }; + i2c1_pins: i2c1 { + groups = "i2c1"; + function = "i2c1"; + }; + pwm0_pins: pwm0 { groups = "pwm0_c"; function = "pwm0"; @@ -84,6 +89,12 @@ }; }; +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + &ehci0 { status = "okay"; }; -- cgit v1.2.3 From b85e1f77d9e285e61f8aa5a3a7e2bc46431d07ee Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Wed, 31 Jan 2018 22:59:03 +0300 Subject: arm64: add Renesas R8A77980 support Add a configuration option for the R-Car V3H (R8A77980) SoC. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/Kconfig.platforms | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index fbedbd8f619a..b51db26f6eaa 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -196,6 +196,12 @@ config ARCH_R8A77970 help This enables support for the Renesas R-Car V3M SoC. +config ARCH_R8A77980 + bool "Renesas R-Car V3H SoC Platform" + depends on ARCH_RENESAS + help + This enables support for the Renesas R-Car V3H SoC. + config ARCH_R8A77995 bool "Renesas R-Car D3 SoC Platform" depends on ARCH_RENESAS -- cgit v1.2.3 From f3a54d6c17f5ec826ff81e4f9f35a11e63211c53 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 2 Feb 2018 21:33:39 +0300 Subject: arm64: dts: renesas: initial R8A77980 SoC device tree The initial R8A77980 SoC device tree including Cortex-A53 CPU, GIC, timer, CPG, RST, and SYSC. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77980.dtsi | 122 ++++++++++++++++++++++++++++++ 1 file changed, 122 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a77980.dtsi diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi new file mode 100644 index 000000000000..6a92bbf55013 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the r8a77980 SoC + * + * Copyright (C) 2018 Renesas Electronics Corp. + * Copyright (C) 2018 Cogent Embedded, Inc. + */ + +#include +#include +#include + +/ { + compatible = "renesas,r8a77980"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + a53_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0>; + clocks = <&cpg CPG_CORE 0>; + power-domains = <&sysc 5>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + + L2_CA53: cache-controller { + compatible = "cache"; + power-domains = <&sysc 21>; + cache-unified; + cache-level = <2>; + }; + }; + + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + extalr_clk: extalr { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a77980-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a77980-rst"; + reg = <0 0xe6160000 0 0x200>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a77980-sysc"; + reg = <0 0xe6180000 0 0x440>; + #power-domain-cells = <1>; + }; + + gic: interrupt-controller@f1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1010000 0 0x1000>, + <0x0 0xf1020000 0 0x20000>, + <0x0 0xf1040000 0 0x20000>, + <0x0 0xf1060000 0 0x20000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc 32>; + resets = <&cpg 408>; + }; + + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_LOW)>; + }; +}; -- cgit v1.2.3 From 00d3375f918d503326bc4e4550b023d1a71e8d29 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 2 Feb 2018 21:36:16 +0300 Subject: arm64: dts: renesas: r8a77980: add SYS-DMAC support Describe SYS-DMAC1/2 in the R8A77980 device tree. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77980.dtsi | 68 +++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index 6a92bbf55013..e5c7cf391334 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -85,6 +85,74 @@ #power-domain-cells = <1>; }; + dmac1: dma-controller@e7300000 { + compatible = "renesas,dmac-r8a77980", + "renesas,rcar-dmac"; + reg = <0 0xe7300000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc 32>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + dmac2: dma-controller@e7310000 { + compatible = "renesas,dmac-r8a77980", + "renesas,rcar-dmac"; + reg = <0 0xe7310000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 217>; + clock-names = "fck"; + power-domains = <&sysc 32>; + resets = <&cpg 217>; + #dma-cells = <1>; + dma-channels = <16>; + }; + gic: interrupt-controller@f1010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; -- cgit v1.2.3 From d0d2ad1ff6e379a8ca6c8e814433e54637fb1516 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 6 Feb 2018 14:05:53 +0100 Subject: arm64: dts: renesas: r8a77970: Remove non-existing STBE region R-Car V3M does not have the Stream Buffer for EtherAVB-IF (STBE). Note that the RAVB driver does not use this region. Fixes: bea2ab136eaacec2 ("arm64: dts: renesas: r8a77970: add EtherAVB support") Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77970.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index 566a7f704830..fc397ccd06b6 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -388,7 +388,7 @@ avb: ethernet@e6800000 { compatible = "renesas,etheravb-r8a77970", "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; + reg = <0 0xe6800000 0 0x800>; interrupts = , , , -- cgit v1.2.3 From fa3d4c67dfe920515a3d840de983a2b3e77d3b94 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 6 Feb 2018 14:05:54 +0100 Subject: arm64: dts: renesas: r8a77995: Remove non-existing STBE region R-Car D3 does not have the Stream Buffer for EtherAVB-IF (STBE). Note that the RAVB driver does not use this region. Fixes: f9ba0c4cfe6169b7 ("arm64: dts: renesas: r8a77995: Add EthernetAVB device node") Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77995.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index 22e633c87d4c..cd3c6a30fc47 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -476,7 +476,7 @@ avb: ethernet@e6800000 { compatible = "renesas,etheravb-r8a77995", "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; + reg = <0 0xe6800000 0 0x800>; interrupts = , , , -- cgit v1.2.3 From 15981bab23cc1caf7070fa10ac39efa5d928dee9 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 10 Nov 2017 23:02:19 +0300 Subject: arm64: dts: renesas: r8a77970: add PFC support Define the generic R8A77970 part of the PFC device node. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77970.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index fc397ccd06b6..8eccfec83c9c 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -166,6 +166,11 @@ #iommu-cells = <1>; }; + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a77970"; + reg = <0 0xe6060000 0 0x504>; + }; + intc_ex: interrupt-controller@e61c0000 { compatible = "renesas,intc-ex-r8a77970", "renesas,irqc"; #interrupt-cells = <2>; -- cgit v1.2.3 From 31bded67ad215be592deda0c9ee8acdfe2067243 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 10 Nov 2017 23:02:20 +0300 Subject: arm64: dts: renesas: eagle: add SCIF0 pins Add the (previously omitted) SCIF0 pin data to the Eagle board's device tree. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77970-eagle.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts index 8fe5c193e049..f174103d2206 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts @@ -52,11 +52,21 @@ clock-frequency = <32768>; }; +&pfc { + scif0_pins: scif0 { + groups = "scif0_data"; + function = "scif0"; + }; +}; + &rwdt { timeout-sec = <60>; status = "okay"; }; &scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + status = "okay"; }; -- cgit v1.2.3 From 9618b2cbcf22fa3c206cac3984288413ef4d7194 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Tue, 13 Feb 2018 14:22:52 +0300 Subject: arm64: dts: renesas: r8a77970: add GPIO support Describe all 6 GPIO controllers in the R8A77970 device tree. Based on the original (and large) patch by Daisuke Matsushita . Signed-off-by: Vladimir Barinov Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77970.dtsi | 90 +++++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index 8eccfec83c9c..31eeca1531f6 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -171,6 +171,96 @@ reg = <0 0xe6060000 0 0x504>; }; + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a77970", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6050000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 22>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 912>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a77970", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6051000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 28>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 911>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a77970", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6052000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 17>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 910>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a77970", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6053000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 17>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 909>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a77970", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6054000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 6>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 908>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a77970", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6055000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 15>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 907>; + }; + intc_ex: interrupt-controller@e61c0000 { compatible = "renesas,intc-ex-r8a77970", "renesas,irqc"; #interrupt-cells = <2>; -- cgit v1.2.3 From 51671b265b2915846826da407a4ab7d4ba52f404 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Tue, 13 Feb 2018 14:24:14 +0300 Subject: arm64: dts: renesas: eagle: specify EtherAVB PHY IRQ Specify EtherAVB PHY IRQ in the Eagle board's device tree, now that we have the GPIO support (previously phylib had to resort to polling). Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77970-eagle.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts index f174103d2206..cb4bd40584cf 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts @@ -41,6 +41,8 @@ phy0: ethernet-phy@0 { rxc-skew-ps = <1500>; reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; }; }; -- cgit v1.2.3 From d7ef367be983185f336ac6e310ac9e469f53cd4a Mon Sep 17 00:00:00 2001 From: Kieran Bingham Date: Wed, 14 Feb 2018 09:55:04 +0000 Subject: arm64: dts: renesas: r8a77995: add FCPV nodes The FCPVB handles the interface between the VSPB and memory, while the FCPVD handles the interface between the VSPD and memory. Signed-off-by: Kieran Bingham Reviewed-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77995.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index cd3c6a30fc47..196a917afea6 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -691,6 +691,33 @@ #phy-cells = <0>; status = "disabled"; }; + + fcpvb0: fcp@fe96f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe96f000 0 0x200>; + clocks = <&cpg CPG_MOD 607>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 607>; + iommus = <&ipmmu_vp0 5>; + }; + + fcpvd0: fcp@fea27000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea27000 0 0x200>; + clocks = <&cpg CPG_MOD 603>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 603>; + iommus = <&ipmmu_vi0 8>; + }; + + fcpvd1: fcp@fea2f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea2f000 0 0x200>; + clocks = <&cpg CPG_MOD 602>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 602>; + iommus = <&ipmmu_vi0 9>; + }; }; timer { -- cgit v1.2.3 From 295952a183d3d10d4f532c623c51c30e25d6a421 Mon Sep 17 00:00:00 2001 From: Kieran Bingham Date: Wed, 14 Feb 2018 09:55:05 +0000 Subject: arm64: dts: renesas: r8a77995: add VSP instances The r8a77995 has a VSPBS to support image processing such as blending of two input images, and has two VSPDs to handle display pipelines with a DU. Signed-off-by: Kieran Bingham Reviewed-by: Laurent Pinchart [simon: updated base address of vsp node to fea28000] Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77995.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index 196a917afea6..621cf30e521d 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -692,6 +692,16 @@ status = "disabled"; }; + vspbs: vsp@fe960000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe960000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 627>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 627>; + renesas,fcp = <&fcpvb0>; + }; + fcpvb0: fcp@fe96f000 { compatible = "renesas,fcpv"; reg = <0 0xfe96f000 0 0x200>; @@ -701,6 +711,16 @@ iommus = <&ipmmu_vp0 5>; }; + vspd0: vsp@fea20000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea20000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 623>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 623>; + renesas,fcp = <&fcpvd0>; + }; + fcpvd0: fcp@fea27000 { compatible = "renesas,fcpv"; reg = <0 0xfea27000 0 0x200>; @@ -710,6 +730,16 @@ iommus = <&ipmmu_vi0 8>; }; + vspd1: vsp@fea28000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea28000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 622>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 622>; + renesas,fcp = <&fcpvd1>; + }; + fcpvd1: fcp@fea2f000 { compatible = "renesas,fcpv"; reg = <0 0xfea2f000 0 0x200>; -- cgit v1.2.3 From 9d9505a2f4eb6aa29639c90b8ad596e62314faec Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Wed, 29 Nov 2017 17:06:46 +0100 Subject: arm64: dts: renesas: draak: enable SDHI2 The single SDHI controller is connected to eMMC. Signed-off-by: Ulrich Hecht Acked-by: Wolfram Sang Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 44 ++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts index af07da240be0..7ea6709d706d 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts +++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts @@ -32,6 +32,24 @@ /* first 128MB is reserved for secure area. */ reg = <0x0 0x48000000 0x0 0x18000000>; }; + + reg_1p8v: regulator0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator1 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; }; &extal_clk { @@ -71,6 +89,18 @@ function = "scif2"; }; + sdhi2_pins: sd2 { + groups = "mmc_data8", "mmc_ctrl"; + function = "mmc"; + power-source = <1800>; + }; + + sdhi2_pins_uhs: sd2_uhs { + groups = "mmc_data8", "mmc_ctrl"; + function = "mmc"; + power-source = <1800>; + }; + usb0_pins: usb0 { groups = "usb0"; function = "usb0"; @@ -125,6 +155,20 @@ status = "okay"; }; +&sdhi2 { + /* used for on-board eMMC */ + pinctrl-0 = <&sdhi2_pins>; + pinctrl-1 = <&sdhi2_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + status = "okay"; +}; + &usb2_phy0 { pinctrl-0 = <&usb0_pins>; pinctrl-names = "default"; -- cgit v1.2.3 From 18f1a773e3f9e6d1eb5549d98bae6f2959edecf2 Mon Sep 17 00:00:00 2001 From: Kieran Bingham Date: Thu, 15 Feb 2018 08:38:19 +0000 Subject: arm64: dts: renesas: r8a77995: add DU support Define the generic r8a77995 part of the DU device node. Signed-off-by: Kieran Bingham Reviewed-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77995.dtsi | 35 +++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index 621cf30e521d..bcf737a20636 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -748,6 +748,41 @@ resets = <&cpg 602>; iommus = <&ipmmu_vi0 9>; }; + + du: display@feb00000 { + compatible = "renesas,du-r8a77995"; + reg = <0 0xfeb00000 0 0x80000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>; + clock-names = "du.0", "du.1"; + vsps = <&vspd0 0 &vspd1 0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb: endpoint { + }; + }; + + port@1 { + reg = <1>; + du_out_lvds0: endpoint { + }; + }; + + port@2 { + reg = <2>; + du_out_lvds1: endpoint { + }; + }; + }; + }; }; timer { -- cgit v1.2.3 From d9366032b63bb544fd7d2fd290a922e8484a52c5 Mon Sep 17 00:00:00 2001 From: Kieran Bingham Date: Wed, 14 Feb 2018 09:55:06 +0000 Subject: arm64: dts: renesas: r8a7795-es1: Fix register mappings on VSPs The VSPD includes a CLUT on RPF2. Ensure that the register space is mapped correctly to support this. Signed-off-by: Kieran Bingham Reviewed-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi index 26769a11a190..f1d5e90503d5 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi @@ -80,7 +80,7 @@ vspd3: vsp@fea38000 { compatible = "renesas,vsp2"; - reg = <0 0xfea38000 0 0x4000>; + reg = <0 0xfea38000 0 0x8000>; interrupts = ; clocks = <&cpg CPG_MOD 620>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; -- cgit v1.2.3 From c5dcfe6552f418df8db03e92e645339cdf746e34 Mon Sep 17 00:00:00 2001 From: Kieran Bingham Date: Wed, 14 Feb 2018 09:55:07 +0000 Subject: arm64: dts: renesas: r8a7795: Fix register mappings on VSPs The VSPD includes a CLUT on RPF2. Ensure that the register space is mapped correctly to support this. Signed-off-by: Kieran Bingham Reviewed-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index ce85704976f0..9dc2b43e59f5 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -2208,7 +2208,7 @@ vspd0: vsp@fea20000 { compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x4000>; + reg = <0 0xfea20000 0 0x8000>; interrupts = ; clocks = <&cpg CPG_MOD 623>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; @@ -2228,7 +2228,7 @@ vspd1: vsp@fea28000 { compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x4000>; + reg = <0 0xfea28000 0 0x8000>; interrupts = ; clocks = <&cpg CPG_MOD 622>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; @@ -2248,7 +2248,7 @@ vspd2: vsp@fea30000 { compatible = "renesas,vsp2"; - reg = <0 0xfea30000 0 0x4000>; + reg = <0 0xfea30000 0 0x8000>; interrupts = ; clocks = <&cpg CPG_MOD 621>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; -- cgit v1.2.3 From 4361e56b751bbebf6a8660cd41429d8a3eb5e278 Mon Sep 17 00:00:00 2001 From: Kieran Bingham Date: Wed, 14 Feb 2018 09:55:08 +0000 Subject: arm64: dts: renesas: r8a7796: Fix register mappings on VSPs The VSPD includes a CLUT on RPF2. Ensure that the register space is mapped correctly to support this. Signed-off-by: Kieran Bingham Reviewed-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index f8e9313f9405..157bd28014ed 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -1903,7 +1903,7 @@ vspd0: vsp@fea20000 { compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x4000>; + reg = <0 0xfea20000 0 0x8000>; interrupts = ; clocks = <&cpg CPG_MOD 623>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; @@ -1923,7 +1923,7 @@ vspd1: vsp@fea28000 { compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x4000>; + reg = <0 0xfea28000 0 0x8000>; interrupts = ; clocks = <&cpg CPG_MOD 622>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; @@ -1943,7 +1943,7 @@ vspd2: vsp@fea30000 { compatible = "renesas,vsp2"; - reg = <0 0xfea30000 0 0x4000>; + reg = <0 0xfea30000 0 0x8000>; interrupts = ; clocks = <&cpg CPG_MOD 621>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; -- cgit v1.2.3 From cfdec2af68acb32c805aaa454f151f8681e07673 Mon Sep 17 00:00:00 2001 From: Kieran Bingham Date: Fri, 16 Feb 2018 12:32:35 +0000 Subject: arm64: dts: renesas: draak: Enable DU Enable the DU, providing only the VGA output for now. Signed-off-by: Kieran Bingham Reviewed-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 51 ++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts index 7ea6709d706d..34c7f58417ba 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts +++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts @@ -27,6 +27,38 @@ stdout-path = "serial0:115200n8"; }; + vga { + compatible = "vga-connector"; + + port { + vga_in: endpoint { + remote-endpoint = <&adv7123_out>; + }; + }; + }; + + vga-encoder { + compatible = "adi,adv7123"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7123_in: endpoint { + remote-endpoint = <&du_out_rgb>; + }; + }; + port@1 { + reg = <1>; + adv7123_out: endpoint { + remote-endpoint = <&vga_in>; + }; + }; + }; + }; + memory@48000000 { device_type = "memory"; /* first 128MB is reserved for secure area. */ @@ -64,6 +96,11 @@ }; }; + du_pins: du { + groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; + function = "du"; + }; + i2c0_pins: i2c0 { groups = "i2c0"; function = "i2c0"; @@ -125,6 +162,20 @@ status = "okay"; }; +&du { + pinctrl-0 = <&du_pins>; + pinctrl-names = "default"; + status = "okay"; + + ports { + port@0 { + endpoint { + remote-endpoint = <&adv7123_in>; + }; + }; + }; +}; + &ehci0 { status = "okay"; }; -- cgit v1.2.3 From 3601d98ceab56e3d04c9c5e029903bee0337cb94 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 16 Feb 2018 21:30:23 +0300 Subject: arm64: dts: renesas: r8a77980: add [H]SCIF support Describe [H]SCIF ports in the R8A77980 device tree. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77980.dtsi | 151 ++++++++++++++++++++++++++++++ 1 file changed, 151 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index e5c7cf391334..eaa546f0a91f 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -56,6 +56,13 @@ method = "smc"; }; + /* External SCIF clock - to be overridden by boards that provide it */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + soc { compatible = "simple-bus"; interrupt-parent = <&gic>; @@ -85,6 +92,150 @@ #power-domain-cells = <1>; }; + hscif0: serial@e6540000 { + compatible = "renesas,hscif-r8a77980", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6540000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 520>, + <&cpg CPG_CORE 19>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x31>, <&dmac1 0x30>, + <&dmac2 0x31>, <&dmac2 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 520>; + status = "disabled"; + }; + + hscif1: serial@e6550000 { + compatible = "renesas,hscif-r8a77980", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6550000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 519>, + <&cpg CPG_CORE 19>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x33>, <&dmac1 0x32>, + <&dmac2 0x33>, <&dmac2 0x32>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 519>; + status = "disabled"; + }; + + hscif2: serial@e6560000 { + compatible = "renesas,hscif-r8a77980", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6560000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 518>, + <&cpg CPG_CORE 19>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x35>, <&dmac1 0x34>, + <&dmac2 0x35>, <&dmac2 0x34>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 518>; + status = "disabled"; + }; + + hscif3: serial@e66a0000 { + compatible = "renesas,hscif-r8a77980", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66a0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 517>, + <&cpg CPG_CORE 19>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x37>, <&dmac1 0x36>, + <&dmac2 0x37>, <&dmac2 0x36>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 517>; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a77980", + "renesas,rcar-gen3-scif", + "renesas,scif"; + reg = <0 0xe6e60000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 207>, + <&cpg CPG_CORE 19>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x51>, <&dmac1 0x50>, + <&dmac2 0x51>, <&dmac2 0x50>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 207>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a77980", + "renesas,rcar-gen3-scif", + "renesas,scif"; + reg = <0 0xe6e68000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 206>, + <&cpg CPG_CORE 19>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x53>, <&dmac1 0x52>, + <&dmac2 0x53>, <&dmac2 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 206>; + status = "disabled"; + }; + + scif3: serial@e6c50000 { + compatible = "renesas,scif-r8a77980", + "renesas,rcar-gen3-scif", + "renesas,scif"; + reg = <0 0xe6c50000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 204>, + <&cpg CPG_CORE 19>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x57>, <&dmac1 0x56>, + <&dmac2 0x57>, <&dmac2 0x56>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 204>; + status = "disabled"; + }; + + scif4: serial@e6c40000 { + compatible = "renesas,scif-r8a77980", + "renesas,rcar-gen3-scif", + "renesas,scif"; + reg = <0 0xe6c40000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 203>, + <&cpg CPG_CORE 19>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x59>, <&dmac1 0x58>, + <&dmac2 0x59>, <&dmac2 0x58>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 203>; + status = "disabled"; + }; + dmac1: dma-controller@e7300000 { compatible = "renesas,dmac-r8a77980", "renesas,rcar-dmac"; -- cgit v1.2.3 From bf6f90832f81710ee944dce05ecbef04d1943664 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 16 Feb 2018 21:32:54 +0300 Subject: arm64: dts: renesas: r8a77980: add EtherAVB support Define the generic R8A77980 part of the EtherAVB device node. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77980.dtsi | 44 +++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index eaa546f0a91f..03845fd74996 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -164,6 +164,50 @@ status = "disabled"; }; + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a77980", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6800000 0 0x800>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc 32>; + resets = <&cpg 812>; + phy-mode = "rgmii"; + #address-cells = <1>; + #size-cells = <0>; + }; + scif0: serial@e6e60000 { compatible = "renesas,scif-r8a77980", "renesas,rcar-gen3-scif", -- cgit v1.2.3 From b9edbce9155c718a1eeed535e88f88d4b6ef7783 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 16 Feb 2018 21:35:22 +0300 Subject: arm64: dts: renesas: initial Condor board device tree Add the initial device tree for the R8A77980 SoC based Condor board. The board has 1 debug serial port (SCIF0); include support for it, so that the serial console can work. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven [simon: correct memory size to 0x78000000 (2GiB)] Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/Makefile | 1 + arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 45 +++++++++++++++++++++++++ 2 files changed, 46 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a77980-condor.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 2186d0193b73..c885eef4e660 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -8,4 +8,5 @@ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb +dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts new file mode 100644 index 000000000000..daf2957d3504 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the Condor board + * + * Copyright (C) 2018 Renesas Electronics Corp. + * Copyright (C) 2018 Cogent Embedded, Inc. + */ + +/dts-v1/; +#include "r8a77980.dtsi" + +/ { + model = "Renesas Condor board based on r8a77980"; + compatible = "renesas,condor", "renesas,r8a77980"; + + aliases { + serial0 = &scif0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0 0x48000000 0 0x78000000>; + }; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&scif0 { + status = "okay"; +}; + +&scif_clk { + clock-frequency = <14745600>; +}; -- cgit v1.2.3 From 8091788f3d3856a0b6eabebf4e34cfecb38cfe96 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 16 Feb 2018 21:38:31 +0300 Subject: arm64: dts: renesas: condor: add EtherAVB support Define the Condor board dependent part of the EtherAVB device node. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts index daf2957d3504..06cf6845765a 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts +++ b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts @@ -15,6 +15,7 @@ aliases { serial0 = &scif0; + ethernet0 = &avb; }; chosen { @@ -28,6 +29,18 @@ }; }; +&avb { + phy-mode = "rgmii-id"; + phy-handle = <&phy0>; + renesas,no-ether-link; + status = "okay"; + + phy0: ethernet-phy@0 { + rxc-skew-ps = <1500>; + reg = <0>; + }; +}; + &extal_clk { clock-frequency = <16666666>; }; -- cgit v1.2.3 From fbdad84cc759abc469e476ee2518d77280e80cd0 Mon Sep 17 00:00:00 2001 From: Dien Pham Date: Mon, 29 Jan 2018 19:21:20 +0100 Subject: arm64: dts: renesas: r8a7796: Update OPPs to support CA53 dfs Describe frequencies, other than the default for CA53 cores. This is a pre-requisite for using providing alternative frequencies for use with CPUFreq with these cores. Signed-off-by: Dien Pham Signed-off-by: Takeshi Kihara Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 157bd28014ed..076a9c9346ae 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -204,11 +204,27 @@ compatible = "operating-points-v2"; opp-shared; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <820000>; clock-latency-ns = <300000>; }; + opp-1300000000 { + opp-hz = /bits/ 64 <1300000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + turbo-mode; + }; }; /* External PCIe clock - can be overridden by the board */ -- cgit v1.2.3 From 85618efe149082b50f846834356b3bc23c4d1141 Mon Sep 17 00:00:00 2001 From: Dien Pham Date: Mon, 29 Jan 2018 19:21:21 +0100 Subject: arm64: dts: renesas: r8a7795: Update OPPs to support CA53 dfs Describe frequencies, other than the default for CA53 cores. This is a pre-requisite for using providing alternative frequencies for use with CPUFreq with these cores. Signed-off-by: Dien Pham Signed-off-by: Takeshi Kihara Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 9dc2b43e59f5..6d53e1cb7b29 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -223,6 +223,16 @@ compatible = "operating-points-v2"; opp-shared; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <820000>; -- cgit v1.2.3 From fd60ea3171c7429a37c5b47a9893f96c704f990d Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Tue, 20 Feb 2018 16:12:09 +0100 Subject: arm64: add Renesas R8A77965 support Add configuration option for the R-Car M3-N (R8A77965) SoC. Signed-off-by: Jacopo Mondi Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/Kconfig.platforms | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index b51db26f6eaa..2b1535cdeb7c 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -190,6 +190,12 @@ config ARCH_R8A7796 help This enables support for the Renesas R-Car M3-W SoC. +config ARCH_R8A77965 + bool "Renesas R-Car M3-N SoC Platform" + depends on ARCH_RENESAS + help + This enables support for the Renesas R-Car M3-N SoC. + config ARCH_R8A77970 bool "Renesas R-Car V3M SoC Platform" depends on ARCH_RENESAS -- cgit v1.2.3 From df863d6f95f57dbb4f7c2f5ec2f230809551b17f Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Tue, 20 Feb 2018 16:12:10 +0100 Subject: arm64: dts: renesas: initial R8A77965 SoC device tree Basic support for the Gen 3 R-Car M3-N SoC. Based on original work from: Takeshi Kihara Magnus Damm Signed-off-by: Jacopo Mondi Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 490 ++++++++++++++++++++++++++++++ 1 file changed, 490 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a77965.dtsi diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi new file mode 100644 index 000000000000..6b6ec653f543 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -0,0 +1,490 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the r8a77965 SoC + * + * Copyright (C) 2018 Jacopo Mondi + * + * Based on r8a7796.dtsi + * Copyright (C) 2016 Renesas Electronics Corp. + */ + +#include +#include + +#define CPG_AUDIO_CLK_I 10 + +/ { + compatible = "renesas,r8a77965"; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + a57_0: cpu@0 { + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x0>; + device_type = "cpu"; + power-domains = <&sysc 0>; + next-level-cache = <&L2_CA57>; + enable-method = "psci"; + }; + + a57_1: cpu@1 { + compatible = "arm,cortex-a57","arm,armv8"; + reg = <0x1>; + device_type = "cpu"; + power-domains = <&sysc 1>; + next-level-cache = <&L2_CA57>; + enable-method = "psci"; + }; + + L2_CA57: cache-controller-0 { + compatible = "cache"; + reg = <0>; + power-domains = <&sysc 12>; + cache-unified; + cache-level = <2>; + }; + }; + + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + extalr_clk: extalr { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External SCIF clock - to be overridden by boards that provide it */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External USB clocks - can be overridden by the board */ + usb3s0_clk: usb3s0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; + + pmu_a57 { + compatible = "arm,cortex-a57-pmu"; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a57_0>, + <&a57_1>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@f1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1010000 0 0x1000>, + <0x0 0xf1020000 0 0x20000>, + <0x0 0xf1040000 0 0x20000>, + <0x0 0xf1060000 0 0x20000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc 32>; + resets = <&cpg 408>; + }; + + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a77965"; + reg = <0 0xe6060000 0 0x50c>; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a77965-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a77965-rst"; + reg = <0 0xe6160000 0 0x0200>; + }; + + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a77965-sysc"; + reg = <0 0xe6180000 0 0x0400>; + #power-domain-cells = <1>; + }; + + gpio0: gpio@e6050000 { + /* placeholder */ + }; + + gpio1: gpio@e6051000 { + /* placeholder */ + }; + + gpio2: gpio@e6052000 { + /* placeholder */ + }; + + gpio3: gpio@e6053000 { + /* placeholder */ + }; + + gpio4: gpio@e6054000 { + /* placeholder */ + }; + + gpio5: gpio@e6055000 { + /* placeholder */ + }; + + gpio6: gpio@e6055400 { + /* placeholder */ + }; + + gpio7: gpio@e6055800 { + /* placeholder */ + }; + + intc_ex: interrupt-controller@e61c0000 { + /* placeholder */ + }; + + dmac0: dma-controller@e6700000 { + /* placeholder */ + }; + + dmac1: dma-controller@e7300000 { + /* placeholder */ + }; + + dmac2: dma-controller@e7310000 { + /* placeholder */ + }; + + scif0: serial@e6e60000 { + /* placeholder */ + }; + + scif1: serial@e6e68000 { + /* placeholder */ + }; + + scif2: serial@e6e88000 { + /* placeholder */ + }; + + scif3: serial@e6c50000 { + /* placeholder */ + }; + + scif4: serial@e6c40000 { + /* placeholder */ + }; + + scif5: serial@e6f30000 { + /* placeholder */ + }; + + avb: ethernet@e6800000 { + /* placeholder */ + }; + + csi20: csi2@fea80000 { + /* placeholder */ + }; + + csi40: csi2@feaa0000 { + /* placeholder */ + }; + + vin0: video@e6ef0000 { + /* placeholder */ + }; + + vin1: video@e6ef1000 { + /* placeholder */ + }; + + vin2: video@e6ef2000 { + /* placeholder */ + }; + + vin3: video@e6ef3000 { + /* placeholder */ + }; + + vin4: video@e6ef4000 { + /* placeholder */ + }; + + vin5: video@e6ef5000 { + /* placeholder */ + }; + + vin6: video@e6ef6000 { + /* placeholder */ + }; + + vin7: video@e6ef7000 { + /* placeholder */ + }; + + ohci0: usb@ee080000 { + /* placeholder */ + }; + + ehci0: usb@ee080100 { + /* placeholder */ + }; + + usb2_phy0: usb-phy@ee080200 { + /* placeholder */ + }; + + ohci1: usb@ee0a0000 { + /* placeholder */ + }; + + ehci1: usb@ee0a0100 { + /* placeholder */ + }; + + i2c0: i2c@e6500000 { + /* placeholder */ + }; + + i2c1: i2c@e6508000 { + /* placeholder */ + }; + + i2c2: i2c@e6510000 { + /* placeholder */ + }; + + i2c3: i2c@e66d0000 { + /* placeholder */ + }; + + i2c4: i2c@e66d8000 { + /* placeholder */ + }; + + i2c5: i2c@e66e0000 { + /* placeholder */ + }; + + i2c6: i2c@e66e8000 { + /* placeholder */ + }; + + i2c_dvfs: i2c@e60b0000 { + /* placeholder */ + }; + + pwm0: pwm@e6e30000 { + /* placeholder */ + }; + + pwm1: pwm@e6e31000 { + /* placeholder */ + }; + + pwm2: pwm@e6e32000 { + /* placeholder */ + }; + + pwm3: pwm@e6e33000 { + /* placeholder */ + }; + + pwm4: pwm@e6e34000 { + /* placeholder */ + }; + + pwm5: pwm@e6e35000 { + /* placeholder */ + }; + + pwm6: pwm@e6e36000 { + /* placeholder */ + }; + + du: display@feb00000 { + /* placeholder */ + + ports { + port@0 { + reg = <0>; + du_out_rgb: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_hdmi0: endpoint { + }; + }; + port@2 { + reg = <2>; + du_out_lvds0: endpoint { + }; + }; + }; + }; + + hsusb: usb@e6590000 { + /* placeholder */ + }; + + pciec0: pcie@fe000000 { + /* placeholder */ + }; + + pciec1: pcie@ee800000 { + /* placeholder */ + }; + + rcar_sound: sound@ec500000 { + /* placeholder */ + + rcar_sound,dvc { + dvc0: dvc-0 { + }; + dvc1: dvc-1 { + }; + }; + + rcar_sound,src { + src0: src-0 { + }; + src1: src-1 { + }; + }; + + rcar_sound,ssi { + ssi0: ssi-0 { + }; + ssi1: ssi-1 { + }; + }; + }; + + usb2_phy1: usb-phy@ee0a0200 { + /* placeholder */ + }; + + sdhi0: sd@ee100000 { + /* placeholder */ + }; + + sdhi1: sd@ee120000 { + /* placeholder */ + }; + + sdhi2: sd@ee140000 { + /* placeholder */ + }; + + sdhi3: sd@ee160000 { + /* placeholder */ + }; + + usb3_phy0: usb-phy@e65ee000 { + /* placeholder */ + }; + + usb3_peri0: usb@ee020000 { + /* placeholder */ + }; + + xhci0: usb@ee000000 { + /* placeholder */ + }; + + wdt0: watchdog@e6020000 { + /* placeholder */ + }; + }; +}; -- cgit v1.2.3 From 5a2cd7e84945bc9acfcada18cb5f66cda9c1529e Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Tue, 20 Feb 2018 16:12:11 +0100 Subject: arm64: dts: renesas: Add R-Car Salvator-x M3-N support Add basic support for R-Car Salvator-X M3-N (R8A77965) board. Based on original work from: Takeshi Kihara Magnus Damm Signed-off-by: Jacopo Mondi Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/Makefile | 1 + arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts | 21 +++++++++++++++++++++ 2 files changed, 22 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index c885eef4e660..9ea5ec0daeba 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-h3ulcb-kf.dtb dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb +dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts new file mode 100644 index 000000000000..75d890d91df9 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the Salvator-X board with R-Car M3-N + * + * Copyright (C) 2018 Jacopo Mondi + */ + +/dts-v1/; +#include "r8a77965.dtsi" +#include "salvator-x.dtsi" + +/ { + model = "Renesas Salvator-X board based on r8a77965"; + compatible = "renesas,salvator-x", "renesas,r8a77965"; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; +}; -- cgit v1.2.3 From 838c1121ca592bd39e33d5687af3eea9fc9d0700 Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Tue, 20 Feb 2018 16:12:13 +0100 Subject: arm64: dts: renesas: r8a77965: Add dmac device nods Add dmac[0-2] device nodes for R-Car M3-N (r8a77965) SoC. Signed-off-by: Jacopo Mondi Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 96 ++++++++++++++++++++++++++++++- 1 file changed, 93 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 6b6ec653f543..b83dafc5745e 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -233,15 +233,105 @@ }; dmac0: dma-controller@e6700000 { - /* placeholder */ + compatible = "renesas,dmac-r8a77965", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc 32>; + resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <16>; }; dmac1: dma-controller@e7300000 { - /* placeholder */ + compatible = "renesas,dmac-r8a77965", + "renesas,rcar-dmac"; + reg = <0 0xe7300000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc 32>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <16>; }; dmac2: dma-controller@e7310000 { - /* placeholder */ + compatible = "renesas,dmac-r8a77965", + "renesas,rcar-dmac"; + reg = <0 0xe7310000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 217>; + clock-names = "fck"; + power-domains = <&sysc 32>; + resets = <&cpg 217>; + #dma-cells = <1>; + dma-channels = <16>; }; scif0: serial@e6e60000 { -- cgit v1.2.3 From 0ea5b2fd38db56aad29e4b6a2028fccde438a110 Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Tue, 20 Feb 2018 16:12:16 +0100 Subject: arm64: dts: renesas: r8a77965: Add SCIF device nodes Add SCIF[0-5] device nodes for M3-N (r8a77965) SoC. Signed-off-by: Jacopo Mondi Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 85 ++++++++++++++++++++++++++++--- 1 file changed, 79 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index b83dafc5745e..3cb1a332314e 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -335,27 +335,100 @@ }; scif0: serial@e6e60000 { - /* placeholder */ + compatible = "renesas,scif-r8a77965", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 207>, + <&cpg CPG_CORE 20>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x51>, <&dmac1 0x50>, + <&dmac2 0x51>, <&dmac2 0x50>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 207>; + status = "disabled"; }; scif1: serial@e6e68000 { - /* placeholder */ + compatible = "renesas,scif-r8a77965", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 206>, + <&cpg CPG_CORE 20>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x53>, <&dmac1 0x52>, + <&dmac2 0x53>, <&dmac2 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 206>; + status = "disabled"; }; scif2: serial@e6e88000 { - /* placeholder */ + compatible = "renesas,scif-r8a77965", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e88000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 310>, + <&cpg CPG_CORE 20>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc 32>; + resets = <&cpg 310>; + status = "disabled"; }; scif3: serial@e6c50000 { - /* placeholder */ + compatible = "renesas,scif-r8a77965", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c50000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 204>, + <&cpg CPG_CORE 20>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x57>, <&dmac0 0x56>; + dma-names = "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 204>; + status = "disabled"; }; scif4: serial@e6c40000 { - /* placeholder */ + compatible = "renesas,scif-r8a77965", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c40000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 203>, + <&cpg CPG_CORE 20>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x59>, <&dmac0 0x58>; + dma-names = "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 203>; + status = "disabled"; }; scif5: serial@e6f30000 { - /* placeholder */ + compatible = "renesas,scif-r8a77965", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6f30000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 202>, + <&cpg CPG_CORE 20>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, + <&dmac2 0x5b>, <&dmac2 0x5a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 202>; + status = "disabled"; }; avb: ethernet@e6800000 { -- cgit v1.2.3 From e34ca96b81a241523f79a244b5551135cf069852 Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Tue, 20 Feb 2018 16:12:18 +0100 Subject: arm64: dts: renesas: r8a77965: Add GPIO nodes Add GPIO nodes to r8a77965 SoC device tree file. Signed-off-by: Jacopo Mondi Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 104 +++++++++++++++++++++++++++--- 1 file changed, 96 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 3cb1a332314e..55f05f79f7f7 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -197,35 +197,123 @@ }; gpio0: gpio@e6050000 { - /* placeholder */ + compatible = "renesas,gpio-r8a77965", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6050000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 16>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc 32>; + resets = <&cpg 912>; }; gpio1: gpio@e6051000 { - /* placeholder */ + compatible = "renesas,gpio-r8a77965", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6051000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 29>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc 32>; + resets = <&cpg 911>; }; gpio2: gpio@e6052000 { - /* placeholder */ + compatible = "renesas,gpio-r8a77965", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6052000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 15>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc 32>; + resets = <&cpg 910>; }; gpio3: gpio@e6053000 { - /* placeholder */ + compatible = "renesas,gpio-r8a77965", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6053000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 16>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc 32>; + resets = <&cpg 909>; }; gpio4: gpio@e6054000 { - /* placeholder */ + compatible = "renesas,gpio-r8a77965", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6054000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 18>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc 32>; + resets = <&cpg 908>; }; gpio5: gpio@e6055000 { - /* placeholder */ + compatible = "renesas,gpio-r8a77965", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6055000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc 32>; + resets = <&cpg 907>; }; gpio6: gpio@e6055400 { - /* placeholder */ + compatible = "renesas,gpio-r8a77965", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6055400 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 906>; + power-domains = <&sysc 32>; + resets = <&cpg 906>; }; gpio7: gpio@e6055800 { - /* placeholder */ + compatible = "renesas,gpio-r8a77965", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6055800 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 224 4>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 905>; + power-domains = <&sysc 32>; + resets = <&cpg 905>; }; intc_ex: interrupt-controller@e61c0000 { -- cgit v1.2.3 From 9e1b00a2ef43049617e1d3e99e258e7b2d9f98ea Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Fri, 23 Feb 2018 14:40:53 +0100 Subject: arm64: dts: renesas: r8a77965: Add "reg" properties Add "reg" properties to place-holder nodes with unit address defined for R-Car M3-N SoC. This silences the following DTC compiler warning: Warning (unit_address_vs_reg): Node /soc/... has a unit name, but no reg property Signed-off-by: Jacopo Mondi Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 51 +++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 55f05f79f7f7..4286453ba92d 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -317,6 +317,7 @@ }; intc_ex: interrupt-controller@e61c0000 { + reg = <0 0xe61c0000 0 0x200>; /* placeholder */ }; @@ -520,130 +521,163 @@ }; avb: ethernet@e6800000 { + reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; /* placeholder */ }; csi20: csi2@fea80000 { + reg = <0 0xfea80000 0 0x10000>; /* placeholder */ }; csi40: csi2@feaa0000 { + reg = <0 0xfeaa0000 0 0x10000>; /* placeholder */ }; vin0: video@e6ef0000 { + reg = <0 0xe6ef0000 0 0x1000>; /* placeholder */ }; vin1: video@e6ef1000 { + reg = <0 0xe6ef1000 0 0x1000>; /* placeholder */ }; vin2: video@e6ef2000 { + reg = <0 0xe6ef2000 0 0x1000>; /* placeholder */ }; vin3: video@e6ef3000 { + reg = <0 0xe6ef3000 0 0x1000>; /* placeholder */ }; vin4: video@e6ef4000 { + reg = <0 0xe6ef4000 0 0x1000>; /* placeholder */ }; vin5: video@e6ef5000 { + reg = <0 0xe6ef5000 0 0x1000>; /* placeholder */ }; vin6: video@e6ef6000 { + reg = <0 0xe6ef6000 0 0x1000>; /* placeholder */ }; vin7: video@e6ef7000 { + reg = <0 0xe6ef7000 0 0x1000>; /* placeholder */ }; ohci0: usb@ee080000 { + reg = <0 0xee080000 0 0x100>; /* placeholder */ }; ehci0: usb@ee080100 { + reg = <0 0xee080100 0 0x100>; /* placeholder */ }; usb2_phy0: usb-phy@ee080200 { + reg = <0 0xee080200 0 0x700>; /* placeholder */ }; ohci1: usb@ee0a0000 { + reg = <0 0xee0a0000 0 0x100>; /* placeholder */ }; ehci1: usb@ee0a0100 { + reg = <0 0xee0a0100 0 0x100>; /* placeholder */ }; i2c0: i2c@e6500000 { + reg = <0 0xe6500000 0 0x40>; /* placeholder */ }; i2c1: i2c@e6508000 { + reg = <0 0xe6508000 0 0x40>; /* placeholder */ }; i2c2: i2c@e6510000 { + reg = <0 0xe6510000 0 0x40>; /* placeholder */ }; i2c3: i2c@e66d0000 { + reg = <0 0xe66d0000 0 0x40>; /* placeholder */ }; i2c4: i2c@e66d8000 { + reg = <0 0xe66d8000 0 0x40>; /* placeholder */ }; i2c5: i2c@e66e0000 { + reg = <0 0xe66e0000 0 0x40>; /* placeholder */ }; i2c6: i2c@e66e8000 { + reg = <0 0xe66e8000 0 0x40>; /* placeholder */ }; i2c_dvfs: i2c@e60b0000 { + reg = <0 0xe60b0000 0 0x425>; /* placeholder */ }; pwm0: pwm@e6e30000 { + reg = <0 0xe6e30000 0 8>; /* placeholder */ }; pwm1: pwm@e6e31000 { + reg = <0 0xe6e31000 0 8>; /* placeholder */ }; pwm2: pwm@e6e32000 { + reg = <0 0xe6e32000 0 8>; /* placeholder */ }; pwm3: pwm@e6e33000 { + reg = <0 0xe6e33000 0 8>; /* placeholder */ }; pwm4: pwm@e6e34000 { + reg = <0 0xe6e34000 0 8>; /* placeholder */ }; pwm5: pwm@e6e35000 { + reg = <0 0xe6e35000 0 8>; /* placeholder */ }; pwm6: pwm@e6e36000 { + reg = <0 0xe6e36000 0 8>; /* placeholder */ }; du: display@feb00000 { + reg = <0 0xfeb00000 0 0x80000>, + <0 0xfeb90000 0 0x14>; /* placeholder */ ports { @@ -666,18 +700,26 @@ }; hsusb: usb@e6590000 { + reg = <0 0xe6590000 0 0x100>; /* placeholder */ }; pciec0: pcie@fe000000 { + reg = <0 0xfe000000 0 0x80000>; /* placeholder */ }; pciec1: pcie@ee800000 { + reg = <0 0xee800000 0 0x80000>; /* placeholder */ }; rcar_sound: sound@ec500000 { + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ /* placeholder */ rcar_sound,dvc { @@ -703,38 +745,47 @@ }; usb2_phy1: usb-phy@ee0a0200 { + reg = <0 0xee0a0200 0 0x700>; /* placeholder */ }; sdhi0: sd@ee100000 { + reg = <0 0xee100000 0 0x2000>; /* placeholder */ }; sdhi1: sd@ee120000 { + reg = <0 0xee120000 0 0x2000>; /* placeholder */ }; sdhi2: sd@ee140000 { + reg = <0 0xee140000 0 0x2000>; /* placeholder */ }; sdhi3: sd@ee160000 { + reg = <0 0xee160000 0 0x2000>; /* placeholder */ }; usb3_phy0: usb-phy@e65ee000 { + reg = <0 0xe65ee000 0 0x90>; /* placeholder */ }; usb3_peri0: usb@ee020000 { + reg = <0 0xee020000 0 0x400>; /* placeholder */ }; xhci0: usb@ee000000 { + reg = <0 0xee000000 0 0xc00>; /* placeholder */ }; wdt0: watchdog@e6020000 { + reg = <0 0xe6020000 0 0x0c>; /* placeholder */ }; }; -- cgit v1.2.3 From ba8b5ad0afdda734001176f59d23a4ab31e61e7a Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Fri, 23 Feb 2018 14:40:54 +0100 Subject: arm64: dts: renesas: r8a77965: Add #address-cells and #size-cells Add "#address-cells" and "#size-cells" properties to all place-holder nodes that have children nodes defined by salvator-x[s].dtsi device tree. This silences the following DTC compiler warnings: Warning (reg_format): "reg" property in /soc/.. has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1) Warning (avoid_default_addr_size): Relying on default #address-cells value for /soc/... Warning (avoid_default_addr_size): Relying on default #size-cells value for /soc/... Signed-off-by: Jacopo Mondi Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 4286453ba92d..61efb2d22257 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -521,6 +521,9 @@ }; avb: ethernet@e6800000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; /* placeholder */ }; @@ -528,11 +531,21 @@ csi20: csi2@fea80000 { reg = <0 0xfea80000 0 0x10000>; /* placeholder */ + + ports { + #address-cells = <1>; + #size-cells = <0>; + }; }; csi40: csi2@feaa0000 { reg = <0 0xfeaa0000 0 0x10000>; /* placeholder */ + + ports { + #address-cells = <1>; + #size-cells = <0>; + }; }; vin0: video@e6ef0000 { @@ -611,6 +624,9 @@ }; i2c2: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0xe6510000 0 0x40>; /* placeholder */ }; @@ -621,6 +637,9 @@ }; i2c4: i2c@e66d8000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0xe66d8000 0 0x40>; /* placeholder */ }; @@ -636,6 +655,9 @@ }; i2c_dvfs: i2c@e60b0000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0xe60b0000 0 0x425>; /* placeholder */ }; @@ -681,6 +703,9 @@ /* placeholder */ ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { reg = <0>; du_out_rgb: endpoint { -- cgit v1.2.3 From 217a7d465b120f3227df592a12bbee9bac165613 Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Fri, 23 Feb 2018 14:40:55 +0100 Subject: arm64: dts: renesas: r8a77965: Remove stale reg property Remove "reg" property from cache-controller-0 device node as it does not have any unit address. This silences the following DTC compiler warning: Warning (unit_address_vs_reg): Node /cpus/cache-controller-0 has a reg or ranges property, but no unit name Signed-off-by: Jacopo Mondi Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 61efb2d22257..0536b94a5ec0 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -47,7 +47,6 @@ L2_CA57: cache-controller-0 { compatible = "cache"; - reg = <0>; power-domains = <&sysc 12>; cache-unified; cache-level = <2>; -- cgit v1.2.3 From 8a93a581457af7475aa8e874402d6ec1e4ee665c Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Fri, 23 Feb 2018 14:40:56 +0100 Subject: arm64: dts: renesas: r8a77965: Add #phy-cells property Add "#phy-cells" property to "usb-phy@e65ee000" device node. This silences the following DTC compiler warning: Warning (phys_property): Missing property '#phy-cells' in node /soc/usb-phy@e65ee000 or bad phandle (referred from /soc/usb@ee020000:phys[0]) Signed-off-by: Jacopo Mondi Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 0536b94a5ec0..1a219674201f 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -795,6 +795,7 @@ usb3_phy0: usb-phy@e65ee000 { reg = <0 0xe65ee000 0 0x90>; + #phy-cells = <0>; /* placeholder */ }; -- cgit v1.2.3 From eccdd3f13a6a166d70c7094d09ef365411882a59 Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Fri, 23 Feb 2018 14:40:57 +0100 Subject: arm64: dts: renesas: r8a77965: Add #pwm-cells property Add "#pwm-cells" property to "pwm@e6e31000" device node. This silences the following DTC compiler warning: Warning (pwms_property): Missing property '#pwm-cells' in node /soc/pwm@e6e31000 or bad phandle (referred from /backlight:pwms[0]) Signed-off-by: Jacopo Mondi Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 1a219674201f..5dff176590d5 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -668,6 +668,7 @@ pwm1: pwm@e6e31000 { reg = <0 0xe6e31000 0 8>; + #pwm-cells = <2>; /* placeholder */ }; -- cgit v1.2.3 From f5af77016bcd80bfe850ca41da51d65bd31f8051 Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Fri, 23 Feb 2018 14:40:58 +0100 Subject: arm64: dts: renesas: r8a77965: Add #interrupt-cells property Add "#interrupt-cells" property and "interrupt-controller" label to "interrupt-controller@e61c0000" device node. This silences the following DTC compiler warnings: Warning (interrupts_property): Missing interrupt-controller or interrupt-map property in /soc/interrupt-controller@e61c0000 Warning (interrupts_property): Missing #interrupt-cells in interrupt-parent /soc/interrupt-controller@e61c000 Signed-off-by: Jacopo Mondi Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 5dff176590d5..0118956cc6e0 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -316,6 +316,8 @@ }; intc_ex: interrupt-controller@e61c0000 { + #interrupt-cells = <2>; + interrupt-controller; reg = <0 0xe61c0000 0 0x200>; /* placeholder */ }; -- cgit v1.2.3 From fe6746059b165ab42e8aa0a2c7b7bf307baad660 Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Fri, 23 Feb 2018 14:40:59 +0100 Subject: arm64: dts: renesas: r8a77965: Move usb2_phy1 up Move "usb2_ph1" place-holder device node next to "usb2_phy0" one. Signed-off-by: Jacopo Mondi Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 0118956cc6e0..8c9648a24ee0 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -604,6 +604,11 @@ /* placeholder */ }; + usb2_phy1: usb-phy@ee0a0200 { + reg = <0 0xee0a0200 0 0x700>; + /* placeholder */ + }; + ohci1: usb@ee0a0000 { reg = <0 0xee0a0000 0 0x100>; /* placeholder */ @@ -771,11 +776,6 @@ }; }; - usb2_phy1: usb-phy@ee0a0200 { - reg = <0 0xee0a0200 0 0x700>; - /* placeholder */ - }; - sdhi0: sd@ee100000 { reg = <0 0xee100000 0 0x2000>; /* placeholder */ -- cgit v1.2.3 From 19591a9b416669419110c8da3f4096d219b810ac Mon Sep 17 00:00:00 2001 From: Takeshi Kihara Date: Mon, 19 Feb 2018 19:20:55 +0100 Subject: arm64: dts: renesas: Add support for Salvator-XS with R-Car M3-N Add initial support for the Renesas Salvator-XS (Salvator-X 2nd version) development board equipped with an R-Car M3-N SiP. Most features are enabled through the shared salvator-xs.dtsi board description. The memory configuration is specific to the M3-N SiP. Signed-off-by: Takeshi Kihara [geert: Switch to SPDX-License-Identifier, update patch description] Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/Makefile | 2 +- .../arm64/boot/dts/renesas/r8a77965-salvator-xs.dts | 21 +++++++++++++++++++++ 2 files changed, 22 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 9ea5ec0daeba..5ede06000ea4 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -7,7 +7,7 @@ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-h3ulcb-kf.dtb dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb -dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb +dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb r8a77965-salvator-xs.dtb dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts new file mode 100644 index 000000000000..8a45fc43348d --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the Salvator-X 2nd version board + * + * Copyright (C) 2017 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a77965.dtsi" +#include "salvator-xs.dtsi" + +/ { + model = "Renesas Salvator-X 2nd version board based on r8a77965"; + compatible = "renesas,salvator-xs", "renesas,r8a77965"; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; +}; -- cgit v1.2.3 From 8952792267fb3e14c8498e6ea9284e0da3f91a1f Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 26 Feb 2018 16:42:22 +0100 Subject: arm64: dts: renesas: r8a77965: Add IIC-DVFS device node Populate the device node for the IIC Bus Interface for DVFS (IIC for DVFS) on R-Car M3-N, and add an alias to fix its bus number. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 8c9648a24ee0..c1ecc1b8385f 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -18,6 +18,10 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + i2c7 = &i2c_dvfs; + }; + psci { compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; @@ -663,9 +667,17 @@ i2c_dvfs: i2c@e60b0000 { #address-cells = <1>; #size-cells = <0>; - + compatible = "renesas,iic-r8a77965", + "renesas,rcar-gen3-iic", + "renesas,rmobile-iic"; reg = <0 0xe60b0000 0 0x425>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 926>; + power-domains = <&sysc 32>; + resets = <&cpg 926>; + dmas = <&dmac0 0x11>, <&dmac0 0x10>; + dma-names = "tx", "rx"; + status = "disabled"; }; pwm0: pwm@e6e30000 { -- cgit v1.2.3 From ba03b432f56e29a8ee639d9e9787da283b2ed09c Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 26 Feb 2018 16:42:23 +0100 Subject: arm64: dts: renesas: r8a77965: Add INTC-EX device node Populate the device node for the Interrupt Controller for External Devices (INTC-EX) on R-Car M3-N, which serves external IRQ pins IRQ[0-5]. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index c1ecc1b8385f..b9aa0e7eaabf 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -320,10 +320,19 @@ }; intc_ex: interrupt-controller@e61c0000 { + compatible = "renesas,intc-ex-r8a77965", "renesas,irqc"; #interrupt-cells = <2>; interrupt-controller; reg = <0 0xe61c0000 0 0x200>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc 32>; + resets = <&cpg 407>; }; dmac0: dma-controller@e6700000 { -- cgit v1.2.3 From 3438ff82ddbaa430ccfcc11fe877691a7e326ae0 Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Tue, 27 Feb 2018 11:22:45 +0100 Subject: arm64: dts: renesas: salvator-common: Override EtherAVB phy-mode As the PHY interface installed on the Salvator-X[S] board, provides TX channel delay, make the "phy-mode" property a board-specific one, meant to override the one specified in the SoC DTSI. Follow up patches will reset the r8a7795/96/965 SoC DTSI to use "rgmii" mode and let the board files override that. Signed-off-by: Jacopo Mondi Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/salvator-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index 89cbb3b95acd..2a7f36abd2dd 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -256,6 +256,7 @@ pinctrl-0 = <&avb_pins>; pinctrl-names = "default"; phy-handle = <&phy0>; + phy-mode = "rgmii-txid"; status = "okay"; phy0: ethernet-phy@0 { -- cgit v1.2.3 From b3635b18bba8fc6bd57b7747d97fc46afcf551b8 Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Tue, 27 Feb 2018 11:22:46 +0100 Subject: arm64: dts: renesas: ulcb: Override EtherAVB phy-mode As the PHY interface installed on the ULCB board provides TX channel delay, make the "phy-mode" property a board-specific one, meant to override the one specified in the SoC DTSI. Follow up patches will reset the r8a7795/96 SoC DTSI to use "rgmii" mode\ and let the board files override that. Signed-off-by: Jacopo Mondi Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/ulcb.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi index 3e7a6b94e9f8..6f814845f8b6 100644 --- a/arch/arm64/boot/dts/renesas/ulcb.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi @@ -146,6 +146,7 @@ pinctrl-0 = <&avb_pins>; pinctrl-names = "default"; phy-handle = <&phy0>; + phy-mode = "rgmii-txid"; status = "okay"; phy0: ethernet-phy@0 { -- cgit v1.2.3 From 9c63dcd4df91687a8378d0af1c25429c5ef23a82 Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Tue, 27 Feb 2018 11:22:47 +0100 Subject: arm64: dts: renesas: draak: Override EtherAVB phy-mode As the PHY interface installed on the Draak board, provides TX channel delay, make the "phy-mode" property a board-specific one, meant to override the one specified in the SoC DTSI. Follow up patches will reset the r8a77995 SoC DTSI to use "rgmii" mode and let the board file override that. Signed-off-by: Jacopo Mondi Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts index 34c7f58417ba..d03f19414028 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts +++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts @@ -189,6 +189,7 @@ pinctrl-names = "default"; renesas,no-ether-link; phy-handle = <&phy0>; + phy-mode = "rgmii-txid"; status = "okay"; phy0: ethernet-phy@0 { -- cgit v1.2.3 From e5daa084cc9f6019a905785f0dfd1ffb146a519a Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Tue, 27 Feb 2018 11:22:48 +0100 Subject: arm64: dts: renesas: eagle: Override EtherAVB phy-mode As the PHY interface installed on the Eagle board provides TX and RX channels delays, make the "phy-mode" property a board-specific one, meant to override the one specified in the SoC DTSI. Follow up patches will reset the r8a77970 SoC DTSI to use "rgmii" mode and let the board file override that. Signed-off-by: Jacopo Mondi Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77970-eagle.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts index cb4bd40584cf..fd3448deb714 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts @@ -36,6 +36,7 @@ &avb { renesas,no-ether-link; phy-handle = <&phy0>; + phy-mode = "rgmii-id"; status = "okay"; phy0: ethernet-phy@0 { -- cgit v1.2.3 From 9dcd1f26b9914864e0218712a666b23cf7e589c8 Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Tue, 27 Feb 2018 11:22:49 +0100 Subject: arm64: dts: renesas: v3msk: Override EtherAVB phy-mode As the PHY interface installed on the V3MSK board provides TX and RX channels delays, make the "phy-mode" property a board-specific one, meant to override the one specified in the SoC DTSI. Follow up patches will reset the r8a77970 SoC DTSI to use "rgmii" mode and let the board file override that. Signed-off-by: Jacopo Mondi Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts index 8624ca87d6b2..bb554eec57c8 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts @@ -34,6 +34,7 @@ &avb { renesas,no-ether-link; phy-handle = <&phy0>; + phy-mode = "rgmii-id"; status = "okay"; phy0: ethernet-phy@0 { -- cgit v1.2.3 From f2402dfd57ea00753dd29159a576e1dd93fdedc2 Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Tue, 27 Feb 2018 11:22:50 +0100 Subject: arm64: dts: renesas: r8a7796: Set EtherAVB phy mode to "rgmii" Set the "phy-mode" property of EtherAVB device to "rgmii" and let board files override it if the installed PHY layer provides delays for the RX/TX channels. Signed-off-by: Jacopo Mondi Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 076a9c9346ae..556eb8e45499 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -974,7 +974,7 @@ clocks = <&cpg CPG_MOD 812>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 812>; - phy-mode = "rgmii-txid"; + phy-mode = "rgmii"; iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From fd685e2eba1decc5cfd17e1005144400d53831f8 Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Tue, 27 Feb 2018 11:22:51 +0100 Subject: arm64: dts: renesas: r8a7795: Set EtherAVB phy mode to "rgmii" Set the "phy-mode" property of EtherAVB device to "rgmii" and let board files override it if the installed PHY layer provides delays for the RX/TX channels. Signed-off-by: Jacopo Mondi Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 6d53e1cb7b29..09953cda3a55 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -873,7 +873,7 @@ clocks = <&cpg CPG_MOD 812>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 812>; - phy-mode = "rgmii-txid"; + phy-mode = "rgmii"; iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From e9131e54d1a834b085766d6318a28b03942fa455 Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Tue, 27 Feb 2018 11:22:52 +0100 Subject: arm64: dts: renesas: r8a77995: Set EtherAVB phy mode to "rgmii" Set the "phy-mode" property of EtherAVB device to "rgmii" and let board files override it if the installed PHY layer provides delays for the RX/TX channels. Signed-off-by: Jacopo Mondi Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77995.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index bcf737a20636..82aed7ee984c 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -512,7 +512,7 @@ clocks = <&cpg CPG_MOD 812>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; resets = <&cpg 812>; - phy-mode = "rgmii-txid"; + phy-mode = "rgmii"; iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From 95c969d12ea19062077448a0081dc657232edd1d Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Tue, 27 Feb 2018 11:22:53 +0100 Subject: arm64: dts: renesas: r8a77970: Set EtherAVB phy mode to "rgmii" Set the "phy-mode" property of EtherAVB device to "rgmii" and let board files override it if the installed PHY layer provides delays for the RX/TX channels. Signed-off-by: Jacopo Mondi Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77970.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index 31eeca1531f6..13ff4305416e 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -519,7 +519,7 @@ clocks = <&cpg CPG_MOD 812>; power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; resets = <&cpg 812>; - phy-mode = "rgmii-id"; + phy-mode = "rgmii"; iommus = <&ipmmu_rt 3>; #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From 862a61d0e4705409271639fca8776020b6cff4a8 Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Tue, 27 Feb 2018 11:22:54 +0100 Subject: arm64: dts: renesas: r8a77965: Add EtherAVB device node Populate the ethernet@e6800000 device node to enable Ethernet interface for R-Car M3-N (R8A77965) SoC. Signed-off-by: Jacopo Mondi Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 43 ++++++++++++++++++++++++++++--- 1 file changed, 40 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index b9aa0e7eaabf..f0871fcdd984 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -535,11 +535,48 @@ }; avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a77965", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc 32>; + resets = <&cpg 812>; + phy-mode = "rgmii"; #address-cells = <1>; #size-cells = <0>; - - reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; - /* placeholder */ + status = "disabled"; }; csi20: csi2@fea80000 { -- cgit v1.2.3 From 972952d39fc1e2274c273ec9f1a47bcce30a5722 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 2 Mar 2018 13:02:21 +0100 Subject: arm64: dts: renesas: r8a77965-salvator-xs: Add SoC name to file header Document clearly which SoC this DTS applies to, to distinguish from Salvator-XS boards equipped with other SoCs. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts index 8a45fc43348d..a83a00deed9e 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts +++ b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source for the Salvator-X 2nd version board + * Device Tree Source for the Salvator-X 2nd version board with R-Car M3-N * * Copyright (C) 2017 Renesas Electronics Corp. */ -- cgit v1.2.3 From cbfa278e20913a9b8380278149fa7e4068ea82e2 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sat, 3 Mar 2018 22:06:21 +0300 Subject: arm64: dts: renesas: r8a77970: add I2C support Define the generic R8A77970 parts of the I2C[0-4] device node. Based on the original (and large) patch by Daisuke Matsushita . Signed-off-by: Vladimir Barinov Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77970.dtsi | 93 +++++++++++++++++++++++++++++++ 1 file changed, 93 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index 13ff4305416e..e44281cc1047 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -19,6 +19,14 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + }; + psci { compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; @@ -338,6 +346,91 @@ <&ipmmu_ds1 22>, <&ipmmu_ds1 23>; }; + i2c0: i2c@e6500000 { + compatible = "renesas,i2c-r8a77970", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6500000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 931>; + dmas = <&dmac1 0x91>, <&dmac1 0x90>, + <&dmac2 0x91>, <&dmac2 0x90>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@e6508000 { + compatible = "renesas,i2c-r8a77970", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 930>; + dmas = <&dmac1 0x93>, <&dmac1 0x92>, + <&dmac2 0x93>, <&dmac2 0x92>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@e6510000 { + compatible = "renesas,i2c-r8a77970", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6510000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 929>; + dmas = <&dmac1 0x95>, <&dmac1 0x94>, + <&dmac2 0x95>, <&dmac2 0x94>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@e66d0000 { + compatible = "renesas,i2c-r8a77970", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 928>; + dmas = <&dmac1 0x97>, <&dmac1 0x96>, + <&dmac2 0x97>, <&dmac2 0x96>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@e66d8000 { + compatible = "renesas,i2c-r8a77970", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 927>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 927>; + dmas = <&dmac1 0x99>, <&dmac1 0x98>, + <&dmac2 0x99>, <&dmac2 0x98>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + hscif0: serial@e6540000 { compatible = "renesas,hscif-r8a77970", "renesas,rcar-gen3-hscif", -- cgit v1.2.3 From 7859eb31e4d457496ace72965f2fbb50e836ef12 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sat, 3 Mar 2018 22:07:16 +0300 Subject: arm64: dts: renesas: eagle: add I2C0 support Define the Eagle board dependent part of the I2C0 device node. The I2C0 bus is populated by ON Semiconductor PCA9653 I/O expander and Analog Devices ADV7511W HDMI transmitter (but we're only describing the former chip now). Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77970-eagle.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts index fd3448deb714..3c5f598c9766 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts @@ -55,7 +55,27 @@ clock-frequency = <32768>; }; +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + io_expander: gpio@20 { + compatible = "onnn,pca9654"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + &pfc { + i2c0_pins: i2c0 { + groups = "i2c0"; + function = "i2c0"; + }; + scif0_pins: scif0 { groups = "scif0_data"; function = "scif0"; -- cgit v1.2.3 From c7a99343cc30704c1d173de9bbe06adaa5e96101 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 5 Mar 2018 18:24:55 +0100 Subject: arm64: dts: renesas: r8a77970: sort subnodes of root node alphabetically Sort root sub-nodes alphabetically for allow for easier maintenance of this file. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77970.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index e44281cc1047..c6db8ea43906 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -27,11 +27,6 @@ i2c4 = &i2c4; }; - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - cpus { #address-cells = <1>; #size-cells = <0>; @@ -68,6 +63,11 @@ clock-frequency = <0>; }; + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + /* External SCIF clock - to be overridden by boards that provide it */ scif_clk: scif { compatible = "fixed-clock"; -- cgit v1.2.3 From 9dd660eb1c201304b5d79012695fc6bca57f99a0 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Tue, 6 Mar 2018 10:34:30 +0100 Subject: arm64: dts: renesas: r8a7795: Add IPMMU-PV1 device node Add r8a7795 IPMMU-PV1 and keep it disabled by default. This device is not present in r8a7795 ES1.x and is removed from the DT of those SoCs. This corrects an omission in 3b7e7848f0e8 ("arm64: dts: renesas: r8a7795: Add IPMMU device nodes") This does not have any runtime effect. Reported-by: Yoshihiro Shimoda Signed-off-by: Simon Horman Reviewed-by: Yoshihiro Shimoda --- arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a7795.dtsi | 9 +++++++++ 2 files changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi index f1d5e90503d5..f9acd125d687 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi @@ -23,6 +23,7 @@ /delete-node/ mmu@febe0000; /delete-node/ mmu@fe980000; + /delete-node/ mmu@fd950000; /delete-node/ mmu@fd960000; /delete-node/ mmu@fd970000; diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 09953cda3a55..0648fe451d09 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -545,6 +545,15 @@ status = "disabled"; }; + ipmmu_pv1: mmu@fd950000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xfd950000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 7>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + #iommu-cells = <1>; + status = "disabled"; + }; + ipmmu_pv2: mmu@fd960000 { compatible = "renesas,ipmmu-r8a7795"; reg = <0 0xfd960000 0 0x1000>; -- cgit v1.2.3 From eb21089c32054ecd6957d294a7125bbf100ff328 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 12 Mar 2018 15:24:14 +0100 Subject: arm64: dts: renesas: r8a7795: Add missing SYS-DMAC2 dmas MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On R-Car H3, on-chip peripheral modules that can make use of DMA are wired to either SYS-DMAC0 only, or to both SYS-DMAC1 and SYS-DMAC2. Add the missing DMA properties pointing to SYS-DMAC2 for HSCIF[0-2], SCIF[0125], and I2C[0-2]. These were initially left out because early firmware versions prohibited using SYS-DMAC2. This restriction has been lifted in IPL and Secure Monitor Rev1.0.6 (released on Feb 25, 2016). Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 50 +++++++++++++++++++------------- 1 file changed, 30 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 0648fe451d09..1d5e3ac0231c 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -1076,8 +1076,9 @@ <&cpg CPG_CORE R8A7795_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x31>, <&dmac1 0x30>; - dma-names = "tx", "rx"; + dmas = <&dmac1 0x31>, <&dmac1 0x30>, + <&dmac2 0x31>, <&dmac2 0x30>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 520>; status = "disabled"; @@ -1093,8 +1094,9 @@ <&cpg CPG_CORE R8A7795_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x33>, <&dmac1 0x32>; - dma-names = "tx", "rx"; + dmas = <&dmac1 0x33>, <&dmac1 0x32>, + <&dmac2 0x33>, <&dmac2 0x32>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 519>; status = "disabled"; @@ -1110,8 +1112,9 @@ <&cpg CPG_CORE R8A7795_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x35>, <&dmac1 0x34>; - dma-names = "tx", "rx"; + dmas = <&dmac1 0x35>, <&dmac1 0x34>, + <&dmac2 0x35>, <&dmac2 0x34>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 518>; status = "disabled"; @@ -1222,8 +1225,9 @@ <&cpg CPG_CORE R8A7795_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x51>, <&dmac1 0x50>; - dma-names = "tx", "rx"; + dmas = <&dmac1 0x51>, <&dmac1 0x50>, + <&dmac2 0x51>, <&dmac2 0x50>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 207>; status = "disabled"; @@ -1238,8 +1242,9 @@ <&cpg CPG_CORE R8A7795_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x53>, <&dmac1 0x52>; - dma-names = "tx", "rx"; + dmas = <&dmac1 0x53>, <&dmac1 0x52>, + <&dmac2 0x53>, <&dmac2 0x52>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 206>; status = "disabled"; @@ -1254,8 +1259,9 @@ <&cpg CPG_CORE R8A7795_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x13>, <&dmac1 0x12>; - dma-names = "tx", "rx"; + dmas = <&dmac1 0x13>, <&dmac1 0x12>, + <&dmac2 0x13>, <&dmac2 0x12>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 310>; status = "disabled"; @@ -1302,8 +1308,9 @@ <&cpg CPG_CORE R8A7795_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x5b>, <&dmac1 0x5a>; - dma-names = "tx", "rx"; + dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, + <&dmac2 0x5b>, <&dmac2 0x5a>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 202>; status = "disabled"; @@ -1335,8 +1342,9 @@ clocks = <&cpg CPG_MOD 931>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 931>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>; - dma-names = "tx", "rx"; + dmas = <&dmac1 0x91>, <&dmac1 0x90>, + <&dmac2 0x91>, <&dmac2 0x90>; + dma-names = "tx", "rx", "tx", "rx"; i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; @@ -1351,8 +1359,9 @@ clocks = <&cpg CPG_MOD 930>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 930>; - dmas = <&dmac1 0x93>, <&dmac1 0x92>; - dma-names = "tx", "rx"; + dmas = <&dmac1 0x93>, <&dmac1 0x92>, + <&dmac2 0x93>, <&dmac2 0x92>; + dma-names = "tx", "rx", "tx", "rx"; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -1367,8 +1376,9 @@ clocks = <&cpg CPG_MOD 929>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 929>; - dmas = <&dmac1 0x95>, <&dmac1 0x94>; - dma-names = "tx", "rx"; + dmas = <&dmac1 0x95>, <&dmac1 0x94>, + <&dmac2 0x95>, <&dmac2 0x94>; + dma-names = "tx", "rx", "tx", "rx"; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; -- cgit v1.2.3 From ca565be2b526a731d02a2fbff96fb0572567ea55 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Tue, 13 Mar 2018 22:26:01 +0300 Subject: arm64: dts: renesas: v3msk: add SCIF0 pins Add the (previously omitted) SCIF0 pin data to the V3M Starter Kit board's device tree. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts index bb554eec57c8..a8ceeac77992 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts @@ -51,6 +51,16 @@ clock-frequency = <32768>; }; +&pfc { + scif0_pins: scif0 { + groups = "scif0_data"; + function = "scif0"; + }; +}; + &scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + status = "okay"; }; -- cgit v1.2.3