From a2c6c1c23bed3506fd87e00c88540ac47832c867 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 7 Apr 2025 10:03:21 +0300 Subject: x86/PCI: Drop 'pci' suffix from intel_mid_pci.c CE4100 PCI specific code has no 'pci' suffix in the filename, intel_mid_pci.c is the only one that duplicates the folder name in its filename, drop that redundancy. While at it, group the respective modules in the Makefile. Signed-off-by: Andy Shevchenko Signed-off-by: Bjorn Helgaas Acked-by: Ingo Molnar Link: https://patch.msgid.link/20250407070321.3761063-1-andriy.shevchenko@linux.intel.com --- MAINTAINERS | 2 +- arch/x86/pci/Makefile | 6 +- arch/x86/pci/intel_mid.c | 406 +++++++++++++++++++++++++++++++++++++++++++ arch/x86/pci/intel_mid_pci.c | 406 ------------------------------------------- 4 files changed, 410 insertions(+), 410 deletions(-) create mode 100644 arch/x86/pci/intel_mid.c delete mode 100644 arch/x86/pci/intel_mid_pci.c diff --git a/MAINTAINERS b/MAINTAINERS index 96b827049501..1f6514d55b17 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12120,7 +12120,7 @@ M: Andy Shevchenko L: linux-kernel@vger.kernel.org S: Supported F: arch/x86/include/asm/intel-mid.h -F: arch/x86/pci/intel_mid_pci.c +F: arch/x86/pci/intel_mid.c F: arch/x86/platform/intel-mid/ F: drivers/dma/hsu/ F: drivers/extcon/extcon-intel-mrfld.c diff --git a/arch/x86/pci/Makefile b/arch/x86/pci/Makefile index 4933fb337983..c1efd5b0d198 100644 --- a/arch/x86/pci/Makefile +++ b/arch/x86/pci/Makefile @@ -8,13 +8,13 @@ obj-$(CONFIG_PCI_OLPC) += olpc.o obj-$(CONFIG_PCI_XEN) += xen.o obj-y += fixup.o -obj-$(CONFIG_X86_INTEL_CE) += ce4100.o obj-$(CONFIG_ACPI) += acpi.o obj-y += legacy.o irq.o -obj-$(CONFIG_X86_NUMACHIP) += numachip.o +obj-$(CONFIG_X86_INTEL_CE) += ce4100.o +obj-$(CONFIG_X86_INTEL_MID) += intel_mid.o -obj-$(CONFIG_X86_INTEL_MID) += intel_mid_pci.o +obj-$(CONFIG_X86_NUMACHIP) += numachip.o obj-y += common.o early.o obj-y += bus_numa.o diff --git a/arch/x86/pci/intel_mid.c b/arch/x86/pci/intel_mid.c new file mode 100644 index 000000000000..b433b1753016 --- /dev/null +++ b/arch/x86/pci/intel_mid.c @@ -0,0 +1,406 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Intel MID PCI support + * Copyright (c) 2008 Intel Corporation + * Jesse Barnes + * + * Moorestown has an interesting PCI implementation: + * - configuration space is memory mapped (as defined by MCFG) + * - Lincroft devices also have a real, type 1 configuration space + * - Early Lincroft silicon has a type 1 access bug that will cause + * a hang if non-existent devices are accessed + * - some devices have the "fixed BAR" capability, which means + * they can't be relocated or modified; check for that during + * BAR sizing + * + * So, we use the MCFG space for all reads and writes, but also send + * Lincroft writes to type 1 space. But only read/write if the device + * actually exists, otherwise return all 1s for reads and bit bucket + * the writes. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#define PCIE_CAP_OFFSET 0x100 + +/* Quirks for the listed devices */ +#define PCI_DEVICE_ID_INTEL_MRFLD_MMC 0x1190 +#define PCI_DEVICE_ID_INTEL_MRFLD_HSU 0x1191 + +/* Fixed BAR fields */ +#define PCIE_VNDR_CAP_ID_FIXED_BAR 0x00 /* Fixed BAR (TBD) */ +#define PCI_FIXED_BAR_0_SIZE 0x04 +#define PCI_FIXED_BAR_1_SIZE 0x08 +#define PCI_FIXED_BAR_2_SIZE 0x0c +#define PCI_FIXED_BAR_3_SIZE 0x10 +#define PCI_FIXED_BAR_4_SIZE 0x14 +#define PCI_FIXED_BAR_5_SIZE 0x1c + +static int pci_soc_mode; + +/** + * fixed_bar_cap - return the offset of the fixed BAR cap if found + * @bus: PCI bus + * @devfn: device in question + * + * Look for the fixed BAR cap on @bus and @devfn, returning its offset + * if found or 0 otherwise. + */ +static int fixed_bar_cap(struct pci_bus *bus, unsigned int devfn) +{ + int pos; + u32 pcie_cap = 0, cap_data; + + pos = PCIE_CAP_OFFSET; + + if (!raw_pci_ext_ops) + return 0; + + while (pos) { + if (raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number, + devfn, pos, 4, &pcie_cap)) + return 0; + + if (PCI_EXT_CAP_ID(pcie_cap) == 0x0000 || + PCI_EXT_CAP_ID(pcie_cap) == 0xffff) + break; + + if (PCI_EXT_CAP_ID(pcie_cap) == PCI_EXT_CAP_ID_VNDR) { + raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number, + devfn, pos + 4, 4, &cap_data); + if ((cap_data & 0xffff) == PCIE_VNDR_CAP_ID_FIXED_BAR) + return pos; + } + + pos = PCI_EXT_CAP_NEXT(pcie_cap); + } + + return 0; +} + +static int pci_device_update_fixed(struct pci_bus *bus, unsigned int devfn, + int reg, int len, u32 val, int offset) +{ + u32 size; + unsigned int domain, busnum; + int bar = (reg - PCI_BASE_ADDRESS_0) >> 2; + + domain = pci_domain_nr(bus); + busnum = bus->number; + + if (val == ~0 && len == 4) { + unsigned long decode; + + raw_pci_ext_ops->read(domain, busnum, devfn, + offset + 8 + (bar * 4), 4, &size); + + /* Turn the size into a decode pattern for the sizing code */ + if (size) { + decode = size - 1; + decode |= decode >> 1; + decode |= decode >> 2; + decode |= decode >> 4; + decode |= decode >> 8; + decode |= decode >> 16; + decode++; + decode = ~(decode - 1); + } else { + decode = 0; + } + + /* + * If val is all ones, the core code is trying to size the reg, + * so update the mmconfig space with the real size. + * + * Note: this assumes the fixed size we got is a power of two. + */ + return raw_pci_ext_ops->write(domain, busnum, devfn, reg, 4, + decode); + } + + /* This is some other kind of BAR write, so just do it. */ + return raw_pci_ext_ops->write(domain, busnum, devfn, reg, len, val); +} + +/** + * type1_access_ok - check whether to use type 1 + * @bus: bus number + * @devfn: device & function in question + * @reg: configuration register offset + * + * If the bus is on a Lincroft chip and it exists, or is not on a Lincroft at + * all, the we can go ahead with any reads & writes. If it's on a Lincroft, + * but doesn't exist, avoid the access altogether to keep the chip from + * hanging. + */ +static bool type1_access_ok(unsigned int bus, unsigned int devfn, int reg) +{ + /* + * This is a workaround for A0 LNC bug where PCI status register does + * not have new CAP bit set. can not be written by SW either. + * + * PCI header type in real LNC indicates a single function device, this + * will prevent probing other devices under the same function in PCI + * shim. Therefore, use the header type in shim instead. + */ + if (reg >= 0x100 || reg == PCI_STATUS || reg == PCI_HEADER_TYPE) + return false; + if (bus == 0 && (devfn == PCI_DEVFN(2, 0) + || devfn == PCI_DEVFN(0, 0) + || devfn == PCI_DEVFN(3, 0))) + return true; + return false; /* Langwell on others */ +} + +static int pci_read(struct pci_bus *bus, unsigned int devfn, int where, + int size, u32 *value) +{ + if (type1_access_ok(bus->number, devfn, where)) + return pci_direct_conf1.read(pci_domain_nr(bus), bus->number, + devfn, where, size, value); + return raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number, + devfn, where, size, value); +} + +static int pci_write(struct pci_bus *bus, unsigned int devfn, int where, + int size, u32 value) +{ + int offset; + + /* + * On MRST, there is no PCI ROM BAR, this will cause a subsequent read + * to ROM BAR return 0 then being ignored. + */ + if (where == PCI_ROM_ADDRESS) + return 0; + + /* + * Devices with fixed BARs need special handling: + * - BAR sizing code will save, write ~0, read size, restore + * - so writes to fixed BARs need special handling + * - other writes to fixed BAR devices should go through mmconfig + */ + offset = fixed_bar_cap(bus, devfn); + if (offset && + (where >= PCI_BASE_ADDRESS_0 && where <= PCI_BASE_ADDRESS_5)) { + return pci_device_update_fixed(bus, devfn, where, size, value, + offset); + } + + /* + * On Moorestown update both real & mmconfig space + * Note: early Lincroft silicon can't handle type 1 accesses to + * non-existent devices, so just eat the write in that case. + */ + if (type1_access_ok(bus->number, devfn, where)) + return pci_direct_conf1.write(pci_domain_nr(bus), bus->number, + devfn, where, size, value); + return raw_pci_ext_ops->write(pci_domain_nr(bus), bus->number, devfn, + where, size, value); +} + +static const struct x86_cpu_id intel_mid_cpu_ids[] = { + X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID, NULL), + {} +}; + +static int intel_mid_pci_irq_enable(struct pci_dev *dev) +{ + const struct x86_cpu_id *id; + struct irq_alloc_info info; + bool polarity_low; + u16 model = 0; + int ret; + u8 gsi; + + if (dev->irq_managed && dev->irq > 0) + return 0; + + ret = pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &gsi); + if (ret) { + dev_warn(&dev->dev, "Failed to read interrupt line: %d\n", ret); + return pcibios_err_to_errno(ret); + } + + id = x86_match_cpu(intel_mid_cpu_ids); + if (id) + model = id->model; + + switch (model) { + case VFM_MODEL(INTEL_ATOM_SILVERMONT_MID): + polarity_low = false; + + /* Special treatment for IRQ0 */ + if (gsi == 0) { + /* + * Skip HS UART common registers device since it has + * IRQ0 assigned and not used by the kernel. + */ + if (dev->device == PCI_DEVICE_ID_INTEL_MRFLD_HSU) + return -EBUSY; + /* + * TNG has IRQ0 assigned to eMMC controller. But there + * are also other devices with bogus PCI configuration + * that have IRQ0 assigned. This check ensures that + * eMMC gets it. The rest of devices still could be + * enabled without interrupt line being allocated. + */ + if (dev->device != PCI_DEVICE_ID_INTEL_MRFLD_MMC) + return 0; + } + break; + default: + polarity_low = true; + break; + } + + ioapic_set_alloc_attr(&info, dev_to_node(&dev->dev), 1, polarity_low); + + /* + * MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to + * IOAPIC RTE entries, so we just enable RTE for the device. + */ + ret = mp_map_gsi_to_irq(gsi, IOAPIC_MAP_ALLOC, &info); + if (ret < 0) + return ret; + + dev->irq = ret; + dev->irq_managed = 1; + + return 0; +} + +static void intel_mid_pci_irq_disable(struct pci_dev *dev) +{ + if (!mp_should_keep_irq(&dev->dev) && dev->irq_managed && + dev->irq > 0) { + mp_unmap_irq(dev->irq); + dev->irq_managed = 0; + } +} + +static const struct pci_ops intel_mid_pci_ops __initconst = { + .read = pci_read, + .write = pci_write, +}; + +/** + * intel_mid_pci_init - installs intel_mid_pci_ops + * + * Moorestown has an interesting PCI implementation (see above). + * Called when the early platform detection installs it. + */ +int __init intel_mid_pci_init(void) +{ + pr_info("Intel MID platform detected, using MID PCI ops\n"); + pci_mmcfg_late_init(); + pcibios_enable_irq = intel_mid_pci_irq_enable; + pcibios_disable_irq = intel_mid_pci_irq_disable; + pci_root_ops = intel_mid_pci_ops; + pci_soc_mode = 1; + /* Continue with standard init */ + acpi_noirq_set(); + return 1; +} + +/* + * Langwell devices are not true PCI devices; they are not subject to 10 ms + * d3 to d0 delay required by PCI spec. + */ +static void pci_d3delay_fixup(struct pci_dev *dev) +{ + /* + * PCI fixups are effectively decided compile time. If we have a dual + * SoC/non-SoC kernel we don't want to mangle d3 on non-SoC devices. + */ + if (!pci_soc_mode) + return; + /* + * True PCI devices in Lincroft should allow type 1 access, the rest + * are Langwell fake PCI devices. + */ + if (type1_access_ok(dev->bus->number, dev->devfn, PCI_DEVICE_ID)) + return; + dev->d3hot_delay = 0; +} +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_d3delay_fixup); + +static void mid_power_off_one_device(struct pci_dev *dev) +{ + u16 pmcsr; + + /* + * Update current state first, otherwise PCI core enforces PCI_D0 in + * pci_set_power_state() for devices which status was PCI_UNKNOWN. + */ + pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); + dev->current_state = (pci_power_t __force)(pmcsr & PCI_PM_CTRL_STATE_MASK); + + pci_set_power_state(dev, PCI_D3hot); +} + +static void mid_power_off_devices(struct pci_dev *dev) +{ + int id; + + if (!pci_soc_mode) + return; + + id = intel_mid_pwr_get_lss_id(dev); + if (id < 0) + return; + + /* + * This sets only PMCSR bits. The actual power off will happen in + * arch/x86/platform/intel-mid/pwr.c. + */ + mid_power_off_one_device(dev); +} + +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, mid_power_off_devices); + +/* + * Langwell devices reside at fixed offsets, don't try to move them. + */ +static void pci_fixed_bar_fixup(struct pci_dev *dev) +{ + unsigned long offset; + u32 size; + int i; + + if (!pci_soc_mode) + return; + + /* Must have extended configuration space */ + if (dev->cfg_size < PCIE_CAP_OFFSET + 4) + return; + + /* Fixup the BAR sizes for fixed BAR devices and make them unmoveable */ + offset = fixed_bar_cap(dev->bus, dev->devfn); + if (!offset || PCI_DEVFN(2, 0) == dev->devfn || + PCI_DEVFN(2, 2) == dev->devfn) + return; + + for (i = 0; i < PCI_STD_NUM_BARS; i++) { + pci_read_config_dword(dev, offset + 8 + (i * 4), &size); + dev->resource[i].end = dev->resource[i].start + size - 1; + dev->resource[i].flags |= IORESOURCE_PCI_FIXED; + } +} +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_fixed_bar_fixup); diff --git a/arch/x86/pci/intel_mid_pci.c b/arch/x86/pci/intel_mid_pci.c deleted file mode 100644 index b433b1753016..000000000000 --- a/arch/x86/pci/intel_mid_pci.c +++ /dev/null @@ -1,406 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Intel MID PCI support - * Copyright (c) 2008 Intel Corporation - * Jesse Barnes - * - * Moorestown has an interesting PCI implementation: - * - configuration space is memory mapped (as defined by MCFG) - * - Lincroft devices also have a real, type 1 configuration space - * - Early Lincroft silicon has a type 1 access bug that will cause - * a hang if non-existent devices are accessed - * - some devices have the "fixed BAR" capability, which means - * they can't be relocated or modified; check for that during - * BAR sizing - * - * So, we use the MCFG space for all reads and writes, but also send - * Lincroft writes to type 1 space. But only read/write if the device - * actually exists, otherwise return all 1s for reads and bit bucket - * the writes. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#define PCIE_CAP_OFFSET 0x100 - -/* Quirks for the listed devices */ -#define PCI_DEVICE_ID_INTEL_MRFLD_MMC 0x1190 -#define PCI_DEVICE_ID_INTEL_MRFLD_HSU 0x1191 - -/* Fixed BAR fields */ -#define PCIE_VNDR_CAP_ID_FIXED_BAR 0x00 /* Fixed BAR (TBD) */ -#define PCI_FIXED_BAR_0_SIZE 0x04 -#define PCI_FIXED_BAR_1_SIZE 0x08 -#define PCI_FIXED_BAR_2_SIZE 0x0c -#define PCI_FIXED_BAR_3_SIZE 0x10 -#define PCI_FIXED_BAR_4_SIZE 0x14 -#define PCI_FIXED_BAR_5_SIZE 0x1c - -static int pci_soc_mode; - -/** - * fixed_bar_cap - return the offset of the fixed BAR cap if found - * @bus: PCI bus - * @devfn: device in question - * - * Look for the fixed BAR cap on @bus and @devfn, returning its offset - * if found or 0 otherwise. - */ -static int fixed_bar_cap(struct pci_bus *bus, unsigned int devfn) -{ - int pos; - u32 pcie_cap = 0, cap_data; - - pos = PCIE_CAP_OFFSET; - - if (!raw_pci_ext_ops) - return 0; - - while (pos) { - if (raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number, - devfn, pos, 4, &pcie_cap)) - return 0; - - if (PCI_EXT_CAP_ID(pcie_cap) == 0x0000 || - PCI_EXT_CAP_ID(pcie_cap) == 0xffff) - break; - - if (PCI_EXT_CAP_ID(pcie_cap) == PCI_EXT_CAP_ID_VNDR) { - raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number, - devfn, pos + 4, 4, &cap_data); - if ((cap_data & 0xffff) == PCIE_VNDR_CAP_ID_FIXED_BAR) - return pos; - } - - pos = PCI_EXT_CAP_NEXT(pcie_cap); - } - - return 0; -} - -static int pci_device_update_fixed(struct pci_bus *bus, unsigned int devfn, - int reg, int len, u32 val, int offset) -{ - u32 size; - unsigned int domain, busnum; - int bar = (reg - PCI_BASE_ADDRESS_0) >> 2; - - domain = pci_domain_nr(bus); - busnum = bus->number; - - if (val == ~0 && len == 4) { - unsigned long decode; - - raw_pci_ext_ops->read(domain, busnum, devfn, - offset + 8 + (bar * 4), 4, &size); - - /* Turn the size into a decode pattern for the sizing code */ - if (size) { - decode = size - 1; - decode |= decode >> 1; - decode |= decode >> 2; - decode |= decode >> 4; - decode |= decode >> 8; - decode |= decode >> 16; - decode++; - decode = ~(decode - 1); - } else { - decode = 0; - } - - /* - * If val is all ones, the core code is trying to size the reg, - * so update the mmconfig space with the real size. - * - * Note: this assumes the fixed size we got is a power of two. - */ - return raw_pci_ext_ops->write(domain, busnum, devfn, reg, 4, - decode); - } - - /* This is some other kind of BAR write, so just do it. */ - return raw_pci_ext_ops->write(domain, busnum, devfn, reg, len, val); -} - -/** - * type1_access_ok - check whether to use type 1 - * @bus: bus number - * @devfn: device & function in question - * @reg: configuration register offset - * - * If the bus is on a Lincroft chip and it exists, or is not on a Lincroft at - * all, the we can go ahead with any reads & writes. If it's on a Lincroft, - * but doesn't exist, avoid the access altogether to keep the chip from - * hanging. - */ -static bool type1_access_ok(unsigned int bus, unsigned int devfn, int reg) -{ - /* - * This is a workaround for A0 LNC bug where PCI status register does - * not have new CAP bit set. can not be written by SW either. - * - * PCI header type in real LNC indicates a single function device, this - * will prevent probing other devices under the same function in PCI - * shim. Therefore, use the header type in shim instead. - */ - if (reg >= 0x100 || reg == PCI_STATUS || reg == PCI_HEADER_TYPE) - return false; - if (bus == 0 && (devfn == PCI_DEVFN(2, 0) - || devfn == PCI_DEVFN(0, 0) - || devfn == PCI_DEVFN(3, 0))) - return true; - return false; /* Langwell on others */ -} - -static int pci_read(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 *value) -{ - if (type1_access_ok(bus->number, devfn, where)) - return pci_direct_conf1.read(pci_domain_nr(bus), bus->number, - devfn, where, size, value); - return raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number, - devfn, where, size, value); -} - -static int pci_write(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 value) -{ - int offset; - - /* - * On MRST, there is no PCI ROM BAR, this will cause a subsequent read - * to ROM BAR return 0 then being ignored. - */ - if (where == PCI_ROM_ADDRESS) - return 0; - - /* - * Devices with fixed BARs need special handling: - * - BAR sizing code will save, write ~0, read size, restore - * - so writes to fixed BARs need special handling - * - other writes to fixed BAR devices should go through mmconfig - */ - offset = fixed_bar_cap(bus, devfn); - if (offset && - (where >= PCI_BASE_ADDRESS_0 && where <= PCI_BASE_ADDRESS_5)) { - return pci_device_update_fixed(bus, devfn, where, size, value, - offset); - } - - /* - * On Moorestown update both real & mmconfig space - * Note: early Lincroft silicon can't handle type 1 accesses to - * non-existent devices, so just eat the write in that case. - */ - if (type1_access_ok(bus->number, devfn, where)) - return pci_direct_conf1.write(pci_domain_nr(bus), bus->number, - devfn, where, size, value); - return raw_pci_ext_ops->write(pci_domain_nr(bus), bus->number, devfn, - where, size, value); -} - -static const struct x86_cpu_id intel_mid_cpu_ids[] = { - X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID, NULL), - {} -}; - -static int intel_mid_pci_irq_enable(struct pci_dev *dev) -{ - const struct x86_cpu_id *id; - struct irq_alloc_info info; - bool polarity_low; - u16 model = 0; - int ret; - u8 gsi; - - if (dev->irq_managed && dev->irq > 0) - return 0; - - ret = pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &gsi); - if (ret) { - dev_warn(&dev->dev, "Failed to read interrupt line: %d\n", ret); - return pcibios_err_to_errno(ret); - } - - id = x86_match_cpu(intel_mid_cpu_ids); - if (id) - model = id->model; - - switch (model) { - case VFM_MODEL(INTEL_ATOM_SILVERMONT_MID): - polarity_low = false; - - /* Special treatment for IRQ0 */ - if (gsi == 0) { - /* - * Skip HS UART common registers device since it has - * IRQ0 assigned and not used by the kernel. - */ - if (dev->device == PCI_DEVICE_ID_INTEL_MRFLD_HSU) - return -EBUSY; - /* - * TNG has IRQ0 assigned to eMMC controller. But there - * are also other devices with bogus PCI configuration - * that have IRQ0 assigned. This check ensures that - * eMMC gets it. The rest of devices still could be - * enabled without interrupt line being allocated. - */ - if (dev->device != PCI_DEVICE_ID_INTEL_MRFLD_MMC) - return 0; - } - break; - default: - polarity_low = true; - break; - } - - ioapic_set_alloc_attr(&info, dev_to_node(&dev->dev), 1, polarity_low); - - /* - * MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to - * IOAPIC RTE entries, so we just enable RTE for the device. - */ - ret = mp_map_gsi_to_irq(gsi, IOAPIC_MAP_ALLOC, &info); - if (ret < 0) - return ret; - - dev->irq = ret; - dev->irq_managed = 1; - - return 0; -} - -static void intel_mid_pci_irq_disable(struct pci_dev *dev) -{ - if (!mp_should_keep_irq(&dev->dev) && dev->irq_managed && - dev->irq > 0) { - mp_unmap_irq(dev->irq); - dev->irq_managed = 0; - } -} - -static const struct pci_ops intel_mid_pci_ops __initconst = { - .read = pci_read, - .write = pci_write, -}; - -/** - * intel_mid_pci_init - installs intel_mid_pci_ops - * - * Moorestown has an interesting PCI implementation (see above). - * Called when the early platform detection installs it. - */ -int __init intel_mid_pci_init(void) -{ - pr_info("Intel MID platform detected, using MID PCI ops\n"); - pci_mmcfg_late_init(); - pcibios_enable_irq = intel_mid_pci_irq_enable; - pcibios_disable_irq = intel_mid_pci_irq_disable; - pci_root_ops = intel_mid_pci_ops; - pci_soc_mode = 1; - /* Continue with standard init */ - acpi_noirq_set(); - return 1; -} - -/* - * Langwell devices are not true PCI devices; they are not subject to 10 ms - * d3 to d0 delay required by PCI spec. - */ -static void pci_d3delay_fixup(struct pci_dev *dev) -{ - /* - * PCI fixups are effectively decided compile time. If we have a dual - * SoC/non-SoC kernel we don't want to mangle d3 on non-SoC devices. - */ - if (!pci_soc_mode) - return; - /* - * True PCI devices in Lincroft should allow type 1 access, the rest - * are Langwell fake PCI devices. - */ - if (type1_access_ok(dev->bus->number, dev->devfn, PCI_DEVICE_ID)) - return; - dev->d3hot_delay = 0; -} -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_d3delay_fixup); - -static void mid_power_off_one_device(struct pci_dev *dev) -{ - u16 pmcsr; - - /* - * Update current state first, otherwise PCI core enforces PCI_D0 in - * pci_set_power_state() for devices which status was PCI_UNKNOWN. - */ - pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); - dev->current_state = (pci_power_t __force)(pmcsr & PCI_PM_CTRL_STATE_MASK); - - pci_set_power_state(dev, PCI_D3hot); -} - -static void mid_power_off_devices(struct pci_dev *dev) -{ - int id; - - if (!pci_soc_mode) - return; - - id = intel_mid_pwr_get_lss_id(dev); - if (id < 0) - return; - - /* - * This sets only PMCSR bits. The actual power off will happen in - * arch/x86/platform/intel-mid/pwr.c. - */ - mid_power_off_one_device(dev); -} - -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, mid_power_off_devices); - -/* - * Langwell devices reside at fixed offsets, don't try to move them. - */ -static void pci_fixed_bar_fixup(struct pci_dev *dev) -{ - unsigned long offset; - u32 size; - int i; - - if (!pci_soc_mode) - return; - - /* Must have extended configuration space */ - if (dev->cfg_size < PCIE_CAP_OFFSET + 4) - return; - - /* Fixup the BAR sizes for fixed BAR devices and make them unmoveable */ - offset = fixed_bar_cap(dev->bus, dev->devfn); - if (!offset || PCI_DEVFN(2, 0) == dev->devfn || - PCI_DEVFN(2, 2) == dev->devfn) - return; - - for (i = 0; i < PCI_STD_NUM_BARS; i++) { - pci_read_config_dword(dev, offset + 8 + (i * 4), &size); - dev->resource[i].end = dev->resource[i].start + size - 1; - dev->resource[i].flags |= IORESOURCE_PCI_FIXED; - } -} -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_fixed_bar_fixup); -- cgit v1.2.3 From 8fe743b5eba0abfbee39fe27b12acfb0df9b8a2d Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 23 Apr 2025 22:16:32 +0200 Subject: PCI: Add CONFIG_MMU dependency It turns out that there are no platforms that have PCI but don't have an MMU, so adding a Kconfig dependency on CONFIG_PCI simplifies build testing kernels for those platforms a lot, and avoids a lot of inadvertent build regressions. Add a dependency for CONFIG_PCI and remove all the ones for PCI specific device drivers that are currently marked not having it. There are a few platforms that have an optional MMU, but they usually cannot have PCI at all. The one exception is Coldfire MCF54xx, but this is mainly for historic reasons, and anyone using those chips should really use the MMU these days. Link: https://lore.kernel.org/lkml/a41f1b20-a76c-43d8-8c36-f12744327a54@app.fastmail.com/ Signed-off-by: Arnd Bergmann Signed-off-by: Bjorn Helgaas Reviewed-by: Martin K. Petersen # SCSI Reviewed-by: Thomas Zimmermann Acked-by: Alex Deucher Link: https://patch.msgid.link/20250423202215.3315550-1-arnd@kernel.org --- drivers/accel/qaic/Kconfig | 1 - drivers/firewire/Kconfig | 2 +- drivers/gpu/drm/Kconfig | 2 +- drivers/gpu/drm/amd/amdgpu/Kconfig | 3 +-- drivers/gpu/drm/ast/Kconfig | 2 +- drivers/gpu/drm/gma500/Kconfig | 2 +- drivers/gpu/drm/hisilicon/hibmc/Kconfig | 1 - drivers/gpu/drm/loongson/Kconfig | 2 +- drivers/gpu/drm/mgag200/Kconfig | 2 +- drivers/gpu/drm/nouveau/Kconfig | 3 +-- drivers/gpu/drm/qxl/Kconfig | 2 +- drivers/gpu/drm/radeon/Kconfig | 2 +- drivers/gpu/drm/tiny/Kconfig | 2 +- drivers/gpu/drm/vmwgfx/Kconfig | 2 +- drivers/gpu/drm/xe/Kconfig | 2 +- drivers/net/ethernet/broadcom/Kconfig | 1 - drivers/pci/Kconfig | 1 + drivers/pci/pci.c | 4 ++-- drivers/scsi/bnx2fc/Kconfig | 1 - drivers/scsi/bnx2i/Kconfig | 1 - drivers/vfio/pci/Kconfig | 2 +- 21 files changed, 17 insertions(+), 23 deletions(-) diff --git a/drivers/accel/qaic/Kconfig b/drivers/accel/qaic/Kconfig index a9f866230058..5e405a19c157 100644 --- a/drivers/accel/qaic/Kconfig +++ b/drivers/accel/qaic/Kconfig @@ -8,7 +8,6 @@ config DRM_ACCEL_QAIC depends on DRM_ACCEL depends on PCI && HAS_IOMEM depends on MHI_BUS - depends on MMU select CRC32 help Enables driver for Qualcomm's Cloud AI accelerator PCIe cards that are diff --git a/drivers/firewire/Kconfig b/drivers/firewire/Kconfig index 905c82e26ce7..a5f5e250223a 100644 --- a/drivers/firewire/Kconfig +++ b/drivers/firewire/Kconfig @@ -83,7 +83,7 @@ config FIREWIRE_KUNIT_SELF_ID_SEQUENCE_HELPER_TEST config FIREWIRE_OHCI tristate "OHCI-1394 controllers" - depends on PCI && FIREWIRE && MMU + depends on PCI && FIREWIRE help Enable this driver if you have a FireWire controller based on the OHCI specification. For all practical purposes, this diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index 2cba2b6ebe1c..6e95d204597e 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -462,7 +462,7 @@ source "drivers/gpu/drm/imagination/Kconfig" config DRM_HYPERV tristate "DRM Support for Hyper-V synthetic video device" - depends on DRM && PCI && MMU && HYPERV + depends on DRM && PCI && HYPERV select DRM_CLIENT_SELECTION select DRM_KMS_HELPER select DRM_GEM_SHMEM_HELPER diff --git a/drivers/gpu/drm/amd/amdgpu/Kconfig b/drivers/gpu/drm/amd/amdgpu/Kconfig index 1a11cab741ac..058e3b3ad520 100644 --- a/drivers/gpu/drm/amd/amdgpu/Kconfig +++ b/drivers/gpu/drm/amd/amdgpu/Kconfig @@ -2,7 +2,7 @@ config DRM_AMDGPU tristate "AMD GPU" - depends on DRM && PCI && MMU + depends on DRM && PCI depends on !UML select FW_LOADER select DRM_CLIENT @@ -68,7 +68,6 @@ config DRM_AMDGPU_CIK config DRM_AMDGPU_USERPTR bool "Always enable userptr write support" depends on DRM_AMDGPU - depends on MMU select HMM_MIRROR select MMU_NOTIFIER help diff --git a/drivers/gpu/drm/ast/Kconfig b/drivers/gpu/drm/ast/Kconfig index da0663542e8a..242fbccdf844 100644 --- a/drivers/gpu/drm/ast/Kconfig +++ b/drivers/gpu/drm/ast/Kconfig @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only config DRM_AST tristate "AST server chips" - depends on DRM && PCI && MMU + depends on DRM && PCI select DRM_CLIENT_SELECTION select DRM_GEM_SHMEM_HELPER select DRM_KMS_HELPER diff --git a/drivers/gpu/drm/gma500/Kconfig b/drivers/gpu/drm/gma500/Kconfig index aa2ea128aa2f..a2acaa699dd5 100644 --- a/drivers/gpu/drm/gma500/Kconfig +++ b/drivers/gpu/drm/gma500/Kconfig @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only config DRM_GMA500 tristate "Intel GMA500/600/3600/3650 KMS Framebuffer" - depends on DRM && PCI && X86 && MMU && HAS_IOPORT + depends on DRM && PCI && X86 && HAS_IOPORT select DRM_CLIENT_SELECTION select DRM_KMS_HELPER select FB_IOMEM_HELPERS if DRM_FBDEV_EMULATION diff --git a/drivers/gpu/drm/hisilicon/hibmc/Kconfig b/drivers/gpu/drm/hisilicon/hibmc/Kconfig index 98d77d74999d..d1f3f5793f34 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/Kconfig +++ b/drivers/gpu/drm/hisilicon/hibmc/Kconfig @@ -2,7 +2,6 @@ config DRM_HISI_HIBMC tristate "DRM Support for Hisilicon Hibmc" depends on DRM && PCI - depends on MMU select DRM_CLIENT_SELECTION select DRM_DISPLAY_HELPER select DRM_DISPLAY_DP_HELPER diff --git a/drivers/gpu/drm/loongson/Kconfig b/drivers/gpu/drm/loongson/Kconfig index 552edfec7afb..d739d51cf54c 100644 --- a/drivers/gpu/drm/loongson/Kconfig +++ b/drivers/gpu/drm/loongson/Kconfig @@ -2,7 +2,7 @@ config DRM_LOONGSON tristate "DRM support for Loongson Graphics" - depends on DRM && PCI && MMU + depends on DRM && PCI depends on LOONGARCH || MIPS || COMPILE_TEST select DRM_CLIENT_SELECTION select DRM_KMS_HELPER diff --git a/drivers/gpu/drm/mgag200/Kconfig b/drivers/gpu/drm/mgag200/Kconfig index 412dcbea0e2d..a962ae564a75 100644 --- a/drivers/gpu/drm/mgag200/Kconfig +++ b/drivers/gpu/drm/mgag200/Kconfig @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only config DRM_MGAG200 tristate "Matrox G200" - depends on DRM && PCI && MMU + depends on DRM && PCI select DRM_CLIENT_SELECTION select DRM_GEM_SHMEM_HELPER select DRM_KMS_HELPER diff --git a/drivers/gpu/drm/nouveau/Kconfig b/drivers/gpu/drm/nouveau/Kconfig index 7b3e979c51ec..d1587639ebb0 100644 --- a/drivers/gpu/drm/nouveau/Kconfig +++ b/drivers/gpu/drm/nouveau/Kconfig @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only config DRM_NOUVEAU tristate "Nouveau (NVIDIA) cards" - depends on DRM && PCI && MMU + depends on DRM && PCI select IOMMU_API select FW_LOADER select FW_CACHE if PM_SLEEP @@ -94,7 +94,6 @@ config DRM_NOUVEAU_SVM bool "(EXPERIMENTAL) Enable SVM (Shared Virtual Memory) support" depends on DEVICE_PRIVATE depends on DRM_NOUVEAU - depends on MMU depends on STAGING select HMM_MIRROR select MMU_NOTIFIER diff --git a/drivers/gpu/drm/qxl/Kconfig b/drivers/gpu/drm/qxl/Kconfig index 69427eb8bed2..d8f24bcae34b 100644 --- a/drivers/gpu/drm/qxl/Kconfig +++ b/drivers/gpu/drm/qxl/Kconfig @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only config DRM_QXL tristate "QXL virtual GPU" - depends on DRM && PCI && MMU && HAS_IOPORT + depends on DRM && PCI && HAS_IOPORT select DRM_CLIENT_SELECTION select DRM_KMS_HELPER select DRM_TTM diff --git a/drivers/gpu/drm/radeon/Kconfig b/drivers/gpu/drm/radeon/Kconfig index f51bace9555d..c479f0c0dd5c 100644 --- a/drivers/gpu/drm/radeon/Kconfig +++ b/drivers/gpu/drm/radeon/Kconfig @@ -2,7 +2,7 @@ config DRM_RADEON tristate "ATI Radeon" - depends on DRM && PCI && MMU + depends on DRM && PCI depends on AGP || !AGP select FW_LOADER select DRM_CLIENT_SELECTION diff --git a/drivers/gpu/drm/tiny/Kconfig b/drivers/gpu/drm/tiny/Kconfig index 54c84c9801c1..6ca12fe7f57a 100644 --- a/drivers/gpu/drm/tiny/Kconfig +++ b/drivers/gpu/drm/tiny/Kconfig @@ -37,7 +37,7 @@ config DRM_BOCHS config DRM_CIRRUS_QEMU tristate "Cirrus driver for QEMU emulated device" - depends on DRM && PCI && MMU + depends on DRM && PCI select DRM_CLIENT_SELECTION select DRM_KMS_HELPER select DRM_GEM_SHMEM_HELPER diff --git a/drivers/gpu/drm/vmwgfx/Kconfig b/drivers/gpu/drm/vmwgfx/Kconfig index 6c3c2922ae8b..aab646b91ca9 100644 --- a/drivers/gpu/drm/vmwgfx/Kconfig +++ b/drivers/gpu/drm/vmwgfx/Kconfig @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 config DRM_VMWGFX tristate "DRM driver for VMware Virtual GPU" - depends on DRM && PCI && MMU + depends on DRM && PCI depends on (X86 && HYPERVISOR_GUEST) || ARM64 select DRM_CLIENT_SELECTION select DRM_TTM diff --git a/drivers/gpu/drm/xe/Kconfig b/drivers/gpu/drm/xe/Kconfig index 5c2f459a2925..2dec62737ff6 100644 --- a/drivers/gpu/drm/xe/Kconfig +++ b/drivers/gpu/drm/xe/Kconfig @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only config DRM_XE tristate "Intel Xe Graphics" - depends on DRM && PCI && MMU && (m || (y && KUNIT=y)) + depends on DRM && PCI && (m || (y && KUNIT=y)) select INTERVAL_TREE # we need shmfs for the swappable backing store, and in particular # the shmem_readpage() which depends upon tmpfs diff --git a/drivers/net/ethernet/broadcom/Kconfig b/drivers/net/ethernet/broadcom/Kconfig index eeec8bf17cf4..aa43984a05cf 100644 --- a/drivers/net/ethernet/broadcom/Kconfig +++ b/drivers/net/ethernet/broadcom/Kconfig @@ -96,7 +96,6 @@ config BNX2 config CNIC tristate "QLogic CNIC support" depends on PCI && (IPV6 || IPV6=n) - depends on MMU select BNX2 select UIO help diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index da28295b4aac..9c0e4aaf4e8c 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -21,6 +21,7 @@ config GENERIC_PCI_IOMAP menuconfig PCI bool "PCI support" depends on HAVE_PCI + depends on MMU help This option enables support for the PCI local bus, including support for PCI-X and the foundations for PCI Express support. diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 4d7c9f64ea24..60a20a0ac41f 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -4257,7 +4257,7 @@ unsigned long __weak pci_address_to_pio(phys_addr_t address) #ifndef pci_remap_iospace int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr) { -#if defined(PCI_IOBASE) && defined(CONFIG_MMU) +#if defined(PCI_IOBASE) unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; if (!(res->flags & IORESOURCE_IO)) @@ -4290,7 +4290,7 @@ EXPORT_SYMBOL(pci_remap_iospace); */ void pci_unmap_iospace(struct resource *res) { -#if defined(PCI_IOBASE) && defined(CONFIG_MMU) +#if defined(PCI_IOBASE) unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; vunmap_range(vaddr, vaddr + resource_size(res)); diff --git a/drivers/scsi/bnx2fc/Kconfig b/drivers/scsi/bnx2fc/Kconfig index ecdc0f0f4f4e..3cf7e08df809 100644 --- a/drivers/scsi/bnx2fc/Kconfig +++ b/drivers/scsi/bnx2fc/Kconfig @@ -5,7 +5,6 @@ config SCSI_BNX2X_FCOE depends on (IPV6 || IPV6=n) depends on LIBFC depends on LIBFCOE - depends on MMU select NETDEVICES select ETHERNET select NET_VENDOR_BROADCOM diff --git a/drivers/scsi/bnx2i/Kconfig b/drivers/scsi/bnx2i/Kconfig index 0cc06c2ce0b8..75ace2302fed 100644 --- a/drivers/scsi/bnx2i/Kconfig +++ b/drivers/scsi/bnx2i/Kconfig @@ -4,7 +4,6 @@ config SCSI_BNX2_ISCSI depends on NET depends on PCI depends on (IPV6 || IPV6=n) - depends on MMU select SCSI_ISCSI_ATTRS select NETDEVICES select ETHERNET diff --git a/drivers/vfio/pci/Kconfig b/drivers/vfio/pci/Kconfig index c3bcb6911c53..2b0172f54665 100644 --- a/drivers/vfio/pci/Kconfig +++ b/drivers/vfio/pci/Kconfig @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only menu "VFIO support for PCI devices" - depends on PCI && MMU + depends on PCI config VFIO_PCI_CORE tristate -- cgit v1.2.3 From 22282967585ac9e5d88d92d804cc3e5b19c47a97 Mon Sep 17 00:00:00 2001 From: Rick Wertenbroek Date: Wed, 23 Apr 2025 11:56:43 +0200 Subject: Documentation: Fix path for NVMe PCI endpoint target driver The path for the driver points to an non-existent file. Update path with the correct file: drivers/nvme/target/pci-epf.c Signed-off-by: Rick Wertenbroek Signed-off-by: Bjorn Helgaas Reviewed-by: Damien Le Moal Link: https://patch.msgid.link/20250423095643.490495-1-rick.wertenbroek@gmail.com --- Documentation/PCI/endpoint/pci-nvme-function.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/PCI/endpoint/pci-nvme-function.rst b/Documentation/PCI/endpoint/pci-nvme-function.rst index df57b8e7d066..a68015317f7f 100644 --- a/Documentation/PCI/endpoint/pci-nvme-function.rst +++ b/Documentation/PCI/endpoint/pci-nvme-function.rst @@ -8,6 +8,6 @@ PCI NVMe Function The PCI NVMe endpoint function implements a PCI NVMe controller using the NVMe subsystem target core code. The driver for this function resides with the NVMe -subsystem as drivers/nvme/target/nvmet-pciep.c. +subsystem as drivers/nvme/target/pci-epf.c. See Documentation/nvme/nvme-pci-endpoint-target.rst for more details. -- cgit v1.2.3 From 1c8a0ed2043c30cee97facd1eb8cff88b6c7ea4a Mon Sep 17 00:00:00 2001 From: Ilpo Järvinen Date: Mon, 7 Apr 2025 13:12:14 +0300 Subject: PCI: Remove unused pci_printk() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit include/linux/pci.h provides low-level pci_printk() interface that is not used since the commits fab874e12593 ("PCI/AER: Descope pci_printk() to aer_printk()") and 588021b28642 ("PCI: shpchp: Remove 'shpchp_debug' module parameter"). PCI logging should not use pci_printk() but pci_*() wrappers that follow the usual logging wrapper patterns. Remove pci_printk(). Signed-off-by: Ilpo Järvinen Signed-off-by: Krzysztof Wilczyński Signed-off-by: Bjorn Helgaas Link: https://lore.kernel.org/r/20250407101215.1376-1-ilpo.jarvinen@linux.intel.com --- include/linux/pci.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/include/linux/pci.h b/include/linux/pci.h index 0e8e3fd77e96..e293ad5d840d 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -2694,9 +2694,6 @@ void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type); #include -#define pci_printk(level, pdev, fmt, arg...) \ - dev_printk(level, &(pdev)->dev, fmt, ##arg) - #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg) #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg) #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg) -- cgit v1.2.3 From af6e3defb11a1c67cd462485655b43b5d70524b1 Mon Sep 17 00:00:00 2001 From: Ilpo Järvinen Date: Mon, 12 May 2025 00:52:23 +0300 Subject: PCI: WARN (not BUG()) when we fail to assign optional resources MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Resource fitting/assignment code checks if there's a remainder in add_list (aka. realloc_head in the inner functions) using BUG_ON(). This problem typically results in a mere PCI device resource assignment failure which does not warrant using BUG_ON(). The machine could well come up usable even if this condition occurs because the realloc_head relates to resources which are optional anyway. Change BUG_ON() to WARN_ON_ONCE() and free the list if it's not empty. [bhelgaas: subject] Reported-by: Tudor Ambarus Signed-off-by: Ilpo Järvinen Signed-off-by: Krzysztof Wilczyński Signed-off-by: Bjorn Helgaas Link: https://lore.kernel.org/linux-pci/5f103643-5e1c-43c6-b8fe-9617d3b5447c@linaro.org Link: https://lore.kernel.org/r/20250511215223.7131-1-ilpo.jarvinen@linux.intel.com --- drivers/pci/setup-bus.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 54d6f4fa3ce1..a0d815557f5c 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -2298,8 +2298,8 @@ void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus) /* Depth last, allocate resources and update the hardware. */ __pci_bus_assign_resources(bus, add_list, &fail_head); - if (add_list) - BUG_ON(!list_empty(add_list)); + if (WARN_ON_ONCE(add_list && !list_empty(add_list))) + free_list(add_list); tried_times++; /* Any device complain? */ @@ -2361,7 +2361,8 @@ void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge) pci_bridge_distribute_available_resources(bridge, &add_list); __pci_bridge_assign_resources(bridge, &add_list, &fail_head); - BUG_ON(!list_empty(&add_list)); + if (WARN_ON_ONCE(!list_empty(&add_list))) + free_list(&add_list); tried_times++; if (list_empty(&fail_head)) @@ -2437,7 +2438,8 @@ int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type) __pci_bus_size_bridges(bridge->subordinate, &added); __pci_bridge_assign_resources(bridge, &added, &failed); - BUG_ON(!list_empty(&added)); + if (WARN_ON_ONCE(!list_empty(&added))) + free_list(&added); if (!list_empty(&failed)) { ret = -ENOSPC; @@ -2493,6 +2495,7 @@ void pci_assign_unassigned_bus_resources(struct pci_bus *bus) __pci_bus_size_bridges(dev->subordinate, &add_list); up_read(&pci_bus_sem); __pci_bus_assign_resources(bus, &add_list, NULL); - BUG_ON(!list_empty(&add_list)); + if (WARN_ON_ONCE(!list_empty(&add_list))) + free_list(&add_list); } EXPORT_SYMBOL_GPL(pci_assign_unassigned_bus_resources); -- cgit v1.2.3 From 75d7b40becfb9de11f9c2ff7138111eb48e76099 Mon Sep 17 00:00:00 2001 From: Ilpo Järvinen Date: Fri, 4 Apr 2025 15:45:47 +0300 Subject: PCI: Remove unnecessary linesplit in __pci_setup_bridge() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit No need to split the line in __pci_setup_bridge() as it is way shorter than the limit. Signed-off-by: Ilpo Järvinen Signed-off-by: Krzysztof Wilczyński Signed-off-by: Bjorn Helgaas Link: https://lore.kernel.org/r/20250404124547.51185-1-ilpo.jarvinen@linux.intel.com --- drivers/pci/setup-bus.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index a0d815557f5c..cc37cdb5e352 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -772,8 +772,7 @@ static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type) { struct pci_dev *bridge = bus->self; - pci_info(bridge, "PCI bridge to %pR\n", - &bus->busn_res); + pci_info(bridge, "PCI bridge to %pR\n", &bus->busn_res); if (type & IORESOURCE_IO) pci_setup_bridge_io(bridge); -- cgit v1.2.3 From ae06c6197c9e53dcb115f1f7aad9e86aa465adae Mon Sep 17 00:00:00 2001 From: Krzysztof Wilczyński Date: Fri, 18 Apr 2025 04:52:51 +0000 Subject: MAINTAINERS: Update Krzysztof Wilczyński email address MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update my e-mail address and add relevant entries to the .mailmap file. [bhelgaas: drop maintainer status change] Signed-off-by: Krzysztof Wilczyński Signed-off-by: Bjorn Helgaas Link: https://patch.msgid.link/20250418045251.7434-1-kwilczynski@kernel.org --- .mailmap | 2 ++ MAINTAINERS | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/.mailmap b/.mailmap index 4f7cd8e23177..5224f3cc2d34 100644 --- a/.mailmap +++ b/.mailmap @@ -413,6 +413,8 @@ Krishna Manikandan Krzysztof Kozlowski Krzysztof Kozlowski Krzysztof Kozlowski +Krzysztof Wilczyński +Krzysztof Wilczyński Kshitiz Godara Kuninori Morimoto Kuogee Hsieh diff --git a/MAINTAINERS b/MAINTAINERS index 1f6514d55b17..d5d1a4aea0e8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18581,7 +18581,7 @@ F: drivers/pci/controller/pcie-xilinx-cpm.c PCI ENDPOINT SUBSYSTEM M: Manivannan Sadhasivam -M: Krzysztof Wilczyński +M: Krzysztof Wilczyński R: Kishon Vijay Abraham I L: linux-pci@vger.kernel.org S: Supported @@ -18632,7 +18632,7 @@ F: drivers/pci/controller/pci-xgene-msi.c PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS M: Lorenzo Pieralisi -M: Krzysztof Wilczyński +M: Krzysztof Wilczyński R: Manivannan Sadhasivam R: Rob Herring L: linux-pci@vger.kernel.org -- cgit v1.2.3 From 308f8c7a626ecd5b9be67181ae67660e165a29b5 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 4 Jun 2025 17:38:30 +0530 Subject: MAINTAINERS: Update Manivannan Sadhasivam email address My Linaro email is going to bounce soon, so switch to the kernel.org alias and add relevant .mailmap entry. [bhelgaas: squash https://patch.msgid.link/20250604120833.32791-3-manivannan.sadhasivam@linaro.org] Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Helgaas Acked-by: Neil Armstrong Link: https://patch.msgid.link/20250604120833.32791-2-manivannan.sadhasivam@linaro.org --- .mailmap | 1 + MAINTAINERS | 38 +++++++++++++++++++------------------- 2 files changed, 20 insertions(+), 19 deletions(-) diff --git a/.mailmap b/.mailmap index 5224f3cc2d34..d6ea8d58694a 100644 --- a/.mailmap +++ b/.mailmap @@ -453,6 +453,7 @@ Maheshwar Ajja Malathi Gottam Manikanta Pubbisetty Manivannan Sadhasivam +Manivannan Sadhasivam Manoj Basapathi Marcin Nowakowski Marc Zyngier diff --git a/MAINTAINERS b/MAINTAINERS index d5d1a4aea0e8..f1a0769ed8ee 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2102,7 +2102,7 @@ F: arch/arm/plat-*/ ARM/ACTIONS SEMI ARCHITECTURE M: Andreas Färber -M: Manivannan Sadhasivam +M: Manivannan Sadhasivam L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-actions@lists.infradead.org (moderated for non-subscribers) S: Maintained @@ -2354,7 +2354,7 @@ F: arch/arm/boot/dts/intel/axm/ F: arch/arm/mach-axxia/ ARM/BITMAIN ARCHITECTURE -M: Manivannan Sadhasivam +M: Manivannan Sadhasivam L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: Documentation/devicetree/bindings/arm/bitmain.yaml @@ -3021,7 +3021,7 @@ F: include/linux/soc/qcom/ F: include/soc/qcom/ ARM/RDA MICRO ARCHITECTURE -M: Manivannan Sadhasivam +M: Manivannan Sadhasivam L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-unisoc@lists.infradead.org (moderated for non-subscribers) S: Maintained @@ -3718,7 +3718,7 @@ F: Documentation/admin-guide/aoe/ F: drivers/block/aoe/ ATC260X PMIC MFD DRIVER -M: Manivannan Sadhasivam +M: Manivannan Sadhasivam M: Cristian Ciocaltea L: linux-actions@lists.infradead.org S: Maintained @@ -6721,7 +6721,7 @@ S: Orphan F: drivers/mtd/nand/raw/denali* DESIGNWARE EDMA CORE IP DRIVER -M: Manivannan Sadhasivam +M: Manivannan Sadhasivam L: dmaengine@vger.kernel.org S: Maintained F: drivers/dma/dw-edma/ @@ -8536,7 +8536,7 @@ S: Maintained F: drivers/edac/pnd2_edac.[ch] EDAC-QCOM -M: Manivannan Sadhasivam +M: Manivannan Sadhasivam L: linux-arm-msm@vger.kernel.org L: linux-edac@vger.kernel.org S: Maintained @@ -14664,7 +14664,7 @@ F: drivers/hid/hid-mcp2221.c MCP251XFD SPI-CAN NETWORK DRIVER M: Marc Kleine-Budde -M: Manivannan Sadhasivam +M: Manivannan Sadhasivam R: Thomas Kopp L: linux-can@vger.kernel.org S: Maintained @@ -15644,7 +15644,7 @@ F: arch/arm64/boot/dts/marvell/armada-3720-eDPU.dts F: arch/arm64/boot/dts/marvell/armada-3720-uDPU.* MHI BUS -M: Manivannan Sadhasivam +M: Manivannan Sadhasivam L: mhi@lists.linux.dev L: linux-arm-msm@vger.kernel.org S: Maintained @@ -18545,7 +18545,7 @@ F: drivers/pci/controller/dwc/pci-exynos.c PCI DRIVER FOR SYNOPSYS DESIGNWARE M: Jingoo Han -M: Manivannan Sadhasivam +M: Manivannan Sadhasivam L: linux-pci@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml @@ -18580,7 +18580,7 @@ F: Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml F: drivers/pci/controller/pcie-xilinx-cpm.c PCI ENDPOINT SUBSYSTEM -M: Manivannan Sadhasivam +M: Manivannan Sadhasivam M: Krzysztof Wilczyński R: Kishon Vijay Abraham I L: linux-pci@vger.kernel.org @@ -18633,7 +18633,7 @@ F: drivers/pci/controller/pci-xgene-msi.c PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS M: Lorenzo Pieralisi M: Krzysztof Wilczyński -R: Manivannan Sadhasivam +M: Manivannan Sadhasivam R: Rob Herring L: linux-pci@vger.kernel.org S: Supported @@ -18779,7 +18779,7 @@ F: Documentation/devicetree/bindings/pci/microchip* F: drivers/pci/controller/plda/*microchip* PCIE DRIVER FOR QUALCOMM MSM -M: Manivannan Sadhasivam +M: Manivannan Sadhasivam L: linux-pci@vger.kernel.org L: linux-arm-msm@vger.kernel.org S: Maintained @@ -18815,7 +18815,7 @@ F: Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml F: drivers/pci/controller/plda/pcie-starfive.c PCIE ENDPOINT DRIVER FOR QUALCOMM -M: Manivannan Sadhasivam +M: Manivannan Sadhasivam L: linux-pci@vger.kernel.org L: linux-arm-msm@vger.kernel.org S: Maintained @@ -19933,7 +19933,7 @@ F: drivers/iommu/arm/arm-smmu/arm-smmu-qcom* F: drivers/iommu/msm_iommu* QUALCOMM IPC ROUTER (QRTR) DRIVER -M: Manivannan Sadhasivam +M: Manivannan Sadhasivam L: linux-arm-msm@vger.kernel.org S: Maintained F: include/trace/events/qrtr.h @@ -19941,7 +19941,7 @@ F: include/uapi/linux/qrtr.h F: net/qrtr/ QUALCOMM IPCC MAILBOX DRIVER -M: Manivannan Sadhasivam +M: Manivannan Sadhasivam L: linux-arm-msm@vger.kernel.org S: Supported F: Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml @@ -19975,7 +19975,7 @@ F: Documentation/devicetree/bindings/media/qcom,*-iris.yaml F: drivers/media/platform/qcom/iris/ QUALCOMM NAND CONTROLLER DRIVER -M: Manivannan Sadhasivam +M: Manivannan Sadhasivam L: linux-mtd@lists.infradead.org L: linux-arm-msm@vger.kernel.org S: Maintained @@ -22510,7 +22510,7 @@ F: Documentation/devicetree/bindings/media/i2c/sony,imx283.yaml F: drivers/media/i2c/imx283.c SONY IMX290 SENSOR DRIVER -M: Manivannan Sadhasivam +M: Manivannan Sadhasivam L: linux-media@vger.kernel.org S: Maintained T: git git://linuxtv.org/media.git @@ -22519,7 +22519,7 @@ F: drivers/media/i2c/imx290.c SONY IMX296 SENSOR DRIVER M: Laurent Pinchart -M: Manivannan Sadhasivam +M: Manivannan Sadhasivam L: linux-media@vger.kernel.org S: Maintained T: git git://linuxtv.org/media.git @@ -24815,7 +24815,7 @@ S: Maintained F: drivers/ufs/host/ufs-mediatek* UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER QUALCOMM HOOKS -M: Manivannan Sadhasivam +M: Manivannan Sadhasivam L: linux-arm-msm@vger.kernel.org L: linux-scsi@vger.kernel.org S: Maintained -- cgit v1.2.3