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author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2014-07-04 11:59:58 -0300 |
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committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-07-10 08:27:09 +0200 |
commit | 9ccd5aeb2901aaaabf77f185e2e5ea3a0b577e86 (patch) | |
tree | 201f29314c86977797f72c8c9e844860862d7082 /tools/perf/scripts/python | |
parent | f475dadf833691e6173dee9ad05953265f6ffe21 (diff) |
drm/i915: fix D_COMP usage on BDW
On HSW, the D_COMP register can be accessed through the mailbox (read
and write) or through MMIO on a MCHBAR offset (read only). On BDW, the
access should be done through MMIO on another address. So to account
for all these cases, create hsw_read_dcomp() with the correct
implementation for reading, and also fix hsw_write_dcomp() to do the
correct thing on BDW.
With this patch, we can now get back from the PC8+ state on BDW. We
were previously getting a black screen and lots of dmesg errors.
Please notice that the bug only happens when you actually reach the
PC8+ states, not when you only allow it.
Testcase: igt/pm_rpm/rte
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions