diff options
| author | Andrzej Hajda <andrzej.hajda@intel.com> | 2022-12-14 08:54:39 +0100 |
|---|---|---|
| committer | Andi Shyti <andi.shyti@linux.intel.com> | 2022-12-15 11:09:24 +0100 |
| commit | 4d5cf7b1680a1e6db327e3c935ef58325cbedb2c (patch) | |
| tree | e84da6e79a3962414411f4a94fc6ebcb93f992dd /tools/perf/scripts/python | |
| parent | 95df9cc24bee8a09d39c62bcef4319b984814e18 (diff) | |
drm/i915: fix TLB invalidation for Gen12.50 video and compute engines
In case of Gen12.50 video and compute engines, TLB_INV registers are
masked - to modify one bit, corresponding bit in upper half of the register
must be enabled, otherwise nothing happens.
Fixes: 77fa9efc16a9 ("drm/i915/xehp: Create separate reg definitions for new MCR registers")
Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221214075439.402485-1-andrzej.hajda@intel.com
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions