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| author | Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> | 2023-01-30 15:38:06 +0530 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2023-02-16 12:29:51 +0200 |
| commit | 06f1b06dc5b75b1a4071c905231d40cd74587a18 (patch) | |
| tree | c452f545264d53654fb94740d89e5e3346f4fe6c /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 61b795a9c35264022cf0bfc49d26e75162a23d5d (diff) | |
drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
A new step of 480MHz has been added on SKUs that have a RPL-U
device id to support 120Hz displays more efficiently. Use a
new quirk to identify the machine for which this change needs
to be applied.
v2: (Matt)
- Add missing clock steps
- Correct reference clock typo
v3: - Revert to RPL-U subplatform (Jani)
v4: - Remove Bspec reference from code (Jani)
Bspec: 55409
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230130100806.1373883-3-chaitanya.kumar.borah@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions