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authorH.J. Lu <hjl.tools@gmail.com>2015-01-23 17:27:09 -0800
committerH.J. Lu <hjl.tools@gmail.com>2015-01-23 18:08:10 -0800
commitede0236c867a28aaed941e7acac9b0a8d89c5acb (patch)
tree4e2330712d893981cefa0fb3747670985ec8664a
parente0da28a1b2ff9112f4aee4cebd4b22fce1ae62ac (diff)
Treat model numbers 0x4a/0x4d as Silvermont
* sysdeps/x86_64/multiarch/init-arch.c (__init_cpu_features): Treat model numbers 0x4a/0x4d as Intel Silvermont architecture.
-rw-r--r--ChangeLog5
-rw-r--r--sysdeps/x86_64/multiarch/init-arch.c2
2 files changed, 7 insertions, 0 deletions
diff --git a/ChangeLog b/ChangeLog
index 306341c65e..c199a5d938 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,5 +1,10 @@
2015-01-23 H.J. Lu <hongjiu.lu@intel.com>
+ * sysdeps/x86_64/multiarch/init-arch.c (__init_cpu_features):
+ Treat model numbers 0x4a/0x4d as Intel Silvermont architecture.
+
+2015-01-23 H.J. Lu <hongjiu.lu@intel.com>
+
[BZ #17870]
* nptl/sem_post.c (__new_sem_post): Replace unsigned long int
with uint64_t.
diff --git a/sysdeps/x86_64/multiarch/init-arch.c b/sysdeps/x86_64/multiarch/init-arch.c
index 47b9655e26..ec71918b25 100644
--- a/sysdeps/x86_64/multiarch/init-arch.c
+++ b/sysdeps/x86_64/multiarch/init-arch.c
@@ -79,6 +79,8 @@ __init_cpu_features (void)
break;
case 0x37:
+ case 0x4a:
+ case 0x4d:
/* Unaligned load versions are faster than SSSE3
on Silvermont. */
#if index_Fast_Unaligned_Load != index_Prefer_PMINUB_for_stringop